JP5460087B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor.

  A lateral field effect transistor (FET) having a source electrode, a drain electrode, and a gate electrode on a semiconductor operating layer is disclosed which has a RESURF structure between the gate and the drain in order to reduce the electric field concentration and increase the breakdown voltage. (For example, refer to Patent Document 1). The field effect transistor disclosed in Patent Document 1 includes a semiconductor operation layer having a RESURF structure formed on a substrate via a buffer layer.

  The RESURF structure is realized by a p-type semiconductor layer made of p-GaN and a RESURF layer made of n-GaN formed on the p-type semiconductor layer. The pressure resistance of this RESURF structure depends on the balance of the number of carriers of the p-type carrier of the p-type semiconductor layer and the n-type carrier of the RESURF layer.

JP 2008-205221 A

  However, the inventors have scrutinized the field effect transistor having the structure disclosed in Patent Document 1 and found that when the substrate is conductive, the desired high breakdown voltage can be achieved even if the balance of the number of carriers in the RESURF structure is adjusted. There was a problem that could not be obtained.

  The present invention has been made in view of the above, and an object of the present invention is to provide a field effect transistor having high pressure resistance.

  In order to solve the above-described problems and achieve the object, a field effect transistor according to the present invention includes a substrate having a p-type conductivity, a high-resistance layer formed on the substrate, and the high-resistance layer. A semiconductor operation layer having a RESURF structure in which a p-type semiconductor layer having a p-type conductivity is disposed on the substrate side, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor operation layer, It is characterized by providing.

  The field effect transistor according to the present invention is the field effect transistor according to the above invention, wherein the semiconductor operation layer includes a resurf layer having an n-type conductivity type formed on the p-type semiconductor layer, The RESURF layer forms the RESURF structure.

  The field effect transistor according to the present invention is the field effect transistor according to the above invention, wherein the semiconductor operation layer is formed on the p-type semiconductor layer and an undoped carrier traveling layer is formed on the carrier traveling layer. The layer includes a carrier supply layer having a different band gap energy, and the p-type semiconductor layer and the carrier traveling layer form the RESURF structure.

  The field effect transistor according to the present invention is characterized in that, in the above invention, the high resistance layer and the semiconductor operation layer are made of a nitride compound semiconductor.

  In the field effect transistor according to the present invention as set forth in the invention described above, the high resistance layer is made of a silicon oxide film, and the semiconductor operation layer is made of a silicon-based semiconductor.

In the field effect transistor according to the present invention, in the above invention, the substrate is made of silicon having a carrier concentration of 1 × 10 ¹² to 1 × 10 ¹⁶ cm ⁻³ , and the p-type semiconductor layer has a thickness of 600 nm. by and consists GaN carrier concentration of 1 × ¹⁰ 16 ^{cm -3,} the RESURF layer is characterized in that the sheet carrier concentration of GaN is ^{1 × 10 12 ~2.5 × 10 12} cm -2 .

  According to the present invention, since the local electric field concentration between the gate and the drain is effectively alleviated, there is an effect that a field effect transistor having high withstand voltage can be realized.

FIG. 1 is a schematic cross-sectional view of the field effect transistor according to the first embodiment. FIG. 2 is a diagram showing the electric field distribution of a field effect transistor using an n-type substrate, using electric lines of force. FIG. 3 is a diagram showing the electric field distribution of the field effect transistor shown in FIG. 1 using lines of electric force. FIG. 4 is a schematic cross-sectional view of the field effect transistor according to the second embodiment. FIG. 5 is a diagram showing the relationship between the carrier concentration of the substrate and the breakdown voltage. FIG. 6 is a diagram showing the relationship between the carrier concentration of the RESURF layer and the breakdown voltage. FIG. 7 is a schematic cross-sectional view of the field effect transistor according to the third embodiment.

  Embodiments of a field effect transistor according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. In the drawings, the same constituent elements are denoted by the same reference numerals as appropriate.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a field effect transistor according to Embodiment 1 of the present invention. This field effect transistor 100 includes a substrate 1 having p-type conductivity such as SiC or Si, and a high-resistance buffer formed on the substrate 1 via an AlN layer 2 to maintain a vertical breakdown voltage. A layer 3 and a semiconductor operation layer 4 formed on the high resistance buffer layer 3 are provided. The semiconductor operation layer 4 includes a p-type semiconductor layer 5 as a carrier traveling layer made of p-GaN, contact layers 6 and 7 made of n ⁺ -GaN, and a RESURF layer 8 made of n ⁻ -GaN. Yes. The field effect transistor 100 includes a source electrode 9, a drain electrode 10, and a gate electrode 12 formed on the semiconductor operation layer 4 via a gate insulating film 11.

  The source electrode 9 and the drain electrode 10 are formed on the contact layers 6 and 7, respectively. The RESURF layer 8 is formed between the gate and the drain so as to be adjacent to the contact layer 7 and partially overlap the gate electrode 12 in the stacking direction. The p-type semiconductor layer 5 and the RESURF layer 8 form a RESURF structure R1 in which the p-type semiconductor layer 5 is disposed on the substrate 1 side. The high resistance buffer layer 3 is formed by alternately laminating GaN layers and AlN layers, for example. If the high resistance buffer layer 3 has such a laminated structure, the high resistance buffer layer 3 has high resistance and can relieve strain caused by a difference in lattice constant generated between the substrate 1 and the semiconductor operation layer 4. Further, the AlN layer 2 prevents the substrate 1 and the high resistance buffer layer 3 from undergoing a chemical reaction such as alloying.

  Next, the electric field distribution in a state where a voltage is applied between the source and the drain of the field effect transistor 100 will be described. First, for comparison, in the field effect transistor 100, the field distribution of the field effect transistor 100a in which the substrate 1 is replaced with the substrate 1a having the n-type conductivity will be described. Next, the field distribution of the field effect transistor 100 will be described. To do.

  FIG. 2 is a diagram showing the electric field distribution of the field effect transistor 100a using an n-type substrate using lines of electric force. Also in the field effect transistor 100a, the p-type semiconductor layer 5 and the RESURF layer 8 form a RESURF structure R1. Therefore, the electric field concentration is moderated to some extent by adjusting the balance of the number of carriers of the p-type carrier C1 of the p-type semiconductor layer 5 and the n-type carrier C2 of the RESURF layer 8.

  However, in the case of this field effect transistor 100a, since the substrate 1a also has the n-type carrier C2, the electric lines of force L bend from the p-type semiconductor layer 5 side to both sides of the substrate 1 and the RESURF layer 8. As a result, regions A1 and A2 where the density of the electric lines of force L is high and electric field concentration occurs are generated.

  On the other hand, FIG. 3 is a diagram showing the electric field distribution of the field effect transistor 100 shown in FIG. 1 using lines of electric force. As shown in FIG. 3, in the case of this field effect transistor 100, the substrate 1 has a p-type carrier C1. Therefore, the electric lines of force L extend from the RESURF layer 8 side through the p-type semiconductor layer 5 toward the substrate 1 side without a large bend, so that a region having a high density of electric lines of force L does not occur and electric field concentration occurs. Absent. As a result, the field effect transistor 100 has high breakdown voltage.

  Further, since the threshold voltage of the field effect transistor 100 depends on the carrier concentration of the p-type semiconductor layer 5, the carrier concentration of the p-type semiconductor layer 5 is limited to some extent in order to realize a desired threshold voltage. On the other hand, in order to reduce the resistance (on-resistance) when the field effect transistor 100 is turned on, it is preferable to increase the carrier concentration of the RESURF layer 8 or increase the thickness of the RESURF layer 8. Therefore, considering that the electric field distribution is controlled by balancing the number of carriers only with the RESURF structure R1, it is difficult to make the threshold voltage and the ON resistance have desired characteristics at the same time.

  However, in this field effect transistor 100, the electric field distribution can be controlled by a balance including the number of carriers of the p-type carrier C1 of the substrate 1. Therefore, for example, in the field effect transistor 100, while setting the carrier concentration of the p-type semiconductor layer 5 to a predetermined value, the carrier concentration or thickness of the RESURF layer 8 is increased, and the carrier concentration of the substrate 1 is set to the number of carriers. If the balance is adjusted, a desired threshold voltage can be realized, and a field effect transistor with low on-resistance and high withstand voltage can be realized.

  Next, an example of a method for manufacturing the field effect transistor 100 will be described below. In the following, the case where the metal organic chemical vapor deposition (MOCVD) method is used will be described, but there is no particular limitation.

First, for example, a substrate 1 made of Si having a (111) plane as a main surface is set in an MOCVD apparatus, and hydrogen gas with a concentration of 100% is used as a carrier gas, trimethylgallium (TMGa), trimethylaluminum (TMAl), and NH _3. Are introduced at a flow rate of 58 μmol / min, 100 μmol / min, and 12 l / min, respectively, and an AlN layer 2, a high-resistance buffer layer 3, and a p-type semiconductor layer 5 are sequentially epitaxially grown on the substrate 1 at a growth temperature of 1050 ° C. Let Note that biscyclopentadienyl magnesium (Cp2Mg) is used as a p-type doping source for the p-type semiconductor layer 5, and the flow rate of Cp2Mg is adjusted so that, for example, the Mg concentration is about 1 × 10 ¹⁹ cm ⁻³ . The Mg concentration is measured by SIMS (secondary ion mass spectrometer). The high-resistance buffer layer 3 is formed by stacking, for example, eight GaN / AlN composite layers having a thickness of 200 nm / 20 nm, and the thicknesses of the AlN layer 2 and the p-type semiconductor layer 5 are, for example, 100 nm and 500 nm, respectively. To do.

Next, using a plasma chemical vapor deposition (PCVD) method, on the p-type semiconductor layer 5, to form a SiO ₂ layer having a thickness of 2 [mu] m, using photolithography and hydrofluoric acid, of the SiO ₂ layer The regions where the contact layers 6 and 7 and the RESURF layer 8 are to be formed are removed. Next, ion implantation of Si ions that are n-type impurities is performed, and a desired amount of Si ions is implanted into each region from which the SiO ₂ layer has been removed. Next, after removing the SiO ₂ layer with hydrofluoric acid, an SiO ₂ film as a protective film for activation annealing is formed on the p-type semiconductor layer 5 to a thickness of 500 nm. Then, in order to activate the implanted Si ions, activation annealing is performed at 1150 ° C. for 4 minutes while flowing a nitrogen gas to form the contact layers 6 and 7 and the RESURF layer 8. The amount of Si ions implanted is, for example, such that the n-type sheet carrier concentration in the contact layers 6 and 7 is about 5 × 10 ¹⁴ cm ⁻² and the sheet carrier concentration in the RESURF layer 8 is about 2 × 10 ¹² cm ^−2. To. The sheet carrier concentration is measured by Hall measurement or SIMS method.

Next, the SiO ₂ film is removed, and a gate insulating film 11 made of, for example, SiO ₂ and having a thickness of 60 nm is formed using a PCVD method using SiH ₄ and N ₂ O as source gases. Next, after part of the gate insulating film 11 is removed with hydrofluoric acid, the source electrode 9 and the drain electrode 10 are formed using a lift-off method. The source electrode 9 and the drain electrode 10 both have a Ti / Al structure with a thickness of 25 nm / 300 nm. The metal film can be formed using a sputtering method or a vacuum evaporation method. Then, after forming the source electrode 9 and the drain electrode 10, annealing is performed at 600 ° C. for 10 minutes.

  Next, a gate electrode 12 having a Ti / Au / Ti structure is formed by using a lift-off method, and the field effect transistor 100 is completed.

  In the above-described manufacturing method, the contact layers 6 and 7 and the RESURF layer 8 are formed by using the ion implantation method, but may be formed by using, for example, a diffusion method or a regrowth method. Further, the n-type impurity is not limited to Si, but may be other impurities.

  As described above, the field effect transistor 100 according to the first embodiment has a high breakdown voltage and further has a desired threshold voltage and a low on-resistance.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic cross-sectional view of the field effect transistor according to the second embodiment. As shown in FIG. 4, the field effect transistor 200 is formed on a substrate 1 having a p-type conductivity and an AlN layer 2 on the substrate 1 in the same manner as the field effect transistor 100 shown in FIG. The high-resistance buffer layer 3 and the semiconductor operation layer 13 formed on the high-resistance buffer layer 3 are provided. The semiconductor operation layer 13 includes a p-type semiconductor layer 14 as a carrier traveling layer made of p-GaN, and an n-type semiconductor layer 15 made of n-GaN and a RESURF layer 16 formed on the p-type semiconductor layer 14. The recess 17 is formed between the n-type semiconductor layer 15 and the RESURF layer 16 to a depth reaching the p-type semiconductor layer 14. The field effect transistor 200 further includes a source electrode 9 and a drain electrode 10 formed on the semiconductor operation layer 13 with the recess portion 17 interposed therebetween. Further, the field effect transistor 200 includes a gate insulating film 18 formed over the semiconductor operation layer 13 including the recess portion 17, and a gate electrode 19 formed on the gate insulating film 18 in the recess portion 17. The recess portion 17 is formed in order to make the field effect transistor 200 normally-off type.

  In addition, each side wall of the recess portion 17 has an angle θ1 and θ2 with respect to the surface of the p-type semiconductor layer 14. The angles θ1 and θ2 are, for example, 90 °. However, if the angle θ2 is less than 90 °, local concentration of the electric field at the corner is alleviated. preferable. Further, if the angles θ1 and θ2 are 30 ° or more, the distance between the source and the drain does not become too long, which is preferable from the viewpoint of miniaturization of the device and cost reduction.

  As in the field effect transistor 100, in the field effect transistor 200, the p-type semiconductor layer 14 and the RESURF layer 16 form a RESURF structure R2 in which the p-type semiconductor layer 14 is disposed on the substrate 1 side. As a result, in a state where a voltage is applied between the source and the drain, the electric lines of force extend from the RESURF layer 16 side through the p-type semiconductor layer 14 toward the substrate 1 side without a large bend as in FIG. Electric field concentration does not occur, and the field effect transistor 200 has high withstand voltage.

  Further, for example, in the field effect transistor 200, while setting the carrier concentration of the p-type semiconductor layer 14 to a predetermined value, the carrier concentration or thickness of the RESURF layer 16 is increased, and the carrier concentration of the substrate 1 is set to the number of carriers. If the balance is adjusted, a desired threshold voltage can be realized, and a field effect transistor with low on-resistance and high withstand voltage can be realized.

  Next, an example of a method for manufacturing the field effect transistor 200 will be described below. First, similarly to the method for manufacturing the field effect transistor 100 described above, the AlN layer 2, the high-resistance buffer layer 3, and the p-type semiconductor layer 14 are sequentially epitaxially grown on the substrate 1.

Next, TMGa and NH ₃ are introduced at a flow rate of 19 μmol / min and 12 l / min, respectively, and at the same time, a predetermined amount of SiH ₄ is introduced as an n-type doping source, the growth temperature is 1050 ° C., and the p-type semiconductor layer 14 is introduced. An n-GaN layer is epitaxially grown thereon. The thickness of this n-GaN layer is, for example, 100 nm. The amount of SiH ₄ introduced is such that the n-type carrier concentration is, for example, 1 × 10 ¹⁷ cm ⁻³ . This carrier concentration is measured by Hall measurement.

Next, a PCVD method is used to form a mask layer made of amorphous silicon (a-Si) on the n-GaN layer with a thickness of 500 nm, and patterning is performed using photolithography and CF ₄ gas to form a recess portion. An opening is formed in a region where 17 is to be formed.

Next, using the mask layer as a mask, a portion of the n-GaN layer and the p-type semiconductor layer 14 immediately below the opening is etched away using Cl ₂ gas as an etching gas, thereby forming the recess 17. As a result, the n-type semiconductor layer 15 and the RESURF layer 16 are formed. Note that since the etching gas also etches the mask layer, the width of the opening gradually increases as the etching progresses. As a result, the sidewalls of the recess portion 17 are inclined at angles θ1 and θ2. The angles θ1 and θ2 can be appropriately adjusted depending on the material and thickness of the mask layer. For example, when the mask layer is made of a-Si, the values of the angles θ1 and θ2 are about 65 °.

  Next, the gate insulating film 18, the source electrode 9, the drain electrode 10, and the gate electrode 12 are formed in the same manner as in the method for manufacturing the field effect transistor 100 described above, and the field effect transistor 200 is completed.

  As described above, the field effect transistor 200 according to the second embodiment is a high breakdown voltage normally-off type, and further has a desired threshold voltage and a low on-resistance.

  Next, the voltage resistance of the field effect transistor 200 according to the second embodiment will be described with reference to simulation calculation results. The simulation software used for the calculation is TCAD of SYNOPSYS.

First, for the field effect transistor 200, the breakdown voltage when a voltage was applied between the source and the drain was calculated. For comparison, the field effect transistor 200 in which the substrate 1 is replaced with an n-type substrate was also calculated. Note that the source-drain voltage when the electric field strength reached 3.3 MV / cm in any part of the device or when the electric field strength in SiO ₂ reached 8 MV / cm was defined as the breakdown voltage. . In addition, as a characteristic value used for the calculation, the thickness of the substrate 1 or the n-type substrate was set to 525 μm. Further, the total thickness of the AlN layer 2 and the high resistance buffer layer 3 was 1800 nm, and the total resistivity was 1 × 10 ⁵ Ωcm or more. The thickness of the p-type semiconductor layer 14 was 600 nm, and the carrier concentration was 1 × 10 ¹⁶ cm ⁻³ . Further, the thickness of the n-type semiconductor layer 15 and the RESURF layer 16 was set to 100 nm. The gate insulating film 18 is a SiO ₂ film having a thickness of 60 nm. The widths of the source electrode 9 and the drain electrode 10 were both 10 μm. Further, the values of the widths W1, W2, and W3 shown in FIG. 4 were set to 3 μm, 4 μm, and 28 μm, respectively. Further, the depth of the recess portion 17 was set to 250 nm.

FIG. 5 is a diagram showing the relationship between the carrier concentration of the substrate and the breakdown voltage. In FIG. 5, the sheet carrier concentration of the n-type semiconductor layer 15 and the RESURF layer 16 is calculated as 2 × 10 ¹² cm ⁻² . As shown in FIG. 5, the breakdown voltage is higher in the case of the substrate 1 which is the p-type substrate than in the case of the n-type substrate, and in particular, the p-type carrier concentration of the substrate 1 is 1 × 10 ¹⁴ cm ⁻³ . In some cases, the breakdown voltage reached 742V. On the other hand, when the carrier concentration of the n-type substrate was 1 × 10 ¹⁴ cm ⁻³ , the breakdown voltage was 378V.

Similarly, the sheet carrier concentration of the n-type semiconductor layer 15 and the RESURF layer 16 was calculated as 1 × 10 ¹² cm ⁻² . In this case, too, the range of the carrier concentration of the substrate shown in FIG. The breakdown voltage was higher in the case of the substrate 1. For example, when the carrier concentration of the substrate is 1 × 10 ¹³ cm ⁻³ , the breakdown voltage was 160 V for the n-type substrate, but reached 526 V for the substrate 1.

FIG. 6 is a diagram showing the relationship between the sheet carrier concentration of the RESURF layer 16 and the breakdown voltage. In FIG. 6, the carrier concentration of the n-type substrate or the substrate 1 is calculated as 1 × 10 ¹³ cm ⁻³ . As shown in FIG. 6, the sheet carrier concentration of the RESURF layer 16 is in the range of 1 × 10 ¹² or more and 2.5 × 10 ¹² cm ⁻² or less with an optimum value of 2 × 10 ¹² cm ⁻² as a peak. The breakdown voltage was higher in the case of the substrate 1 which was a p-type substrate than in the case of an n-type substrate. Further, regarding the margin of carrier concentration of the RESURF layer 16 when a breakdown voltage of 550 V or higher is achieved, the margin M1 in the case of the substrate 1 is larger than the margin M2 in the case of the n-type substrate.

  As shown in FIGS. 5 and 6, the field effect transistor 200 according to the second embodiment having a p-type substrate has a high breakdown voltage. Further, for example, when the field effect transistor 200 has a breakdown voltage comparable to that of an n-type substrate, the width between the gate electrode 19 and the drain electrode 10 can be shortened, so that the resistance between the gate and the drain can be lowered. A further low on-resistance can be realized. In the case of the field effect transistor 200, since the margin of the carrier concentration of the RESURF layer 16 when achieving a predetermined breakdown voltage is large, manufacturability and design freedom are increased.

  The carrier concentration of the substrate 1 at which the breakdown voltage is maximized also depends on the thicknesses and carrier concentrations of the p-type semiconductor layer 14 and the RESURF layer 16. Therefore, for example, it is preferable to design the p-type semiconductor layer 14 and the RESURF layer 16 according to a desired threshold voltage, on-resistance, etc., and to determine the carrier concentration of the substrate 1 according to this.

(Embodiment 3)
Next, a third embodiment of the present invention will be described. FIG. 7 is a schematic cross-sectional view of the field effect transistor according to the third embodiment. As shown in FIG. 7, the field effect transistor 300 is formed on a substrate 1 having a p-type conductivity and an AlN layer 2 on the substrate 1 in the same manner as the field effect transistor 100 shown in FIG. The high-resistance buffer layer 3 and the semiconductor operation layer 20 formed on the high-resistance buffer layer 3 are provided. The semiconductor operation layer 20 includes a p-type semiconductor layer 21 made of p-GaN, carrier running layers 22 and 23 made of undoped GaN, and a carrier supply layer 24 made of AlGaN formed on the carrier running layers 22 and 23, respectively. , 25, and the recess 26 is formed between the carrier supply layer 24 and the carrier supply layer 25 to a depth reaching the surface of the p-type semiconductor layer 21. Further, the field effect transistor 300 includes a source electrode 9 and a drain electrode 10 formed on the semiconductor operation layer 20 with the recess 26 interposed therebetween. The field effect transistor 300 further includes a gate insulating film 27 formed over the semiconductor operation layer 20 including the recess 26 and a gate electrode 28 formed on the gate insulating film 27 in the recess 26.

  Since the carrier supply layers 24 and 25 have higher band gap energy than the carrier traveling layers 22 and 23, the two-dimensional electron gas 22a is present in the vicinity of the heterojunction interface between the carrier traveling layers 22 and 23 and the carrier supply layers 24 and 25. , 23a are generated. The field effect transistor 300 realizes a low on-resistance and a high-speed switching operation by using the two-dimensional electron gases 22a and 23a as carriers.

  Further, the formation of the recess portion 26 causes the field effect transistor 300 to operate as a normally-off type. Further, similarly to the field effect transistor 200 shown in FIG. 4, the inclination angle of each side wall of the recess portion 26 with respect to the surface of the p-type semiconductor layer 21 is, for example, 90 °, but less than 90 °, or even 65 ° or less. Is preferably 30 ° or more.

  In the field effect transistor 300, the p-type semiconductor layer 21 and the carrier traveling layer 23 form a RESURF structure R3 in which the p-type semiconductor layer 21 is disposed on the substrate 1 side. In the RESURF structure R3, the n-type carrier is a two-dimensional electron gas 23a. As a result, in a state where a voltage is applied between the source and drain, the lines of electric force extend from the carrier traveling layer 23 side through the p-type semiconductor layer 21 toward the substrate 1 side without a large bend as in FIG. The electric field concentration does not occur, and the field effect transistor 300 has high withstand voltage.

This field effect transistor 300 can be manufactured by a method substantially similar to the method for manufacturing the field effect transistor 200 described above. The carrier running layers 22 and 23 have a thickness of 100 nm, for example. Further, when forming the AlGaN layers to be the carrier supply layers 24 and 25, for example, TMAl, TMGa, and NH ₃ are introduced at flow rates of 125 μmol / min, 19 μmol / min, and 12 l / min, respectively, and at the same time, n-type A predetermined amount of SiH ₄ is introduced as a doping source, and epitaxial growth is performed at a growth temperature of 1050 ° C., for example, by a thickness of 100 nm.

In the above embodiment, the high resistance buffer layer is formed by alternately laminating GaN layers and AlN layers, for example, as long as it has a resistivity of about 1 × 10 ⁵ Ωcm or more. There is no particular limitation. For example, the chemical formula _{Al x In y Ga 1-xy} As u P v N 1-uv ( although, 0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1,0 ≦ u ≦ 1,0 ≦ v ≦ 1, It can be made of a nitride compound semiconductor represented by u + v <1), in which layers having different compositions are alternately stacked.

  In addition, the semiconductor operation layer in the above embodiment is not limited to GaN or AlGaN, and can be a nitride compound semiconductor having a desired conductivity type and band gap energy.

  Further, the material of the semiconductor operation layer is not limited to the nitride compound semiconductor, but may be other semiconductor materials such as a silicon semiconductor. For example, it can be used for a lateral electronic device created on an SOI substrate, a lateral electronic device on SiC, or the like.

DESCRIPTION OF SYMBOLS 1, 1a Substrate 2 AlN layer 3 High resistance buffer layer 4, 13, 20 Semiconductor operation layer 5, 14, 21 P-type semiconductor layer 6, 7 Contact layer 8 RESURF layer 9 Source electrode 10 Drain electrode 11, 18, 27 Gate insulation Film 12, 19, 28 Gate electrode 15 N-type semiconductor layer 16 Resurf layer 17, 26 Recessed portion 22, 23 Carrier traveling layer 22a, 23a Two-dimensional electron gas 24, 25 Carrier supply layer 100, 100a, 200, 300 Field effect transistor A1, A2 region C1 p-type carrier C2 n-type carrier L electric field lines M1, M2 margins R1-R3 RESURF structure W1-W3 width θ1, θ2 angle

Claims (6)

a silicon substrate having a p-type conductivity,
A high resistance layer made of a nitride compound semiconductor formed on the silicon substrate;
A semiconductor operating layer made of a nitride compound semiconductor having a RESURF structure formed on the high resistance layer and having a p-type semiconductor layer having a p-type conductivity disposed on the silicon substrate side;
A source electrode, a drain electrode, and a gate electrode formed on the semiconductor operation layer;
Wherein the silicon substrate is a field effect transistor having a carrier concentration and wherein the ^-3 der Rukoto ^{1 × 10 14 ~1 × 10 16} cm. The silicon substrate has a carrier concentration of 1 × 10 ¹⁴ ~ 1x10 ¹⁵ cm ^-3 The field effect transistor according to claim 1, wherein The RESURF layer has a sheet carrier concentration of 1 × 10 ¹² ~ 2.5 × 10 ¹² cm ^-2 The field effect transistor according to claim 1 or 2, wherein The semiconductor operation layer includes an n-type resurf layer formed on the p-type semiconductor layer, and the p-type semiconductor layer and the resurf layer form the resurf structure. The field effect transistor according to any one of claims 1 to 3, wherein The semiconductor operation layer includes an undoped carrier traveling layer formed on the p-type semiconductor layer, and a carrier supply layer formed on the carrier traveling layer and having a band gap energy different from that of the carrier traveling layer, p-type semiconductor layer and the carrier transit layer, the field-effect transistor according to any one of claims 1-3, characterized in that forming the RESURF structure. Field effect transistor according to claim 4, before Symbol p-type semiconductor layer and the RESURF layer cite claim 3, characterized in that it consists G aN.

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