JP2011171440A - Group iii nitride-based hetero field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride-based hetero field-effect transistor that has low resistance against electron transfer during ON-operation, and in which gate leakage current of a gate electrode and two-dimensional electron gas is hard to occur during OFF-operation. <P>SOLUTION: The group III nitride-based hetero field-effect transistor includes a substrate, a carrier transit layer arranged on the substrate, a barrier layer installed on the carrier transit layer to form a hetero interface, a recess structure dug to the inside of the carrier transit layer from a part on the barrier layer, an insulating layer disposed on the recess structure and the gate electrode arranged on the insulating layer. The carrier transit layer and the barrier layer consist of group III nitride semiconductor. The insulating layer includes side insulating layers formed on sides of the recess structure and a bottom insulating layer formed on the bottom of the recess structure. The side insulating layer is thicker than the bottom insulating layer. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a group III nitride hetero field effect transistor, and more particularly to a group III nitride hetero field effect transistor using a nitride semiconductor.

  Group III nitride semiconductors typified by GaN, AlGaN, InGaN, and the like are materials that can improve characteristics such as high breakdown voltage, high speed operation, high heat resistance, and low on-resistance when used in electronic devices. For this reason, group III nitride semiconductors have been attempted to be used in electronic devices as a semiconductor material that replaces conventional Si.

  For example, group III nitride hetero-field effect transistors (HFETs) using group III nitride semiconductors are expected to be applied to high-efficiency power conversion devices and high-frequency power devices.

  Generally, in a group III nitride HFET, a GaN layer and an AlGaN layer are stacked and used. By laminating the GaN layer and the AlGaN layer, spontaneous polarization and piezoelectric polarization can be generated between the two layers, and a polarization electric field is generated due to these. Due to the effect of this polarization electric field, a high-concentration two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is formed in the vicinity of the interface between the GaN layer and the AlGaN layer. Here, by forming 2DEG, the resistance of the carrier during the on-operation of the device can be reduced.

  On the other hand, in order to use a group III nitride HFET as a switching element for large voltage / high power, the source electrode and drain electrode of the group III nitride HFET are turned off in a state where no voltage is applied to the gate electrode. It is necessary to use a so-called normally-off type in which no current flows between the two. For example, Patent Document 1 discloses a normally-off group III nitride HFET. A group III nitride HFET disclosed in Patent Document 1 will be described with reference to the drawings.

FIG. 13 is a schematic cross-sectional view showing an example of a conventional group III nitride hetero-field effect transistor. As shown in FIG. 13, a conventional group III nitride hetero-field effect transistor 111 has a buffer layer (not shown) made of a multiple nitride layer of an undoped AlN layer and an undoped GaN layer on a substrate 112 made of Si. A nitride semiconductor layer 113 made of p-type GaN, a carrier traveling layer 114 made of undoped GaN, and a barrier layer 115 made of undoped AlN, undoped Al _0.3 Ga _0.7 N, and undoped GaN. ing.

  A recess structure 125 is formed by digging from a part on the barrier layer 115 to a partial depth of the carrier traveling layer 114, and the source electrode 120 is formed on a part of the upper surface of the barrier layer 115 other than the recess structure 125. And a drain electrode 121 are provided. Further, the surface of the barrier layer 115 other than the source electrode 120 and the drain electrode 121 is covered with an insulating layer 141.

  A gate electrode 122 is formed on the insulating layer 141 on the inner surface of the recess structure 125. In this structure, the 2DEG 116 is formed at the interface between the carrier traveling layer 114 and the barrier layer 115, so that the resistance during the on operation can be kept low.

JP 2009-200096 A

  As described above, the Group III nitride semiconductor HFET 111 of Patent Document 1 has the advantage of low resistance during on-operation, while the side surface portion of the insulating layer 141 is in direct contact with the 2DEG 116, and thus the voltage applied to the gate electrode 122. Is 0, that is, when the group III nitride semiconductor HFET 111 is turned off, a gate leakage current tends to flow from the 2DEG 116 in the lateral direction of the recess structure 125 to the gate electrode 122. Here, the “gate leakage current” refers to a tunnel current that flows mainly because the insulating layer 141 is thin and a leak current that flows through defects formed inside the insulating layer 141.

  Moreover, the insulating layer 141 is often formed by a sputtering method or a CVD method. When the insulating layer 141 is formed by these film forming methods, the thickness of the insulating layer 141 on the side surface of the recess structure 125 is reduced. There is a tendency to be thinner than the thickness of the insulating layer 141 on the bottom surface of the structure 125, which facilitates the generation of a gate leakage current during the off operation, and makes it difficult to solve the above problem.

  The present invention has been made in view of such a current situation, and is a group III nitride hetero-field effect transistor that has low resistance to electron transfer during on operation and suppresses leakage current from the gate electrode during off operation. The purpose is to provide.

  The group III nitride hetero-field effect transistor of the present invention includes a substrate, a carrier traveling layer provided on the substrate, a barrier layer provided on the carrier traveling layer so as to form a heterointerface, A recess structure dug from a part on the barrier layer to the inside of the carrier travel layer, an insulating layer provided on the recess structure, and a gate electrode provided on the insulating layer, Each of the barrier layers is made of a group III nitride semiconductor, and the insulating layer includes a side surface insulating layer formed on the side surface of the recess structure and a bottom surface insulating layer formed on the bottom surface of the recess structure. The thickness of the layer is greater than the thickness of the bottom insulating layer.

Such an insulating _{layer, SiO 2, Si 3 N 4} , TiO 2, HfO 2, HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrAlO, ZrAlON, ZrSiO, ZrSiON, HfZrSiON, HfZrAlON, MgF 2, CaF 2, It is preferable to include one or more materials selected from the group consisting of SrF ₂ , BaF ₂ , Al ₂ O ₃ , AlON, Ta ₂ O ₅ , ZnO, MgO, CaO, LaAlO ₂ and LaAlO ₃ .

  When the thickness of the bottom insulating layer is T and the thickness of the side insulating layer is S, it is preferable that 1.05 ≦ S / T ≦ 2.

  The group III nitride hetero-field effect transistor of the present invention has the above-described configurations, so that the resistance of electron transfer is low during the on operation, and the gate leakage current from the two-dimensional electron gas to the gate electrode during the off operation. It has the effect that it is hard to generate | occur | produce.

It is typical sectional drawing which shows an example of the group III nitride type | system | group hetero field effect transistor of this invention. It is typical sectional drawing which shows an example of the group III nitride type | system | group hetero field effect transistor of this invention. It is typical sectional drawing which shows the state after forming the nitride laminated body on a board | substrate. It is typical sectional drawing which shows the state after forming an insulating layer and a 1st resist on the nitride laminated body. It is typical sectional drawing which shows the state after forming a recess structure in the nitride laminated body. It is typical sectional drawing which shows the state after forming a 2nd resist only in a part of barrier layer. It is typical sectional drawing which shows the state after forming an insulating layer on a recess structure and a part of barrier layer. It is typical sectional drawing which shows the state after forming a 3rd resist on an insulating layer. It is typical sectional drawing which shows the state after forming an insulating layer on the upper surface of a barrier layer. It is typical sectional drawing which shows the state after forming a 4th resist on an insulating layer. It is typical sectional drawing which shows the state after forming a side surface insulating layer in the side surface of a recess structure. It is typical sectional drawing which shows the state after forming a source electrode and a drain electrode. It is typical sectional drawing which shows an example of the conventional group III nitride type | system | group hetero field effect transistor.

  Hereinafter, the group III nitride semiconductor HFET of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description. In the drawings of the present application, the same reference numerals represent the same or corresponding parts. In addition, dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings, and do not represent actual dimensional relationships.

The group III nitride semiconductor HFET used in the present invention has B _v Al _w Ga _x In _y Tl _z N (0 ≦ v ≦ 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, v + w + x + y + z = 1). Here, B represents boron, Al represents aluminum, Ga represents gallium, In represents indium, Tl represents thallium, and N represents nitrogen. Further, v represents the content ratio of boron, w represents the content ratio of aluminum, x represents the content ratio of gallium, y represents the content ratio of indium, and z represents the content ratio of thallium. In this specification, for example, a nitride semiconductor layer made of a nitride semiconductor crystal represented by the formula of Al _w Ga _x N (0 <w <1, 0 <x <1, w + x = 1) is referred to as “ It may be abbreviated as “AlGaN layer”.

(Embodiment 1)
<III-nitride hetero-field effect transistor>
FIG. 1 is a schematic cross-sectional view of a group III nitride hetero-field effect transistor according to the present embodiment. In the group III nitride hetero-field effect transistor 11 of the present embodiment, as shown in FIG. 1, a nitride semiconductor layer 13 is formed on a substrate 12, and a carrier is formed on the nitride semiconductor layer 13. The traveling layer 14 and the barrier layer 15 are epitaxial wafers laminated in this order.

  The nitride semiconductor layer 13, the carrier traveling layer 14, and the barrier layer 15 are collectively referred to as a nitride stacked body 30, and the interface between the carrier traveling layer 14 and the barrier layer 15 is referred to as a heterojunction interface. Here, the composition of the carrier traveling layer 14 and the barrier layer 15 is adjusted, and the two-dimensional electron gas 16 is generated by the effect of polarization electrolysis.

  Further, the source electrode 20 and the drain electrode 21 are provided in contact with the upper surface of the barrier layer 15 so as to make ohmic contact with the barrier layer 15. A part of the nitride laminate 30 between the source electrode 20 and the drain electrode 21 has a region where a part of the carrier traveling layer 14 and the barrier layer 15 are not formed. This region is referred to as a recess structure 25. Then, an insulating layer is formed on the upper surface and side wall surface of the recess structure 25 and the upper surface of the barrier layer 15. In particular, the gate electrode 22 is formed on the insulating layer of the recess structure 25.

  Here, the insulating layer formed on the bottom surface of the recess structure 25 is referred to as a bottom surface insulating layer 41, and the insulating layers formed on the side surfaces of the recess structure 25 are referred to as side surface insulating layers 43 and 44. The group III nitride hetero field effect transistor 11 of the present embodiment is characterized in that the total thickness of the side insulating layers 43 and 44 is larger than the thickness of the bottom insulating layer 41 of the recess structure 25.

  Thus, since the total thickness of the side insulating layers 43 and 44 is thicker than the thickness of the bottom insulating layer 41, the resistance of the current channel at the bottom surface of the recess structure is reduced during the on operation, and the two-dimensional electron gas 16 is reduced during the off operation. It is possible to make it difficult to generate a gate leakage current from the gate electrode 22 to the gate electrode 22.

  In the following, the operation of the group III nitride hetero-field effect transistor of the present embodiment will be described.

<Operation of Group III Nitride Hetero Field Effect Transistor>
In the group III nitride hetero-field effect transistor of the present embodiment, the two-dimensional electron gas 16 on the source electrode 20 side and the two-dimensional electron gas 16 on the drain electrode 21 side are separated by a recess structure 25. It is a normally-off type field effect transistor. For this reason, in a state where no voltage is applied to the gate electrode 22 or in a state where 0 V is applied, even if a voltage is applied between the source electrode 20 and the drain electrode 21, no current flows through the channel. .

  On the other hand, when a positive voltage is applied to the gate electrode 22, electrons are accumulated in the carrier traveling layer 14 in contact with the bottom insulating layer 41 and the side insulating layers 43 and 44. The two-dimensional electron gas 16 on the source electrode 20 side and the two-dimensional electron gas 16 on the drain electrode 21 side are electrically connected by the electrons. When a voltage is applied to the source electrode 20 and the drain electrode 21 in this state, a current flows through the channel and an on operation occurs.

  Below, each part which comprises the group III nitride type | system | group hetero field effect transistor of this Embodiment is demonstrated.

<Board>
In the present embodiment, the substrate 12 may be a conventionally known substrate as long as it is a substrate 12 used for a field effect transistor. Examples of the material of the substrate 12 include Si, GaN, SiC, AlN, GaAs, and ZnO. When Si is used as the substrate 12, a high resistance Si substrate is preferably used.

<Nitride semiconductor layer>
In the present embodiment, nitride semiconductor layer 13 is preferably provided between substrate 12 and carrier travel layer 14. By providing the nitride semiconductor layer 13 in this manner, distortion of the crystal lattice of the substrate 12 and the crystal lattice of the carrier traveling layer 14 can be relaxed. Note that if the crystal lattice of the substrate 12 and the crystal lattice of the carrier traveling layer 14 are hardly distorted, the nitride semiconductor layer 13 may not be formed.

  Such a nitride semiconductor layer 13 may be either a single layer or a plurality of layers. When the nitride semiconductor layer 13 is a single layer, for example, AlN, GaN, AlGaN or the like can be used as the material. On the other hand, when the nitride semiconductor layer 13 is a plurality of layers, an AlN / GaN multilayer, an AlGaN / GaN multilayer, or the like can be used for the nitride semiconductor layer 13. The nitride semiconductor layer 13 is preferably a multiple layer in which a thick undoped GaN layer is stacked on a thin undoped AlN layer. Note that the expression “GaN / AlN” indicates that the upper surface is GaN and the lower surface is AlN.

In the group III nitride hetero-field effect transistor of the present embodiment, as the nitride semiconductor layer 13, it is preferable to use an undoped or doped nitride semiconductor such as GaN, AlGaN, InGaN, AlInN, AlGaInN, It is more preferable that In _1-x Ga _x N (0 <x ≦ 1).

<Carrier travel layer>
In the present embodiment, the carrier traveling layer 14 may be either a single layer or a multilayer nitride semiconductor layer. When the carrier traveling layer 14 is composed of a single nitride semiconductor layer, undoped AlGaN or doped AlGaN, AlInN, AlGaInN, or the like may be used.

On the other hand, when the carrier traveling layer 14 is formed of a multilayer nitride semiconductor layer, a multiple AlGaN layer including a plurality of AlGaN layers having different Al composition ratios and doping concentrations, GaN / Al _0.25 Ga _0.75 N / AlN, GaN / AlGaN, InGaN / AlGaN, InGaN / AlGaN / AlN, etc. may be used. It should be noted that other doped nitride semiconductor layers can be used for each layer constituting the multilayer nitride semiconductor layer.

<Barrier layer>
In the present embodiment, it is preferable that barrier layer 15 has a wider forbidden band width than that of nitride semiconductor layer 13 and carrier traveling layer 14. As a material of the barrier layer 15, undoped or doped nitride semiconductor such as GaN, AlGaN, InGaN, AlInN, AlGaInN, or the like can be used.

<Recess structure>
In the present embodiment, the recess structure 25 corresponds to a portion of the nitride laminate 30 where the barrier layer 15 and the carrier traveling layer 14 are not formed. In FIG. 1, the side surface of the recess structure 25 is inclined with respect to the surface of the carrier traveling layer 14. However, the side surface of the recess structure 25 is not limited to such a form. It may be perpendicular to the surface of the layer 14.

<Insulating layer>
In the present embodiment, as shown in FIG. 1, the insulating layers are a bottom surface insulating layer 41 formed on the bottom surface of the recess structure 25 and side surface insulating layers 43 and 44 formed on the side walls of the recess structure 25. And an insulating layer formed on the barrier layer 15. The bottom insulating layer 41 and the side insulating layers 43 and 44 form a MIS capacitor structure between the carrier traveling layer 14 and the barrier layer 15 (hereinafter, these two layers are also referred to as “semiconductor layer”) and the gate electrode 22. It is provided to generate a charge in the semiconductor layer when a positive gate voltage is applied, thereby forming a current channel. The insulating layer formed on the barrier layer 15 is provided for protecting the device surface and for suppressing the current collapse phenomenon which is a problem particularly in the group III nitride HFET.

  And the thickness of the side surface insulating layers 43 and 44 is characterized by being thicker than the thickness of the bottom surface insulating layer 41. Since the side insulating layers 43 and 44 are thick, the gate leakage current from the two-dimensional electron gas 16 to the gate electrode 22 can be suppressed during the off operation.

  The thickness of the bottom insulating layer 41 described above is preferably set to an appropriate thickness in consideration of resistance control during the on operation and insulation resistance during the on operation. The thickness of the bottom insulating layer 41 is preferably 1 nm or more and 500 nm or less, more preferably 2.5 nm or more and 100 nm or less. If the thickness of the bottom insulating layer 41 exceeds 500 nm, the on-resistance of the channel increases because the density of charges generated in the gate channel portion of the bottom surface of the recess structure 25 at the time of the on operation decreases, which is not preferable. On the other hand, if the thickness of the bottom insulating layer 41 is less than 1 nm, the insulation as the gate insulating film is not sufficiently secured, which is not preferable.

  On the other hand, the thickness of the side insulating layers 43 and 44 may be set to be thicker than that of the bottom insulating layer so that a leak gate current is not generated from the side surface of the recess structure 25 where the electric field concentrates during the off operation.

  The insulating layer formed on the inner surface of the recess structure 25 is preferably a material having a high dielectric constant. By using a material having a high dielectric constant, the electric resistance of the current channel formed inside the carrier traveling layer 14 in contact with the gate electrode 22 can be reduced, and the resistance during the on-operation can be reduced. .

  Here, when the thickness of the bottom insulating layer 41 is T and the thickness of the side insulating layers 43 and 44 is S, it is preferable that 1.05 ≦ S / T ≦ 2. Such thicknesses of the bottom surface insulating layer 41 and the side surface insulating layers 43 and 44 can remarkably obtain the effect of reducing the resistance of electron transfer when turned on and suppressing the generation of gate leakage current when turned off. More preferably, 1.1 ≦ S / T ≦ 1.5.

  FIG. 2 is a schematic cross-sectional view showing another embodiment of the group III nitride hetero-field effect transistor of the present invention. In FIG. 1, for convenience of explanation, the bottom insulating layer 41, the insulating layer 42, and the side insulating layers 43 and 44 are depicted so as to have boundaries dividing them. As shown in FIG. 2, each insulating layer may not be divided. That is, for example, when the bottom and side surfaces of the recess structure 25 and the insulating layer formed on the barrier layer 15 are all the same material, the boundary between the insulating layers 40 is clear as shown in FIG. You don't have to.

Such an insulating layer is preferably made of a material having a high dielectric constant from the viewpoint of accumulating a large amount of electrons on the bottom surface of the recess structure 25. That is, the material used for the insulating layer is SiO ₂ , Si ₃ N ₄ , TiO ₂ , HfO ₂ , HfAlO, HfAlON, HfSiO, HfSiON, ZrO ₂ , ZrAlO, ZrAlON, ZrSiO, ZrSiON, HfZrSiON, HfZrAlON, MgF ₂ , CaF. ₂ , one or more materials selected from the group consisting of SrF ₂ , BaF ₂ , Al ₂ O ₃ , AlON, Ta ₂ O ₅ , ZnO, MgO, CaO, LaAlO ₂ , and LaAlO ₃ are preferably included.

The bottom surface insulating layer 41 and the side surface insulating layers 43 and 44 may be made of the same material or different materials. Among the materials constituting the insulating layer, it is preferable to select materials according to the needs of each element, such as current collapse suppression effect, thermal stability, chemical stability, current leakage resistance, etc. Suitable materials for the layer include HfO ₂ , HfAlO, HfAlON, HfSiO, HfSiON, ZrO ₂ , ZrAlO, ZrAlON, ZrSiO, ZrSiON, HfZrSiON, HfZrAlON, Ta ₂ O _{5 and the} like.

Further, the configuration of the insulating layer is not limited to a single layer, and may be composed of a plurality of parts. When the insulating layer has a plurality of portions, a configuration such as SiN _x / SiO ₂ , SiO ₂ / SiN _x , SiN _x / SiO ₂ / SiN _x can be used. In addition, the notation “SiO ₂ / SiN _x ” indicates that the side in contact with the carrier traveling layer 14 is SiO ₂ and the side in contact with the recess structure 25 is SiN _x . As described above, when the insulating layer is made of SiO ₂ / SiN _{x, the} collapse phenomenon can be suppressed by the insulating layer in contact with the recess structure 25, and higher electron mobility can be obtained.

  In the case where an insulating layer including a plurality of parts is formed, it is preferable to perform heat treatment at a high temperature of 800 ° C. to 1200 ° C. after the insulating layer is formed. By performing the heat treatment at such a high temperature, the layers constituting the insulating layer can be integrated. This eliminates the contact surface of each layer that is the source of charge trapping, and makes it difficult for hysteresis to occur in the characteristics of the gate electrode 22.

<Source electrode, drain electrode>
In the present embodiment, the source electrode 20 and the drain electrode 21 are ohmic electrodes that are in ohmic contact with the barrier layer 15, and preferably both are formed of a single layer or a multilayer metal layer. Examples of the electrode material used for the source electrode 20 and the drain electrode 21 include Hf / Al / Hf / Au, Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x. Etc.

<Gate electrode>
In the present embodiment, the gate electrode 22 is a Schottky electrode that controls the concentration of electrons at the interface between the insulating layer and the carrier traveling layer 14. By adjusting the bias voltage applied to the gate electrode 22, the concentration of electrons at the interface between the insulating layer and the carrier traveling layer 14 can be controlled, and the channel formation can be controlled. Examples of the metal material used for the gate electrode 22 include Ti / Al, Ni / Au, Ti / Au, Pt / Au, Ni / Au, W, WN _x , and WSi _x .

(Production method)
The group III nitride hetero-field effect transistor of the present embodiment can be manufactured as follows.

  FIG. 3 is a schematic cross-sectional view showing a state after the first nitride semiconductor layer is formed on the substrate. In the present embodiment, as shown in FIG. 3, nitride laminate 30 is formed by laminating nitride semiconductor layer 13, carrier traveling layer 14, and barrier layer 15 in this order on substrate 12.

Methods for forming the nitride stack 30 include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and halide vapor deposition (HVPE). It is preferable to use a phase epitaxy method or the like. When the nitride laminate 30 is formed using the MOCVD method, it is preferable to introduce trimethylgallium (TMG), trimethylammonium (TMA), ammonia (NH ₃ ), or the like into the MOCVD apparatus.

  FIG. 4 is a schematic cross-sectional view showing a state after the first resist is formed on the nitride laminate. A first resist 51 is formed on the upper surface of the barrier layer 15 of the nitride laminate 30 obtained above in a portion other than the portion where the recess structure is formed.

  FIG. 5 is a schematic cross-sectional view showing a state after the recess structure is formed in the nitride laminate. Using the first resist 51 formed on the nitride laminate 30 as an etching mask, the thickness T1 of the nitride laminate 30 (that is, all of the barrier layer 15 and the carrier travel) is applied to the portion where the etching mask is not formed. The recess structure 25 is formed in the nitride laminate 30 by removing the upper part of the layer 14 by dry etching (FIG. 5). Then, after forming the recess structure 25, the first resist 51 is removed. Next, the upper surface and inner wall surface of the recess structure 25 and the upper surface of the barrier layer 15 are washed with sulfuric acid / hydrogen peroxide solution, and further washed with hydrochloric acid / hydrogen peroxide solution.

  FIG. 6 is a schematic cross-sectional view showing a state after the second resist is formed on only a part of the barrier layer. As shown in FIG. 6, a second resist 52 is formed on the upper surface of the barrier layer 15 cleaned as described above. Thereby, an insulating layer can be formed on the upper surface of the recess structure 25 and the barrier layer 15 in which the second resist 52 is not formed in a later step.

  FIG. 7 is a schematic cross-sectional view showing a state after an insulating layer is formed on a part of the recess structure and the barrier layer. An insulating layer 41 is formed on the barrier layer 15 and the recess structure 25 other than the second resist 52 formed as described above. Then, by lifting off the second resist 52, the insulating layer 41 is formed only on the recess structure 25 and part of the barrier layer 15 (FIG. 7).

  FIG. 8 is a schematic cross-sectional view showing a state after the third resist is formed on the insulating layer. As shown in FIG. 8, a third resist 53 is formed so as to cover the insulating layer 41. By forming the third resist 53 in this way, an insulating layer can be formed only in a portion where the barrier layer 15 is exposed in a later step (FIG. 8).

FIG. 9 is a schematic cross-sectional view showing a state after an insulating layer is formed on the upper surface of the barrier layer. FIG.
In this state, after the insulating layer 42 is formed on the portion of the upper surface of the barrier layer 15 that is not covered with the third resist 53, the third resist 53 is removed (FIG. 9). Examples of the method for forming the insulating layers 41 and 42 include a CVD method, an electron beam vacuum deposition method, and a vacuum sputtering method. In this way, the insulating layers 41 and 42 are formed on the recess structure 25 and the barrier layer 15.

  FIG. 10 is a schematic cross-sectional view showing a state after the fourth resist is formed on the insulating layer. Next, a fourth resist 54 is formed on the bottom surfaces of the barrier layer 15 and the recess structure 25. As shown in FIG. 10, by covering the portion of the recess structure 25 excluding the side wall with the fourth resist 54, the side insulating layer 44 can be further formed only on the side wall portion of the recess structure 25 in a later step.

  FIG. 11 is a schematic cross-sectional view showing a state after the side surface insulating layer is formed on the side surface of the recess structure. After the fourth resist is formed as shown in FIG. 10, a side insulating layer 44 is formed on the insulating layer 41 on the side surface of the recess structure 25 as shown in FIG. 11. In this way, the thickness of the side insulating layer can be made larger than the thickness of the bottom insulating layer.

  Next, it is preferable to perform a heat treatment to integrate the interface between the bottom insulating layer 41 and the side insulating layer 44. In this way, by adapting the bottom insulating layer 41 and the side insulating layer 44, charge trapping at the interface between them is eliminated, and hysteresis in the characteristics of the gate electrode 22 hardly occurs.

Here, the heat treatment temperature is preferably 800 ° C. or more and 1200 ° C. or less, and the atmosphere is preferably O ₂ , N ₂ , NO, NO _2, a mixed gas thereof, or the like. However, from the viewpoint of promoting integration of the bottom surface insulating layer 41 and the side surface insulating layer 44, it is more preferable to include O ₂ . The heat treatment time is preferably 3 minutes or more and 100 minutes or less. In addition, this heat treatment also has an effect of reducing the interface order of the surfaces in contact with the bottom surface insulating layer 41, the side surface insulating layer 44, and the nitride laminate 30.

  Then, a portion of the insulating layer 42 on the upper surface of the barrier layer where the source electrode and the drain electrode are formed is removed by a photolithography technique and an etching technique to form a contact region.

  FIG. 12 is a schematic cross-sectional view showing a state after forming the source electrode and the drain electrode. After performing the above annealing, as shown in FIG. 12, the source electrode 20 and the drain electrode 21 are formed on the contact region from which the insulating layer 42 on the barrier layer 15 is removed by using the photolithography technique and the EB evaporation method. Form.

  Then, ohmic contact is made between the source electrode 20 and the drain electrode 21 and the channel by alloying by heat treatment. The method of obtaining the ohmic contact is not limited to the method of alloying by heat treatment, but a method of forming an ohmic contact by a tunnel current mechanism, an n-type impurity such as Si in the contact region at a high concentration by ion implantation or the like. After doping, a method of forming the source electrode 20 and the drain electrode 21 in the contact region, the contact region is removed by etching from the surface of the barrier layer 15 to the inside of the carrier traveling layer 14, and the source electrode 20 and the drain on the etched surface A method of bringing the electrode 21 into contact can be used.

  Next, the gate electrode 22 made of, for example, Ni / Au is formed on the insulating layer 41 by using a photolithography technique and an EB vapor deposition method. Through the above steps, the group III nitride hetero-field effect transistor of the present embodiment as shown in FIG. 1 can be manufactured.

  The group III nitride hetero-field effect transistor shown in FIG. 1 was produced as follows.

In this embodiment, first, as shown in FIG. 3, a high resistance Si substrate 12 is prepared, and a metal organic chemical vapor deposition (MOCVD) method is formed on the high resistance Si substrate 12. The nitride semiconductor layer 13 made of AlN and GaN, the carrier traveling layer 14 made of i-GaN having a thickness of 100 nm, and the barrier layer 15 made of undoped Al _0.25 Ga _0.75 N having a thickness of 100 nm are formed in this order. did.

  Next, a first resist 51 was formed on the barrier layer 15 using a CVD method. Then, as shown in FIG. 4, the portion of the first resist 51 that becomes the recess structure 25 was removed using a photolithography technique.

  Next, as shown in FIG. 5, an ICP (Inductively Coupled Plasma) -RIE apparatus is applied to a portion of the barrier layer 15 where the first resist 51 is not formed, that is, a portion where the barrier layer 15 is exposed. The recess structure 25 was formed by removing the barrier layer 15 and the 50 nm thick portion from above the carrier traveling layer 14. Thereafter, the first resist 51 was removed.

Next, after cleaning the upper surface and inner wall surface of the recess structure 25 with sulfuric acid / hydrogen peroxide solution and further with hydrochloric acid / hydrogen peroxide solution, a second resist 52 is formed on the barrier layer 15 (FIG. 6). ). Then, an insulating layer 41 made of SiO _{2 having} a thickness of 30 nm is formed on the barrier layer 15 and the recess structure 25 not covered with the second resist 52 by using a plasma CVD method, and the second resist is removed (FIG. 7). ).

Thereafter, a third resist 53 was formed so as to cover the upper surface of the insulating layer 41 (FIG. 8). Then, after forming an insulating layer 42 made of Si ₃ N _{4 having} a thickness of 30 nm on the barrier layer 15 by using plasma CVD, the third resist 53 was removed (FIG. 9). Si ₃ N ₄ is effective in reducing the so-called current collapse, and can be suppressed by increasing the carrier resistance when turned on by being stacked on the surface of the barrier layer 15. Next, a fourth resist 54 was formed on the bottom surfaces of the barrier layer 15 and the recess structure 25 (FIG. 10).

In this way, the bottom insulating layers 41 and 42 are covered with the fourth resist, and the side insulating layer 44 made of SiO _{2 having} a thickness of 30 nm is formed on the insulating layer 41 on the inner wall surface of the recess structure 25 by plasma CVD. Formed (FIG. 11). Since the relative dielectric constant of SiO ₂ is relatively small as 3.9, a large amount of electrons are not accumulated at the interface between the bottom surface of the recess structure 25 and the insulating layer 41 when a constant voltage is applied to the gate electrode 22. The on-resistance can be reduced by keeping the mobility of the above high.

  After forming the side insulating layer 44 as described above, the insulating layer 41 and the side insulating layer 44 were heat-treated at 1000 ° C. for 60 minutes in an oxygen atmosphere. In this embodiment, in FIG. 1, since the material of the bottom insulating layer 41 and the side insulating layer 43 is the same, the boundary line separating these two layers is not clear.

  Then, the insulating layer 42 in the upper surface of the barrier layer 15 where the source electrode and the drain electrode are formed was removed by photolithography. Then, annealing was performed at 1000 ° C. in a nitrogen atmosphere, thereby reducing the interface state of the surface in contact with the insulating layer 42 and the nitride laminate 30.

  Thereafter, as shown in FIG. 12, the source electrode 20 having a stacked structure of Hf / Al / Hf / Au and the source electrode 20 are formed in the contact region of the barrier layer 15 using a photolithography technique and an EB deposition method. A drain electrode 21 having the same composition was formed. The source electrode 20 and the drain electrode 21 were in ohmic contact with the barrier layer 15 by performing heat treatment at 800 ° C. for 1 minute in a vacuum atmosphere.

  Next, the gate electrode 22 which is a Schottky electrode based on WN was formed on the bottom insulating layer 41 of the recess structure 25 by using a photolithography technique and an EB vapor deposition method. Through the above steps, the group III nitride hetero-field effect transistor of this example was fabricated.

  The group III nitride hetero-field effect transistor of Example 1 fabricated as described above is less susceptible to gate leakage current from the two-dimensional electron gas to the gate electrode even when the transistor is turned off. It was hard to deteriorate. This is considered to be effective because the thickness of the side surface insulating layer is larger than the thickness of the bottom surface insulating layer.

(Comparative Example 1)
For the Group III nitride hetero-field effect transistor of Example 1, the Group III nitride system of Comparative Example 1 was obtained in the same manner as in Example 1 except that the side insulating layer 44 was not formed. A terror field effect transistor was fabricated.

  The group III nitride hetero-field effect transistor of Comparative Example 1 produced in this way is prone to gate leakage current from the two-dimensional electron gas to the gate electrode when the transistor is off, and the device is likely to deteriorate. Met.

  As is apparent from the above description, the Group III nitride hetero-field effect transistor according to the present invention of Example 1 is in an off state as compared with the Group III nitride hetero-field effect transistor of Comparative Example 1. It is clear that the gate leakage current from the two-dimensional electron gas to the gate electrode is suppressed. From this, it was confirmed that the gate leakage current at the off time can be suppressed when the thickness of the side surface insulating layer is larger than the thickness of the bottom surface insulating layer.

  Although the embodiments and examples of the present invention have been described as described above, it is also planned from the beginning to appropriately combine the configurations of the above-described embodiments and examples.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention suppresses a gate leakage current from a recess structure when a two-dimensional carrier gas formed at an interface between a carrier transit layer and a barrier layer is applied to a semiconductor device that uses a current channel. Deterioration of characteristics can be suppressed. Examples of such semiconductor elements include HFETs and field effect diodes.

  11, 111 III-nitride hetero-field effect transistor, 12, 112 substrate, 13, 113 nitride semiconductor layer, 14, 114 carrier transit layer, 15, 115 barrier layer, 16, 116 two-dimensional electron gas, 20, 120 source electrode, 21, 121 drain electrode, 22, 122 gate electrode, 25, 125 recess structure, 30 nitride laminate, 40, 141 insulating layer, 41 bottom insulating layer, 42 insulating layer, 43, 44 side insulating layer, 51 1st resist, 52 2nd resist, 53 3rd resist, 54 4th resist.

Claims (3)

A substrate,
A carrier running layer provided on the substrate;
A barrier layer provided on the carrier traveling layer so as to form a heterointerface;
A recess structure dug from a part on the barrier layer to the inside of the carrier traveling layer;
An insulating layer provided on the recess structure;
A gate electrode provided on the insulating layer,
Both the carrier traveling layer and the barrier layer are made of a group III nitride semiconductor,
The insulating layer includes a side insulating layer formed on a side surface of the recess structure, and a bottom insulating layer formed on a bottom surface of the recess structure,
The group III nitride hetero field effect transistor, wherein the side insulating layer is thicker than the bottom insulating layer. The insulating _{layer, SiO 2, Si 3 N 4} , TiO 2, HfO 2, HfAlO, HfAlON, HfSiO, HfSiON, ZrO 2, ZrAlO, ZrAlON, ZrSiO, ZrSiON, HfZrSiON, HfZrAlON, MgF 2, CaF 2, SrF 2 _{3. The} group III according to claim 1, comprising one or more materials selected from the group consisting of BaF ₂ , Al ₂ O ₃ , AlON, Ta ₂ O ₅ , ZnO, MgO, CaO, LaAlO ₂ and LaAlO _3. Nitride hetero field effect transistor. When the thickness of the bottom insulating layer is T and the thickness of the side insulating layer is S,
The group III nitride hetero field effect transistor according to claim 1 or 2, wherein 1.05≤S / T≤2.

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