JP5361156B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a metal-encapsulated wafer level chip size package (CSP) and a manufacturing method thereof.

  In a conventional wafer level CSP, a multilayer wiring formed on a semiconductor substrate is resin-sealed using a resin insulating film such as polyimide or benzocyclobutene (BCB).

  However, since the water absorption of polyimide is high, saturated moisture may ooze out inside. Moreover, although the water absorption of BCB is low, the permeation | transmission of a water | moisture content may occur also in the interface of a metal and BCB and BCB itself. Moisture that permeates or permeates into these layers may cause corrosion of the multilayer wiring.

  Due to the problem of moisture resistance, a CSP sealed with a resin insulating film cannot be used for applications that require high reliability.

In order to improve moisture resistance, a semiconductor device has been proposed in which a metal film is formed on the upper surface and side surfaces of a resin insulating film and the resin insulating film is covered with the metal film (see, for example, Patent Document 1).
JP 2002-359257 A

  However, even when the resin insulating film is covered with a metal film as in the semiconductor device disclosed in Patent Document 1, for example, moisture may enter from the interface between the metal film and the semiconductor substrate.

  Further, in order to electrically connect the element formed on the front surface side of the semiconductor substrate to an external circuit, it is necessary to provide a through electrode in the substrate and provide a connection terminal for the external circuit on the back surface side. Here, when a silicon substrate is used as the substrate, each through electrode needs to be insulated from the surroundings.

  However, if the silicon substrate is thick, it is difficult to form a through electrode and a separation film that insulates the through electrode from the surroundings. This is because if the substrate is thick, the aspect ratio becomes large, so that an embedding defect is likely to occur. On the other hand, if the silicon substrate is simply made thinner, the mechanical strength becomes lower and handling after the film is made thinner becomes difficult.

  The present invention has been made in view of the above-mentioned problems, and the object of the present invention is to form the peripheral wiring so as to surround the chip, so that moisture entering from the interface between the metal film and the silicon substrate An object of the present invention is to provide a semiconductor device and a method for manufacturing the same which prevent an influence such as corrosion of an internal multilayer wiring and, as a result, further improve moisture resistance.

  In order to achieve the above-described object, the semiconductor device of the present invention has the following configuration.

A dicing area and a chip area defined by the dicing area are set in the semiconductor substrate .

An element is formed on the first main surface side which is one main surface of the semiconductor substrate.

A penetration separation portion is formed from the first main surface of the semiconductor substrate to the second main surface, which is the main surface opposite to the first main surface.

  A through electrode is formed in the through separation portion from the first main surface to the second main surface.

A wiring insulating film is formed on the first main surface of the semiconductor substrate. Then, that have chip line is formed on the wiring insulating film.

A metal film integrally formed on the upper surface and side surfaces of the wiring insulating film is provided, and the film thickness of the metal film is larger than that of the semiconductor substrate.

  The method for manufacturing a semiconductor device according to the present invention includes the following steps.

Next, the semiconductor base plate, forming the through isolation groove from the first major surface is one main surface toward the second major surface is opposite to the main surface of the first main surface.

Next, to form an oxide film to form a penetrating separation portion in the through isolation trench.

Next, an element is formed on the first main surface side of the semiconductor substrate.

Then, on the first main surface of the semiconductor substrate, forming a wiring insulating film covering the device, a step of forming a chip interconnection wiring insulating film, and forming the through electrode in the through isolation portion Do.

Next, a metal film having a thickness larger than that of the semiconductor substrate is formed so as to integrally cover the upper surface and side surfaces of the wiring insulating film.

  According to the semiconductor device of the present invention, since the peripheral wiring that surrounds the chip wiring is formed, the moisture resistance is further improved as compared with sealing with only the metal film.

  According to the method for manufacturing a semiconductor device of the present invention, since the peripheral wiring is formed in the same process as the internal chip wiring, it is possible to manufacture a semiconductor device with improved moisture resistance without increasing the number of processes. it can.

  Further, a metal film formed as a protective film can be used as a support. This metal film maintains the mechanical strength and ease of handling, so that the semiconductor substrate can be made thin. For this reason, the through isolation part and the through electrode may be exposed to the second main surface when the semiconductor substrate is thinned later, and the through isolation part and the through electrode can be formed with a low aspect ratio. . As a result, the risk of poor filling of the through electrode and the through separation portion is reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(Structure of Semiconductor Device of First Embodiment)
The structure of the semiconductor device of the first embodiment will be described with reference to FIG. FIG. 1 is a schematic diagram for explaining the semiconductor device of the first embodiment, and shows a cut end surface of a main part. This semiconductor device is a metal-sealed wafer level CSP.

  The semiconductor device 10 includes a semiconductor substrate 20, elements 40 a and 40 b, a through separation part 34, a through electrode 54 a, a wiring insulating film 100, a peripheral wiring 110, a chip wiring 120, and a metal film 80.

  A dicing area 28 and a chip area 22 defined by the dicing area 28 are set in the semiconductor substrate 20. The chip area 22 is an area that is a constituent unit of the CSP. The dicing area 28 is an area portion remaining around the chip area 22 when each chip is separated from the wafer.

  The chip region 22 has a central region 24 and a peripheral region 26 around the central region 24. The central region 24 is a region where a semiconductor element (hereinafter also simply referred to as an element) is formed.

  Here, an example will be described in which the semiconductor substrate 20 is a p-type silicon substrate and includes p-type MOS field effect transistor (PMOS) 40a and n-type MOS field effect transistor (NMOS) 40b as elements. In the following description, the PMOS 40a and the NMOS 40b may be collectively referred to as the element 40.

  The element 40 (40a, 40b) is formed in the central region 24 on the first main surface 20a side, which is one main surface of the semiconductor substrate 20. Here, the PMOS 40a is formed in the n-well 30, and the NMOS 40b is formed in a region where the n-well 30 is not formed.

  An element isolation film 32 is formed around the element 40. The element isolation film 32 may be formed by filling a groove with an oxide film by so-called trench isolation, or may be formed by a LOCOS method.

  An impurity diffusion layer 48 is provided on the first main surface 20 a side of the peripheral region 26 of the semiconductor substrate 20. This impurity diffusion layer 48 is implanted with the same impurity as the region functioning as the source or drain of the PMOS 40a or NMOS 40b.

  A through separation portion 34 is formed in the central region 24 of the semiconductor substrate 20. The through separation portion 34 is formed from the first main surface 20a to the second main surface 20b which is the main surface opposite to the first main surface 20a. Although a method for forming the through isolation portion 34 will be described later, it is formed by embedding an oxide film in the same manner as in the trench isolation.

  The through-electrode 54a is formed in the through-separation part 34 from the first main surface 20a to the second main surface 20b. The through electrode 54a can be formed in a multilayer wiring structure in the same manner as a conventionally known conductive plug for connecting between wirings, and is formed by, for example, filling the opening with tungsten.

  The wiring insulating film 100 is formed on the first main surface 20 a of the semiconductor substrate 20. Here, an example in which a first interlayer insulating film 50, a second interlayer insulating film 60, and an upper insulating film 70 are sequentially stacked as the wiring insulating film 100 will be described.

  A chip wiring 120 is provided in the central region 24 of the wiring insulating film 100. The chip wiring 120 includes a first layer wiring 58, a second layer wiring 68, a first layer conductive plug 52, a second layer conductive plug 62, and a through electrode plug 54b. The first layer wiring 58 is a wiring pattern formed on the first interlayer insulating film 50, and the second layer wiring 68 is a wiring pattern formed on the second interlayer insulating film 60. A plurality of first layer conductive plugs 52 are formed in the first interlayer insulating film 50 and electrically connect the element 40 and the first layer wiring 58. A plurality of through electrode plugs 54 b are formed in the first interlayer insulating film 50, and electrically connect the through electrode 54 a and the first layer wiring 58. In addition, a plurality of second layer conductive plugs 62 are formed in the second interlayer insulating film 60, and electrically connect the first layer wiring 58 and the second layer wiring 68.

  Here, the chip wiring 120 has been described as an example of the two-layer structure of the first layer wiring 58 and the second layer wiring 68 as a multilayer wiring structure, but the present invention is not limited to this example. The chip wiring 120 may be formed with one layer, or may be formed with three or more layers.

  The peripheral wiring 110 is formed in the peripheral region 26 of the wiring insulating film 100 so as to surround the central region 24 from the upper surface 100 a to the lower surface 100 b of the wiring insulating film 100. The peripheral wiring 110 includes a first layer peripheral wiring 59, a second layer peripheral wiring 69, a first layer peripheral plug 56, a second layer peripheral plug 66, and an upper layer peripheral plug 76.

  The first layer peripheral wiring 59 and the second layer peripheral wiring 69 are formed on the first interlayer insulating film 50 and the second interlayer insulating film 60, respectively. The first layer peripheral plug 56 is formed in the first interlayer insulating film 50 and electrically connects the impurity diffusion layer 48 and the first layer peripheral wiring 59. The second peripheral plug 66 is formed in the second interlayer insulating film 60 and electrically connects the first layer peripheral wiring 59 and the second layer peripheral wiring 69. The upper layer peripheral plug 76 is formed in the upper layer insulating film 70, and electrically connects the second layer peripheral wiring 69 and the metal film 80 formed on the wiring insulating film 100. The peripheral wiring 110 is formed on the impurity diffusion layer 48 in the peripheral region 26 and makes the potential of the metal film 80 equal to the substrate potential of the semiconductor substrate 20.

  The first layer peripheral plug 56, the second layer peripheral plug 66, the upper layer peripheral plug 76, the first layer peripheral wiring 59 and the second layer peripheral wiring 69 are continuously formed so as to surround the central region 24.

  Although a method of forming the wiring insulating film 100, the peripheral wiring 110, and the chip wiring 120 will be described later, these are formed by the same method and material as those of a conventionally known multilayer wiring structure.

  The metal film 80 is formed on the upper surface 100a and the side surface 100c so as to cover the entire wiring insulating film 100 by, for example, copper plating. The metal film 80 is formed from the side surface 100 c of the wiring insulating film 100 over the first main surface 20 a of the semiconductor substrate 20 in the dicing region 28. With this metal film 80, metal sealing is performed on the wiring insulating film 100 and the region of the semiconductor substrate 20 in contact with the wiring insulating film 100.

  A metal external terminal 90 is formed on the second main surface 54ab of the through electrode 54a. Since the first main surface 20a side of the semiconductor substrate 20 is metal-sealed, the connection between the element 40 and the outside is performed from the second main surface 20b which is the back surface through the through electrode 54a and the external terminal 90.

  According to the semiconductor device of the first embodiment, since the peripheral wiring 110 surrounding the chip wiring 120 is formed, even if moisture enters from the interface between the metal film 80 and the semiconductor substrate 20, the peripheral wiring 110 is formed in the peripheral region. Intrusion of moisture into the water can be prevented. Therefore, the moisture resistance of the semiconductor device of this embodiment is further improved as compared with the case of the semiconductor device sealed only with the metal film 80.

  Here, the thickness of the semiconductor substrate 20 is preferably about 10 μm at the maximum by the thinning process.

  The through separation part 34 and the through electrode 54a are formed before the semiconductor substrate 20 is thinned, but the depth of the through separation part 34 and the through electrode 54a may be larger than the thickness of the semiconductor substrate 20 after the thinning. Therefore, by setting the thickness of the semiconductor substrate 20 to 10 μm or less, the depth of the through separation part 34 and the through electrode 54a becomes about 10 μm, and the aspect ratio can be reduced. For this reason, generation | occurrence | production of embedding defect etc. can be suppressed and the reliability of an element increases.

  The thickness of the metal film 80 is preferably several tens to several hundreds of micrometers in order to maintain mechanical strength after the thin film of the semiconductor substrate. According to this configuration, even when the semiconductor substrate 20 is thin, the thickness of the metal film 80 is maintained by the thickness of the semiconductor device 10 as a whole, which is a CSP. For example, even if the thickness of the silicon substrate in the CSP, which was conventionally about 50 μm, is 10 μm, if the thickness of the metal film is 40 μm, the thickness of the entire CSP does not change. Is easy.

(Method for Manufacturing Semiconductor Device of First Embodiment)
With reference to FIGS. 2-6, the manufacturing method of the semiconductor device of 1st Embodiment is demonstrated. 2 to 6 are process diagrams for explaining the semiconductor device manufacturing method of the first embodiment.

  FIG. 2A is a schematic plan view of the semiconductor substrate 20. FIG. 2B shows a cut end surface taken along the line AA in FIG. FIGS. 3A, 3B, and 3C are views subsequent to FIG. 2B and show a cut end surface of a main part of the structure formed in each step. 4 (A) and 4 (B) are diagrams subsequent to FIG. 3 (C). 4A is a schematic plan view, and FIG. 4B shows a cut end surface taken along line BB in FIG. 4A. FIGS. 5 and 6 are views subsequent to FIG. 4B and showing a cut end surface of the main part of the structure formed in each step.

  First, the semiconductor substrate 20c is prepared. A dicing area 28 and a plurality of chip areas 22 defined by the dicing area 28 are set in the semiconductor substrate 20c. The chip region 22 has a central region 24 and a peripheral region 26 around the central region 24 (FIGS. 2A and 2B).

  After a semiconductor element and a wiring pattern are formed on the first main surface 20a of the semiconductor substrate 20c by the process described below, metal sealing is performed. Thereafter, dicing is performed along dicing lines set in the dicing area 28 between the chip areas 22 to obtain individual chips. As described above, the semiconductor device manufactured by the manufacturing method of this embodiment is a so-called wafer level CSP in which metal-sealed packaging is performed in a wafer state without cutting a chip.

  Here, an example in which a p-type silicon substrate is used as the semiconductor substrate 20c and PMOS and NMOS are formed as semiconductor elements will be described. Here, the thickness of the semiconductor substrate 20c is, for example, about several hundred μm. Since a method for forming PMOS and NMOS on a p-type silicon substrate is well known in the art, description thereof may be omitted in the following description.

  An n-type impurity is implanted to form an n-well 30 on the first major surface 20a side of the semiconductor substrate 20c. Here, the depth of the n-well 30 from the first major surface 20a is about 3 μm.

  Next, conventionally known photolithography and dry etching are performed on the central region 24 of the semiconductor substrate 20 from the first main surface 20a toward the second main surface 20b, which is the main surface opposite to the first main surface 20a. Thus, the element isolation trench 31 and the through isolation trench 33 are formed. Specifically, the following steps are performed. First, a mask that exposes a region where the element isolation trench 31 and the through isolation trench 33 are to be formed is formed. Next, the exposed portion of the semiconductor substrate 20c is removed by etching. Thereafter, a new mask is formed to expose the region where the through isolation trench 33 is to be formed, and the exposed portion of the semiconductor substrate 20c is removed by etching. Here, the element isolation trench 31 is formed to a depth of 2 μm, for example, which is shallower than the depth of the n-well. Further, the through isolation groove 33 is formed deeper than the element isolation groove 31, for example, to a depth of about 10 μm.

  Next, the element isolation trench 31 and the through isolation trench 33 are filled with an oxide film to form the element isolation film 32 and the through isolation portion 34. Specifically, for example, the following steps are performed.

  First, an oxide film is formed on the bottom and side surfaces of the element isolation trench 31 and the through isolation trench 33 by thermal oxidation. Next, an oxide film is deposited in the element isolation trench 31 and the through isolation trench 33 and on the first main surface 20a of the semiconductor substrate 20c by a chemical vapor deposition (CVD) method. Thereafter, for example, a planarization process is performed by a chemical mechanical polishing (CMP) method, and the element isolation trench 31 and the through isolation trench 33 are filled with an oxide film to obtain the element isolation film 32 and the through isolation portion 34. (FIG. 3 (A)).

  Here, an example has been described in which element isolation is performed by so-called trench isolation in which element isolation trenches (trench) 31 are filled with an oxide film, but the present invention is not limited to this example. For example, the element isolation film 32 may be formed by a well-known local oxidation of silicon (LOCOS) method. In this case, since the formation of the element isolation groove 31 is unnecessary, the through isolation groove 33 may be formed by a single etching process.

  Next, the element 40 is formed in the central region 24 on the first main surface 20a side of the semiconductor substrate 20c. Here, as the element 40, the PMOS 40a is formed in the n-well 30, and the NMOS 40b is formed in the region of the semiconductor substrate 20c where the n-well 30 is not formed. The formation of the PMOS 40a and the NMOS 40b may be performed by any conventionally known suitable method. For example, after laminating a silicon oxide film and a polysilicon film having a low resistance by implantation of impurities on the first main surface 20a in order, the silicon oxide film and the polysilicon film are patterned to form gate insulating films, respectively. 42a and 42b and gate electrodes 44a and 44b are processed. Further, impurity diffusion layers 46a and 46b functioning as a source and a drain are formed at positions sandwiching the gate electrodes 44a and 44b, respectively. Thereafter, after forming a metal film on the impurity diffusion layers 46a and 46b by sputtering, heat treatment is performed to silicide the surfaces of the impurity diffusion layers 46a and 46b on the first main surface 20a side.

  In the step of forming the element, the impurity diffusion layers 46a and 46b functioning as the source and drain are formed, and at the same time, the impurity diffusion layer 48 is formed on the peripheral region 26 on the first main surface 20a side of the semiconductor substrate 20c. It is formed (FIG. 3B).

  Next, the wiring insulating film 100, the peripheral wiring 110, and the chip wiring 120 are formed on the first main surface 20a of the semiconductor substrate 20c, and the through electrode 54a is formed in the through separation portion 34. The peripheral wiring 110 is formed in the peripheral region 26 of the wiring insulating film 100 from the upper surface 100 a to the lower surface 100 b of the wiring insulating film 100 and surrounds the central region 24. The chip wiring 120 is formed in the central region 24 of the wiring insulating film 100.

  Here, an example in which the chip wiring 120 has a two-layer structure will be described.

  First, the first interlayer insulating film 50 is formed on the first major surface 20a of the semiconductor substrate 20c. The first interlayer insulating film 50 is formed by depositing a silicon oxide film by, for example, a CVD method and then planarizing by a CMP method.

  Next, photolithography and dry etching are performed on the first interlayer insulating film 50 in the central region 24. By this etching, an element contact hole 51 exposing a part of the element 40 such as the PMOS 40a and the NMOS 40b is formed. FIG. 3C shows an element contact hole 51 that exposes the impurity diffusion layers 46a and 46b. In this step, a contact hole that exposes the gate electrodes 44a and 44b may also be formed, but the illustration is omitted here.

  At the same time as the formation of the element contact hole 51, the through electrode hole 53 is also formed. The through-electrode hole 53 is formed in the first interlayer insulating film 50 and the through-isolation part 34 and exposes the bottom 33 a of the through-isolation groove 33.

  Further, along with the formation of the element contact hole 51 and the through electrode hole 53, the first layer peripheral groove 55 exposing the first main surface 20a of the semiconductor substrate 20c is formed in the first interlayer insulating film 50 of the peripheral region 26. To do. The first layer peripheral groove 55 is continuously formed so as to surround the central region 24.

  The first interlayer insulating film 50 in the dicing region 28 is also removed during the etching for forming the element contact hole 51, the through-electrode hole 53, and the first layer peripheral groove 55.

  Next, a first layer conductive plug 52 is formed by embedding a conductor in the element contact hole 51. Further, the conductor 54 is embedded in the through-electrode hole 53 to form the through-electrode 54 a in the semiconductor substrate 20 c and the through-electrode plug 54 b in the first interlayer insulating film 50. Further, the first layer peripheral plug 56 is formed by embedding a conductor in the first layer peripheral groove 55. The formation of the first-layer conductive plug 52, the through-electrode plug 54b, the through-electrode 54a, and the first-layer peripheral plug 56 may be performed in the same manner as a conventionally known contact plug. For example, titanium nitride (TiN) and tungsten (W) are sequentially deposited by using the CVD method to fill the element contact hole 51, the through-electrode hole 53, and the first layer peripheral groove 55, and then perform the CMP method. By using and flattening, the first layer conductive plug 52, the through electrode plug 54b, the through electrode 54a, and the first layer peripheral plug 56 are formed (FIG. 3C).

  Next, a first layer wiring 58 is formed on the first interlayer insulating film 50. The first layer wiring 58 connects between the first layer conductive plugs 52 or between the first layer conductive plugs 52 and the through electrode plugs 54b. Further, a first layer peripheral wiring 59 surrounding the central region 24 is formed on the first layer peripheral plug 56. The first layer wiring 58 and the first layer peripheral wiring 59 are formed by forming a metal film on the first interlayer insulating film 50 by sputtering, for example, and then performing patterning. As a material of the first layer wiring 58 and the first layer peripheral wiring 59, any suitable material such as copper or aluminum alloy may be selected.

  Next, a second interlayer insulating film 60 that covers the first layer wiring 58 and the first layer peripheral wiring 59 is formed on the first interlayer insulating film 50. Next, photolithography and dry etching are performed on the second interlayer insulating film 60 to open a via hole 61 that exposes a portion of the first layer wiring 58 and a second layer that exposes the first layer peripheral wiring 59. A peripheral groove 65 is formed. The second layer peripheral groove 65 is continuously formed so as to surround the central region 24.

  As in the case of the first interlayer insulating film 50, the second interlayer insulating film 60 deposited in the dicing region 28 is also removed during the etching for forming the via hole 61 and the second layer peripheral groove 65.

  Next, the second layer conductive plug 62 and the second layer peripheral plug 66 are formed by filling the via hole 61 and the second layer peripheral groove 65, and then the second layer wiring 68 and the second layer wiring 68 are formed on the second interlayer insulating film 60. A two-layer peripheral wiring 69 is formed.

  Next, an upper insulating film 70 that covers the second layer wiring 68 and the second layer peripheral wiring 69 is formed on the second interlayer insulating film 60. Similarly to the first interlayer insulating film 50 and the second interlayer insulating film 60, the upper insulating film 70 can be a silicon oxide film formed by a CVD method. The upper insulating film 70 may be a resin insulating film formed by applying a resin such as polyimide.

  The first interlayer insulating film 50, the second interlayer insulating film 60, and the upper insulating film 70 are each formed with a thickness of several hundred nm.

  Although an example in which the chip wiring 120 has a two-layer structure has been described here, the present invention is not limited to this example. The chip wiring 120 may have a single-layer structure or an n-layer structure (n is an integer of 2 or more). In the case of a one-layer structure, an upper insulating film may be formed after the first layer wiring and the first layer peripheral wiring are formed. In the case of the n-layer structure, after forming the first layer wiring and the first layer peripheral wiring, the kth layer (k is an integer of 2 or more and n or less) insulating film, kth layer wiring, kth layer peripheral wiring. The k-th layer conductive plug and the k-th layer peripheral plug may be formed sequentially from k to 2 to n.

  Next, the upper insulating film 70 is etched to form an upper peripheral groove 75 that exposes the second peripheral wiring 69. At this time, the upper insulating film 70 deposited in the dicing region 28 is also removed.

  Next, an upper layer peripheral plug 76 may be formed by embedding a conductor in the upper layer peripheral groove 75 (FIGS. 4A and 4B), or in the step of forming the metal film 80 in the next step. Then, the metal film 80 may be embedded in the upper peripheral groove 75.

  Next, the metal film 80 is formed on the upper surface 100a and the side surface 100c of the wiring insulating film 100 configured to include the first interlayer insulating film 50, the second interlayer insulating film 60, and the upper layer insulating film 70. The metal film 80 is formed by any one of sputtering, plating and vapor deposition, or a combination thereof.

  The metal film 80 is also used as a support when the semiconductor substrate 20c is thinned in a later process. For this reason, the metal film 80 may be formed with a thickness that can maintain the mechanical strength of the wafer after the semiconductor substrate 20c is thinned, and is formed with a thickness of several tens of μm to several hundreds of μm. Further, if the thickness of the metal film 80 is 40 μm or more, it is convenient for handling at the time of mounting, for example, it can be easily held after being divided into individual chips (FIG. 5).

  Next, using the metal film 80 as a support, the semiconductor substrate 20 is ground from the second main surface 20b side, that is, mechanically polished, and thinned until the through electrode 54a is exposed. Note that, after grinding, for example, chemical etching (wet etching) using an etchant containing hydrofluoric acid and nitric acid may be performed.

  Here, since the depth of the through electrode 54a is 10 μm, the thickness of the semiconductor substrate 20 after thinning is set to 10 μm at the maximum. On the other hand, in order to control the potential of the semiconductor substrate 20 or the n-well 30, the thickness of the semiconductor substrate 20 after thinning is preferably set to 3 μm at least as a thickness at which the element isolation film 32 is not exposed (see FIG. 6).

  Next, the external terminal 90 is formed on the second main surface 54ab of the through electrode 54a.

  Thereafter, dicing is performed along the dicing line 29 (see FIG. 6) to divide each chip. As a result, the metal-sealed wafer level CSP described with reference to FIG. 1 is obtained.

  If the metal film 80 remains on the dicing line 29, the blade of the dicing apparatus may be clogged with metal powder generated during dicing. Therefore, before dicing, it is desirable to remove the portion of the metal film dicing region 28 along the dicing line 29 by, for example, conventionally known photolithography and etching.

  According to the manufacturing method of the semiconductor device of the first embodiment, the semiconductor substrate can be thinned to 10 μm or less by using the metal film 80 as a support. For this reason, the through electrode and the through separation portion for separating the through electrode from the surroundings can be formed with a low aspect ratio, and as a result, it is possible to suppress the occurrence of embedding defects. Further, since the peripheral wiring 110 surrounding the central region 24 can be formed at the same time as the formation of the chip wiring 120, a wafer level CSP having excellent moisture resistance can be formed without increasing the number of processes. it can.

  In the first embodiment, an example in which the element is a PMOS and an NMOS has been described. However, the present invention is not limited to this. Depending on the settings, any desired number of suitable active or passive elements can be formed. In the case where no impurity diffusion layer is formed in the central region, such as when no PMOS or NMOS is formed as an element, the impurity diffusion layer may be formed alone in the peripheral region.

(Structure of Semiconductor Device of Second Embodiment)
With reference to FIG. 7, the semiconductor device of 2nd Embodiment is demonstrated. FIG. 7 is a schematic view for explaining the semiconductor device of the second embodiment, and shows a cut end surface of a main part.

  The semiconductor device of the second embodiment is different from the first embodiment in that a peripheral oxide film is provided on a semiconductor substrate in the peripheral region. Since the other points are the same as in the first embodiment, a duplicate description is omitted.

  In the semiconductor device 11 of the second embodiment, the peripheral region 26 is further divided into a first peripheral region 26a and a second peripheral region 26b. The first peripheral region 26 a is set adjacent to the central region 24 so as to surround the central region 24. The second peripheral area 26b is set so as to surround the first peripheral area 26a.

  The impurity diffusion layer 49 is formed on the first main surface 20 a side of the first peripheral region 26 a of the semiconductor substrate 20, and the peripheral wiring 110 is connected to the impurity diffusion layer 49.

  A peripheral oxide film 36 is formed in the second peripheral region 26b surrounding the first peripheral region 26a from the first main surface 20a to the second main surface 20b.

  According to the semiconductor device 10 of the first embodiment, the peripheral wiring 110 surrounding the central region 24 has improved moisture resistance compared to the conventional metal-encapsulated wafer level CSP. There remains a slight possibility that moisture permeates from the interface with the wiring insulating film 100 to corrode the peripheral wiring 110 and eventually corrode the chip wiring 120.

  On the other hand, according to the semiconductor device 11 of the second embodiment, since the oxide film is formed around the semiconductor substrate 20, the side surface of the chip region 22 is covered with the oxide film. For this reason, the side surface is covered with the same kind of material, and even when moisture enters from the interface between the metal film and the silicon substrate, the oxide film can more effectively prevent intrusion into the inside. .

(Method for Manufacturing Semiconductor Device of Second Embodiment)
With reference to FIG. 8, the manufacturing method of the semiconductor device of 2nd Embodiment is demonstrated. 8A, 8B, and 8C are process diagrams for explaining the method of manufacturing the semiconductor device of the second embodiment, and are cut end faces of the main part of the structure formed in each process. Is shown.

  The manufacturing method of the semiconductor device of the second embodiment is different from the first embodiment in that an oxide film is formed on the semiconductor substrate in the peripheral region. Since the other points are the same as in the first embodiment, a duplicate description is omitted.

  As the peripheral area 26, a first peripheral area 26a surrounding the central area 24 and a second peripheral area 26b surrounding the first peripheral area 26a are set.

  In the step of forming the through separation groove 33, the second peripheral region 26 b of the semiconductor substrate 20 c is etched together to form the peripheral through groove 35 that surrounds the central region 24 and has the same depth as the through separation groove 33.

  In the step of forming the through separation part 34, the peripheral through groove 35 is buried to form the peripheral oxide film 36 (FIG. 8A).

  In the step of forming the element 40, the impurity diffusion layer 49 is formed on the first main surface 20a side of the first peripheral region 26a (FIG. 8B).

  Next, in the same manner as described with reference to FIG. 3C, the first layer conductive plug 52, the through electrode plug 54b, the through electrode 54a, and the first layer peripheral plug 56 are formed (FIG. 8C). )).

  Subsequent processes are the same as those of the semiconductor device manufacturing method according to the first embodiment, and a description thereof will be omitted.

  According to the manufacturing method of the semiconductor device of the second embodiment, the peripheral oxide film 36 surrounding the central region 24 is formed at the same time as the through-separation portion 34. Therefore, a semiconductor having better moisture resistance without increasing the number of processes. An apparatus can be provided.

(Structure of Semiconductor Device of Third Embodiment)
With reference to FIG. 9, the semiconductor device of 3rd Embodiment is demonstrated. FIG. 9 is a schematic view for explaining the semiconductor device of the third embodiment, and shows a cut end surface of a main part.

  The semiconductor device of the third embodiment is different from the first embodiment in the structure of the peripheral region. Since the other points are the same as in the first embodiment, a duplicate description is omitted.

  In the semiconductor device 12 of the third embodiment, a peripheral oxide film 37 surrounding the central region 24 is formed in the peripheral region 26 of the semiconductor substrate 20 from the first main surface 20a to the second main surface 20b. Furthermore, the semiconductor device 12 of the third embodiment includes a peripheral through electrode 56a in the peripheral oxide film 37 from the first main surface 20a to the second main surface 20b.

  The peripheral wiring 110 is connected to the peripheral through electrode 56a.

  According to the semiconductor device 12 of the third embodiment, since the peripheral oxide film is formed in the peripheral region 26, the side surfaces 22 c and 100 c of the chip region 22 are covered with the oxide films 37 and 100. The peripheral oxide film 37 and the wiring insulating film 100 are both oxide films. For this reason, the interface between the silicon and the oxide film does not exist on the side surfaces 22c and 100c of the chip region 22. As a result, even if moisture enters from the interface between the metal film 80 and the semiconductor substrate 20, the oxide film can prevent intrusion into the inside.

  Further, since the peripheral through electrode 56a is provided in the peripheral oxide film 37, the metal film 80 can be brought into an electrically floating state. Further, by forming the wiring pattern on the second main surface 20b side that is the back surface, the potential of the metal film 80 can be set to an arbitrary value even after metal sealing.

(Method for Manufacturing Semiconductor Device of Third Embodiment)
With reference to FIG. 10, the manufacturing method of the semiconductor device of 3rd Embodiment is demonstrated. FIGS. 10A and 10B are process diagrams for explaining the method of manufacturing the semiconductor device according to the third embodiment, and show cut end surfaces of main parts of the structure formed in each process. .

  The semiconductor device manufacturing method of the third embodiment is different from the first embodiment in the steps for the peripheral region. Since the other points are the same as in the first embodiment, a duplicate description is omitted.

  In the step of forming the through separation groove 33, the peripheral region 26 of the semiconductor substrate 20 c is etched together to form the peripheral through groove 39 that surrounds the central region 24 and has the same depth as the through separation groove 33.

  In the step of forming the through isolation portion 34, the through isolation trench 33 is embedded, and the peripheral through trench 39 is embedded to form the peripheral oxide film 37 (FIG. 10A).

  Thereafter, an element is formed as in the first embodiment. In the semiconductor device manufacturing method of the third embodiment, no impurity diffusion layer is formed in the peripheral region 26.

  In the step of forming the element contact hole 51, the through electrode hole 53, and the first layer peripheral groove 55, the first layer peripheral groove 55 is formed from the first interlayer insulating film 50 to the peripheral oxide film 37, and the peripheral through hole is formed. The bottom surface 39a of the groove 39 is exposed.

  In the step of forming the conductive plug and the peripheral plug, the peripheral through groove 35 is further embedded to form the peripheral through electrode 56a in the peripheral oxide film 37 (FIG. 10B).

  Subsequent processes are the same as those of the semiconductor device manufacturing method according to the first embodiment, and a description thereof will be omitted.

  In addition, according to the semiconductor device manufacturing method of the third embodiment, the peripheral oxide film and the peripheral through electrode around the silicon substrate can be formed simultaneously with the through isolation part and the through electrode, so that the number of processes is not increased.

(Modification of the third embodiment)
A modification of the semiconductor device of the third embodiment will be described with reference to FIG. The semiconductor device of this modification is different from the semiconductor device of the third embodiment described with reference to FIG. 13 in the structure on the second main surface side, and the other points are the same, so redundant description is omitted. To do.

  The semiconductor device 13 according to the modification includes a back surface insulating film 130 on the second main surface 20 b and an external terminal 90 on the back surface insulating film 130. A backside wiring pattern 140 that electrically connects the external terminal 90 and the through electrode 54 a is formed in the backside insulating film 130.

  Before forming the external terminal 90, the following steps are performed.

  First, the 1st back surface insulating film 132 is formed on the 2nd main surface 20b.

  Next, a back contact hole 133 exposing the through electrode 54 a is opened in the first back insulating film 132.

  Next, the back contact hole 133 is filled, and further, the back wiring pattern 140 is formed on the first back insulating film 132.

  Next, a second back surface insulating film 136 that covers the back surface wiring pattern 140 is formed on the first back surface insulating film 132. The first back surface insulating film 132 and the second back surface insulating film 136 constitute a back surface insulating film 130.

  Next, a via hole 137 exposing the back wiring pattern 140 is formed in the second back insulating film 136.

  Next, the via hole 137 is filled with the conductor 138, and the external terminal 90 is formed on the conductor 138.

  According to the configuration of this modification, the arrangement of the external terminals can be changed by patterning the back surface wiring pattern without changing the elements and the wiring pattern.

  Each step of forming the back surface insulating film 130, the back surface wiring pattern 140, and the like can be performed by any conventionally known and suitable method similar to the formation of the interlayer insulating film and the chip wiring on the first main surface 20a side. good.

  Here, although it demonstrated as a modification of 3rd Embodiment, this modification is applicable also about 1st Embodiment and 2nd Embodiment.

  In each of the above embodiments, the metal film 80, the kth layer wiring, the kth layer peripheral wiring, the kth layer conductive plug, the kth layer peripheral plug, and the upper layer peripheral plug are formed by, for example, a conventionally known damascene process. It may be used as a copper wiring.

1 is a schematic diagram of a semiconductor device according to a first embodiment. FIG. 6 is a process diagram (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment; FIG. 6 is a process diagram (part 2) illustrating the method for producing the semiconductor device of the first embodiment; FIG. 6 is a process diagram (part 3) illustrating the method for producing the semiconductor device of the first embodiment; FIG. 9 is a process diagram (part 4) illustrating the method for producing the semiconductor device of the first embodiment; FIG. 11 is a process diagram (part 5) illustrating the method for producing the semiconductor device of the first embodiment; It is the schematic of the semiconductor device of 2nd Embodiment. It is process drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. It is the schematic of the semiconductor device of 3rd Embodiment. It is process drawing which shows the manufacturing method of the semiconductor device of 3rd Embodiment. It is the schematic which shows the modification of the semiconductor device of 3rd Embodiment.

Explanation of symbols

10, 11, 12, 13 Semiconductor device 20, 20c Semiconductor substrate 20a First main surface 20b, 54ab Second main surface 22 Chip region 24 Central region 26 Peripheral region 26a First peripheral region 26b Second peripheral region 28 Dicing region 29 Dicing region Line 30 n-well 31 element isolation groove 32 element isolation film 33 through isolation groove
34 Through-separation part 35, 39 Peripheral through-groove 35a, 39a Bottom surface 36, 37 Peripheral oxide film 40 Element 40a PMOS
40b NMOS
42a, 42b Gate insulating film 44a, 44b Gate electrode 46a, 46b, 48, 49 Impurity diffusion layer 50 First interlayer insulating film 52 First layer conductive plug 54a Through electrode 54b Through electrode plug 55 First layer peripheral groove 56a Peripheral through hole Electrodes 56, 56b First layer peripheral plug 58 First layer wiring 59 First layer peripheral wiring 60 Second interlayer insulating film 62 Second layer conductive plug 65 Second layer peripheral groove 66 Second layer peripheral plug 68 Second layer wiring 69 Second layer peripheral wiring 70 Upper layer insulating film 75 Upper layer peripheral groove 76 Upper layer peripheral plug 80 Metal film 90 External terminal 100 Wiring insulating film 100a Upper surface 100b Lower surface 100c Side surface 110 Peripheral wiring 120 Chip wiring 130 Back surface insulating film
140 Backside wiring pattern

Claims (27)

And dicing region, the semiconductor base plate and the chip area defined by said dicing area is set,
An element formed on the first main surface is one main surface of the semiconductor substrate,
Before Symbol first main surface of the semiconductor substrate, and the penetrating separation portion formed over a second main surface which is opposite to the main surface of the first main surface,
A through electrode formed in the through separation portion from the first main surface to the second main surface;
A wiring insulating film formed on the first main surface of the semiconductor substrate ;
Chip wiring formed in the wiring insulating film;
A metal film integrally formed on the upper surface and side surface of the wiring insulating film ,
A semiconductor device , wherein the thickness of the metal film is larger than that of the semiconductor substrate .   The semiconductor device according to claim 1, wherein the metal film has a film thickness that functions as a support body that maintains the mechanical strength of the semiconductor substrate.   3. The semiconductor device according to claim 1, wherein the thickness of the metal film is four times or more the thickness of the semiconductor substrate.   The metal film has a thickness of 40 μm or more,
  The semiconductor device according to claim 1, wherein the semiconductor substrate has a thickness of 3 to 10 μm. The chip region includes a central region and a peripheral region around the central region;
The wiring insulating film of the peripheral region includes a peripheral wiring formed so as to surround the central region from the upper surface to the lower surface,
  The element is provided in the central region on the first main surface side;
  The semiconductor device according to claim 1, wherein the through-separation part and the chip wiring are provided in the central region. The first main surface side of the front Symbol peripheral region includes an impurity diffusion layer,
The semiconductor device according to claim 5 , wherein the peripheral wiring is electrically connected to the impurity diffusion layer. 6. The semiconductor device according to claim 5 , wherein a peripheral oxide film surrounding the central region is formed on the semiconductor substrate in the peripheral region from the first main surface to the second main surface. . The peripheral region includes a first peripheral region adjacent to the central region, and a second peripheral region surrounding the first peripheral region,
Said semiconductor substrate, said first main surface side of the first peripheral area, comprising an impurity diffusion layer,
The peripheral wiring is electrically connected to the impurity diffusion layer, and a peripheral oxide film is formed in the second peripheral region from the first main surface to the second main surface. The semiconductor device according to claim 5 . A peripheral through electrode is provided in the peripheral oxide film from the first main surface to the second main surface,
The semiconductor device according to claim 7 , wherein the peripheral wiring is electrically connected to the peripheral through electrode. Wherein the second main surface, the semiconductor device according to any one of claims 1 to 9, characterized in that it comprises the through electrode is electrically connected to the external pin. Forming a hand of penetrating separation groove from the first main surface is the main surface toward the second major surface is opposite to the main surface of the first main surface of the semi-conductor board,
Forming a penetrating separation portion to form an oxide film on the through isolation trench,
Forming an element on the first main surface side of the semiconductor substrate;
Forming a wiring insulating film covering the element on the first main surface of the semiconductor substrate ;
Forming a chip wiring before Symbol wire insulating film,
Forming a through electrode before Symbol penetrating separation portion,
A step of integrally covering a top surface and a side surface of the wiring insulating film , and forming a metal film having a film thickness larger than the film thickness of the semiconductor substrate ;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 11, wherein the metal film is formed to a thickness that functions as a support body that maintains the mechanical strength of the semiconductor substrate.   13. The method of manufacturing a semiconductor device according to claim 11, wherein in the step of forming the metal film, the film thickness of the metal film is formed to be four times or more the film thickness of the semiconductor substrate.   In the step of forming the metal film, the thickness of the metal film is formed to 40 μm or more,
  The method of manufacturing a semiconductor device according to claim 11, wherein, in the thinning step, the semiconductor substrate is thinned until the film thickness becomes 3 to 10 μm. The method of manufacturing a semiconductor device according to claim 11, wherein the through electrode is exposed from the second main surface side. 15. The method according to claim 11, further comprising a step of thinning the semiconductor substrate until the through electrode is exposed from the second main surface side after forming the metal film. Semiconductor device manufacturing method. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of forming an external terminal on the through electrode exposed from the second main surface side. A plurality of chip regions having a central region and a peripheral region around the central region are set in the semiconductor substrate,
The step of forming the wiring insulating film, the chip wiring, and the through electrode further includes the step of forming a peripheral wiring surrounding the central region from the upper surface to the lower surface in the wiring insulating film of the peripheral region. A method for manufacturing a semiconductor device according to claim 11, wherein: The step of forming the wiring insulating film, the chip wiring, the through electrode, and the peripheral wiring,
Forming a first interlayer insulating film on the first main surface of the semiconductor substrate;
An element contact hole exposing the element portion and a through electrode hole exposing the bottom of the through isolation trench are formed in the central region of the first interlayer insulating film, and the first interlayer insulation is formed. Forming a first layer peripheral groove exposing the first main surface in the peripheral region of the film;
A contact hole for said element to form a first layer conductive plug by filling a conductor, embeds the hole for the through electrodes, thereby forming the through electrode in the interior of the penetrating separation portion, the first interlayer insulating film Forming a through-electrode plug in the first layer, filling the first layer peripheral groove, and forming a first layer peripheral plug;
By forming a first layer wiring on the first interlayer insulating film, the chip wiring composed of the first layer wiring, the first layer conductive plug and the through electrode plug is formed, and the first wiring is formed. Forming a first layer peripheral wiring covering the layer peripheral plug;
The wiring insulation in which the first interlayer insulating film and the upper insulating film are stacked by forming an upper insulating film covering the first layer wiring and the first layer peripheral wiring on the first interlayer insulating film. Forming a film;
Forming an upper peripheral groove in the peripheral region of the upper insulating film, exposing the first layer peripheral wiring and surrounding the central region;
Forming the peripheral wiring composed of the upper peripheral plug, the first peripheral plug and the first peripheral wiring by filling the upper peripheral groove and forming an upper peripheral plug;
The method of manufacturing a semiconductor device according to claim 18, comprising: The chip wiring has an n-layer structure (n is an integer of 2 or more),
The step of forming the wiring insulating film, the chip wiring, the through electrode, and the peripheral wiring,
Forming a first interlayer insulating film on the first main surface of the semiconductor substrate;
An element contact hole exposing the element portion and a through electrode hole exposing the bottom of the through isolation groove are formed in the central region of the first interlayer insulating film, and the first interlayer insulation is formed. Forming a first layer peripheral groove exposing the first main surface in the peripheral region of the film;
A contact hole for said element to form a first layer conductive plug by filling a conductor, embeds the hole for the through electrodes, thereby forming the through electrode in the interior of the penetrating separation portion, the first interlayer insulating film Forming a through-electrode plug in the first layer, filling the first layer peripheral groove, and forming a first layer peripheral plug;
Forming a first layer wiring on the first interlayer insulating film and forming a first layer peripheral wiring covering the first layer peripheral plug;
Forming a k-th interlayer insulating film covering the k-1 layer wiring and the k-1 layer peripheral wiring on the k-1 interlayer insulating film (k is an integer of 2 to n);
The k-1th layer peripheral wiring is exposed in the peripheral region of the kth interlayer insulating film and the kth via hole exposing the k-1th layer wiring portion in the central region of the kth interlayer insulating film. And forming a k-th layer peripheral groove surrounding the central region;
Filling the kth via hole with a conductor to form a kth layer conductive plug, filling the kth layer peripheral groove to form a kth layer peripheral plug ;
A step of forming a k-th layer wiring on the k-th interlayer insulating film and forming a k-th layer peripheral wiring covering the k-th layer peripheral plug by repeatedly changing k from 2 to n;
On the n interlayer insulating film, by forming an upper insulating film which covers the first n layer wiring及beauty the n layer peripheral wiring, the wiring insulating said first 1~n interlayer insulating film and the upper insulating film is stacked Forming a film and obtaining the chip wiring comprising the through-electrode plug, the first to n-layer conductive plugs, and the first to n-layer wiring;
Forming an upper peripheral groove in the peripheral region of the upper insulating film, exposing the n-th layer peripheral wiring and surrounding the central region;
Embed said upper peripheral groove, by forming an upper peripheral plug, forming a top layer around the plug, consists of a 1~n layer peripheral plug及beauty first 1~n layer peripheral wiring the peripheral wiring,
The method of manufacturing a semiconductor device according to claim 18, comprising: 21. The method of manufacturing a semiconductor device according to claim 18 , wherein in the step of forming the element, an impurity diffusion layer is formed on the first main surface side of the peripheral region. In the step of forming the through separation groove, the peripheral region of the semiconductor substrate is etched together to surround the central region, and a peripheral through groove having the same depth as the through separation groove is formed,
21. The method of manufacturing a semiconductor device according to claim 18 , wherein, in the step of forming the through isolation portion, a peripheral oxide film is formed by filling the peripheral through groove. As the peripheral region, a first peripheral region adjacent to the central region and a second peripheral region surrounding the first peripheral region are set,
In the step of forming the through separation groove, the second peripheral region of the semiconductor substrate is etched together to form a peripheral through groove that surrounds the central region and has the same depth as the through separation groove,
In the step of forming the through isolation part, a peripheral oxide film is formed by filling the peripheral through groove,
21. The method of manufacturing a semiconductor device according to claim 18 , wherein in the step of forming the element, an impurity diffusion layer is formed on the first main surface side of the first peripheral region. Method. In the step of forming the through isolation part, a peripheral oxide film is formed by filling the peripheral through groove,
In the step of forming the first layer peripheral groove, the first layer peripheral groove is formed in the peripheral oxide film to the same depth as the through electrode hole,
In the step of forming the conductive plug and the first layer surrounding the plug, embedded together said first layer peripheral groove, claim and forming a peripheral through electrode in said peripheral oxide film 19 to 21 The manufacturing method of the semiconductor device as described in any one of these . The method for manufacturing a semiconductor device according to any one of claims 11 to 24 , further comprising a step of forming an external terminal on the second main surface of the through electrode. Forming a first back surface insulating film on the second main surface of the semiconductor substrate;
Opening a back contact hole exposing the through electrode in the first back insulating film;
Burying the back contact hole, and further forming a back wiring on the first back insulating film;
Forming a second back surface insulating film covering the back surface wiring on the first back surface insulating film;
Forming a via hole that exposes a portion of the backside wiring in the second backside insulating film;
Embedding the via hole with a conductive material, further, a method of manufacturing a semiconductor device according to any one of claims 11 to 24, further comprising the step of forming the external terminals on the electrically conductor. After forming the external terminal,
The dicing region between chip regions, a manufacturing method of a semiconductor device according to claim 25 or 26, characterized in that singulation each chip region by performing dicing.

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