CN112185981B - Preparation method of three-dimensional memory structure - Google Patents
Preparation method of three-dimensional memory structure Download PDFInfo
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- CN112185981B CN112185981B CN202011058962.4A CN202011058962A CN112185981B CN 112185981 B CN112185981 B CN 112185981B CN 202011058962 A CN202011058962 A CN 202011058962A CN 112185981 B CN112185981 B CN 112185981B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
本发明提供一种三维存储器结构及其制备方法，该三维存储器结构包括外围电路芯片；存储阵列芯片，与所述外围电路芯片键合，所述存储阵列芯片包括栅极堆叠结构，所述栅极堆叠结构具有核心区域和台阶区域，所述栅极堆叠结构包括靠近所述外围电路芯片的第一栅极堆叠结构和远离所述外围电路芯片的第二栅极堆叠结构；第一多级台阶结构，形成于所述第一栅极堆叠结构的台阶区域中，所述第一多级台阶结构的台面朝向所述外围电路芯片；第二多级台阶结构，形成于所述第二栅极堆叠结构的台阶区域中，所述第二多级台阶结构的台面背离所述外围电路芯片。通过在存储阵列芯片的台阶区域的正面和背面各形成部分台阶的形成，可减小台阶区所占面积，提高存储密度。
The invention provides a three-dimensional memory structure and a preparation method thereof. The three-dimensional memory structure includes a peripheral circuit chip; a storage array chip is bonded to the peripheral circuit chip, and the storage array chip includes a gate stack structure, and the gate The stack structure has a core area and a step area, and the gate stack structure includes a first gate stack structure close to the peripheral circuit chip and a second gate stack structure away from the peripheral circuit chip; a first multi-level stepped structure , formed in the stepped area of the first gate stack structure, the mesa of the first multi-level stepped structure faces the peripheral circuit chip; the second multi-level stepped structure is formed in the second gate stack structure In the step region of the second step structure, the mesa of the second multi-step step structure is away from the peripheral circuit chip. By forming partial steps on the front side and the back side of the step area of the memory array chip, the area occupied by the step area can be reduced and the storage density can be improved.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a method for preparing a three-dimensional memory structure.
Background
In a three-dimensional memory architecture which bonds two chips together, a peripheral circuit which is responsible for data I/O and memory unit operation can be independently processed on a wafer, and the processing mode is favorable for selecting a proper advanced logic process so as to enable NAND to obtain higher I/O interface speed and more operation functions; and the memory cells will also be processed independently on another wafer. After the two wafers are finished respectively, the two wafers can be bonded and connected with a circuit through a metal VIA (Vertical Interconnect access) to form a final three-dimensional memory product.
In the memory array chip of the three-dimensional memory architecture, the steps are introduced to lead out different gate layers through the word line connecting column formed on the steps, the steps in the step area are formed by etching the gate stack structure from the side, away from the substrate, of the gate stack structure, and the mesas of all the steps in the step area face to the peripheral circuit chip. As the integration degree of the three-dimensional memory is higher, the three-dimensional memory has been developed from 32 layers to 64 layers or even higher, and as the number of layers is increased, the area occupied by the step region is larger and smaller, and the area occupied by the core region is smaller and smaller, which limits the increase of the storage density of the three-dimensional memory.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a three-dimensional memory structure, which is used to solve the technical problems of large occupied area of a step region and low storage capacity of a three-dimensional memory.
To achieve the above and other related objects, the present invention provides a three-dimensional memory structure, comprising:
a peripheral circuit chip;
a memory array chip bonded with the peripheral circuit chip, the memory array chip including a gate stack structure having a core region and a step region, the gate stack structure including a first gate stack structure close to the peripheral circuit chip and a second gate stack structure far from the peripheral circuit chip;
a first multi-step structure formed in a step region of the first gate stack structure, a mesa of the first multi-step structure facing the peripheral circuit chip;
and the second multi-stage step structure is formed in the step region of the second grid stacking structure, and the mesa of the second multi-stage step structure is deviated from the peripheral circuit chip.
In an optional embodiment, the memory array chip further comprises a first interconnect layer formed on the gate stack structure, and the peripheral circuit chip comprises a second interconnect layer, and the peripheral circuit chip is bonded to the bonding contact of the first interconnect layer of the memory array chip through the bonding contact of the second interconnect layer.
In an optional embodiment, the memory array chip further includes a semiconductor material layer disposed on a surface of the gate stack structure away from the peripheral circuit chip.
In an alternative embodiment, the material of the semiconductor material layer comprises polysilicon.
In an optional embodiment, a vertical channel structure is disposed in the core region of the gate stack structure, the vertical channel structure penetrates through the gate stack structure and extends into the semiconductor material layer, and the vertical channel structure includes a functional sidewall layer and a channel layer sequentially disposed from outside to inside in a radial direction.
In an optional embodiment, the memory array chip further includes an isolation protection layer formed on the semiconductor material layer.
In an optional embodiment, the memory array chip further includes a gate line gap filling layer, and the gate line gap filling layer penetrates through the gate stack structure.
In an alternative embodiment, the material of the gate line gap filling layer includes silicon nitride or silicon oxide.
In an alternative embodiment, the three-dimensional memory structure further includes a plurality of first word line connection pillars formed on each first step of the first multi-step structure.
In an alternative embodiment, the three-dimensional memory structure further includes a plurality of second word line connection pillars formed on second steps of each level of the second multi-level step structure.
To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional memory structure, the method comprising:
preparing a memory array chip comprising: forming a gate stack structure on the semiconductor substrate, wherein the gate stack structure is provided with a core region and a step region and comprises a first gate stack structure and a second gate stack structure positioned between the first gate stack structure and the semiconductor substrate; forming a first multi-step structure in a step region of the first gate stack structure, a mesa of the first multi-step structure facing the peripheral circuit chip;
arranging a peripheral circuit chip on one side of the first grid stacking structure far away from the semiconductor substrate;
and forming a second multi-stage step structure in the step region of the second gate stack structure from the side far away from the peripheral circuit chip, wherein the mesa of the second multi-stage step structure is far away from the peripheral circuit chip.
In an alternative embodiment of the method of the invention,
the peripheral circuit chip includes a second interconnect layer;
the step of preparing the memory array chip further comprises the step of forming a first interconnection layer between the gate stack structure and the peripheral circuit chip;
the step of arranging a peripheral circuit chip on the side of the memory array chip far away from the semiconductor substrate comprises the step of bonding the peripheral circuit chip with the bonding contact of the first interconnection layer of the memory array chip through the bonding contact of the second interconnection layer.
In an optional embodiment, in the step of forming the gate stack structure on the semiconductor substrate, a semiconductor material layer is further formed between the gate stack structure and the semiconductor substrate.
In an alternative embodiment, the material of the semiconductor material layer comprises polysilicon.
In an optional embodiment, the step of manufacturing the memory array chip further includes a step of disposing a vertical channel structure in the core region of the gate stack structure, where the vertical channel structure penetrates through the gate stack structure and extends into the semiconductor material layer, and the vertical channel structure includes a functional sidewall layer and a channel layer sequentially disposed from outside to inside in a radial direction.
In an optional embodiment, a thinning stop layer is further formed between the gate stack structure and the semiconductor substrate, and the step of forming the second multi-step structure in the step region of the second gate stack structure includes:
removing the semiconductor substrate to expose the thinning stop layer;
and forming a second multi-step structure in the second gate stack structure.
In an optional embodiment, the step of preparing the memory array chip further includes a step of forming a gate line gap filling layer, where the gate line gap filling layer penetrates through the gate stack structure.
In an alternative embodiment, the material of the gate line gap filling layer includes silicon nitride or silicon oxide.
In an optional embodiment, the step of fabricating the memory array chip further includes a step of forming a first word line connection pillar on each first step of the first multi-step structure.
In an optional embodiment, the method for fabricating a three-dimensional memory structure further includes a step of forming a second word line connection pillar on each second step of the second multi-step structure.
In the invention, in a three-dimensional memory architecture bonding two chips (a peripheral circuit chip and a memory array chip), partial steps are respectively formed on the front surface (the side close to the peripheral circuit chip) and the back surface (the side far away from the peripheral circuit chip) of the memory array chip, the partial steps arranged on the front surface of the memory array chip are used for leading out a gate layer close to the peripheral circuit chip, and the partial steps arranged on the back surface of the memory array chip are used for leading out a gate layer far away from the peripheral circuit chip, so that the occupied area of a step area in the three-dimensional memory structure can be effectively reduced, and the memory density is improved.
Drawings
FIG. 1 is a flow chart illustrating the fabrication of a three-dimensional memory structure according to the present invention.
Fig. 2 is a schematic cross-sectional view illustrating a patterned photoresist layer formed on a side of a memory array chip away from a peripheral circuit chip in a process of fabricating a three-dimensional memory structure according to the present invention.
FIG. 3 is a schematic cross-sectional view illustrating a downward etching process based on the patterned photoresist layer in the process of fabricating a three-dimensional memory structure according to the present invention.
Fig. 4 is a schematic cross-sectional view illustrating a second multi-step formed in the step region of the second gate stack structure in the process flow of fabricating the three-dimensional memory structure according to the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a second step cap layer formed in the second multi-step in the process flow of fabricating the three-dimensional memory structure according to the present invention.
Fig. 6 is a schematic cross-sectional view illustrating a second word line connecting pillar formed on each step of the second multi-step covered with the second step covering layer in the process of fabricating the three-dimensional memory structure according to the present invention.
FIG. 7 is a schematic cross-sectional view illustrating the removal of the thinning stop layer in the process flow of fabricating the three-dimensional memory structure according to the present invention.
Description of the element reference numerals
100 peripheral circuit chip
110 second semiconductor substrate
120 peripheral circuit dielectric layer
130 second interconnect layer
131 peripheral interconnection line
132 peripheral via interconnect
133 second bonding contact
134 second silicon nitride layer
200 memory array chip
210 thinning the stop layer
220 isolation protective layer
230 layer of semiconductor material
240 grid stacking structure
240a second gate stack structure
240b first gate stack structure
241 grid layer
242 interlayer dielectric layer
250 first interconnect layer
251 first interconnection line
252 first via interconnect
253 second interconnection line
254 second via interconnect
255 first bonding contact
256 first silicon nitride layer
260 vertical channel structure
270 gate line gap filling layer
280a second wordline connection stud
280b first wordline connection stud
280c peripheral pad connection post
290a first step coverage
290b second step coating
300 patterned photoresist layer
310 first opening
400 second opening
500 step groove
S10-S30
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the X-stacking three-dimensional memory architecture, a three-dimensional memory is formed by bonding a memory array chip and a peripheral circuit chip to each other. In a memory array chip, the gate stack structure needs to be etched from a side of the gate stack structure away from a substrate to form a plurality of steps in a step region of the gate stack structure, and a word line connection column electrically connected to a corresponding gate layer is formed on each step to achieve the purpose of leading out each gate layer in the gate stack structure. As the integration degree of the three-dimensional memory is higher, the three-dimensional memory has been developed from 32 layers to 64 layers or even higher, and as the number of layers is increased, the area occupied by the step region is larger and smaller, and the area occupied by the core region is smaller and smaller, which limits the increase of the storage density of the three-dimensional memory.
Based on this, the embodiment of the invention provides a three-dimensional memory structure and a preparation method thereof, by forming partial steps on the front surface (the side close to a peripheral circuit chip) and the back surface (the side far away from the peripheral circuit chip) of a memory array chip respectively, the partial steps arranged on the front surface of the memory array chip are used for leading out a gate layer close to the peripheral circuit chip, and the partial steps arranged on the back surface of the memory array chip are used for leading out a gate layer far away from the peripheral circuit chip, so that the occupied area of a step region in the three-dimensional memory structure can be effectively reduced, and the memory density is improved.
Example one
Referring to fig. 1, the present embodiment describes a method for manufacturing a three-dimensional memory structure, which adopts an X-stacking three-dimensional memory architecture and is composed of a memory array chip 200 and a peripheral circuit chip 100 that are bonded to each other. Referring to fig. 1, the preparation method includes:
step S10, preparing the memory array chip 200, includes: sequentially forming a thinning stop layer 210 and a gate stack structure 240 on the semiconductor substrate, wherein the gate stack structure 240 has a core region and a step region, and the gate stack structure 240 comprises a first gate stack structure 240b far away from the semiconductor substrate and a second gate stack structure 240a close to the semiconductor substrate; forming a first multi-step structure in the step region of the first gate stack structure 240 b;
step S20, disposing the peripheral circuit chip 100 on a side of the memory array chip 200 away from the semiconductor substrate;
step S30, forming a second multi-step structure in the step region of the second gate stack structure 240a from a side away from the peripheral circuit chip 100, where a mesa of the second multi-step structure is away from the peripheral circuit chip 100.
The method for manufacturing the three-dimensional memory structure of the present embodiment will be described in detail with reference to the schematic diagrams corresponding to the steps.
Referring to fig. 2, step S10 is performed to provide a first semiconductor substrate (not shown), and the thinning stop layer 210 is formed on the semiconductor substrate. The first semiconductor substrate may be, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like, such as a Silicon substrate. The material of the thinning Stop Layer 210 may be, for example, silicon nitride (of course, other suitable materials are also possible), the first semiconductor substrate is completely removed by depositing silicon nitride on the first semiconductor substrate as the subsequent Chemical Mechanical Planarization (CMP) Process for removing the thinning Stop Layer 210(Stop Layer) of the first semiconductor substrate, and the Process Window (Process Window) for removing the first semiconductor substrate on the back of the memory array chip 200 by the chemical mechanical planarization Process can be greatly improved by providing the thinning Stop Layer 210 made of silicon nitride.
Referring to fig. 2, step S10 is continued to sequentially form an isolation protection layer 220, a semiconductor material layer 230, and a gate stack structure 240 on the thinning stop layer 210. The material of the isolation protection layer 220 may be, for example, one of silicon dioxide, silicon nitride or silicon oxynitride, such as silicon dioxide, and the material of the semiconductor material layer 230 may be, for example, polysilicon. The gate stack structure 240 has a core region for forming a vertical channel structure 260 for data storage and a step region on one side (or peripheral side) of the core region for leading out a corresponding gate layer 241 through a word line connection pillar. The gate stack structure 240 includes alternately stacked interlayer dielectric layers 242 and gate layers 241, adjacent interlayer dielectric layers 242 and gate layers 241 form a stacked layer pair, and the gate stack structure 240 may include two portions, namely a first gate stack structure 240b close to the first semiconductor substrate and a second gate stack structure 240a far away from the first semiconductor substrate; the first gate stack structure 240b and the second gate stack structure 240a respectively include a plurality of level pairs. As an example, in the gate stack structure 240, the number of layers of the gate layer 241 may include 32 layers, 64 layers, 96 layers, 128 layers, and the like, and specifically, the interlayer dielectric layer 242 and the gate in the gate stack structure 240The number of layers of the pole layer 241 can be set according to actual needs, and is not limited herein; the gate layer 241 is made of a conductive material, including but not limited to any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W); the material of the interlayer dielectric layer 242 may include, but is not limited to, silicon oxide (SiO)2) And (3) a layer. The interlayer dielectric Layer 242 and the gate Layer 241 may be formed by a process including, but not limited to, Physical Vapor Deposition (PVD) process, Chemical Vapor Deposition (CVD) process, or Atomic Layer Deposition (ALD) process.
Referring to fig. 2, step S10 is continuously performed to form a first multi-step structure in the step region of the first gate stack structure 240b, where the first multi-step structure includes multiple first steps, each first step includes at least one stacked layer pair of the first gate stack structure 240b, and a top surface of each first step exposes a surface of the gate layer 241 or the interlayer dielectric layer 242 of the corresponding stacked layer pair. Specifically, a number of first steps may be formed in the step region, for example, by performing a repeated etch-trim process on the first gate stack structure 240b using a patterned mask (not shown), the top surface of each first step exposing the end surface of the corresponding interlayer dielectric layer 242 or gate electrode layer 241, the patterned mask may include a photoresist or a carbon-based polymer material, and the patterned mask may be removed after forming the steps. In this embodiment, each stage of the first step includes at least one stacked layer pair, and fig. 2 only shows that each stage of the first step includes one stacked layer pair. Only the case including the 4-step first step is shown in fig. 2, and it is understood that the number of steps of the first step may be adjusted as necessary.
Referring to fig. 2, step S10 is continued, after forming a first multi-step structure in the step region of the first gate stack structure 240b, a first step covering layer 290a is filled in the step region where the first multi-step structure is formed, wherein the first step covering layer may be made of one of silicon dioxide, silicon nitride or silicon oxynitride, such as silicon dioxide; etching the first step coverage layer 290a downward through photolithography and etching processes to form a plurality of first contact holes in the first step coverage layer 290a of the step region, the first contact holes exposing the gate layer 241 in the corresponding first step; filling a conductive material in the first contact hole to form a first word line connection post 280b, wherein the first word line connection post 280b is connected with the corresponding gate layer 241, so that the gate layer 241 is led out; the material of the first word line connection stud 280b may be, for example, a conductive material, including but not limited to any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W).
It should be noted that, referring to fig. 2, when the bottommost first step etching is performed, for example, the second gate stack structure 240a may be directly and continuously etched downward until the surface of the semiconductor material layer 230 is exposed, so that the gate layer 241 in the left region of the bottommost first step may be completely removed, so as to form a filling trench in a region of the second gate stack structure 240a away from the core region (a region of the left region in fig. 2 where the gate layer 241 is not disposed), where the filling trench is simultaneously filled when the surface of the first multi-step structure covers the first step covering layer 290a later. Thus, when the first contact holes are formed in the second step cover 290b of the step region, a pad contact hole may be formed in the leftmost region of the gate stack structure 240 at the same time, and the pad contact hole sequentially penetrates through the gate stack structure 240, the semiconductor material layer 230 and the isolation protection layer 220, so that the peripheral pad connection post 280c is also formed in the pad contact hole when the first word line connection post 280b is formed. It is understood that in some embodiments, the peripheral pad connection post 280c may also be formed at the time of the subsequent formation of the second word line connection post 280 a.
Referring to fig. 2, in step S10, a step of forming a vertical channel structure 260 in the gate stack structure 240 sequentially penetrating the gate stack structure 240 and extending the metal in the semiconductor material layer 230 is further included. The vertical channel structure 260 includes a filling insulation core, a channel layer surrounding the filling insulation core, and a functional sidewall surrounding the channel layer, the functional sidewall includes a blocking layer, a storage layer, and a tunneling layer sequentially formed on the sidewall of the channel hole from the sidewall to the center of the channel hole, and the semiconductor material layer 230 is located at the periphery of the channel layer and contacts with the sidewall of the channel layer. As an example, the material of the blocking layer and the tunneling layer includes silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the storage layer comprises silicon nitride; as an example, the material filling the insulating core may comprise silicon oxide.
Referring to fig. 2, in step S10, a gate line gap is formed in the gate stack structure 240 to sequentially penetrate through the gate stack structure 240, and a gate line gap filling layer formed by silicon nitride, silicon oxide, or silicon oxynitride is filled in the gate line gap, where the gate line gap may separate the three-dimensional memory structure into independent memory blocks. In addition, when the gate stack structure 240 is formed, the gate layer 241 may be replaced by the gate sacrificial layer in the gate sacrificial layer and the interlayer dielectric layer 242 which are alternately stacked based on the gate line gap to form the gate stack structure 240.
Referring to fig. 2, in step S10, after the first word line connection stud 280b is formed in the gate stack structure 240, a first interconnection layer 250 is formed on the gate stack structure 240 to form the memory array chip 200. The first interconnect layer 250 may include an inter-metal dielectric layer and first interconnect lines 251, 253, first via interconnects 252, second via interconnects 254, and first bonding contacts 255 formed in the inter-metal dielectric layer, and the top portions (lower ends in fig. 2) of the first word line connection post 280b and the channel layer of the vertical channel structure 260 and the top portions (lower ends in fig. 2) are connected to the respective first interconnect layers 250 through respective plugs; the materials of the first interconnect line 251, the second interconnect line 253, the first via interconnect 252, the second via interconnect 254, and the first bonding contact 255 include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the intermetal dielectric layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. As an example, the intermetal dielectric layer includes an interconnection line and a via interconnection gap filled in the first interconnection layer 250, the first silicon nitride layer 256, and a silicon oxide material.
Referring to fig. 2, step S20 is executed to dispose the peripheral circuit chip 100 on a side of the memory array chip 200 away from the semiconductor substrate. The peripheral circuit chip 100 includes a second semiconductor substrate 110 and any suitable digital, analog, and/or mixed signal peripheral circuits formed on the second semiconductor substrate 110 for facilitating three-dimensional memory operations. The second semiconductor substrate 110 may be, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like, such as a Silicon substrate. The peripheral circuitry may include one or more page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage reference sources, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). In this embodiment, the peripheral circuit chip 100 may be, for example, a CMOS chip, a transistor (not shown) including a CMOS structure, a second interconnect layer 130, and a peripheral circuit dielectric layer 120 are formed on the second semiconductor substrate 110, the peripheral circuit dielectric layer 120 is filled around the CMOS structure and in the second interconnect layer 130, the second interconnect layer 130 includes a peripheral interconnect line 131, a peripheral via interconnect 132, and a second bonding contact 133 formed on a surface of the peripheral circuit chip 100 away from the second semiconductor substrate 110; the materials of the peripheral interconnection line 131, the peripheral via interconnection 132, and the second bonding contact 133 include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the peripheral circuit dielectric layer 120 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof; as an example, the peripheral circuit dielectric layer 120 includes a second silicon nitride layer 134 and a silicon oxide material filled in the interconnection line and via interconnection gaps of the second interconnection layer 130. Bonding is performed through the second Bonding contacts 133 of the second interconnect layer 130 of the peripheral circuit chip 100 and the first Bonding contacts 255 of the memory array chip 200 to form a Bonding Interface (Bonding Interface) between the memory array chip 200 and the surface of the peripheral circuit chip 100, as shown by the horizontal dotted line in fig. 2.
Referring to fig. 2-7, step S30 is executed to form a second multi-step structure in the step region of the second gate stack structure 240a from a side away from the peripheral circuit chip 100, where a mesa of the second multi-step structure is away from the peripheral circuit chip 100. The method specifically comprises the following steps: step S31, for example, the first semiconductor substrate may be removed by a mechanochemical grinding process, stopping on the surface of the thinning stop layer 210, so as to completely remove the first semiconductor substrate (see fig. 2); step S32 is forming a second multi-step structure in the second gate stack structure 240a (see fig. 2-7).
In step S32, referring to fig. 2, a patterned photoresist layer 300 may be formed on the surface of the thinning-stop layer 210, wherein the patterned photoresist layer 300 has a first opening 310, and the first opening 310 is used as an etching window for forming a second multi-step structure; next, referring to fig. 3, based on the patterned photoresist layer 300, etching down to sequentially remove the thinning stop layer 210, the isolation protection layer 220, and the semiconductor material layer 230 exposed by the first opening 310, so as to expose the gate layer 241 (or the interlayer dielectric layer 242) of the second gate stack structure 240a and the adjacent stacked layer pair of the semiconductor material layer 230, thereby forming a second opening 400, where the second opening 400 defines a range of a second multi-step structure; referring to fig. 4, a step groove 500 of a second multi-step structure formed by a plurality of second steps is formed in the second gate stack structure 240a by performing a repeated etching-trimming process on the second gate stack structure 240a exposed by the second opening 400 using a patterned mask (not shown), a top surface of each second step exposes end surfaces of the interlayer dielectric layer 242 or the gate layer 241 of the corresponding stacked layer pair, the patterned mask may include a photoresist or a carbon-based polymer material, and the patterned mask may be removed after forming the steps; then, referring to fig. 5, the step trench 500 is filled with a second step covering layer 290b, which may be made of one of silicon dioxide, silicon nitride or silicon oxynitride, such as silicon dioxide; then, referring to fig. 6, the second step covering layer 290b is etched downward through photolithography and etching processes to form a plurality of second contact holes in the second step covering layer 290b of the step region, and the second contact holes expose the gate layer 241 in the corresponding second step; filling a conductive material in the second contact hole to form a second word line connection post 280a, wherein one end of the second word line connection post 280a is connected to the corresponding gate layer 241, and the other end of the second word line connection post 280a penetrates through the second step capping layer 290b to electrically connect the corresponding word line to the peripheral circuit chip 100; the material of the second word line connection stud 280a may be, for example, a conductive material including, but not limited to, any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W).
In an alternative embodiment, referring to fig. 7, after step S30, for example, a step of removing the thinning stop layer 210 by an etching process is further included, in which the thinning stop layer 210 is removed to expose the peripheral pad connection post 280c described above, and the interconnect layer of the peripheral circuit chip 100 is electrically connected to the pad formed on the surface of the memory array chip 200 away from the peripheral circuit chip 100 through the peripheral pad connection post 280 c.
It should be noted that, in the three-dimensional memory structure prepared in the first embodiment, because partial steps are respectively formed on the front surface (the side close to the peripheral circuit chip 100) and the back surface (the side far from the peripheral circuit chip 100) of the memory array chip 200, the partial step (the first multi-step structure) arranged on the front surface of the memory array chip 200 is used for leading out the gate layer 241 in the first gate stack structure 240b from the side close to the peripheral circuit chip 100, and the partial step (the first multi-step structure) arranged on the back surface of the memory array chip 200 is used for leading out the gate layer 241 in the second gate stack structure 240a from the side far from the peripheral circuit chip 100, so that the area occupied by the step region in the three-dimensional memory structure can be effectively reduced, and the storage density can be improved.
Example two
Referring to fig. 7, an embodiment of the invention further introduces a three-dimensional memory structure prepared by the preparation process of the first embodiment, wherein the three-dimensional memory structure includes a peripheral circuit chip 100, a memory array chip 200, a first multi-step structure and a second multi-step structure. The memory array chip 200 is disposed on the peripheral circuit chip 100, the memory array chip 200 includes a gate stack structure 240, the gate stack structure 240 has a core region and a step region, the gate stack structure 240 includes a first gate stack structure 240b close to the peripheral circuit chip 100 and a second gate stack structure 240a far from the peripheral circuit chip 100; the first multi-step structure is formed in the step region of the first gate stack structure 240b, with a mesa thereof facing the peripheral circuit chip 100; the second multi-step structure is formed in the step region of the second gate stack structure 240a, and the mesa of the second multi-step structure faces away from the peripheral circuit chip 100.
Referring to fig. 7, in the present embodiment, the memory array chip 200 further includes a first interconnection layer 250 formed between the gate stack structure 240 and the peripheral circuit chip 100, and the first interconnection layer 250 is used for bonding with the second interconnection layer 130 on the surface of the peripheral circuit chip 100. The first interconnect layer 250 may include an inter-metal dielectric layer, and first interconnect lines 251, 253, first via interconnects 252, second via interconnects 254, and first bonding contacts 255 formed in the inter-metal dielectric layer, and tops (lower ends in fig. 7) of the first word line connection post 280b and channel layers of the vertical channel structure 260 are connected to the respective first interconnect layers 250 through respective plugs; the materials of the first interconnect line 251, the second interconnect line 253, the first via interconnect 252, the second via interconnect 254, and the first bonding contact 255 include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the intermetal dielectric layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof; as an example, the intermetal dielectric layer includes an interconnection line and a via interconnection gap filled in the first interconnection layer 250, the first silicon nitride layer 256, and a silicon oxide material.
Referring to fig. 7, in the present embodiment, the peripheral circuit chip 100 includes a second semiconductor substrate 110 and any suitable digital, analog and/or mixed signal peripheral circuits formed on the second semiconductor substrate 110 for facilitating three-dimensional memory operations. The second semiconductor substrate 110 may be, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like, such as a Silicon substrate. The peripheral circuitry may include one or more page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers, charge pumps, current or voltage reference sources, or any active or passive component of circuitry (e.g., transistors, diodes, resistors, or capacitors). In this embodiment, the peripheral circuit chip 100 may be, for example, a CMOS chip, a transistor (not shown) including a CMOS structure, a second interconnect layer 130, and a peripheral circuit dielectric layer 120 are formed on the second semiconductor substrate 110, the peripheral circuit dielectric layer 120 is filled around the CMOS structure and in the second interconnect layer 130, the second interconnect layer 130 includes a peripheral interconnect line 131, a peripheral via interconnect 132, and a second bonding contact 133 formed on a surface of the peripheral circuit chip 100 away from the second semiconductor substrate 110; the materials of the peripheral interconnection line 131, the peripheral via interconnection 132, and the second bonding contact 133 include, but are not limited to, W, Co, Cu, Al, silicide, or any combination thereof; the peripheral circuit dielectric layer 120 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof; as an example, the peripheral circuit dielectric layer 120 includes a second silicon nitride layer 134 and a silicon oxide material filled in the interconnection line and via interconnection gaps of the second interconnection layer 130. Bonding is performed through the second Bonding contacts 133 of the second interconnect layer 130 of the peripheral circuit chip 100 and the first Bonding contacts 255 of the memory array chip 200 to form a Bonding Interface (Bonding Interface) between the memory array chip 200 and the surface of the peripheral circuit chip 100, as shown by the horizontal dotted line in fig. 7.
Referring to fig. 7, in the present embodiment, the memory array chip 200 further includes a semiconductor material layer 230 and an isolation protection layer 220, wherein the semiconductor layer is disposed on a surface of the gate stack structure 240 away from the peripheral circuit chip 100; the isolation protection layer 220 is formed on the semiconductor material layer 230; the material of the semiconductor material layer 230 may be, for example, polysilicon, and the material of the isolation protection layer 220 may be, for example, one of silicon dioxide, silicon nitride or silicon oxynitride, such as silicon dioxide.
Referring to fig. 7, in the present embodiment, the gate stack structure 240 has a core region for forming a vertical channel structure 260 for data storage and a step region located at one side (or a peripheral side) of the core region, where the step region is used to lead out a corresponding gate layer 241 through a word line connection pillar. The gate stack structure 240 includes alternately stacked interlayer dielectric layers 242 and gate layers 241, adjacent interlayer dielectric layers 242 and gate layers 241 form a stacked layer pair, and the gate stack structure 240 may include two portions, namely a first gate stack structure 240b close to the first semiconductor substrate and a second gate stack structure 240a far away from the first semiconductor substrate; the first gate stack structure 240b and the second gate stack structure 240a respectively include a plurality of level pairs. For example, in the gate stack structure 240, the number of layers of the gate layer 241 may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and specifically, the number of layers of the interlayer dielectric layer 242 and the gate layer 241 in the gate stack structure 240 may be set according to actual needs, which is not limited herein; the gate layer 241 is made of a conductive material, including but not limited to any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W); the material of the interlayer dielectric layer 242 may include, but is not limited to, silicon oxide (SiO)2) And (3) a layer. Can adoptIncluding but not limited to a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process to form the interlevel dielectric Layer 242 and the gate Layer 241.
Referring to fig. 7, in the present embodiment, a vertical channel structure 260 is disposed in a core region of the gate stack structure 240, the vertical channel structure 260 penetrates through the gate stack structure 240 and extends into the semiconductor material layer 230, the vertical channel structure includes a functional sidewall layer and a channel layer sequentially disposed from outside to inside in a radial direction, the functional sidewall includes a barrier layer, a storage layer and a tunneling layer sequentially formed on a sidewall of the channel hole from a sidewall of the channel hole to a center, and the semiconductor material layer 230 is located at a periphery of the channel layer and contacts with a sidewall of the channel layer. As an example, the material of the blocking layer, the tunneling layer comprises silicon oxide or silicon oxynitride, such as silicon oxynitride; the material of the storage layer comprises silicon nitride; as an example, the material filling the insulating core may comprise silicon oxide.
Referring to fig. 7, in the present embodiment, the memory array chip 200 further includes a gate line gap filling layer 270, and the gate line gap filling layer 270 penetrates through the gate stack structure. The gate line gap filling layer may be made of, for example, silicon nitride, silicon oxide, or silicon oxynitride, and the gate line gap filling layer may separate the three-dimensional memory structure into independent memory blocks.
Referring to fig. 7, in the present embodiment, the memory array chip 200 further includes an isolation protection layer 220 formed on the semiconductor material layer 230, and the isolation protection layer 220 may be made of one of silicon dioxide, silicon nitride or silicon oxynitride, such as silicon dioxide.
Referring to fig. 7, in the present embodiment, the three-dimensional memory structure further includes a plurality of first word line connection pillars 280b formed on first steps of each level of the first multi-level step structure, one end of each of the first word line connection pillars 280b is connected to a corresponding gate layer 241, and the other end extends to one side of the peripheral circuit chip 100 and is connected to the first interconnection layer 250 through a plug, so as to realize the leading-out of the corresponding gate layer 241; the material of the first word line connection stud 280b may be, for example, a conductive material, including but not limited to any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W).
Referring to fig. 7, in the present embodiment, the three-dimensional memory structure further includes a plurality of second word line connection pillars 280a formed on each step of the second multi-step structure, one end of each second word line connection pillar 280a is connected to the corresponding gate layer 241, and the other end extends to a side away from the peripheral circuit chip 100, so as to achieve the leading-out of the corresponding gate layer 241; the material of the second word line connection stud 280a may be, for example, a conductive material including, but not limited to, any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof, such as tungsten (W).
Referring to fig. 7, in the present embodiment, the three-dimensional memory structure further includes a first step covering layer 290a filled on the step surface of the first multi-step structure, and a second step covering layer 290b filled on the step surface of the second multi-step structure; the first wordline connection post 280b is formed in the first step cap 290a and the second wordline connection post 280a is formed in the second step cap 290 b.
Referring to fig. 7, in the present embodiment, the second three-dimensional memory structure further includes a peripheral pad connection pillar 280c, the peripheral pad connection pillar 280c is located in a region of the gate stack structure 240 away from the core region (a region of the gate layer 241 not disposed at the leftmost side in fig. 7), the peripheral pad connection pillar 280c sequentially penetrates through the gate stack structure 240, the semiconductor material layer 230 and the isolation protection layer 220, and the interconnect layer of the peripheral circuit chip 100 and a pad formed on the surface of the memory array chip 200 away from the peripheral circuit chip 100 can be electrically connected through the peripheral pad connection pillar 280 c.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for preparing a three-dimensional memory structure is characterized by comprising the following steps:
preparing a memory array chip comprising: forming a gate stack structure on a semiconductor substrate, wherein the gate stack structure is provided with a core region and a step region and comprises a first gate stack structure and a second gate stack structure positioned between the first gate stack structure and the semiconductor substrate; forming a first multi-step structure in the step region of the first gate stack structure, wherein the mesa of the first multi-step structure faces towards an external circuit chip, and a thinning stop layer is further formed between the gate stack structure and the semiconductor substrate;
after the first multi-step structure is formed, arranging a peripheral circuit chip on one side of the first grid stacking structure far away from the semiconductor substrate;
after the peripheral circuit chip is arranged, a second multi-stage step structure is formed in the step region of the second grid stacking structure from one side far away from the peripheral circuit chip, and the table top of the second multi-stage step structure is far away from the peripheral circuit chip;
wherein the step of forming a second multi-step structure in the step region of the second gate stack structure comprises:
removing the semiconductor substrate to expose the thinning stop layer;
forming a patterned light resistance layer on the surface of the thinning stop layer, wherein the patterned light resistance layer is provided with a first opening which is used as an etching window for forming a second multi-stage step structure subsequently;
etching downwards based on the patterned photoresist layer, and removing the thinning stop layer exposed by the first opening to expose the second gate stack structure;
and forming a second multi-step structure in the second gate stack structure by using an etching-trimming process.
2. The method of claim 1, wherein the peripheral circuit chip comprises a second interconnect layer;
the step of preparing the memory array chip further comprises the step of forming a first interconnection layer between the gate stack structure and the peripheral circuit chip;
the step of arranging the peripheral circuit chip on the side of the memory array chip far away from the semiconductor substrate comprises the step of bonding the peripheral circuit chip with the bonding contact of the first interconnection layer of the memory array chip through the bonding contact of the second interconnection layer.
3. The method as claimed in claim 1, wherein a semiconductor material layer is formed between the gate stack structure and the semiconductor substrate in the step of forming the gate stack structure on the semiconductor substrate.
4. The method of claim 3, wherein the material of the semiconductor material layer comprises polysilicon.
5. The method as claimed in claim 3, wherein the step of fabricating the memory array chip further comprises the step of disposing a vertical channel structure in the core region of the gate stack structure, wherein the vertical channel structure extends through the gate stack structure and into the semiconductor material layer, and the vertical channel structure comprises a functional sidewall layer and a channel layer sequentially disposed from outside to inside in a radial direction.
6. The method of claim 1, wherein the step of forming the memory array chip further comprises a step of forming a gate line gap filling layer, wherein the gate line gap filling layer penetrates through the gate stack structure.
7. The method of claim 6, wherein the gate line gap filling layer comprises silicon nitride or silicon oxide.
8. The method for fabricating a three-dimensional memory structure according to claim 1, wherein the step of fabricating a memory array chip further comprises a step of forming a first word line connection stud on each of the first steps of the first multi-step structure.
9. The method of claim 1, further comprising forming a second word line connection pillar on each second step of the second multi-step structure.
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| CN112951802A (en) * | 2021-02-22 | 2021-06-11 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN114175251B (en) | 2021-02-22 | 2023-05-02 | 长江存储科技有限责任公司 | Contact structure of three-dimensional memory device and forming method thereof |
| CN112802849B (en) * | 2021-03-29 | 2023-04-21 | 长江存储科技有限责任公司 | A kind of three-dimensional memory and its manufacturing method |
| CN115172379A (en) * | 2021-04-21 | 2022-10-11 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| KR102881610B1 (en) | 2021-05-20 | 2025-11-06 | 삼성전자주식회사 | Three-dimensional semiconductor memory device and electronic system including the same |
| EP4288996B1 (en) * | 2021-08-30 | 2025-10-01 | Yangtze Memory Technologies Co., Ltd. | Contact structure and method of forming the same |
| CN116075932B (en) | 2021-08-30 | 2025-11-11 | 长江存储科技有限责任公司 | Three-dimensional memory and method for manufacturing the same |
| CN116017984B (en) * | 2021-10-19 | 2025-12-30 | 长江存储科技有限责任公司 | Three-dimensional memory and its fabrication method |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107658317A (en) * | 2017-09-15 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor device and preparation method thereof |
| CN108377660A (en) * | 2015-12-22 | 2018-08-07 | 桑迪士克科技有限责任公司 | Through-Memory Hierarchical Via Structures for Three-dimensional Memory Devices |
| CN109155320A (en) * | 2018-08-16 | 2019-01-04 | 长江存储科技有限责任公司 | The embedded pad structure and its manufacturing method of three-dimensional storage part |
| CN109314114A (en) * | 2018-06-28 | 2019-02-05 | 长江存储科技有限责任公司 | Ladder structure for double-sided wiring in three-dimensional memory devices |
| CN109417075A (en) * | 2018-09-20 | 2019-03-01 | 长江存储科技有限责任公司 | Multi-layer stacked three-dimensional memory device |
| CN110692138A (en) * | 2019-08-02 | 2020-01-14 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
| CN111033739A (en) * | 2019-11-05 | 2020-04-17 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
| CN111146202A (en) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
| CN111492483A (en) * | 2018-08-21 | 2020-08-04 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with bonding structure connected to bit lines and method of making the same |
| WO2020171874A1 (en) * | 2019-02-18 | 2020-08-27 | Sandisk Technologies Llc | Bonded assembly including a semiconductor-on-insulator die and methods for making the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010620B (en) * | 2017-11-21 | 2021-04-13 | 长江存储科技有限责任公司 | A manufacturing method of high-stacked 3D NAND flash memory and 3D NAND flash memory |
| US10651153B2 (en) * | 2018-06-18 | 2020-05-12 | Intel Corporation | Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding |
| CN109712977B (en) * | 2019-01-15 | 2020-11-17 | 长江存储科技有限责任公司 | Three-dimensional memory device and preparation method thereof |
| JP2020150037A (en) * | 2019-03-11 | 2020-09-17 | キオクシア株式会社 | Semiconductor devices and their manufacturing methods |
| CN111403404B (en) * | 2020-03-02 | 2021-08-13 | 长江存储科技有限责任公司 | Storage structure and preparation method thereof |
-
2020
- 2020-09-30 CN CN202011058962.4A patent/CN112185981B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108377660A (en) * | 2015-12-22 | 2018-08-07 | 桑迪士克科技有限责任公司 | Through-Memory Hierarchical Via Structures for Three-dimensional Memory Devices |
| CN107658317A (en) * | 2017-09-15 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor device and preparation method thereof |
| CN109314114A (en) * | 2018-06-28 | 2019-02-05 | 长江存储科技有限责任公司 | Ladder structure for double-sided wiring in three-dimensional memory devices |
| CN109155320A (en) * | 2018-08-16 | 2019-01-04 | 长江存储科技有限责任公司 | The embedded pad structure and its manufacturing method of three-dimensional storage part |
| CN111492483A (en) * | 2018-08-21 | 2020-08-04 | 桑迪士克科技有限责任公司 | Three-dimensional memory device with bonding structure connected to bit lines and method of making the same |
| CN109417075A (en) * | 2018-09-20 | 2019-03-01 | 长江存储科技有限责任公司 | Multi-layer stacked three-dimensional memory device |
| CN111146202A (en) * | 2018-11-06 | 2020-05-12 | 三星电子株式会社 | Semiconductor device with a plurality of transistors |
| WO2020171874A1 (en) * | 2019-02-18 | 2020-08-27 | Sandisk Technologies Llc | Bonded assembly including a semiconductor-on-insulator die and methods for making the same |
| CN110692138A (en) * | 2019-08-02 | 2020-01-14 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
| CN111033739A (en) * | 2019-11-05 | 2020-04-17 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
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|---|---|
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