JP5160895B2 - 電子モジュールの製造方法 - Google Patents
電子モジュールの製造方法 Download PDFInfo
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- JP5160895B2 JP5160895B2 JP2007542017A JP2007542017A JP5160895B2 JP 5160895 B2 JP5160895 B2 JP 5160895B2 JP 2007542017 A JP2007542017 A JP 2007542017A JP 2007542017 A JP2007542017 A JP 2007542017A JP 5160895 B2 JP5160895 B2 JP 5160895B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 239000010410 layer Substances 0.000 claims description 217
- 239000004020 conductor Substances 0.000 claims description 134
- 238000000034 method Methods 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 34
- 239000012790 adhesive layer Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 5
- 239000012528 membrane Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 description 51
- 239000000853 adhesive Substances 0.000 description 50
- 239000011810 insulating material Substances 0.000 description 42
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 8
- 229920000642 polymer Polymers 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000011888 foil Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000005553 drilling Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000002848 electrochemical method Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 239000003223 protective agent Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
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- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82047—Reshaping, e.g. forming vias by mechanical means, e.g. severing, pressing, stamping
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- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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Description
本発明は特に、1つ以上の構成部品を設置ベース(基材)中に埋め込み、導体パターン構造に接続する製造方法に関するものである。製造される電子モジュールは回路ボード状のモジュールとすることができ、いくつかの構成部品を含み、これらの構成部品は、電子モジュール内に製造した導体構造を通して互いに電気的に接続されている。この電子モジュールは、いくつかの接点端子が接続された超小型回路を含むことができる。超小型回路に加えて、あるいは超小型回路の代わりに、他の構成部品、例えば受動構成部品も設置ベース中に埋め込むことができる。従ってその意図は、一般にケースに入れずに回路ボードに(回路ボードの表面に)取り付けられる構成部品を電子モジュール内に埋め込むことにある。他の重要な構成部品群は、回路ボードへの取り付け用に一般にケースに入れられた構成部品から成る。本発明が関係する電子モジュールはもちろん、他の種類の構成部品を含むこともできる。
段階Aでは、導体層4、及び導体層4の第1面上の絶縁層10から成る適切な層状膜を、プロセスの出発材料として用意する。支持層12が導体層4の一方の面上にある層状膜も出発材料として用意することができる。支持層12は随意的であり、図2のみに破線で示す。上記層状膜は、例えば、処理に適した支持ベース12を選んで、適切な導体膜をこの支持ベース12の表面に取り付けて導体層4を作ると共に、絶縁膜を取り付けて絶縁層10を作る。
絶縁層10は例えばエポキシ製とすることができる。
接触開口17は、構成部品6の電気接触に必要なバイアから作られる。接触開口17は、絶縁層10及び導体層4を通して、例えばレーザーで、あるいは穿孔によって機械的に作製される。図の実施例では、接触開口17は導体層4の第1面の向きから穿孔され、支持層12の材料まで延びる。図の実施例では、位置合わせにおける手助けとして利用することのできるバイア3を、接触開口17に加えて作製する。
段階Cでは、接着層5を絶縁層10上の、構成部品6を取り付けるべき領域内に塗布する。これらの領域を接続領域と称することがある。接着層5は例えば接触開口17を利用して位置合わせすることができる。接着層の厚さは、構成部品6を接着層5上に押圧した際に接着剤が構成部品6と絶縁層10との間の空間を完全に充たすように選択する。構成部品6が接触突起7を含む場合には、接触層5の厚さはより大きく、構成部品6と絶縁層10との間の空間が充たされるように、例えば接触突起7の高さの約1.1〜10倍にすべきである。構成部品6用に形成される接着層5の表面積は、対応する構成部品6の表面積より少し大きくすることもでき、このことは不適切な充填の恐れを軽減する手助けにもなる。
段階Dでは、構成部品6を電子モジュール内の定位置に設定する。このことは例えば、構成部品6を接着層5中に押圧する組立機(アセンブリ・マシン)を利用することによって行うことができる。この組立段階では、米国特許US 6,284,564 B1及び米国特許US 6,475,877 B1に開示された方法で進めることができるが、あらゆる場合において、接触開口17を利用して構成部品6を同等に正確に定位置に置くことができる。より概略的な位置合わせでは、バイア3または他の利用可能な位置合わせマークがボード内に作製されていれば、こうしたものを使用することもできる。
接着された構成部品6用の既製の孔2または凹部が存在する絶縁材料層1を、絶縁層10上に配置する。絶縁材料層1は適切なポリマーベースから製造することができ、このポリマーベース内には、構成部品6のサイズ及び位置に応じて選択した孔または凹部を何らかの適切な方法を用いて作製する。このポリマーベースは例えば、回路ボード産業において知られ、そして広範に使用されているプリプレグベースとすることができる。
段階Fでは、パターン化されていない絶縁材料層11を絶縁材料層1上に設定し、そして導体層9をその上に設定する。絶縁材料層1と同様に、絶縁材料層11は適切なポリマー膜、例えば上述したプリプレグベースから製造することができる。導体層9は、例えば銅箔、あるいはこの目的に適した他のいくつかの膜とすることができる。
この段階では、層1、11、及び9を、熱及び圧力を利用して加圧し、(層1及び11内の)ポリマーが、導体層4と9との間にある構成部品6の周りに一体化された強固な層を形成するようにする。この手順は第2の導体層9を非常に均一かつ平坦に作製する。
段階Hでは、導体材料を接触開口17内に成長させる。プロセスの例では、この導体材料をベース上の他の箇所にも同時に成長させ、これにより導体層4及び9の厚さも増加させる。所望すれば、この導体材料は孔3内にも成長させることができる。
段階Iでは、所望の導体パターン14及び19を、ベースの表面上の導体層4及び9から作製する。導体層4のみを用いる実施例では、ベースの一方の面上のみにパターンを形成する。導体層4のみから導体パターンを形成することによって進めることも可能である。こうした実施例では、パターン化されていない導体層9は、例えば電子モジュールを機械的に支持または保護する層として、あるいは電磁放射に対する保護として作用することができる。
Claims (10)
- 構成部品を含む回路ボード状の電子モジュールを製造する方法であって、前記構成部品は、導体パターン層に電気的に接続される少なくとも1つの接触領域を有する方法において、
少なくとも導体層、及び該導体層の第1面上の絶縁層を具えた層状膜を用意するステップと;
前記導体層及び前記絶縁層を共に貫通する接触開口を前記導体層内に作製するステップであって、前記接触開口の相互位置は、前記構成部品の各々の前記接触領域の相互位置に対応するステップと;
前記接触開口の製造後に、前記構成部品の各々を、前記層状膜の前記絶縁層の表面に取り付け、前記構成部品の前記接触領域が、これに対応する前記接触開口に位置合わせされるように、前記構成部品を位置決めするステップと;
少なくとも前記接触開口内及び前記構成部品の前記接触領域において、前記構成部品を前記導体層に接続する導体材料を作製するステップと;
前記構成部品を前記導体層に接続する導体材料を作製した後に、前記導体層をパターン化して導体パターン層を形成するステップと
を具え、
前記導体材料を作製するステップは、まず、化学的成長法を用いて、薄い金属層を成長させ、次に、電気化学的成長法を用いて、この成長を継続させることを特徴とする電子モジュールの製造方法。 - 前記接点開口を作製する前に、前記層状膜は、前記導体層、及び前記導体層の第1面上の前記絶縁層から成ることを特徴とする請求項1に記載の方法。
- 前記接点開口を作製する前に、前記層状膜は、前記導体層の第2面上に支持層を具えていることを特徴とする請求項1に記載の方法。
- 前記接点開口を作製する前に、前記層状膜の前記導体層は基本的にすべて導体材料から成り、後に前記導体層から前記導体パターン層を作製することを特徴とする請求項1〜3に記載の方法。
- 前記層状膜の前記絶縁層がエポキシ製であることを特徴とする請求項1〜4に記載の方法。
- 前記層状膜の前記絶縁層の厚さが10ミクロン以下であり、好適には4〜7ミクロンの範囲内にあることを特徴とする請求項1〜5に記載の方法。
- 前記構成部品を、接着層によって前記絶縁層に取り付けることを特徴とする請求項1〜6に記載の方法。
- 構成部品を含む回路ボード状の電子モジュールを製造する方法であって、前記構成部品は、導体パターン層に電気的に接続される少なくとも1つの接触領域を有する方法において、
少なくとも導体層、及び該導体層の第1面上の絶縁層を具えた層状膜を用意するステップと;
前記導体層及び前記絶縁層を共に貫通する接触開口を前記導体層内に作製するステップであって、前記接触開口の相互位置は、前記構成部品の各々の前記接触領域の相互位置に対応するステップと;
前記接触開口の製造後に、前記構成部品の各々を、前記層状膜の前記絶縁層の表面に取り付け、前記構成部品の前記接触領域が、これに対応する前記接触開口に位置合わせされるように、前記構成部品を位置決めするステップと;
少なくとも前記接触開口内及び前記構成部品の前記接触領域において、前記構成部品を前記導体層に接続する導体材料を作製するステップと;
前記構成部品を前記導体層に接続する導体材料を作製した後に、前記導体層をパターン化して導体パターン層を形成するステップと
を具え、
前記導体材料を作製するステップにおいて、前記接触開口に導電ペーストを充填することによって前記導体材料を形成することを特徴とする電子モジュールの製造方法。 - 前記電子モジュール内に少なくとも1つの第2導体パターン層を製造することを特徴とする請求項1〜8に記載の方法。
- 前記導体層に取り付ける少なくとも1つの前記構成部品が、パッケージで封止されていない超小型回路であることを特徴とする請求項1〜9に記載の方法。
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