JP5141393B2 - Level-up conversion circuit - Google Patents

Description

  The present invention relates to a level-up conversion circuit that levels up a small amplitude digital signal to a large amplitude digital signal.

  LSI (large scale integrated circuit) has been finely processed for high integration, and accordingly, the breakdown voltage of the gate oxide film of the transistor is lowered, and the power supply voltage of the internal logic cannot be increased. Yes. In addition, the power supply voltage of the internal logic is in the direction of lowering to reduce power consumption.

  However, in a system in which an LSI is mounted, the H level voltage of the interface signal is often required to be higher than the H level voltage of the signal in the internal logic. In this case, the power supply voltage of the I / O unit that inputs and outputs interface signals is set higher than the power supply voltage of the internal logic.

  In such a case, a signal transmission from the I / O unit to the internal logic requires a level down conversion circuit that downgrades the large amplitude digital signal to the small amplitude digital signal. Conversely, signal transmission from the internal logic to the I / O unit requires a level-up conversion circuit that levels up a large amplitude digital signal to a small amplitude digital signal.

  FIG. 11 is a circuit diagram showing an example of a conventional level-up conversion circuit. In FIG. 11, SIN is an input digital signal having a relatively small amplitude. The L (low) level voltage is 0 V, and the H (high) level voltage is a relatively low power supply voltage VDDL (for example, 1.8 V). It is what. This level-up conversion circuit receives an input digital signal SIN, and outputs a relatively large-amplitude output digital signal obtained by leveling up the H level voltage to a power supply voltage VDDH (for example, 5 V) higher than the power supply voltage VDDL. The signal SOUT is output.

  In FIG. 11, P1 is an input terminal for inputting the input digital signal SIN, INV1 is an inverter that inverts the input digital signal SIN, LUC1 is a level-up converter, and INV2 is a voltage at the node N3 of the level-up converter LUC1. Is an inverter that outputs the output digital signal SOUT, and P2 is an output terminal to which the output digital signal SOUT output from the inverter INV2 is applied.

  In the inverter INV1, N1 is an input terminal, N2 is an output terminal, L1 is a VDDL power supply line for supplying a power supply voltage VDDL, PM1 is a PMOS transistor, and NM1 is an NMOS transistor. The input terminal N1 is connected to the input terminal P1 of the level-up conversion circuit. The PMOS transistor PM1 has a source connected to the VDDL power supply line L1, a gate connected to the input terminal N1, and a drain connected to the output terminal N2. The NMOS transistor NM1 has a source grounded, a gate connected to the input terminal N1, and a drain connected to the output terminal N2.

  In the level-up conversion unit LUC1, L2 is a VDDH power supply line that supplies the power supply voltage VDDH, INPUT1 is an input circuit, LT1 is a latch circuit, and CM1 is a current mirror circuit.

  The input circuit INPUT1 has NMOS transistors NM2 and NM3. The NMOS transistor NM2 has a drain connected to the node N3, a gate connected to the input terminal P1 of the level-up conversion circuit, and a source grounded. The NMOS transistor NM3 has a drain connected to the node N4, a gate connected to the output terminal N2 of the inverter INV1, and a source grounded.

  The latch circuit LT1 includes PMOS transistors PM2 and PM3. The PMOS transistor PM2 has a source connected to the node N5, a drain connected to the node N3, and a gate connected to the node N4. The PMOS transistor PM3 has a source connected to the node N6, a drain connected to the node N4, and a gate connected to the node N3.

  The current mirror circuit CM1 has PMOS transistors PM4 and PM5. The PMOS transistor PM4 has a source connected to the VDDH power supply line L2, a drain connected to the node N5, and a gate connected to the node N5 and the gate of the PMOS transistor PM5. The PMOS transistor PM5 has a source connected to the VDDH power supply line L2 and a drain connected to the node N6.

  In the inverter INV2, N7 is an input terminal, N8 is an output terminal, PM6 is a PMOS transistor, and NM4 is an NMOS transistor. The input terminal N7 is connected to the node N3. The output terminal N8 is connected to the output terminal P2 of the level-up conversion circuit. The PMOS transistor PM6 has a source connected to the VDDH power supply line L2, a gate connected to the input terminal N7, and a drain connected to the output terminal N8. The NMOS transistor NM4 has a gate connected to the input terminal N7, a drain connected to the output terminal N8, and a source grounded.

  In this example, the NMOS transistors NM2, NM3, NM4 and the PMOS transistors PM2 to PM6 have a breakdown voltage with respect to the power supply voltage VDDH, and the gate oxide films thereof are thicker than the gate oxide films of the PMOS transistor PM1 and the NMOS transistor NM1. . The threshold voltage of the NMOS transistors NM2 and NM3 is set to 1.6 V, for example.

  12 to 14 are circuit diagrams for explaining the operation of the conventional level-up conversion circuit shown in FIG. For example, as shown in FIG. 12, when the input digital signal SIN is 0 V (L level), in the inverter INV1, the PMOS transistor PM1 is turned on and the NMOS transistor NM1 is turned off, and the output digital signal / SIN of the inverter INV1 is VDDL ( H level). As a result, in the level-up conversion unit LUC1, the NMOS transistor NM2 is turned off, the NMOS transistor NM3 is turned on, the PMOS transistor PM2 is turned on, and the PMOS transistor PM3 is turned off.

  Here, if the threshold voltage of the PMOS transistors PM2 to PM6 is Vthp, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |). Further, the potential of the node N4 is 0V. In the inverter INV2, the PMOS transistor PM6 is turned off, the NMOS transistor NM4 is turned on, and the output digital signal SOUT becomes 0V (L level).

  From this state, as shown in FIG. 13, when the input digital signal SIN changes to VDDL (H level), the NMOS transistor NM2 is turned on. In the inverter INV1, the PMOS transistor PM1 is turned off and the NMOS transistor NM1 is turned on, so that the output digital signal / SIN of the inverter INV1 changes from VDDL (H level) to 0 V (L level). Therefore, the NMOS transistor NM3 is turned off.

  As a result, a through current flows through the PMOS transistors PM4 and PM2 and the NMOS transistor NM2, and the potential of the node N3 falls from (VDDH− | Vthp |). In this case, since the gate potential of the PMOS transistor PM3 also falls from (VDDH− | Vthp |), a through current also flows through the PMOS transistors PM5 and PM3, and the potential of the node N4 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the decreasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the increasing direction. Then, the PMOS transistor PM2 is turned off, the PMOS transistor PM3 is turned on, the potential of the node N5 is (VDDH− | Vthp |), the potential of the node N3 is 0V, and the potentials of the nodes N6 and N4 are, for example, (VDDH−2). × | Vthp |). In the inverter INV2, the PMOS transistor PM6 is turned on, the NMOS transistor NM4 is turned off, and the output digital signal SOUT changes from 0 V (L level) to VDDH (H level).

  The reason why the potentials of the nodes N6 and N4 are (VDDH−2 × | Vthp |) is that the NMOS transistor NM3 has a leakage current. The magnitudes of the potentials of the nodes N6 and N4 differ depending on the size and temperature of the transistors.

  Thereafter, as shown in FIG. 14, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned off. In the inverter INV1, the PMOS transistor PM1 is turned on and the NMOS transistor NM1 is turned off, and the output digital signal / SIN of the inverter INV1 changes from 0 V (L level) to VDDL (H level). Therefore, the NMOS transistor NM3 is turned on.

  As a result, a through current flows through the PMOS transistors PM5 and PM3 and the NMOS transistor NM3, and the potential of the node N4 drops from (VDDH−2 × | Vthp |). In this case, since the gate potential of the PMOS transistor PM2 also falls from (VDDH-2 × | Vthp |), a through current flows through the PMOS transistors PM4 and PM2, and the potential of the node N3 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the increasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the decreasing direction. Then, the PMOS transistor PM2 is turned on, the PMOS transistor PM3 is turned off, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |), and the potential of the node N4 is 0V. In the inverter INV2, the PMOS transistor PM6 is turned off and the NMOS transistor NM4 is turned on, and the output digital signal SOUT changes from VDDH (H level) to 0 V (L level).

Thus, in the conventional level-up conversion circuit shown in FIG. 11, when the input digital signal SIN changes from 0 V (L level) to VDDL (H level), the output digital signal SOUT changes from 0 V (L level) to VDDH ( H level). When the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the output digital signal SOUT changes from VDDH (H level) to 0 V (L level).
JP 2006-135560 A JP 2006-279203 A

  In the conventional level-up conversion circuit shown in FIG. 11, as shown in FIG. 14, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned from ON to OFF. NM3 changes from OFF to ON, PMOS transistor PM2 changes from OFF to ON, and PMOS transistor PM3 changes from ON to OFF. The potential of the node N3 increases from 0V to (VDDH− | Vthp |), and the potential of the node N4 decreases from (VDDH−2 × | Vthp |) to 0V.

  Here, when the NMOS transistor NM3 is turned from OFF to ON, the potential of the node N5 is lower than the power supply voltage VDDH (VDDH− | Vthp |), so the source / drain of the PMOS transistor PM2 The time until the inter-voltage becomes | Vthp |, that is, the time until the PMOS transistor PM2 is turned on becomes longer. As a result, the time until the potential of the node N3 rises from 0V to (VDDH− | Vthp |) becomes longer, and the time until the output digital signal SOUT changes from VDDH (H level) to 0V (L level). It will be long.

  FIG. 15 shows a simulation of the relationship between the power supply voltage VDDH on the high voltage side and the delay time (the time from the transition of the input digital signal SIN to the transition of the output digital signal SOUT) in the conventional level-up conversion circuit shown in FIG. FIG. 6 is a diagram showing the result of the analysis, in which the low-voltage power supply voltage VDDL is 1.8V.

  In FIG. 15, Q1 is a power supply when the input digital signal SIN rises from 0V (L level) to VDDL (H level), and as a result, the output digital signal SOUT rises from 0V (L level) to VDDH (H level). The voltage VDDH vs. delay time characteristics are shown. Q2 is a power supply voltage VDDH when the input digital signal SIN falls from VDDL (H level) to 0 V (L level), and as a result, the output digital signal SOUT falls from VDDH (H level) to 0 V (L level). The delay time characteristic is shown.

  Here, the delay time when the output digital signal SOUT rises is about 1 ns when the power supply voltage VDDH is 5 V and 2.5 V, and is not greatly affected by the decrease of the power supply voltage VDDH. However, the delay time when the output digital signal SOUT falls is about 1 ns when the power supply voltage VDDH is 5V and about 30 ns when the power supply voltage VDDH is 2.5V. That is, the delay time of the fall of the output digital signal SOUT is extended about 30 times (about 1 ns → about 30 ns) when the power supply voltage VDDH is reduced from 5V to 2.5V.

  Therefore, for example, when the conventional level-up conversion circuit shown in FIG. 11 is used for clock output, the amount of change in delay time due to fluctuations in the power supply voltage VDDH due to noise or the like appears as clock jitter, and the jitter is defined (for example, In the next generation in-vehicle communication system), there is a problem of causing marginless. Further, when the power supply voltage VDDH is lowered, the delay time increases, so that there is a problem that it cannot be used for a high-speed signal line with a lowered power supply voltage.

  In view of this point, the present invention reduces fluctuations in delay time due to fluctuations in the power supply voltage on the high voltage side, and, for example, when used for clock output, reduces clock jitter and obtains high reliability. It is another object of the present invention to provide a level-up conversion circuit that can be used for a high-speed signal line in which the power supply voltage on the high voltage side is lowered.

  The level-up conversion circuit disclosed herein includes an input circuit, a latch circuit, a current mirror circuit, and a potential raising circuit. The input circuit has first and second transistors of a first conductivity type, an input digital signal is given to the gate of the first transistor, and the input digital signal is inverted to the gate of the second transistor The inverted input digital signal is provided.

  The latch circuit includes third and fourth transistors of a second conductivity type, the drain of the third transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is connected to the first transistor. Connected to the drain of the second transistor, the gate of the third transistor is connected to the drain of the fourth transistor, the gate of the fourth transistor is connected to the drain of the third transistor, and the third transistor The first output digital signal is obtained at the drain of the transistor.

  The current mirror circuit includes fifth and sixth transistors of the second conductivity type, and the source of the fifth and sixth transistors is a power supply on the high voltage side higher than the high level voltage of the input digital signal. Connected to a first power supply line for supplying voltage, connected the drain of the fifth transistor to the source of the third transistor, and connected the drain of the sixth transistor to the source of the fourth transistor. The gate of the fifth transistor is connected to the drain of the fifth transistor, or the gate of the sixth transistor is connected to the drain of the sixth transistor.

  The potential raising circuit includes seventh and eighth transistors of the second conductivity type, and the source, drain and gate of the seventh transistor are the first power line, the drain of the fifth transistor and the fifth transistor, respectively. Connected to the drain of the third transistor, and the source, drain and gate of the eighth transistor are connected to the first power line, the drain of the sixth transistor and the drain of the fourth transistor, respectively. It is.

  In the disclosed level-up conversion circuit, when the input digital signal is at an H level, the first transistor is ON, the second transistor is OFF, the third transistor is OFF, and the fourth transistor is ON. It becomes. From this state, when the input digital signal changes to L level, the first transistor is turned off, the second transistor is turned on, the third transistor is turned on, and the fourth transistor is turned off.

  Here, the seventh transistor is turned ON when the first transistor is ON, and raises the source potential of the third transistor to the power supply voltage on the high voltage side. The eighth transistor is turned on when the second transistor is turned on, and raises the source potential of the fourth transistor to the power supply voltage on the high voltage side.

  As a result, the latch state of the latch circuit changes, that is, the third transistor changes from ON to OFF and the fourth transistor changes from OFF to ON, and the third transistor turns from OFF to ON. And the fourth transistor can be smoothly changed from ON to OFF. Furthermore, when the input digital signal changes from the H level to the L level, the time during which the third transistor is turned from OFF to ON can be shortened, and the delay time of the first output digital signal can be shortened. it can.

  Therefore, according to the disclosed level-up conversion circuit, the fluctuation of the delay time of the output digital signal due to the fluctuation of the power supply voltage on the high voltage side can be reduced, and when the present invention is used for clock output, Jitter can be reduced and high reliability can be obtained. Further, even if the power supply voltage on the high voltage side is lowered, the delay time can be shortened, so that it can be used for a high-speed signal line in which the power supply voltage on the high voltage side is lowered.

  The first to third embodiments of the present invention will be described below with reference to FIGS. 1 to 4 and FIGS. 6 to 10, the same parts as those shown in FIG. 11 are denoted by the same reference numerals, and redundant description thereof is omitted.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the first embodiment of the present invention, as a level-up conversion unit, an LUC2 having a circuit configuration different from that of the conventional level-up conversion unit LUC1 shown in FIG. 11 is provided. It is comprised similarly to.

  The level-up conversion unit LUC2 is provided with a potential raising circuit composed of PMOS transistors PM7 and PM8, and the others are configured in the same manner as the level-up conversion unit LUC1 shown in FIG.

  The PMOS transistors PM7 and PM8 have the same gate oxide film as the PMOS transistors PM4 and PM5. The PMOS transistor PM7 has a source connected to the VDDH power supply line L2, a drain connected to the node N5, and a gate connected to the node N3. The PMOS transistor PM8 has a source connected to the VDDH power supply line L2, a drain connected to the node N6, and a gate connected to the node N4.

  2 to 4 are circuit diagrams for explaining the operation of the first embodiment of the present invention. For example, as shown in FIG. 2, when the input digital signal SIN is 0V (L level), the output digital signal / SIN of the inverter INV1 is VDDL (H level).

  As a result, in the level-up conversion unit LUC2, the NMOS transistor NM2 is turned off, the NMOS transistor NM3 is turned on, the PMOS transistor PM2 is turned on, the PMOS transistor PM3 is turned off, the PMOS transistor PM7 is turned off, and the PMOS transistor PM8 is turned on. In this case, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |), the potential of the node N6 is VDDH, and the potential of the node N4 is 0V. Therefore, the output digital signal SOUT is 0 V (L level).

  From this state, as shown in FIG. 3, when the input digital signal SIN changes to VDDL (H level), the NMOS transistor NM2 is turned on. Further, the output digital signal / SIN of the inverter INV1 changes from VDDL (H level) to 0 V (L level), and the NMOS transistor NM3 is turned off.

  As a result, a through current flows through the PMOS transistors PM4 and PM2 and the NMOS transistor NM2, and the potential of the node N3 falls from (VDDH− | Vthp |). In this case, since the gate potential of the PMOS transistor PM3 also falls from (VDDH− | Vthp |), a through current also flows through the PMOS transistors PM5 and PM3, and the potential of the node N4 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the decreasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the increasing direction. Then, the PMOS transistor PM2 is turned off, the PMOS transistor PM3 is turned on, the PMOS transistor PM7 is turned on, and the PMOS transistor PM8 is turned off. In this case, the potential of the node N5 is VDDH, the potential of the node N3 is 0 V, and the potentials of the nodes N6 and N4 are (VDDH− | Vthp |). Therefore, the output digital signal SOUT of the inverter INV2 changes from 0V (L level) to VDDH (H level).

  The reason why the potentials of the nodes N6 and N4 are (VDDH− | Vthp |) is that the NMOS transistor NM3 has a leakage current. The magnitudes of the potentials of the nodes N6 and N4 differ depending on the size and temperature of the transistors.

  Thereafter, as shown in FIG. 4, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned off. Further, the output digital signal / SIN of the inverter INV1 changes from 0 V (L level) to VDDL (H level), and the NMOS transistor NM3 is turned on.

  As a result, a through current flows through the PMOS transistors PM5 and PM3 and the NMOS transistor NM3, and the potential of the node N4 drops from (VDDH− | Vthp |). In this case, since the gate potential of the PMOS transistor PM2 also falls from (VDDH− | Vthp |), a through current flows through the PMOS transistors PM4 and PM2, and the potential of the node N3 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the increasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the decreasing direction. Then, the PMOS transistor PM2 is turned on, the PMOS transistor PM3 is turned off, the PMOS transistor PM7 is turned off, and the PMOS transistor PM8 is turned on. In this case, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |), the potential of the node N6 is VDDH, and the potential of the node N4 is 0V. Therefore, the output digital signal SOUT of the inverter INV2 changes from VDDH (H level) to 0 V (L level).

  Thus, in the first embodiment of the present invention, when the input digital signal SIN changes from 0 V (L level) to VDDL (H level), the output digital signal SOUT changes from 0 V (L level) to VDDH (H level). To change. When the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the output digital signal SOUT changes from VDDH (H level) to 0 V (L level).

  In the first embodiment of the present invention, as shown in FIG. 4, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned off and the NMOS transistor NM3 is turned off. To ON, the PMOS transistor PM2 changes from OFF to ON, and the PMOS transistor PM3 changes from ON to OFF. The potential of the node N3 increases from 0V to (VDDH− | Vthp |), and the potential of the node N4 decreases from (VDDH− | Vthp |) to 0V.

  Here, when the NMOS transistor NM3 changes from OFF to ON, the potential of the node N5 is the power supply voltage VDDH, unlike the conventional level-up conversion circuit (VDDH− | Vthp |) shown in FIG. . As a result, the time until the source-drain voltage of the PMOS transistor PM2 becomes | Vthp |, that is, the time until the PMOS transistor PM2 is turned on is shortened. Therefore, the time until the potential of the node N3 rises from 0V to (VDDH− | Vthp |) is shortened, and the time until the output digital signal SOUT changes from VDDH (H level) to 0V (L level) is short. Become.

  FIG. 5 shows the relationship between the power supply voltage VDDH on the high voltage side and the delay time (the time from the transition of the input digital signal SIN to the transition of the output digital signal SOUT) in the first embodiment of the present invention by simulation. It is a figure which shows a result, and is a case where the power supply voltage VDDL by the side of a low voltage is 1.8V.

  In FIG. 5, Q3 is a power supply when the input digital signal SIN rises from 0V (L level) to VDDL (H level), and as a result, the output digital signal SOUT rises from 0V (L level) to VDDH (H level). The voltage VDDH vs. delay time characteristics are shown. Q4 is a power supply voltage VDDH when the input digital signal SIN falls from VDDL (H level) to 0 V (L level), and as a result, the output digital signal SOUT falls from VDDH (H level) to 0 V (L level). The delay time characteristic is shown.

  Here, the delay time when the output digital signal SOUT rises is about 1 ns when the power supply voltage VDDH is 5 V and 2.5 V, and is not greatly affected by the decrease of the power supply voltage VDDH. The delay time when the output digital signal SOUT falls is about 1 ns when the power supply voltage VDDH is 5V, and about 2.2 ns when the power supply voltage VDDH is 2.5V. That is, the fluctuation of the delay time of the falling edge of the output digital signal SOUT due to the fluctuation of the power supply voltage VDDH is significantly smaller than that of the level-up conversion circuit shown in FIG.

  As described above, according to the first embodiment of the present invention, it is possible to reduce the variation in the delay time when the output digital signal SOUT falls due to the variation in the power supply voltage VDDH on the high voltage side. Therefore, when the first embodiment of the present invention is used for clock output, for example, clock jitter can be reduced and high reliability can be obtained. Further, even when the power supply voltage VDDH on the high voltage side is lowered, the delay time at the time of falling can be shortened, so that it can be used for a high-speed signal line in which the power supply voltage VDDH on the high voltage side is lowered.

(Second Embodiment)
FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment of the present invention, a level-up conversion unit LUC3 having a configuration different from that of the level-up conversion unit LUC2 provided in the first embodiment of the present invention is provided as a level-up conversion unit. It is comprised similarly to a form.

  The level-up conversion unit LUC3 is provided with a current mirror circuit CM2 having a configuration different from that of the current mirror circuit CM1 provided by the level-up conversion unit LUC2 shown in FIG. 1 as the current mirror circuit. The configuration is the same as LUC2.

  In the current mirror circuit CM2, the gate of the PMOS transistor PM5 is connected to the node N6 instead of connecting the gate of the PMOS transistor PM4 to the node N5, and the others are configured similarly to the current mirror circuit CM1 shown in FIG. It is.

  7 to 9 are circuit diagrams for explaining the operation of the second embodiment of the present invention. For example, as shown in FIG. 7, when the input digital signal SIN is 0V (L level), the output digital signal / SIN of the inverter INV1 is VDDL (H level).

  As a result, in the level-up conversion unit LUC3, the NMOS transistor NM2 is turned off, the NMOS transistor NM3 is turned on, the PMOS transistor PM2 is turned on, the PMOS transistor PM3 is turned off, the PMOS transistor PM7 is turned off, and the PMOS transistor PM8 is turned on. In this case, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |), the potential of the node N6 is VDDH, and the potential of the node N4 is 0V. Therefore, the output digital signal SOUT is 0 V (L level).

  The reason why the potentials of the nodes N5 and N3 are (VDDH− | Vthp |) is that the NMOS transistor NM2 has a leakage current. The magnitudes of the potentials of the node N5 and the node N3 vary depending on the size and temperature of the transistor.

  From this state, as shown in FIG. 8, when the input digital signal SIN changes to VDDL (H level), the NMOS transistor NM2 is turned on. Further, the output digital signal / SIN of the inverter INV1 becomes 0V (L level), and the NMOS transistor NM3 is turned OFF.

  As a result, a through current flows through the PMOS transistors PM4 and PM2 and the NMOS transistor NM2, and the potential of the node N3 falls from (VDDH− | Vthp |). In this case, since the gate potential of the PMOS transistor PM3 also falls from (VDDH− | Vthp |), a through current also flows through the PMOS transistors PM5 and PM3, and the potential of the node N4 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the decreasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the increasing direction. Then, the PMOS transistor PM2 is turned off, the PMOS transistor PM3 is turned on, the PMOS transistor PM7 is turned on, and the PMOS transistor PM8 is turned off. In this case, the potential of the node N5 is VDDH, the potential of the node N3 is 0 V, and the potentials of the nodes N6 and N4 are (VDDH− | Vthp |). Therefore, the output digital signal SOUT of the inverter INV2 becomes VDDH (H level).

  Thereafter, as shown in FIG. 9, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned off. Further, the output digital signal / SIN of the inverter INV1 becomes VDDL (H level), and the NMOS transistor NM3 is turned on.

  As a result, a through current flows through the PMOS transistors PM5 and PM3 and the NMOS transistor NM3, and the potential of the node N4 drops from (VDDH− | Vthp |). In this case, since the gate potential of the PMOS transistor PM2 also falls from (VDDH− | Vthp |), a through current flows through the PMOS transistors PM4 and PM2, and the potential of the node N3 rises from 0V.

  Therefore, in this case, the source-gate voltage of the PMOS transistor PM2 changes in the increasing direction, and the source-gate voltage of the PMOS transistor PM3 changes in the decreasing direction. Then, the PMOS transistor PM2 is turned on, the PMOS transistor PM3 is turned off, the PMOS transistor PM7 is turned off, and the PMOS transistor PM8 is turned on. In this case, the potentials of the nodes N5 and N3 are (VDDH− | Vthp |), the potential of the node N6 is VDDH, and the potential of the node N4 is 0V. Therefore, the output digital signal SOUT of the inverter INV2 changes from VDDH (H level) to 0 V (L level).

  Thus, in the second embodiment of the present invention, when the input digital signal SIN changes from 0 V (L level) to VDDL (H level), the output digital signal SOUT changes from 0 V (L level) to VDDH (H level). To change. When the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the output digital signal SOUT changes from VDDH (H level) to 0 V (L level).

  In the second embodiment of the present invention, as shown in FIG. 9, when the input digital signal SIN changes from VDDL (H level) to 0 V (L level), the NMOS transistor NM2 is turned off and the NMOS transistor NM3 is turned off. To ON, the PMOS transistor PM2 changes from OFF to ON, and the PMOS transistor PM3 changes from ON to OFF. The potential of the node N3 increases from 0V to (VDDH− | Vthp |), and the potential of the node N4 decreases from (VDDH− | Vthp |) to 0V.

  Here, when the NMOS transistor NM3 changes from OFF to ON, the potential of the node N5 is the power supply voltage VDDH, unlike the conventional level-up conversion circuit (VDDH− | Vthp |) shown in FIG. . As a result, the time until the source-drain voltage of the PMOS transistor PM2 becomes | Vthp |, that is, the time until the PMOS transistor PM2 is turned on is shortened. Therefore, the time until the potential of the node N3 rises from 0V to (VDDH− | Vthp |) is shortened, and the time until the output digital signal SOUT changes from VDDH (H level) to 0V (L level) is short. Become.

  As described above, according to the second embodiment of the present invention, it is possible to reduce the fluctuation of the delay time when the output digital signal SOUT falls due to the fluctuation of the power supply voltage VDDH on the high voltage side. Therefore, when the second embodiment of the present invention is used, for example, for clock output, clock jitter can be reduced and high reliability can be obtained. Further, even when the power supply voltage VDDH on the high voltage side is lowered, the delay time at the time of falling can be shortened, so that it can be used for a high-speed signal line in which the power supply voltage VDDH on the high voltage side is lowered.

(Third embodiment)
FIG. 10 is a circuit diagram showing a third embodiment of the present invention. The third embodiment of the present invention is based on the premise that the power supply voltage VDDH on the high voltage side is equal to or lower than the withstand voltage of the PMOS transistor PM1 and NMOS transistor NM1 constituting the inverter INV1.

  In the third embodiment of the present invention, the gate oxide films of the NMOS transistors NM2, NM3, NM4 and the PMOS transistors PM2 to PM8 are the same as the gate oxide films of the PMOS transistor PM1 and the NMOS transistor NM2, and the circuit configuration is the first of the present invention. This is the same as in the embodiment.

  According to the third embodiment of the present invention, when the power supply voltage VDDH on the high voltage side is equal to or lower than the withstand voltage of the PMOS transistor PM1 and the NMOS transistor NM1 constituting the inverter INV1, the output is caused by the fluctuation of the power supply voltage VDDH on the high voltage side. It is possible to reduce the fluctuation of the delay time when the digital signal SOUT falls. Therefore, when the third embodiment of the present invention is used for clock output, for example, clock jitter can be reduced and high reliability can be obtained. Further, even when the power supply voltage VDDH on the high voltage side is lowered, the delay time at the time of falling can be shortened, so that it can be used for a high-speed signal line in which the power supply voltage VDDH on the high voltage side is lowered.

  In the third embodiment of the present invention, the gate of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM4. Instead, the gate of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM5. May be.

1 is a circuit diagram showing a first embodiment of the present invention. It is a circuit diagram for demonstrating operation | movement of 1st Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of 1st Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of 1st Embodiment of this invention. It is a figure which shows the result of having analyzed the relationship between the power supply voltage by the side of the high voltage in 1st Embodiment of this invention, and delay time by simulation. It is a circuit diagram which shows 2nd Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of 2nd Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of 2nd Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of 2nd Embodiment of this invention. It is a circuit diagram which shows 3rd Embodiment of this invention. It is a circuit diagram which shows an example of the conventional level-up conversion circuit. It is a figure for demonstrating operation | movement of the conventional level-up conversion circuit shown in FIG. It is a figure for demonstrating operation | movement of the conventional level-up conversion circuit shown in FIG. It is a figure for demonstrating operation | movement of the conventional level-up conversion circuit shown in FIG. It is a figure which shows the result of having analyzed by simulation the relationship between the power supply voltage and the delay time of the high voltage side in the conventional level-up conversion circuit shown in FIG.

Explanation of symbols

SIN ... Input digital signal P1 ... Input terminal SOUT ... Output digital signal P2 ... Output terminal INV1, INV2 ... Inverter LUC1 to LUC3 ... Level-up conversion unit INPUT1 ... Input circuit LT1 ... Latch circuit CM1, CM2 ... Current mirror circuit PM1-PM8 ... PMOS transistors NM1 to NM4 ... NMOS transistors

Claims (4)

An inverted input digital signal having first and second transistors of the first conductivity type, wherein an input digital signal is given to the gate of the first transistor, and the input digital signal is inverted to the gate of the second transistor An input circuit, and
A third transistor and a fourth transistor of the second conductivity type; the drain of the third transistor is connected to the drain of the first transistor; and the drain of the fourth transistor is the drain of the second transistor. The gate of the third transistor is connected to the drain of the fourth transistor, the gate of the fourth transistor is connected to the drain of the third transistor, and the drain of the third transistor is connected to the drain of the third transistor. A latch circuit adapted to obtain a first output digital signal;
First and second transistors of the second conductivity type, and a source of the fifth and sixth transistors for supplying a power supply voltage on a high voltage side higher than a high level voltage of the input digital signal. The drain of the fifth transistor is connected to the source of the third transistor, the drain of the sixth transistor is connected to the source of the fourth transistor, and the fifth transistor A current mirror circuit in which the gate of the sixth transistor is connected to the drain of the fifth transistor or the gate of the sixth transistor is connected to the drain of the sixth transistor;
And having a second conductivity type seventh and eighth transistors, and the source, drain and gate of the seventh transistor are the first power line, the drain of the fifth transistor and the third transistor, respectively. A potential raising circuit connected to the drain, and the source, drain and gate of the eighth transistor connected to the first power line, the drain of the sixth transistor and the drain of the fourth transistor, respectively;
A level-up conversion circuit comprising: A power supply voltage that is the same voltage as the high-level voltage of the input digital signal is supplied, and has a second inverter that inverts the input digital signal and outputs the inverted input digital signal;
2. The level-up conversion circuit according to claim 1, wherein gate oxide films of the first to eighth transistors are thicker than gate oxide films of transistors constituting the inverter. A power supply voltage that is the same voltage as the high-level voltage of the input digital signal is supplied, and has a second inverter that inverts the input digital signal and outputs the inverted input digital signal;
2. The level-up conversion circuit according to claim 1, wherein the gate oxide films of the first to eighth transistors have the same thickness as the gate oxide films of the transistors constituting the inverter.   A third inverter which is supplied with the power supply voltage on the high voltage side, inputs the first output digital signal to an input terminal, and obtains a second output digital signal at an output terminal; The level-up conversion circuit according to any one of claims 1 to 3.

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