JP4954614B2 - Method for manufacturing ferroelectric memory device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

A ferroelectric memory (FeRAM) is a non-volatile memory capable of low voltage and high speed operation, and a memory cell can be composed of one transistor / one capacitor (1T / 1C), so that it can be integrated like a DRAM. Therefore, it is expected as a large-capacity nonvolatile memory. For example, Patent Document 1 discloses a contact between a tungsten plug and a capacitor (in order to prevent oxidation of the tungsten plug, which may deteriorate memory characteristics and reliability in the 1T / 1C type (stack type) ferroelectric memory device). It is described that a diffusion prevention layer is provided on the contact region) and the side wall of the capacitor electrode.
JP 2004-172330 A JP 2004-31533 A

  By the way, in a stack type ferroelectric memory device, a capacitor is formed in a region on a substrate including a plug formation region. Therefore, in order to produce a capacitor having good characteristics, a capacitor formation surface (a plug surface and its periphery). The flatness of the surface of the interlayer insulating film is extremely important. For example, Patent Document 1 describes that a CMP (Chemical Mechanical Polishing) process or an etch-back process is performed after forming a tungsten plug for such a planarization process. It is almost unsuitable for mass production. In addition, since the surface of the tungsten plug has large crystal grains, irregularities are likely to occur, and it is difficult to improve the crystal orientation of the layer formed on the surface of the tungsten plug.

  The present invention has been made in view of the above-described problems of the prior art, and provides a semiconductor device in which the crystal orientation of a device constituent layer in a semiconductor device having a conductive connection structure through a plug is improved. With the goal. It is another object of the present invention to provide a method for manufacturing a semiconductor device that can improve the crystal orientation of each layer constituting a device such as a capacitor.

The method of manufacturing a ferroelectric memory device according to the present invention includes a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, and includes the region on the plug. A method of manufacturing a ferroelectric memory device in which a first electrode, a ferroelectric film, and a second electrode are sequentially stacked in a region on an interlayer insulating film, wherein the through hole is formed in the interlayer insulating film on the substrate. Forming a plug conductive layer by burying a first conductive film made of tungsten in the through hole, and titanium nitride on the interlayer insulating film including a recess formed on the plug conductive layer Forming a second conductive film made of a material film or a titanium alloy nitride film, and subjecting the second conductive film on the interlayer insulating film to CMP to embed the second conductive film in the recess, The surface of the second conductive film is Forming an amorphous layer on a surface portion of the second conductive film, and forming a bond between hydrogen and nitrogen with respect to the second conductive film and the interlayer insulating film. A step of exciting and irradiating plasma of a gas contained in the structure; a step of forming a titanium layer having self-orientation of c-axis orientation with respect to the amorphous layer and the interlayer insulating film; and After forming, the titanium layer is nitrided by heat treatment under a nitrogen atmosphere, thereby forming a titanium nitride layer; forming a barrier layer on the titanium nitride layer; and Forming a first electrode.
In order to solve the above problems, a semiconductor device is a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, wherein the plug is A plug conductive layer embedded in the through-hole and an amorphous layer formed on the surface of the plug conductive layer, and a conductive film is formed on the amorphous layer on the plug surface. Features.
According to this configuration, since the amorphous layer is formed on the surface of the plug conductive layer and the conductive film is formed on the amorphous layer, the influence of the crystal orientation of the plug conductive layer is cut off by the amorphous layer, and the plug conductive A conductive film having crystal orientation that does not depend on the orientation of the layers can be formed. Therefore, by forming a device using the conductive film, excellent crystal orientation can be obtained for each layer constituting the device, and a high-performance device can be obtained.

Further, the semiconductor device of the present invention is a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate, wherein the plug is in the through hole. And a second conductive film embedded in a recess formed on the plug conductive layer, and a third conductive layer is formed on the amorphous layer on the plug surface. A conductive film is formed.
When the plug conductive layer is formed by embedding the first conductive film in the through hole, the surface of the plug conductive layer is formed inside the through hole from the surface of the interlayer insulating film, and a recess called a recess is formed in the plug conductive layer. May be formed on top. If the conductive film is formed directly on the plug conductive layer having such a recess, the desired crystal orientation may not be obtained due to the step difference of the recess. Therefore, in the present invention, it is possible to improve the crystal orientation of the conductive film formed on the plug by embedding the second conductive film in the recess to flatten the plug surface. Since the amorphous layer is formed on the surface of the second conductive film, the influence of the orientation state of the plug conductive layer and the second conductive film can be cut off by the amorphous layer, thereby forming the plug on the plug. Good crystal orientation can also be obtained for the conductive film to be formed.

  In the semiconductor device of the present invention, the second conductive film is a titanium nitride film or a titanium alloy nitride film. According to this configuration, excellent flatness can be obtained on the surfaces of the plug and the interlayer insulating film.

  In the semiconductor device of the present invention, the third conductive film is a titanium film or a titanium compound film. According to this configuration, since the third conductive film can be formed as a self-alignment layer, desired crystal orientation can be easily obtained in combination with the action of the amorphous layer, contributing to higher performance of the device. It becomes the composition to do.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention manufactures a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate. A method of forming the through hole in the interlayer insulating film on the substrate; forming a plug conductive layer by embedding a first conductive film in the through hole; and on the plug conductive layer Forming a second conductive film on the interlayer insulating film including the formed recess; and performing a CMP process on the second conductive film on the interlayer insulating film to embed the second conductive film in the recess. And a step of forming an amorphous layer on the surface portion of the second conductive film.
According to this manufacturing method, after the first conductive film is embedded in the through hole to form the plug conductive layer, the second conductive film is formed, and planarized by CMP treatment, thereby forming a recess on the plug conductive layer. On the other hand, the second conductive film is embedded, and by implementing the first conductive film in the through hole, good flatness on the surface of the interlayer insulating film can be obtained, and the second conductive film is included. With respect to the thin film formed in the region, it is possible to effectively prevent the disorder of the crystal orientation caused by the unevenness (step) of the formation surface. In addition, since the amorphous layer is formed on the surface of the second conductive film during the CMP process of the second conductive film, it is possible to prevent the crystal orientation of the second conductive film from affecting the crystal orientation of the thin film, and to obtain a better crystal orientation. A thin film having properties can be formed. Therefore, if a capacitor is formed on the plug conductive layer and the second conductive film, extremely good crystal orientation can be obtained for each layer constituting the capacitor.

  The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device having a conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on the substrate, Forming the through hole in the interlayer insulating film, forming a plug conductive layer by embedding the first conductive film in the through hole, and including a recess formed on the plug conductive layer. Forming a second conductive film on the interlayer insulating film; performing a CMP process on the second conductive film on the interlayer insulating film to embed the second conductive film in the recess; and Forming an amorphous layer on the surface portion of the second conductive film by performing reverse sputtering on the surface of the film and the interlayer insulating film. That is, reverse sputtering can be used as the amorphous layer forming step.

  It is preferable to form a titanium nitride film or a titanium alloy nitride film as the second conductive film. Further, TiN is preferably used as the titanium nitride constituting the second conductive film, and TiAlN is preferably used as the titanium alloy nitride. By forming the second conductive film using these materials, the recess on the plug conductive layer can be flattened easily and with high accuracy.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that the surface of the second conductive film is oxidized in the CMP process of the second conductive film. By setting it as such a manufacturing method, when performing a surface modification process with respect to a 2nd electrically conductive film, it becomes easy to make a surface modification process function effectively.

  In the method for manufacturing a semiconductor device according to the present invention, the step of irradiating the second conductive film and the interlayer insulating film by exciting a plasma of a gas having a bond of hydrogen and nitrogen in a molecular structure; It is preferable to include a step of forming a self-alignment layer made of a substance having self-orientation with respect to the interlayer insulating film including the amorphous layer on the surface of the two conductive films. In the manufacturing method according to the present invention, the surface portion of the second conductive film is formed into an amorphous layer by CMP treatment and is oxidized, so that the surface of the second conductive film is exposed by exciting and irradiating the ammonia gas plasma. An O—N—H bond in which a nitrogen atom and a hydrogen atom are bonded to a part of oxygen atoms is formed. Therefore, when the self-orientation layer is formed in the subsequent process, it is possible to inhibit the bonding of the substance having self-orientation and the oxygen atom, and the migration of the substance is promoted to improve the self-orientation. Sex can work. As a result, a self-alignment layer having extremely good crystal orientation can be formed. If a component layer of a device such as a capacitor is formed on the self-alignment layer, excellent crystal orientation can be obtained for each component layer. It is possible to manufacture a device having

  In the semiconductor device manufacturing method of the present invention, it is preferable to form a c-axis oriented titanium layer as the self-alignment layer. According to this manufacturing method, preferable crystal orientation can be obtained for the constituent layers of devices such as capacitors.

  In the production method of the present invention, it is preferable that after the titanium layer is formed, the titanium layer is subjected to nitriding treatment by heat treatment in a nitrogen atmosphere. By using such a manufacturing method, an effect of improving the oxidation resistance by previously nitriding the titanium layer and an effect of improving the contact resistance of the surface of the second conductive film oxidized by the CMP process are obtained. Thus, a semiconductor device capable of forming a device having excellent electrical characteristics and reliability can be obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Semiconductor device)
FIG. 1 is a cross-sectional view schematically showing a semiconductor device (ferroelectric memory device) 100 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 includes a ferroelectric capacitor 30, a plug 20, and a switching transistor 18 of the ferroelectric capacitor 30. In this embodiment, a 1T / 1C type (1 transistor / 1 capacitor type) memory cell is described. However, the present invention is not limited to a 1T / 1C type memory cell.

  The switching transistor 18 includes a gate insulating film 11, a gate conductive layer 13 provided on the gate insulating film 11, and a first impurity region 17 and a second impurity region 19 which are source / drain regions. The ferroelectric capacitor 30 is formed on the titanium nitride layer 12, the barrier layer 14 formed on the titanium nitride layer 12, the first electrode 32 formed on the barrier layer 14, and the first electrode 32. A ferroelectric layer 34 and a second electrode 36 formed on the ferroelectric layer 34 are provided.

  The plug 20 that electrically connects the switching transistor 18 and the ferroelectric capacitor 30 is formed in a through hole 24 formed through the interlayer insulating film 26 that covers the switching transistor 18. The second impurity region 19 and the titanium nitride layer 12 of the ferroelectric capacitor 30 are interposed. The plug 20 has a first base layer 22a provided in the through hole 24, a second base layer 22b formed on the first base layer 22a, and a hole surrounded by the second base layer 22b, for example, Plug conductive layer 22 formed by filling a first conductive film made of tungsten, molybdenum, tantalum, titanium, nickel or the like, and a second conductive film formed so as to cover the ferroelectric capacitor 30 side of plug conductive layer 22 21. The plug conductive layer 22 is preferably formed using tungsten among the metal materials mentioned above.

  In the semiconductor device according to the present invention, the illustrated upper surface of the plug conductive layer 22 is located on the inner side of the through hole 24 with respect to the surface of the interlayer insulating film 26, and a so-called recess is formed on the plug conductive layer 22. The boundary between the surface of the plug 20 and the surface of the interlayer insulating film 26 is adjusted to be flat by the second conductive film 21 formed in the recess so as to cover the plug conductive layer 22. . The second conductive film 21 is a conductive film made of titanium nitride or titanium alloy nitride, and can be specifically formed of TiN, TiAlN, or the like. In the present invention, by forming the second conductive film using these materials, the surface of the interlayer insulating film 26 in the region where the plug 20 is formed can have good flatness.

  An amorphous layer is formed on the surface portion 21a of the second conductive film 21, and the titanium nitride layer 12 is formed on the amorphous layer. Since the amorphous layer is formed on the surface portion 21a in this manner, the influence of the crystal orientation of the plug conductive layer 22 made of tungsten or the like and the crystal orientation of the second conductive film 21 made of the titanium compound is influenced by the titanium nitride layer 12. It is possible to effectively prevent the crystal orientation from being reached, and to obtain a desired crystal orientation for the titanium nitride layer 12.

  At least a part of the titanium nitride layer (third conductive film) 12 formed in a region on the interlayer insulating film 26 including the second conductive film 21 is provided on the plug 20. The titanium nitride layer 12 is crystalline and has a (111) orientation. The titanium nitride layer 12 can be formed by nitriding a Ti film, and can be made of TiN. A method for forming the titanium nitride layer 12 will be described later. The thickness of the titanium nitride layer 12 is preferably 5 nm to 20 nm.

The barrier layer 14 is not particularly limited as long as it is made of a material having conductivity and oxygen barrier properties. Examples of the material for forming the barrier layer 14 include TiAlN, TiAl, TiSiN, TiN, TaN, and TaSiN. Among these, it is more preferable to use TiAlN. When the barrier layer 14 is made of TiAlN, the composition (atomic ratio) of titanium, aluminum, and nitrogen in the barrier layer 14 is 0 <x when the composition of the barrier layer 14 is represented by the chemical formula Ti _(1-x) Al _x N _y. More preferably, ≦ 0.3 and 0 <y.

  The barrier layer 14 is preferably a crystalline thin film, and is preferably a polycrystalline film or a single crystal film having a (111) orientation. By setting the crystal orientation of the barrier layer 14 to the (111) orientation, the first electrode 32 having a crystal orientation ((111) orientation) reflecting the crystal orientation of the barrier layer 14 can be formed on the barrier layer 14. Because it can. The film thickness of the barrier layer 14 is preferably at least 20 nm, and more preferably, for example, 100 to 200 nm. This is because the first electrode 32 having a crystal orientation reflecting the crystal orientation of the barrier layer 14 at the time of film formation is satisfactorily formed on the barrier layer 14.

  The first electrode 32 can be formed using at least one metal material selected from platinum, ruthenium, rhodium, palladium, osmium, and iridium. Further, it is preferably made of platinum or iridium, more preferably made of iridium. The first electrode 32 may be a single layer film of the above metal material or a multilayer film in which a plurality of metal films are stacked. The first electrode 32 is preferably a crystalline thin film epitaxially grown on the barrier layer 14. In addition, the ferroelectric layer 34 formed on the first electrode 32 is preferably epitaxially grown on the first electrode 32.

  For example, when the barrier layer 14 belongs to a cubic system and the crystal orientation is a (111) orientation, or when the barrier layer 14 belongs to a hexagonal system and the crystal orientation is a (001) orientation, the first electrode The crystal orientation of 32 is preferably (111) orientation. According to this configuration, when the ferroelectric layer 34 is formed on the first electrode 32, the crystal orientation of the ferroelectric layer 34 can be easily set to the (111) orientation.

The ferroelectric layer 34 includes a ferroelectric material. This ferroelectric substance preferably has a perovskite crystal structure represented by the general formula of A _{1 -b} B _{1 -a} X _a O ₃ . A may contain Pb, and a part of Pb may be substituted with La. B is Zr or Ti. X is at least one metal element selected from V, Nb, Ta, Cr, Mo, W, Ca, Sr, and Mg. As the ferroelectric substance contained in the ferroelectric layer 34, a known material that can be used as the ferroelectric layer can be used. For example, (Pb (Zr, Ti) O ₃ ) (PZT), SrBi can be used. ₂ Ta ₂ O ₉ (SBT), (Bi, La) ₄ Ti ₃ O ₁₂ (BLT). Among these, the material of the ferroelectric layer 34 is preferably PZT. In this case, the first electrode 32 is more preferably iridium from the viewpoint of device reliability.

  When PZT is used as the ferroelectric layer 34, it is preferable to make the titanium content in the PZT larger than the zirconium content in order to obtain a larger amount of spontaneous polarization. PZT having such a composition belongs to tetragonal crystal, and its spontaneous polarization axis is c-axis. In this case, since an a-axis orientation component orthogonal to the c-axis is present at the same time, when PZT is oriented in the c-axis, the a-axis orientation component does not contribute to polarization reversal, and thus the ferroelectric characteristics may be impaired. . On the other hand, by setting the crystal orientation of PZT used for the ferroelectric layer 34 to the (111) orientation, the a-axis can be oriented in a direction shifted by a certain angle from the substrate normal. That is, since the polarization axis has a component in the substrate normal direction, it can contribute to polarization inversion. Therefore, when the ferroelectric layer 34 is made of PZT and the titanium content in the PZT is larger than the zirconium content, the crystal orientation of the PZT is preferably the (111) orientation in terms of good hysteresis characteristics. .

  The second electrode 36 can be formed of the above-described materials exemplified as materials usable for the first electrode 32, or aluminum, silver, nickel, or the like can be used. The second electrode 36 may be a single layer film of the metal material exemplified above, or may be a multilayer film in which a plurality of metal films are stacked. The second electrode 36 is preferably a single layer film of platinum or a laminated film of an iridium oxide film and an iridium film.

  In the semiconductor device 100 of the present embodiment, the second conductive film 21 is formed on the ferroelectric capacitor 30 side of the plug 20 to flatten the surface of the interlayer insulating film 26 on which the ferroelectric capacitor 30 is formed and the plug 20. Therefore, it is possible to effectively prevent a decrease in crystal orientation of the first electrode 32, the ferroelectric layer 34, and the like due to a step between the plug 20 and the surrounding interlayer insulating film 26, and the crystal orientation Thus, a ferroelectric memory including the high-quality ferroelectric capacitor 30 having excellent properties can be configured.

  Although details will be described later, since the amorphous layer is formed on the surface portion 21a of the second conductive film 21 in the step of forming the plug 20, the crystalline structure of the plug conductive layer 22 on the lower layer side is formed by the amorphous layer. The first electrode 32 and the ferroelectric layer resulting from the difference in material between the surface of the plug 20 and the surface of the interlayer insulating film 26 are prevented from being reflected by the crystal structure of each layer constituting the ferroelectric capacitor 30 on the side. A decrease in the crystal orientation of 34 can also be prevented. Furthermore, since the first electrode 32 of the ferroelectric capacitor 30 is provided on the plug 20 via the titanium nitride layer 12 and the barrier layer 14, the crystal structure of the lower layer (plug 20) is not reflected better. The first electrode 32 and the ferroelectric layer 34 can be formed.

  A case is assumed in which the first electrode 32 of the ferroelectric capacitor 30 is directly disposed on the plug conductive layer 22 of the plug 20. In this case, when the plug conductive layer 22 is made of a material having high crystallinity, the crystal orientation of the plug conductive layer 22 may affect the crystal orientation of the first electrode 32. For example, when the plug conductive layer 22 of the plug 20 is made of tungsten, since tungsten has high crystallinity, when the first electrode 32 is directly provided on the plug conductive layer 22 made of tungsten, the crystal structure of the plug conductive layer 22 Affects the crystal structure of the first electrode 32, making it difficult to make the first electrode 32 have a desired crystal structure. Furthermore, since the ferroelectric layer 34 is provided on the first electrode 32, the crystal orientation of the first electrode 32 may affect the crystal orientation of the ferroelectric layer 34. Then, since the crystal orientation of the ferroelectric layer 34 reflects the crystal orientation of the first electrode 32, the hysteresis characteristic of the ferroelectric capacitor 30 may be deteriorated as a result of polarization occurring in an undesired direction.

  In contrast, according to the ferroelectric capacitor 30 of the present embodiment, the second conductive film 21 is provided on the contact portion side of the plug 20 with the ferroelectric capacitor 30, and the surface of the second conductive film 21 is further provided. By forming the amorphous layer in the portion 21a, it is possible to prevent the crystal orientation of the plug conductive layer 22 of the plug 20 from being reflected in the crystal orientation of the first electrode 32 and the ferroelectric layer 34. Furthermore, since the first electrode 32 is provided on the plug 20 via the titanium nitride layer 12 and the barrier layer 14, the crystal orientation of the plug conductive layer 22 is less affected by the first electrode 32. Thereby, the ferroelectric capacitor 30 having excellent hysteresis characteristics can be obtained.

  When the cross-sectional area of the plug 20 is the same, the smaller the planar area of the ferroelectric capacitor 30 is, the smaller the ratio of the planar area of the ferroelectric capacitor 30 to the cross-sectional area of the plug 20 is. Due to this crystal orientation, the problem of crystal orientation extending to the first electrode 32 and the ferroelectric layer 34 becomes more serious. On the other hand, according to the ferroelectric capacitor 30 of the present embodiment, for the reason described above, even when the ferroelectric capacitor 30 is further miniaturized, it is useful in that a decrease in hysteresis characteristics can be prevented. It is.

  Further, according to the ferroelectric capacitor 30 of the present invention, the first electrode 32 is provided above the crystalline barrier layer 14. Thereby, the crystal orientation of the 1st electrode 32 provided on the barrier layer 14 can be improved. As a result, since the ferroelectric layer 34 having excellent crystal orientation can be provided on the first electrode 32, the hysteresis characteristics are excellent.

  In particular, as described above, when the ferroelectric layer 34 is made of PZT and the titanium content in the PZT is greater than the zirconium content, the crystal orientation of the PZT is (111) oriented in that the hysteresis characteristics are good. Is preferred. According to the ferroelectric capacitor 30 of the present embodiment, since the barrier layer 14 having the crystal orientation (111) is provided, the crystal orientation of the first electrode 32 and the ferroelectric layer 34 is (111). ) Easy to align. Thereby, the ferroelectric capacitor 30 of the present embodiment is excellent in hysteresis characteristics.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the embodiment will be described with reference to the drawings.
FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3C are cross-sectional views schematically showing an example of the manufacturing process of the semiconductor device 100 of FIG. 2 and 3, the switching transistor 18 in the semiconductor device 100 of FIG. 1 is shown in a simplified manner.

The manufacturing method of the semiconductor device 100 of the present embodiment includes the following steps S1 to S6.
(S1) A step of forming the through hole 24 in the interlayer insulating film 26 formed on the substrate 10. (S2) The first conductive film is formed on the interlayer insulating film 26 including the inside of the through hole 24, and the plug conductive layer 22 embedded in the through hole 24 by removing the first conductive film on the interlayer insulating film 26. Forming. (S3) A step of forming a second conductive film on the interlayer insulating film 26 including the recess on the plug conductive layer 22. (S4) The second conductive film on the interlayer insulating film 26 is removed by a CMP (Chemical Mechanical Polishing) process, the second conductive film is embedded in the recess on the plug conductive layer 22, and the interlayer insulation including the region where the plug 20 is formed Flattening the upper surface of the film 26; (S5) A step of converting the titanium layer into the titanium nitride layer 12 by forming a titanium layer on the plug 20 and performing heat treatment in an atmosphere containing nitrogen. (S6) A step of laminating the barrier layer 14, the first electrode 32, the ferroelectric layer 34, and the second electrode 36 on the titanium nitride layer 12.

  First, the switching transistor 18 is formed on the semiconductor substrate 10 (see FIG. 1). Next, an oxide film such as TEOS (tetraethylorthosilicate), BPSG (boron phosphorus silicate glass), NSG (non-doped silicate glass) is formed by, for example, atmospheric pressure or low pressure CVD. At this time, if the thickness of the oxide film is about 1 μm or more, the switching transistor 18 can be sufficiently covered. Subsequently, the interlayer insulating film 26 can be formed by planarizing the surface of the oxide film by CMP treatment. Thereafter, the through hole 24 is formed in the interlayer insulating film 26 using, for example, a photolithography method and a dry etching method.

  Next, a titanium film as the first underlayer 22a and a titanium nitride film as the second underlayer 22b are stacked on the interlayer insulating film 26 in which the through holes 24 are formed by using a sputtering method or the like, and further the first A tungsten film is formed as a conductive film. Next, the first base layer 22a, the second base layer 22b, and the first conductive film on the interlayer insulating film 26 are removed by CMP treatment, so that the first base layer 22a, the second base layer 22b, and the first conductive film are removed in the through hole 24 as shown in FIG. A plug conductive layer 22 is formed by embedding the first conductive film via the first base layer 22a and the second base layer 22b. At this time, a recess 24a made of a recess having a depth of about 30 nm is formed on the plug conductive layer 22 by the CMP process.

  Next, as shown in FIG. 2B, a second conductive film 121 made of titanium nitride or titanium alloy nitride, for example, TiN or TiAlN is formed on the interlayer insulating film 26 by sputtering or the like. The film thickness of the second conductive film 121 during film formation is about 100 nm to 500 nm. Next, the second conductive film 121 on the interlayer insulating film 26 is removed by CMP treatment, and the second conductive film 21 is embedded in the recess 24a as shown in FIG. In this manner, the first base layer 22a, the second base layer 22b, the plug conductive layer 22 embedded in the through hole 24, and the second conductive layer made of titanium nitride or titanium alloy nitride embedded in the recess 24a. A plug 20 having a film 21 is formed. By embedding the second conductive film 21 in the recess 24a in this manner, the upper surface of the plug 20 shown in the figure can be flush with the surface of the interlayer insulating film 26, and the ferroelectric capacitor 30 is formed in a subsequent process. A region on the substrate to be formed can be satisfactorily planarized.

In the manufacturing method according to the present invention, acidic slurry is used so that the surface of the second conductive film embedded in the recess 24a is oxidized during the CMP process of the second conductive film 121. As such a slurry, a slurry prepared by adding about twice the amount of hydrogen peroxide (H ₂ O ₂ ) added as an oxidizing agent to a slurry for polishing a metal film can be used. Then, as shown in FIG. 2 (c), titanium nitride or titanium alloy nitriding is performed on the surface portion 21a (a portion having a depth of several nm or less) of the second conductive film 21 by CMP treatment using such acidic slurry. A weak oxide layer is formed in which the product is partially oxidized. Here, for convenience, the layer constituting the surface portion 21a is called a weakly oxidized layer. This is because titanium nitride or titanium alloy nitriding on the outermost surface of the second conductive film 21 is performed by CMP treatment using an acidic slurry. This shows a state in which the crystal structure of the object is disturbed and oxygen atoms are bonded to some of the constituent elements on the outermost surface. Therefore, since the surface of the second conductive film 21 is not covered with an oxide such as titanium or aluminum constituting the second conductive film 21, the second conductive film 21 and the titanium nitride layer formed on the upper surface thereof are used. 12 is not insulated.

  In the surface portion 21a, the crystal structure of the second conductive film 21 is disturbed to form an amorphous layer. Generally, the amorphous layer has an effect of cutting off the influence of the underlying crystal orientation. In FIG. 5, the crystal orientation of tungsten constituting the plug conductive layer 22 can be cut off by the surface portion 21 a, and the orientation state of the thin film formed on the second conductive film 21 in the subsequent step is the plug conductive layer 22 to the second conductive layer. The film 21 will not be affected.

  In addition, in order to make the formation of the amorphous layer in the surface portion 21a more reliable, a reverse sputtering process may be further performed on the second conductive film 21 after the CMP process on the second conductive film 121. For example, by irradiating the surface of the second conductive film 21 and the interlayer insulating film 26 with RF plasma excited with argon gas, an amorphous layer can be easily formed on the surface portion 21a.

Next, as shown in FIG. 2D, NH ₃ plasma treatment is performed on the region on the interlayer insulating film 26 including the plug 20. The NH ₃ plasma treatment is a treatment for modifying the surface of the plug 20 by irradiating the surface of the plug 20 (surface portion 21a) and the surface of the interlayer insulating film 26 with ammonia gas plasma. By performing such surface modification treatment, a self-orientation layer can be formed by forming a self-orientation material not only on the interlayer insulating film 26 made of silicon oxide but also on the plug 20. it can. In the case of this embodiment, a titanium layer is formed as a self-alignment layer, and this is nitrided to obtain a highly oriented titanium nitride layer 12.
As the NH ₃ plasma treatment conditions in the above process, for example, the flow rate of NH ₃ gas introduced into the chamber is 350 sccm, the pressure in the chamber is 1 Torr, the substrate temperature is 400 ° C., and the high frequency of 13.56 MHz supplied to the substrate. The power of the power source is set to 100 W, the power of the 350 kHz high frequency power source supplied to the plasma generation region is set to 55 W, the distance between the electrode and the semiconductor substrate 10 is set to 350 mils, and the plasma irradiation time is set to 60 seconds.

Next, as shown in FIG. 3A, a titanium layer (self-alignment layer) 12a having a thickness of about 20 nm is formed on the plug 20 and the interlayer insulating film 26 surface-modified by NH ₃ plasma treatment by sputtering or the like. Form. The film thickness of the titanium layer 12a is preferably 5 nm to 20 nm in order to improve the orientation control of the barrier layer 14 formed on the titanium nitride layer 12 formed by nitriding the titanium layer 12a. If the thickness of the titanium layer 12a is less than 5 nm, it becomes difficult to control the barrier layer 14 to the (111) orientation. On the other hand, if the thickness of the titanium layer 12a exceeds 20 nm, the titanium layer The nitridation of 12a is difficult to proceed.

In the present embodiment, titanium, which is a self-orienting material, is c-axis aligned on the interlayer insulating film 26 and the second conductive film 21 by the previous NH ₃ plasma treatment, and the (002) -oriented titanium layer 12a is formed. Obtainable. By the way, it is known that when a titanium layer is formed without performing NH ₃ plasma treatment, good crystal orientation cannot be obtained even on the interlayer insulating film 26. This is because titanium is easily bonded to oxygen atoms, and therefore, when the film is formed without any surface modification treatment, it easily bonds to oxygen atoms on the surface of the interlayer insulating film 26, which is a silicon oxide, and the orientation axis of the titanium crystal is c. This is probably because crystal growth occurs in a state deviated from the axis.

On the other hand, the (002) -oriented titanium layer 12a can be easily obtained on the interlayer insulating film 26 by performing the NH ₃ plasma treatment. This is because the NH ₃ plasma treatment causes NH ₃ groups derived from NH ₃ to bond to oxygen atoms (O) exposed on the surface of the silicon oxide constituting the interlayer insulating film 26, thereby causing interlayer insulation. It is considered that this is because an O—N—H bond is formed on the surface of the film 26. Then, nitrogen atoms and hydrogen atoms can be bonded to the surface oxygen atoms that are easily bonded to titanium, thereby reducing the reactivity between the interlayer insulating film 26 and titanium. As a result, it is considered that the c-axis of the titanium crystal can be oriented in a direction perpendicular to the substrate.

As described above, the NH ₃ plasma treatment is extremely effective for orienting titanium or the like on the silicon oxide film, but in the present embodiment, the surface portion 21a of the second conductive film 21 is subjected to the CMP treatment. Since it is oxidized to form a weakly oxidized layer, the surface portion 21a also contains a large amount of oxygen atoms. Therefore, the NH ₃ plasma treatment described above functions effectively also on the surface portion 21a. Then, the planarizing action of the recess 24a by the second conductive film 21 described above, the effect of blocking the influence of the crystal orientation of the plug conductive layer 22 and the second conductive film 21 by the amorphous surface portion 21a, and the NH ₃ plasma. By the action of promoting titanium migration by the treatment, the (002) -oriented titanium layer 12a can be obtained even on the second conductive film 21.
Therefore, according to the manufacturing method of the present embodiment, the (002) -oriented titanium layer 12 a can be formed on the entire surface of the interlayer insulating film 26 and the plug 20.

  Next, as shown in FIG. 3B, the titanium layer 12a is nitrided by an RTA (Rapid Thermal Annealing) process in a nitrogen atmosphere to obtain the titanium nitride layer 12. The conditions for the RTA treatment are, for example, 650 ° C. and 2 minutes. This nitriding treatment has the following two effects. First, the titanium layer is oxidized by the heat treatment (recovery annealing treatment) in the oxygen atmosphere after the ferroelectric capacitor 30 is formed by nitriding in advance by the RTA treatment in this step. Can be prevented. Second, since the surface portion 21a of the second conductive film 21 is an amorphous weak oxide layer by the previous CMP process, the ferroelectric capacitor 30 and the plug 20 are caused by the surface portion 21a. Contact resistance may increase. On the other hand, by performing the RTA process, titanium can be diffused from the titanium layer 12a to the surface portion 21a simultaneously with the nitridation of the titanium layer 12a, so that the second conductive film 21 and the titanium nitride layer 12 are ohmically connected. be able to.

  Next, as shown in FIG. 3C, the constituent layers of the ferroelectric capacitor 30 are sequentially laminated on the titanium nitride layer 12, and the laminated film is patterned to manufacture the semiconductor device 100 according to the present invention. can do. The manufacturing process after the barrier layer 14 will be briefly described below.

On the titanium nitride layer 12, the barrier layer 14 made of TiAlN or the like described above is formed by sputtering or CVD. In this embodiment, since the titanium nitride layer 12 exhibits good (002) orientation, a TiAlN film epitaxially grown in the (111) orientation can be formed on the barrier layer 14.
Next, an iridium film having a thickness of, for example, 100 nm is formed on the barrier layer 14 using a sputtering method or the like, thereby forming the first electrode 32. In this embodiment, since the barrier layer 14 exhibits a good (111) orientation, an iridium film having a good (111) orientation can also be obtained for the first electrode 32.

  Next, a ferroelectric layer 34 is formed on the first electrode 32 by forming a PZT film having a film thickness of, for example, 100 nm using a spin-on method, a sputtering method, an MOCVD method, or the like. As described above, since the iridium film of the first electrode 32 exhibits a good (111) orientation, a PZT film having a good (111) orientation can also be obtained for the ferroelectric layer 34. When the content of titanium in PZT is larger than the content of zirconium, the crystal orientation of PZT is preferably a (111) orientation in terms of good hysteresis characteristics. Therefore, by setting the crystal orientation of the barrier layer 14 to the (111) orientation, both the first electrode 32 and the ferroelectric layer 34 can be set to the (111) orientation. Therefore, the ferroelectric capacitor 30 having excellent hysteresis characteristics. Can be obtained.

Next, on the ferroelectric layer 34, for example, a second electrode 36 made of a laminated film of an iridium oxide film having a thickness of 100 nm and an iridium film having a thickness of 100 nm is formed. A method of forming the second electrode 36 can be selected as appropriate according to the material of the second electrode 36, and examples thereof include a sputtering method and a CVD method.
When the formation of the above layers is completed, a resist layer having a predetermined pattern is formed on the second electrode 36, and patterning is performed by photolithography using the resist layer R1 as a mask. Thereby, the semiconductor device 100 including the stacked ferroelectric capacitor 30 is obtained (see FIG. 1). The ferroelectric capacitor 30 included in the semiconductor device 100 includes a first electrode 32 provided on the barrier layer 14, a ferroelectric layer 34 provided on the first electrode 32, and the ferroelectric layer 34. And a second electrode 36.

In addition, when the conductive connection structure to the second electrode 36 is further formed in the semiconductor device 100, the following steps may be further performed.
First, a hydrogen barrier film covering the ferroelectric capacitor 30 formed on the substrate 10 is formed by depositing aluminum oxide (AlOx) using a sputtering method or an ALD (Atomic Layer Deposition) method. Next, an interlayer insulating film that covers the hydrogen barrier film is formed by forming a silicon oxide film using PE-TEOS or HDP (high density plasma CVD), and the surface of the formed silicon oxide film is subjected to CMP. Flatten by processing. When the interlayer insulating film is formed, a through hole reaching the second electrode 36 through the interlayer insulating film and the hydrogen barrier film is formed by a photolithography method and a dry etching method. By forming the first base layer, the second base layer, and the plug conductive layer by the same formation method, a plug that contacts the ferroelectric capacitor 30 can be formed.

As described above, according to the manufacturing method of the semiconductor device 100 of this aspect, the following operational effects are obtained.
First, the titanium nitride layer 12 is formed by embedding the second conductive film 21 made of titanium nitride or titanium alloy nitride in the recess 24 a formed when the plug conductive layer 22 is embedded in the through hole 24. The surface can be satisfactorily flattened, and the deterioration of the crystal orientation of the constituent layers of the ferroelectric capacitor 30 caused by unevenness on the substrate can be prevented.
Further, in the manufacturing method of the present embodiment, an amorphous weak oxide layer is formed on the surface portion 21a of the second conductive film 21 by using acidic slurry in the CMP process when the second conductive film 21 is embedded in the recess 24a. Is forming. Since the surface portion 21a is amorphous, the crystal orientation of the lower plug conductive layer 22 and the second conductive film 21 can be cut off, and the titanium layer 12a formed on the plug 20 is brought into a desired orientation state. It becomes possible to control. Further, since the surface portion 21a is a weakly oxidized layer, the NH ₃ plasma treatment which is a surface modification process functions effectively also in the surface portion 21a, and the interlayer insulating film in which the NH ₃ plasma treatment is performed on the titanium layer 12a. Self-orientation similar to that of the 26 surface can be obtained.

  Further, the titanium layer 12a formed on the plug 20 is subjected to RTA treatment in an atmosphere containing nitrogen to convert the titanium layer 12a to the titanium nitride layer 12. Therefore, the titanium nitride layer 12 has good crystal orientation. Further, the crystal orientation of the barrier layer 14 formed on the titanium nitride layer 12 can also be improved. In addition, since the titanium layer 12a is converted into the titanium nitride layer 12 in advance by the RTA treatment, in a later process (for example, recovery annealing (heat treatment in an oxygen atmosphere) for recovering the characteristics of the ferroelectric layer 34), The titanium nitride layer 12 can be prevented from being oxidized. Furthermore, as a result of the titanium in the titanium layer 12a being diffused into the surface portion 21a of the second conductive film 21 by the RTA process, the contact resistance of the surface portion 21a, which is a weak oxide layer, can be improved.

  The semiconductor device (ferroelectric memory device) 100 includes a mobile phone, a personal computer, a liquid crystal device, an electronic notebook, a pager, a POS terminal, an IC card, a mini-disc player, a liquid crystal projector, and an engineering workstation (EWS). It can be applied to various electronic devices such as a word processor, a television, a viewfinder type or a monitor direct view type video tape recorder, an electronic desk calculator, a car navigation device, a device equipped with a touch panel, a clock, a game device, an electrophoresis device, etc. .

1 is a schematic cross-sectional view of a semiconductor device according to an embodiment. Sectional process drawing for demonstrating the manufacturing method of a semiconductor device. Sectional process drawing for demonstrating the manufacturing method of a semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Semiconductor device (ferroelectric memory device), 10 Semiconductor substrate, 12 Titanium nitride layer, 14 Barrier layer, 18 Switching transistor, 20 Plug, 21 2nd conductive film, 21a Surface part, 22 Plug conductive layer (1st conductive film) ), 22a First underlayer, 22b Second underlayer, 26 Interlayer insulating film, 30 Ferroelectric capacitor, 32 First electrode, 34 Ferroelectric layer, 36 Second electrode

Claims (3)

A conductive connection structure through a plug provided in a through hole formed in an interlayer insulating film on a substrate is provided, and a first electrode and a ferroelectric are formed in a region on the interlayer insulating film including a region on the plug A method for manufacturing a ferroelectric memory device in which a body film and a second electrode are sequentially stacked ,
Forming the through hole in the interlayer insulating film on the substrate;
Burying a first conductive film made of tungsten in the through hole to form a plug conductive layer;
Forming a second conductive film made of a titanium nitride film or a titanium alloy nitride film on the interlayer insulating film including the recess formed on the plug conductive layer;
The second conductive film on the interlayer insulating film is subjected to a CMP process, the second conductive film is embedded in the recess, and then the surface of the second conductive film is subjected to a reverse sputtering process, whereby the second conductive film Forming an amorphous layer on the surface of the film;
I have a,
Irradiating the second conductive film and the interlayer insulating film by exciting plasma of a gas having a bond of hydrogen and nitrogen in a molecular structure;
Forming a titanium layer having self-orientation of c-axis orientation with respect to the amorphous layer and the interlayer insulating film;
Forming the titanium layer by performing nitriding treatment of the titanium layer by heat treatment under a nitrogen atmosphere after forming the titanium layer;
Forming a barrier layer on the titanium nitride layer and forming the first electrode on the barrier layer;
A method for manufacturing a ferroelectric memory device , comprising: Wherein the CMP process of the second conductive film, method of manufacturing a ferroelectric memory device according to claim 1, wherein the oxidizing the surface of the second conductive film.   The method includes forming the barrier layer having a (111) orientation on the titanium nitride layer and forming the first electrode having a (111) orientation on the barrier layer. A method for manufacturing a ferroelectric memory device according to claim 1.

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