JP4840730B2 - Device tester, timing calibration method - Google Patents

Description

  The present invention relates to a device tester that calibrates signal timing in a device tester that performs an electrical test of a device under test, and a timing calibration method.

  In recent years, an integrated circuit (IC: Integrated Circuit) has been increased in capacity, speed, and size (high density). In a device having such an integrated circuit, a high-speed and complicated process is required for electrical function testing as the density of the integrated circuit increases.

  In a device tester performing such an electrical function test, a function test such as an access time margin is performed on a device under test (Device Under Test: hereinafter referred to as “DUT”), for example, various microcomputers. .

  In recent functional tests that require high-speed and complicated processes, a test signal to the DUT must also be applied with high precision at the intended timing. In order to match such timing, a variable delay circuit is usually provided between the signal generator and the driver, and the delay amount is adjusted to calibrate the timing between the signals.

  Some DUTs have a differential input and a single input, and a test signal corresponding to both inputs must be output to the DUT. However, due to the difference in electrical properties between the two signals, a separate comparator must be provided between the signal generator and the DUT, and the variable delay circuit including the timing skew caused by the variation in the characteristics of the comparators must be provided. A great deal of time was spent adjusting the amount of delay. In order to solve such a problem, a technique (for example, Patent Document 1) is disclosed in which both signals are received by a multiplexer and timing calibration is performed by a single comparator.

  On the other hand, with an increase in the density of DUTs, the number of relay cards that relay between the central control unit and the DUT and the number of modules in the relay cards are steadily increasing. The timing calibration in such a relay card will be described below.

  FIG. 8 is a functional block diagram showing a schematic function of a conventional device tester 10 for performing timing calibration. In the device tester 10, a test signal output from each relay card 14 is output to the DUT 16 in response to a control signal from the central control unit 12, and an input signal from the DUT 16 is captured by the relay card 14. Specifically, the test signal generated by the integrated circuit 20 is output from the output driver 24 to the DUT 16 through the output variable delay circuit 22, and the input signal from the DUT 16 is input to the input flip-flop 32 through the input comparator 30. A signal latched by the strobe signal delayed by the input variable delay circuit 34 is taken into the integrated circuit 20.

  In the calibration of the output timing of the test signal in the device tester 10, the output of the output driver 24 of the relay card 14 is received by the reference comparator 42 of the reference card 40, and the received signal and the reference strobe are received by the reference flip-flop 44. The output variable delay circuit 22 is adjusted by comparing the latch timing with the signal.

  In the calibration of the input timing, the reference signal output from the reference driver 46 of the reference card 40 is received by the input comparator 30, and the input flip-flop 44 uses the reference signal and the slope signal from the input variable delay circuit 34. The input variable delay circuit 34 is adjusted by comparing with the latch timing.

Further, the reference signal, the output driver 24 and the input comparator 30 are connected via a relay tournament 50 of the reference card 40 and a relay tournament 52 of the relay card 14.
JP 2006-071290 A

  In the conventional timing calibration as described above, the relay tournaments 50 and 52 are connected in a one-to-one relationship, so that the reference signal, the output driver, and the input comparator are always in a one-to-one relationship. Therefore, as the total calibration time, the number of relay cards 14 M × the number of pins in the relay card 14 × unit calibration time is required. Since the calibration time becomes longer as the DUT becomes more accurate, the test efficiency is lowered.

  As a result of earnestly examining the above problem, the inventors of the present application pay attention to the fact that no other relay card is processed while the specific relay card is compared with the reference signal, and the reference signal is sent to each relay card. It has been found that the calibration time can be shortened by transferring once, and the present invention has been completed.

  The present invention has been made in view of the above-described problems of conventional device testers. The object of the present invention is to transfer a reference signal into a relay card and adjust a variable delay circuit in parallel for each relay card. Thus, there is provided a new and improved device tester and timing calibration method capable of completing timing calibration in a short time and improving test efficiency.

In order to solve the above-described problems, according to an aspect of the present invention, there is provided a device tester for performing an electrical test of a device under test, comprising a relay card including a plurality of modules including an output unit and an input unit, A reference card that supplies a reference timing serving as a reference for output, and the relay card further includes a first relay relay that connects an arbitrary module of the plurality of modules and the reference card, an arbitrary module, and another module. A second relay relay that can switch the connection of the modules in a one-to-multiple manner, and based on the reference timing, any module of each of the plurality of relay cards is calibrated, and each of the plurality of relay cards is based on any module in parallel A device tester is provided in which other modules are calibrated.

  Here, the reference timing is temporarily transferred to an arbitrary module in the relay card, and other modules are adjusted based on the reference timing. Accordingly, calibration on the relay board can be executed in parallel with other relay boards, and timing calibration can be completed in a short time.

In order to solve the above problems, according to another aspect of the present invention, there is provided a device tester for performing an electrical test of a device under test, an output variable delay circuit for adjusting a delay of a signal to the device under test, and a delay A plurality of output units including an output driver for outputting the signal to the device under test, an input comparator for inputting the signal from the device under test, and an input variable delay circuit for adjusting the output signal of the input comparator to adjust the delay of the strobe signal. A plurality of input units each composed of an input flip-flop latched by a delay signal; a first relay relay that connects a sub-reference output unit that is one of a plurality of output units and a reference card; and one of a plurality of input units A second relay relay capable of switching connection between the sub-reference output unit, a sub-reference input unit constituting one module, and other output units excluding the sub-reference output unit. A plurality of relay card with bets, a reference comparator for inputting a signal from the output driver, a reference input section consisting of a reference flip-flop for latching the reference strobe signal the output signal of the reference comparator, the output variable delay circuit and an input comprising a central control unit to calibrate the variable delay circuit, a central control unit, to the reference input section based calibrate the output variable delay circuit sub-reference output unit arbitrary output unit, based on the sub-reference output unit The input variable delay circuit of the sub-reference input unit is calibrated, and a plurality of relay cards each calibrate the output variable delay circuit of the output unit other than the sub-reference output unit in parallel with the sub-reference input unit as a reference. A device tester is provided.

  The reference timing can be transferred by connecting the input unit and the output unit. Therefore, in the present invention, in order to transfer the reference timing to all the output units, (1) transfer to any output unit, (2) transfer from any output unit to the input unit, and (3) all other from the input unit. Has been moved to the output section. With such a three-stage transition configuration, once the reference timing is shifted to an arbitrary output unit, the reference input unit becomes unnecessary and can be used for other purposes.

  In the present invention, one of the existing output units for outputting a test signal to the device under test is used as an arbitrary output unit that relays the transition of the reference timing. Therefore, the object of the present invention can be achieved without newly providing a relay circuit, and the cost and occupied area can be reduced.

  The central control unit sequentially calibrates the output variable delay circuit of any output unit of each of the plurality of relay cards with the reference input unit as a reference, and the plurality of relay cards are input in parallel with each of the arbitrary output units. The input variable delay circuit of the output unit can be calibrated, and the output variable delay circuit of the output unit other than the arbitrary output unit can be calibrated with reference to the input unit.

  Here, by transferring the reference timing to each relay card, first, the reference timing corresponding to the number of relay cards is created, and the transferred reference timing is transferred to the calibration target circuit in parallel with each relay card. Therefore, timing calibration can be completed in a short time, and test efficiency can be improved. For example, when M relay cards and the number of pins N in the relay card 14 are N, the calibration time, which conventionally takes M × N, is M + N.

  It is also possible to calibrate the input variable delay circuits of a plurality of input units with a plurality of input units with reference to an arbitrary output unit.

  With this configuration, all input units in addition to all output units can be adjusted together, and the calibration time can be further shortened.

In order to solve the above problems, according to another aspect of the present invention, there is provided a device tester for performing an electrical test of a device under test, an output variable delay circuit for adjusting a delay of a signal to the device under test, and a delay A plurality of output units including an output driver for outputting the signal to the device under test, an input comparator for inputting the signal from the device under test, and an input variable delay circuit for adjusting the output signal of the input comparator to adjust the delay of the strobe signal. A plurality of input units each composed of an input flip-flop latched by a delay signal; a first relay relay that connects a sub-reference input unit that is one of the plurality of input units and a reference card; and one of a plurality of output units a is a second relay relay for connecting the other input portion except for the sub-reference output unit and the sub-reference input portion constituting the single module the sub reference input section A plurality of relay cards obtaining a reference driver for outputting a reference signal, and a central control unit to calibrate the output variable delay circuit and the input variable delay circuit, the central control unit, the sub-reference input and a reference driver to reference calibrate input variable delay circuit parts to calibrate the output variable delay circuit sub-reference output unit with respect to the sub-reference input unit, the sub-reference input with respect to the sub-reference output unit a plurality of relay cards are each parallel A device tester is provided that calibrates an input variable delay circuit of an input unit other than the unit.

  In the present invention, in order to transfer the reference timing to all input units, (1) transfer to any input unit, (2) transfer from any input unit to the output unit, and (3) all other inputs from the output unit. Moved to the department. With such a three-stage transition configuration, once the reference timing is shifted to an arbitrary input unit, the reference driver is not necessary and can be used for other purposes.

  Further, a timing calibration method for calibrating the timing of the signal of the device tester using the above-described device tester is also provided.

  The component corresponding to the technical idea in the device tester described above and the description thereof can also be applied to the timing calibration method.

  As described above, the device tester according to the present invention transfers the reference timing in the relay card and adjusts the variable delay circuit in parallel for each relay card, thereby completing the timing calibration in a short time and improving the test efficiency. It becomes possible to do.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  After setting the DUT, the device tester according to the embodiment of the present invention applies a test signal to the DUT according to a pattern program in which the test order is written, and acquires a signal output from the DUT accordingly. In order to facilitate understanding regarding such DUT testing, the overall structure of the device tester will be described first.

(First embodiment: device tester 100)
FIG. 1 is a block diagram illustrating a schematic configuration of a device tester 100 according to the first embodiment. The device tester 100 includes a main body 110 and a test head 120. A performance board 130 is placed on the test head 120, and a DUT 140 is placed on the performance board 130. In the present embodiment, the DUT 140 is an SOC (System On Chip) IC, for example, a digital IC such as a microcomputer or an ASIC.

  The main body 110 is provided with a central control unit 114 that performs a test process set through a user interface 112. The test head 120 is also referred to as a relay card (PE (Pin Electronics) card) including, for example, a test terminal connected to each device terminal of the DUT 140 and a pin module connected to the test terminal and performing a test function in units of 32. .) 122 is provided. The relay card 122 reflects a command related to the function test from the main body 110 on the test terminal.

  The performance board 130 can be fitted to the test head 120 and can be mounted with the DUT 140, and electrically connects a plurality of test terminals to the device terminals of the DUT 140.

  In the present embodiment, the central control unit 114 applies a test signal to the DUT 140 via the relay card 122 and captures a signal from the DUT 140. At this time, the device tester 100 determines how much the test target DUT 140 is deviated from the intended operation timing and whether the deviation is within an allowable range.

  However, there may be a timing skew (timing deviation) in output or input to the DUT 140 through aging of the device or temperature change with time. Such a timing skew causes the normal DUT 140 to be determined to be abnormal or causes the abnormal DUT 140 to be determined to be normal, which causes a problem that the functional test of the DUT 140 cannot be performed accurately. Therefore, the central control unit 114 calibrates the output or input timing to a normal timing before starting the test of the DUT 140 in order to suppress such timing skew.

  Such timing calibration may be performed periodically every predetermined time, or may be performed temporarily before starting the test or after replacing parts. However, the timing calibration as in the present embodiment does not need to be frequently performed for the calibration of the DC level. For example, the frequency can be once a day to several months.

  Hereinafter, the input / output system will be described based on the functional blocks of the relay card 122, and the timing calibration of each circuit therein will be described.

  FIG. 2 is a functional block diagram showing a schematic function of the device tester 100. According to the functional block diagram, the device tester 100 includes a central control unit 114, a relay card 122, and a reference card 144, and the relay card 122 is connected to the DUT 140.

  The central control unit 114 includes an integrated circuit such as a CPU, and manages and controls the entire device tester 100. Further, input / output of a test signal to the DUT 140 of the relay card 122 is controlled according to a test program for performing the test. Further, at the time of timing calibration, a control signal is transmitted to the relay card 122 and the reference card 144 to support the transfer of the reference timing performed by the connection between them.

  The relay card 122 includes an integrated circuit 150, an output unit 152, an input unit 154, a sub reference output unit 170, a sub reference input unit 172, a first relay relay 180, and a second relay relay 182. Consists of.

  Here, the integrated circuit 150 decodes the control signal from the central control unit 114, generates a test signal to be applied to the DUT 140 and a strobe signal for latching the signal from the DUT 140, and captures the latched signal. .

  The output unit 152 delays the test signal output from the integrated circuit 150 to the DUT 140 by a delay amount adjusted by timing calibration described later, and outputs the test signal thus delayed to the DUT 140. And such combinations are provided for the number of N pins to be output to the DUT 140. A sub-reference output unit 170 described later is a part of the output unit 152. A combination of the output unit 152 and the input unit 154 can also be expressed in units of modules.

  The input unit 154 includes an input comparator 164 that inputs a signal from the DUT 140, and an input flip-flop 168 that latches the output signal of the input comparator 164 with a delay signal from the input variable delay circuit 166. There are provided as many as N pins to be output to the DUT 140. The input variable delay circuit 166 delays the strobe signal output from the integrated circuit 150 by a delay amount adjusted by timing calibration described later. Further, a sub-reference input unit 172 described later is a part of the input unit 154.

  Similar to the output unit 152, the sub-reference output unit 170 includes an output variable delay circuit 160 and an output driver 162, and functions as the output unit 152 in normal times. On the other hand, at the time of timing calibration, the reference timing is transferred from the reference card 144 prior to the other output unit 152 and becomes a reference for the sub-reference input unit 172 and other input units 154.

  Similar to the input unit 154, the sub-reference input unit 172 includes an input comparator 164, an input variable delay circuit 166, and an input flip-flop 168, and functions as the input unit 154 in a normal state. On the other hand, at the time of timing calibration, the reference timing is transferred from the sub reference output unit 170 prior to the other input unit 154 or simultaneously with the other input unit 154, and the other output units 152 except for the sub reference output unit 170 The standard.

  The first relay relay 180 plays a role of connecting both when the reference timing is transferred from the reference card 144 to the sub-reference output unit 170 at the time of timing calibration.

  The second relay relay 182 is configured by a relay tournament capable of switching one to a plurality of connections, and the reference timing is set from the sub reference input unit 172 to the other output units 152 excluding the sub reference output unit 170 at the time of timing calibration. Connect both when transferred. The second relay relay 182 and a reference relay described later may be configured by connecting a plurality of 1 to 4 relay tournaments in a tree.

  The reference card 144 is connected to a plurality of relay cards 122 and provides a reference timing for adjusting the delay amounts of the output variable delay circuit 160 and the input variable delay circuit 166 in each relay card 122. The reference card 144 in this embodiment is configured by a relay tournament that can switch connection between the integrated circuit 190 that receives the control signal from the central control unit 114 and controls the reference card 144 and a plurality of relay cards 122. It includes a reference relay 192, a reference comparator 194 that receives a signal from the output driver 162, and a reference input unit 198 that includes a reference flip-flop 196 that latches the output signal of the reference comparator 194 with a reference strobe signal.

  In the present embodiment, the timing calibration of at least the output unit 152 in the relay card 122 is executed with the configuration as described above, and at the time of the test, the DUT 140 can be tested at the correct timing thus calibrated.

  In the above-described timing calibration, in order to transfer the reference timing set in the reference card 144 to all the output units 152, (1) the reference timing is transferred to the sub-reference output unit 170 as an arbitrary output unit 152, and (2 3) a three-step procedure is performed, in which the sub-reference output unit 170 is transferred to a sub-reference input unit 172 as an arbitrary input unit 154, and (3) the sub-reference input unit 172 is transferred to all other output units 152. Hereinafter, the three-stage timing calibration will be described in detail with reference to FIGS.

  FIG. 3 is a functional block diagram for explaining the transition of the reference timing from the reference input unit 198 to the sub-reference output unit 170. The bold line in the figure represents the first-stage transition. According to FIG. 3, since the first relay relay 180 is closed and the reference relay 192 is connected to the relay card 122, the output variable delay circuit 160 of the sub reference output unit 170 includes the output driver 162 and the first relay. The relay 180 is connected to a reference flip-flop 196 through a reference relay 192 of the reference card 144 and a reference comparator 194.

  In the reference card 144, the integrated circuit 190 applies a reference timing to the clock terminal of the reference flip-flop 196, and takes in the output of the reference comparator 194 latched by the reference timing.

  The central control unit 114 calibrates the output variable delay circuit 160 of the sub reference output unit 170 in the relay card 122 based on this reference timing. Specifically, the delay amount of the output variable delay circuit 160 of the sub-reference output unit 170 is adjusted, the timing of the output signal from the output driver 162 is changed little by little, and the output signal of the reference flip-flop 196 in the reference card 144 is inverted. The adjustment of the delay amount is stopped when the change timing between the output signal from the output driver 162 and the reference timing becomes equal. The delay amount at this time becomes the calibration value of the output variable delay circuit 160, and the output signal of the sub reference output unit 170 indicates the reference timing in the same manner as the reference card 144.

  Further, the timing calibration shown in FIG. 3 is performed on the output variable delay circuit 160 of the sub-reference output unit 170 of all the M relay cards 122 by sequentially switching the reference relay 192. Therefore, this timing calibration requires unit calibration time × M calibration times.

  In addition, once the reference timing is transferred to the sub-reference output unit 170, the reference input unit 198 is not necessary, so that the reference card 144 and the relay card 122 can be separated and used for another purpose.

  FIG. 4 is a functional block diagram for explaining the transition of the reference timing from the sub reference output unit 170 to the sub reference input unit 172. According to FIG. 4, the first relay relay 180 that was closed in FIG. 3 is opened, and the output variable delay circuit 160 of the sub reference output unit 170 is input to the sub reference input unit 172 through the output driver 162 and the input comparator 164. The flip-flop 168 is connected.

  In the relay card 122, the integrated circuit 150 applies a strobe signal to the clock terminal of the input flip-flop 168, and takes in the output of the input comparator 164 latched by the strobe signal.

  The central control unit 114 adjusts the delay amount of the input variable delay circuit 166 of the sub-reference input unit 172, changes the timing of the strobe signal little by little, and when the output data from the input flip-flop 168 is inverted, that is, the output The adjustment of the delay amount is stopped when the change timings of the output signal as the reference timing from the driver 162 and the delayed strobe signal become equal. The delay amount at this time becomes the calibration value of the input variable delay circuit 166, and the strobe signal of the sub reference input unit 172 indicates the reference timing in the same manner as the reference card 144 and the sub reference output unit 170.

  Further, the timing calibration shown in FIG. 4 is performed in parallel on each of the M relay cards 122. Therefore, the timing calibration requires a calibration time corresponding to the unit calibration time.

  FIG. 5 is a functional block diagram for explaining the transition of the reference timing from the sub reference input unit 172 to the output unit 152 other than the sub reference output unit 170. According to FIG. 5, the second relay relay 182 sequentially switches the output unit 152 connected to the sub reference input unit 172, and the output variable delay circuit 160 of the other output unit 152 includes the output driver 162, the second relay relay 182, The input comparator 164 is connected to the input flip-flop 168 of the sub reference input unit 172.

  Then, in the relay card 122, the integrated circuit 150 applies a strobe signal to the clock terminal of the input flip-flop 168 of the sub-reference input unit 172 through the input variable delay circuit 166 whose delay amount is calibrated as described above. The output of the input comparator 164 latched by the strobe signal is taken in.

  The central control unit 114 calibrates the output variable delay circuit 160 of the other output unit 152 based on the strobe signal. Specifically, in each of the other output units 152, the delay amount of the output variable delay circuit 160 is adjusted, the timing of the output signal from the output driver 162 is changed little by little, and the input flip-flop 168 of the sub-reference input unit 172 is changed. The adjustment of the delay amount is stopped when the output signal is inverted, that is, when the change timing between the output signal from the output driver 162 and the delayed strobe signal (reference timing) becomes equal. The delay amount at this time becomes the calibration value of the output variable delay circuit 160 in the other output unit 152, and the reference timing is reflected in all the output signals of the other output units 152.

  Further, the timing calibration shown in FIG. 5 is performed in parallel on each of the M relay cards 122, similarly to the timing calibration shown in FIG. Therefore, the timing calibration requires unit calibration time × (N−1) pin calibration time equal to the number of other output units 152.

  As described above, in this embodiment, by transferring the reference timing to each relay card 122, first, the reference timing corresponding to the number of relay cards 122 is created, and the transferred reference timing is transferred in parallel to each relay card 122. Is transferred to a circuit to be calibrated, here another output unit 152. Therefore, timing calibration can be completed in a short time, and test efficiency can be improved.

  In the case where the number of relay cards 122 is M and the number of pins in the relay card 122 is N, the calibration time, which conventionally takes M × N, is shortened to M + 1 + (N−1), that is, M + N. For example, when there are 32 relay cards 122 and the number of pins by one relay card 122 is 16, the conventional calibration time was 32 × 16 and 512 times of calibration, but in this embodiment, 32 + 16 and 48 times of processing. Just do it. Such a calibration time becomes more effective as the number of M and N increases.

  In the present embodiment, as described above, one of the output units 152 that outputs the test signal to the DUT 140 is used as the sub-reference output unit 170 that relays the transition of the reference timing. Therefore, the object of the present embodiment can be achieved without newly providing a relay circuit, and the cost and occupied area can be reduced.

  Further, in this embodiment, the input variable delay circuit 166 may be calibrated with respect to the input unit 154 except the sub reference input unit 172 with reference to the sub reference output unit 170. With this configuration, in addition to all the output units 152, all the input units 154 can be adjusted together, and the order of adjustment includes (1) the sub reference output unit 170 and (2) all the inputs including the sub reference input unit 172. By using all the output units 152 except the unit 154 and (3) the sub-reference output unit 170, the calibration time can be further shortened.

  In the three-stage timing calibration of the present embodiment, the error that occurs when the reference timing is transferred is three times that of the conventional calibration. However, this error is not a problem because it is negligibly small compared to the required timing accuracy.

(Timing calibration method)
Further, a timing calibration method for calibrating the timing of the signal of the device tester 100 using the device tester 100 described above is also provided.

  FIG. 6 is a flowchart showing the overall flow of the timing calibration method. In the timing calibration method, first, the reference comparator 194 of the reference card 144 and any one of the M relay cards 122 are connected through the reference relay 192 and the first relay relay 180, and the reference card 144 has a reference. Based on the timing (reference signal), the output variable delay circuit 160 of the sub-reference output unit 170, which is an arbitrary output unit of the relay card 122, is calibrated (S600). When such calibration is completed, it is determined whether calibration has been completed for all M relay cards 122 (S602). If not completed, the reference relay 192 is switched to the next relay card 122, and the sub-card of the relay card 122 is switched. The reference output unit 170 is calibrated.

  When calibration of all M relay cards 122 is completed, each relay card 122 starts timing calibration of other calibration target circuits in the relay card 122 in parallel. Here, first, the input variable delay circuit 166 of the sub-reference input unit 172, which is an arbitrary input unit, is calibrated using the sub-reference output unit 170 as a reference (S604).

  Subsequently, the output variable delay circuit 160 in any of the output units 152 other than the sub reference output unit 170 is calibrated using the sub reference input unit 172 as a reference (S606). When such calibration is completed, it is determined whether calibration has been completed for all N−1 output units 152 except for the sub-reference output unit 170 (S608). If not completed, the second relay relay 182 is connected to the next output unit. Then, the output variable delay circuit 160 of the output unit 152 is calibrated. When calibration is completed for all N-1 output units 152, the timing calibration method is terminated.

  As described above, the timing calibration process shown in S600 is performed M times, the timing calibration shown in S604 is performed once, the timing calibration shown in S606 is performed N-1 times, and the calibration is performed as shown in the description of the device tester 100. Time can be completed with M + N only.

(Second Embodiment: Device Tester)
In the first embodiment, the output unit 152 and the input unit 154 in the relay card 122 are calibrated using the reference input unit 198 of the reference card 144. However, a signal from the reference driver of the reference card 144 is used. It is also possible. In the second embodiment, the output unit 152 and the input unit 154 in the relay card 122 are calibrated by a signal from the reference driver of the reference card 144.

  FIG. 7 is a functional block diagram showing a schematic function of the device tester 700 in the second embodiment. According to such a functional block diagram, the device tester 700 includes a central control unit 114, a relay card 122, and a reference card 702.

  Since the central control unit 114 and the relay card 122 already described as constituent elements in the first embodiment have substantially the same functions, a duplicate description is omitted. Here, the reference card 702 having a different configuration is mainly used. explain.

  The reference card 702 is connected to a plurality of relay cards 122 and provides a reference timing for adjusting the delay amounts of the output variable delay circuit 160 and the input variable delay circuit 166 in each relay card 122. The reference card 702 in the present embodiment is configured by a relay tournament that can switch connection between the integrated circuit 190 that receives the control signal from the central control unit 114 and controls the reference card 702 and a plurality of relay cards 122. A reference relay 192 and a reference driver 710 that outputs a reference signal are included.

  In the second embodiment, in order to transfer the reference timing to all the input units 154, the reference timing is (1) transferred to the sub-reference input unit 172 as an arbitrary input unit 154, and (2) the sub-reference input unit 172. To the sub-reference output unit 170, which is an arbitrary output unit 152, and (3) from the sub-reference output unit 170 to all other input units 154. With such a three-stage transition configuration, once the reference timing is transferred to the arbitrary input unit 154, the reference driver 710 is not necessary and can be used for another purpose.

  Of the three stages of calibration, only the transition from the reference driver 710 to the sub-reference input unit 172 will be described here. First, the first relay relay 180 is closed, the reference relay 192 is connected to the relay card 122, and the reference driver 710 of the reference card 702 is passed through the reference relay 192, the first relay relay 180 of the relay card 122, and the input comparator 164. It is connected to the input flip-flop 168 of the sub reference input unit 172.

  In the relay card 122, the integrated circuit 150 applies a strobe signal to the clock terminal of the input flip-flop 168, and takes in the output of the input comparator 164 latched by the strobe signal.

  The central control unit 114 adjusts the delay amount of the input variable delay circuit 166 of the sub-reference input unit 172, changes the timing of the strobe signal little by little, and when the output data from the input flip-flop 168 is inverted, that is, the reference When the change timing between the reference timing from the driver 710 and the delayed strobe signal becomes equal, the adjustment of the delay amount is stopped. The delay amount at this time becomes the calibration value of the input variable delay circuit 166, and the strobe signal of the sub reference input unit 172 indicates the reference timing in the same manner as the reference card 702.

  Subsequently, as described in the first embodiment, the M relay cards 122 are calibrated in parallel with each other in parallel with the sub reference input unit 172 calibrated above as a reference. Then, the input variable delay circuit 166 of the input unit 154 other than the sub reference input unit 172 is calibrated using the sub reference output unit 170 as a reference.

  The device tester 700 can transfer the reference timing into the relay card 122 and adjust the variable delay circuit in parallel for each relay card 122 to complete the timing calibration in a short time, thereby improving the test efficiency. It is.

  In addition, a timing calibration method for calibrating the signal timing of the device tester 700 using the device tester 700 in the second embodiment described above is also provided.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

It is a block diagram which shows the schematic structure of the device tester in 1st Embodiment. It is a functional block diagram showing a schematic function of a device tester in the same embodiment. It is a functional block diagram for demonstrating transfer of the reference timing from the reference | standard input part to a sub reference | standard output part in the embodiment. It is a functional block diagram for demonstrating transfer of the reference timing from the sub reference | standard output part in the same embodiment to a sub reference | standard input part. It is a functional block diagram for demonstrating transfer of the reference timing from the sub reference | standard input part in the same embodiment to output parts other than a sub reference | standard output part. It is the flowchart which showed the whole flow of the timing calibration method in the embodiment. It is the functional block diagram which showed the schematic function of the device tester in 2nd Embodiment. It is a functional block diagram showing a schematic function of a conventional device tester.

Explanation of symbols

100, 700 Device tester 114 Central control unit 122 Relay card 140 DUT
144, 702 Reference card 152 Output unit 154 Input unit 160 Output variable delay circuit 162 Output driver 164 Input comparator 166 Input variable delay circuit 168 Input flip-flop 170 Sub reference output unit 172 Sub reference input unit 180 First relay relay 182 Second relay Relay 192 Reference relay 194 Reference comparator 196 Reference flip-flop 198 Reference input 710 Reference driver

Claims (5)

A device tester for conducting an electrical test of a device under test,
A relay card comprising a plurality of modules comprising an output unit and an input unit;
A reference card for supplying a reference timing as a reference for input and output;
With
Further, the relay card includes a first relay relay that connects an arbitrary module of the plurality of modules and the reference card, and a second relay that can switch the connection between the arbitrary module and another module in a one-to-multiple manner. With a relay,
Based on the reference timing, any module of each of the plurality of relay cards is calibrated,
A device tester, wherein another module is calibrated in parallel with each of the plurality of relay cards based on the arbitrary module. A device tester for conducting an electrical test of a device under test,
A plurality of output units each including an output variable delay circuit for adjusting a delay of a signal to the device under test, an output driver for outputting the delayed signal to the device under test, and a signal from the device under test; A plurality of input units each including an input comparator and an input flip-flop that latches an output signal of the input comparator with a delay signal of an input variable delay circuit that adjusts a delay of a strobe signal; and a sub that is one of the plurality of output units A first relay relay that connects a reference output unit and a reference card that supplies a reference timing that serves as an input / output reference, and is one of the plurality of input units and constitutes one module with the sub-reference output unit A plurality of relay cards comprising a second relay relay capable of connecting and switching a sub-reference input unit and other output units excluding the sub-reference output unit;
A reference input unit comprising a reference comparator for inputting a signal from the output driver, and a reference flip-flop for latching the output signal of the reference comparator by a reference strobe signal;
A central control unit for calibrating the output variable delay circuit and the input variable delay circuit;
With
The central control unit calibrates the output variable delay circuit of the sub-reference output unit with reference to the reference input unit, and calibrates the input variable delay circuit of the sub-reference input unit with reference to the sub-reference output unit. The device tester characterized in that the plurality of relay cards calibrate the output variable delay circuit of the output unit other than the sub reference output unit in parallel with each other in reference to the sub reference input unit. A device tester for conducting an electrical test of a device under test,
A plurality of output units each including an output variable delay circuit for adjusting a delay of a signal to the device under test, an output driver for outputting the delayed signal to the device under test, and a signal from the device under test; A plurality of input units each including an input comparator and an input flip-flop that latches an output signal of the input comparator by a delay signal of an input variable delay circuit that adjusts a delay of a strobe signal; and a sub that is one of the plurality of input units A first relay relay that connects a reference input unit and a reference card that supplies a reference timing serving as a reference for input and output, and is one of the plurality of output units and constitutes one module with the sub reference input unit A plurality of relay cards comprising a second reference relay connecting a sub-reference output unit and an input unit other than the sub-reference input unit;
A reference driver that outputs a reference signal;
A central control unit for calibrating the output variable delay circuit and the input variable delay circuit;
With
The central control unit calibrates the input variable delay circuit of the sub-reference input unit with reference to the reference driver, calibrates the output variable delay circuit of the sub-reference output unit with reference to the sub-reference input unit, The device tester, wherein the plurality of relay cards each calibrate the input variable delay circuit of an input unit other than the sub reference input unit in parallel with the sub reference output unit as a reference. A timing calibration method for calibrating the timing of a signal of a device tester that conducts an electrical test of a device under test,
Based on the reference timing, sequentially calibrate the output variable delay circuit of the sub- reference output unit of each of the plurality of relay cards,
Calibrating the input variable delay circuit of the sub-reference input unit based on the sub-reference output unit,
A timing calibration method, wherein the plurality of relay cards each calibrate output variable delay circuits of output units other than the sub reference output unit in parallel with each other based on the sub reference input unit. A timing calibration method for calibrating the timing of a signal of a device tester that conducts an electrical test of a device under test,
Based on the reference signal, sequentially calibrate the input variable delay circuit of the sub-reference input section of each of the plurality of relay cards,
Calibrating the output variable delay circuit of the sub-reference output unit based on the sub-reference input unit,
A timing calibration method, wherein the plurality of relay cards calibrate in parallel an input variable delay circuit of an input unit other than the sub-reference input unit in parallel with the sub-reference output unit as a reference.

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