JP2862288B2 - IC test equipment - Google Patents

Description

The present invention relates to an IC test apparatus for testing an IC such as a memory.

[Prior Art] FIG. 2 shows a conventional IC test apparatus. In the figure, 100 is an IC test apparatus main body, 200 is a test head, 300 is an IC under test, and 400 is a signal distributor.

The IC test apparatus main body 100 compares and determines whether or not the response output signal of the IC 300 under test matches the expected value with the pattern generator 101 that generates the test pattern signal. Logic comparator 102 to judge as defective
And a reference timing signal generator 103 for generating a reference timing signal for calibration.

The test head 200 includes a plurality of boards B1, B2,... Bn, and a plurality of drive circuit systems DR1, DR2,.
And signal capture circuit systems CP1 to CPn that capture response output signals output from the IC under test 300.

The output terminals of the drive circuit system and the input terminals of the signal capture circuit system are commonly connected to the drive circuit systems DR1 to DRn and the respective signal capture circuit systems CP1 to CPn, and the common connection points X1 to Xn are connected to each board B1.
To Bn input / output terminals OU1 to OUn.

 The test of the IC under test 300 is performed as follows.

A test pattern signal is output from the pattern generator 101, and the test pattern signal is given to each terminal of the IC under test 300 through drive circuit systems DR1 to DRn mounted on each of the boards B1 to Bn.

At the timing when each terminal of the IC under test 300 is switched to the output mode, the signal capture circuit systems CP1 to CPn operate and the IC under test 30
The response output signal output from 0 is fetched and the logic comparator 102
Send to

The logical comparator 102 performs a logical comparison between the expected value pattern signal given from the pattern generator 102 and the response output signal taken from the IC under test 300, and performs a test every time a mismatch is detected.
The IC 300 is determined to be defective. The test operation is performed in this manner.

By the way, the drive circuit systems DR1 to DRn and the signal acquisition circuit system CP1
~ CPn is provided corresponding to the number of terminals of the IC under test 300,
Generally, several hundred channels are provided.

Although not shown, each drive circuit system DR1 to DRn is provided with a variable delay element in the middle, and the variable delay element adjusts the phase of a test pattern signal applied to each terminal of the IC under test 300 to match the intended phase. It is a structure that can be done. In other words, the structure is such that the adjustment can be performed so that the delay amounts of all the drive circuit systems DR1 to DRn are matched.

Also, the signals fetched by the signal fetch circuit systems CP1 to CPn must be read into the IC test apparatus main body 100 in the same phase.
For this purpose, delay means for adjusting the delay time are also provided in the signal capture circuit systems CP1 to CPn, and the structure is such that adjustment can be performed to match the delay times of the signal capture circuit systems CP1 to CPn. Adjusting the delay time between the channels of the drive circuit system and the signal acquisition circuit system is hereinafter referred to as timing adjustment.

The timing adjustment of the drive circuit systems DR1 to DRn and the signal capture circuit systems CP1 to CPn is performed as follows.

A reference timing signal generator 103 is provided in the IC test apparatus main body 100.
Is provided. The reference timing signal output from the reference timing signal generator 103 is distributed by the signal distributor 400 to at least the number of boards B1 to Bn constituting the test head 200.

The signal distributor 400 is also provided with variable delay elements VRA1 to VRAn, and adjusts the variable delay elements VRA1 to VRAn to adjust the output terminal A1.
AnAn can be adjusted to match the delay time of the reference timing signal output to An.

The reference timing signals distributed to the output terminals A1 to An of the signal distributor 400 are connected to the test head 20 through the cables K1 to Kn.
0 is input to each of the input terminals T1 to Tn of the boards B1 to Bn.

Each board B1 to Bn internally has a reference timing signal applied to input terminals T1 to Tn for calibration supplied to common connection points X1 to Xn of drive circuit systems DR1 to DRn and signal capture circuit systems CP1 to CPn. Timing signal supply paths CL1 to CLn are provided.

Each of the calibration timing signal supply paths CL1 to CLn is also provided with a variable delay element VRB1 to VRBn, and each of the calibration timing signal supply paths CL1 to CLn to the input terminals T1 to Tn and the common connection points X1 to Xn.
Are configured to be able to make the delay times of the two constant.

With such a configuration, the reference timing signal generator 103
The reference timing signal output from the signal distributor 400 is distributed by the signal distributor 400, input to the input terminals T1 to Tn of the boards B1 to Bn through the cables K1 to Kn, and supplied to the calibration timing signal supply path.
It is supplied to common connection points X1 to Xn through CL1 to CLn.

Delay element VR provided in the supply path of this reference timing signal
A1 to VRAn and VRB1 to VRAn are shipped with the common connection point X1
Calibration is performed so that a reference timing signal whose phase matches .about.Xn can be given.

During actual use, the signal capture circuit system CP1 to CPn and the drive circuit system DR
When performing the timing adjustment of 1 to DRn, the timing adjustment is performed using this reference timing signal supply path as a reference for calibration.

That is, the timing adjustment of the signal acquisition circuit systems CP1 to CPn is performed as follows.

Signal distributor 400 and calibration timing signal supply paths CL1 to CL
The reference timing signal is supplied to the common connection points X1 to Xn through n.

This reference timing signal is taken into the signal acquisition circuit systems CP1 to CPn, and the taken reference timing signal is sent to the IC test apparatus main body 100 to detect the difference in the delay amount of each channel,
Signal acquisition circuit system so that the difference between the delay amounts is all zero
The variable delay elements (not particularly shown) provided in CP1 to CPn are adjusted.

By this adjustment, the delay amounts of the signal acquisition circuit systems CP1 to CPn are adjusted to a constant value.

Next, timing signals are output from the drive circuit systems DR1 to DRn, and the timing signals are captured by the signal capture circuit systems CP1 to CPn.

This time, the variable delay elements provided in the drive circuit systems DR1 to DR2 are adjusted so that the difference between the delay amounts of the timing signals acquired by the signal acquisition circuit systems CP1 to CPn becomes zero over all the channels. By this adjustment, the delay amounts of the drive circuit systems DR1 to DRn are calibrated.

"Problems to be solved by the invention" Conventionally, the distributor 400, the cables K1 to Kn, and the respective boards B1 to B
n, the calibration reference timing signals are provided to the common connection points X1 to Xn through the calibration timing signal supply paths CL1 to CLn provided in n, and the delay times of the signal acquisition circuit systems CP1 to CPn are calibrated. Delay time adjustment error, board B
Calibration timing signal supply paths CL1 to CLn provided on 1 to Bn
The delay time adjustment error and the propagation delay time error of the cables K1 to Kn are accumulated, thereby causing the signal acquisition circuit system CP1 to CP
There is a disadvantage that the timing adjustment of Pn cannot be adjusted with high accuracy.

In addition, drive circuit system using this signal capture circuit system CP1-CPn
Since the timing adjustment of DR1 to DRn is performed, the drive circuit system DR1
There is a disadvantage that the timing adjustment of ~ DRn cannot be performed with high accuracy.

An object of the present invention is to accurately calibrate a reference timing signal supply circuit including a distributor 400, calibration timing signal supply paths CL1 to CLn, and cables K1 to Kn, thereby enabling signal acquisition circuit systems CP1 to CPn and Drive circuit system DR1 to DRn
It is an object of the present invention to provide an IC test apparatus capable of performing the timing adjustment with high accuracy.

According to the present invention, a plurality of boards mounted on a test head interposed between an IC under test and a test apparatus, and a plurality of boards mounted on the plurality of boards and tested on the IC under test. A plurality of drive circuit systems for supplying a pattern signal; and an input terminal connected to each output terminal of the plurality of drive circuit systems. When the IC under test operates in the output mode, the IC under test
A plurality of signal acquisition circuit systems for acquiring a signal output by the first device and sending the signal to a test apparatus main body; a first signal distributor for distributing a reference timing signal to at least a number of signals corresponding to the number of boards; A first variable delay element which is mounted on the distributor and provides an arbitrary delay amount to each distributed signal; an input terminal provided on each of the plurality of boards for receiving the reference timing signal distributed by the first signal distributor; A plurality of calibration timing signals are supplied by giving an appropriate delay amount to the reference timing signal given to this input terminal and providing a reference timing signal to a common connection point between the drive circuit system and the signal acquisition circuit system at the same time. And a second signal distributor for distributing the reference timing signal to a number of signals corresponding to the number of signal acquisition circuit systems mounted on the board. A second variable delay element for giving an arbitrary amount of delay to the distributed signal and outputting the delayed signal to the input terminal of the signal acquisition circuit system; The configuration is such that a calibration reference timing signal can be directly supplied to input / output terminals of each board using a jig.

According to the configuration of the present invention, by calibrating the timing calibration jig in advance, it is possible to provide the input / output terminal of each board with the reference timing signal whose phase matches exactly.

As a result, by using this reference timing signal to calibrate the timing error of the signal acquisition circuit system, the signal acquisition circuit system can be accurately calibrated.

Next, the reference timing signal is supplied by adjusting the delay amount of the variable delay element provided in the signal distributor and the variable delay element provided in the calibration timing signal supply path using the signal acquisition circuit system that has been accurately calibrated as a reference. Calibrate the timing of the system.

Therefore, the reference timing signal supply system is calibrated with high accuracy similarly to the signal acquisition circuit system. Therefore, the timing calibration of the signal acquisition circuit system and the timing calibration of the drive circuit system, which are performed using the reference timing signal supply system, can be accurately performed thereafter.

FIG. 1 shows an embodiment of the present invention. In the figure, 100 is an IC test apparatus main body, 200 is a test head, and 400 is a first signal distributor.

In the present invention, a jig 500 for timing adjustment is provided. The jig 500 transmits the second signal distributor 501 and the reference timing signal distributed by the second signal distributor 501 to the test head 2.
The variable delay elements VRC1 to VRCn provided to the input / output terminals OU1 to OUn of each of the boards B1 to Bn constituting the 00.

The same reference timing signal as provided to the first signal distributor 400 is given to the signal distributor 501 of the timing adjustment jig 500, and this reference timing signal is supplied to at least each of the boards B1 to B1.
Bn is distributed to a number of signals corresponding to the number of input / output terminals OU1 to OUn, and the distributed timing signals are passed through variable delay elements VRC1 to VRCn to input / output terminals OU1 of each board B1 to Bn.
Give to ~ OUn.

Variable delay elements VRC1 to VRCn of the timing adjustment jig 500
Are calibrated in advance, and the variable delay elements VRC1 to VRCn
The phases of the reference timing signals output through the control circuit are matched.

In this adjustment, the cable 502 to the second signal distributor 501 is common, and the delay elements VRC1 to VRCn and the input / output terminal OU1 are used.
It can be performed accurately because the cable connecting ~ OUn can be shortened.

At the time of initial shipment adjustment, the timing of the signal acquisition circuit systems CP1 to CPn is adjusted using the timing adjustment jig 500. This adjustment adjusts variable delay elements (not particularly shown) provided in the signal acquisition circuit systems CP1 to CPn, for example, adjusts the timing of a strobe pulse, and adjusts the timing of reading a signal.

With this adjustment, the timing of the signal acquisition circuit systems CP1 to CPn is initially adjusted, and the first signal distributor 400, the cables K1 to Kn, and the calibration timing signal supply path are based on the signal acquisition circuit systems CP1 to CPn. Calibrate CL1 to CLn.

This calibration uses the variable delay element V provided in the first signal distributor 400.
RA1 to VRAn and the variable delay elements VRB1 to VRBn of the calibration timing signal supply paths CL1 to CLn provided on each of the boards B1 to Bn are adjusted. In rare cases, the output timings of the signal capture circuit systems CP1 to CPn are adjusted so that all channels match.

By this adjustment, the timing error of the reference timing signal supply system is calibrated, and thereafter, the signal acquisition circuit systems CP1 to CPn and the drive circuit system are based on the reference timing signal supply system.
Calibrate the timing of DR1 to DRn.

[Effects of the Invention] As described above, according to the present invention, by providing the timing calibration jig 500, it is possible to accurately calibrate a timing signal supply system used as a standard for calibration at all times.

Therefore, by calibrating the signal acquisition circuit systems CP1 to CPn using the timing signal supply system calibrated by the jig on a daily basis, the signal acquisition circuit systems CP1 to CPn can be calibrated with high accuracy. The timing of the circuits DR1 to DRn can be calibrated accurately.

In some cases, the timing of the calibration timing signal supply system is calibrated by using the jig 500, so that the timing error due to the aging of the calibration timing signal supply system can be calibrated. Therefore, there is an advantage that the reference value of the calibration timing signal supply path can always be maintained correctly.

Although not specifically described above, the first signal distributor 40
The variable delay elements VRA1 to VRAn provided at 0 and the variable delay elements VRB1 to VRBn provided at the calibration timing signal supply paths CL1 to CLn
If the delay amount is automatically adjusted by the controller 104 provided in the IC test apparatus main body 100, the timing adjustment of the calibration timing signal supply system can be automatically performed, which is convenient.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a block diagram for explaining a conventional technique. 100: IC test apparatus main body, 101: pattern generator, 102: logical comparator, 103: reference timing signal generator, 200: test head, B1 to Bn: board, VRA1 to VRAn and VRB1 to VRBn: variable delay element, 400: first signal distributor, 500: timing adjustment jig.

Claims (1)

(57) [Claims] A. A plurality of boards mounted on a test head interposed between an IC under test and a test apparatus main body, and a test pattern signal is provided to the plurality of boards and provided to the IC under test. A plurality of drive circuit systems; and an input terminal connected to each output terminal of the plurality of drive circuit systems. When the IC under test operates in the output mode, the signal output from the IC under test is fetched to perform the test. A plurality of signal acquisition circuit systems to be sent to the apparatus main body; a first signal distributor for distributing the reference timing signal to at least a number of signals corresponding to the number of the boards; and a first signal distributor mounted on the first signal distributor for each distribution. A plurality of first variable delay elements for providing an arbitrary amount of delay to a given signal, and an appropriate amount of delay for the reference timing signal provided on each of the plurality of boards and distributed by the first signal distributor. At the same time B. a plurality of calibration timing signal supply paths to be provided to the input terminals of the signal acquisition circuit system; and B. the signal acquisition circuit system which mounts the reference timing signal on the board. A second signal distributor for distributing the signals to a number corresponding to the number of signals, giving an arbitrary delay amount to each of the distributed signals, and outputting the delayed signal to an input terminal of the signal acquisition circuit system. An IC test apparatus comprising: a second variable delay element; and a timing calibration jig comprising: