JP2009288064A - Semiconductor test apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test apparatus and method for simultaneously achieving shortness of a time necessary for calibration and improvement of test precision. <P>SOLUTION: The semiconductor test apparatus 1 includes: a plurality of test modules 12a, 12b for testing DUT 50 being an object to be tested; controllers 13a, 13b for being provided corresponding to each of the test modules 12a, 12b and controlling calibration of the corresponding test modules 12a, 12b; and switches 14a, 14b for switching connection relationship of the test modules 12a, 12b and DUT 50. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus and method for testing a semiconductor device.

  A semiconductor test apparatus applies a test signal to a semiconductor device to be tested (hereinafter referred to as a DUT (Device Under Test)) and compares the signal obtained from the DUT with a predetermined expected value to test the DUT. Do. In this semiconductor test apparatus, there is an error in the value (voltage value or current value) of the test signal applied to the DUT, the power supply voltage supplied to the DUT, etc. If there is a deviation in the timing of comparison with the value, the DUT test cannot be performed with high accuracy. For this reason, in the semiconductor test apparatus, various calibrations are performed periodically or as required by the user.

  FIG. 4 is a block diagram showing an outline of the configuration of a conventional semiconductor test apparatus. As shown in FIG. 4, a conventional semiconductor test apparatus 100 is roughly configured by a CPU (Central Processing Unit) 101 and a test module 102. The CPU 101 controls the test module 102 according to the test program created by the user, and causes the power supply voltage supply to the DUT 200 and the functional test of the DUT 200 to be performed. When various calibrations are performed by the test module 102, sequence control related to calibration is performed.

  The test module 102 includes a pin electronics that applies a test signal to the DUT 200 and receives a signal from the DUT 200, a power source supply unit that supplies power voltage to the DUT 200 (both not shown), and the like. Below, the power supply voltage supply and functional test with respect to DUT200 are implemented. Various calibrations are performed according to the sequence control of the CPU 101. Here, the calibration performed by the test module 102 includes, for example, calibration of the current value supplied to the DUT 200. In this calibration, a reference resistor with a known resistance value is used, a voltage drop due to a current flowing through the reference resistor is measured, and the current value is calibrated so that the voltage drop becomes a predetermined value.

Patent Document 1 below discloses a conventional calibration device that calibrates the DC voltage level of a measuring device such as a semiconductor tester.
JP 2004-28607 A

  By the way, the conventional semiconductor test apparatus 100 shown in FIG. 4 cannot calibrate the test module 102 during the functional test of the DUT 200, and conversely, calibrates the test module 102. The DUT 200 cannot be tested while in the process. This is because the parts or circuits used for calibration are also used during testing of the DUT 200. For this reason, the calibration of the test module 102 needs to be performed while the test of the DUT 200 is interrupted, which causes a problem that the test efficiency is lowered.

  Further, it is desirable to frequently calibrate the test module 102 in order to improve the test accuracy. However, as described above, since the calibration of the test module 102 needs to interrupt the test of the DUT 200, the calibration cannot be frequently performed in order to prevent a decrease in test efficiency. Although the accuracy required for the DUT test is obtained at present, it is likely that calibration will be required frequently when performing a test that requires a high accuracy in the future, and a decrease in test efficiency is expected.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor test apparatus and method capable of simultaneously reducing the time required for calibration and improving test accuracy.

In order to solve the above problems, a semiconductor test apparatus according to the present invention is a semiconductor test apparatus (1) that tests a semiconductor device based on a signal obtained by applying a test signal to the semiconductor devices (50, 50a to 50d). -3) are provided corresponding to each of the plurality of test units (12a, 12b, 24, 27) for testing the semiconductor device and the plurality of test units, and controls calibration of the corresponding test unit. A calibration control unit (13a, 13b, 25, 28) and a switch unit (14a, 14b, 26, 29a to 29d, 31) for switching the connection relationship between the plurality of test units and the semiconductor device are provided. Yes.
According to the present invention, while the test of the semiconductor device is performed using one test unit of the plurality of test units, the calibration of the other test unit of the plurality of test units is performed on the semiconductor device. Performed in parallel with the test.
The semiconductor test apparatus of the present invention is characterized in that the test unit performs at least one of a power supply voltage supply and a function test of the semiconductor device on the semiconductor device.
The semiconductor test apparatus of the present invention controls the switch unit so that the corresponding test unit is electrically disconnected from the semiconductor device when the calibration control unit controls calibration of the corresponding test unit. When the test of the semiconductor device is performed by the corresponding test unit, the switch unit is controlled so that the corresponding test unit is connected to the semiconductor device.
Further, in the semiconductor test apparatus of the present invention, when one specific test unit among the plurality of test units is calibrated with another test unit, the semiconductor device is replaced with the other test unit. It is characterized by conducting a test.
Furthermore, in the semiconductor test apparatus according to the present invention, when any one of the plurality of test units is calibrated, another test unit can test the semiconductor device instead of the test unit. It is characterized by doing.
In order to solve the above-described problems, a semiconductor test method of the present invention is a semiconductor test method for testing a semiconductor device based on a signal obtained by applying a test signal to a semiconductor device (50). The first test unit (12a) of the first and second test units (12a, 12b) to be tested is used to test the semiconductor device and to calibrate the second test unit (12b). And a second step of testing the semiconductor device using the calibrated second test unit instead of the first test unit.

  According to the present invention, while the test of the semiconductor device is performed using one test unit of the plurality of test units, the calibration of the other test unit of the plurality of test units is performed. Since it is performed in parallel with the test, the time required for calibration of the test section can be apparently made substantially zero. For this reason, even if the test part is frequently calibrated, the test efficiency does not decrease, and it is possible to simultaneously reduce the time required for calibration and improve the test accuracy.

  Hereinafter, a semiconductor test apparatus and method according to embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a main configuration of the semiconductor test apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus 1 of the present embodiment includes a CPU 11, test modules 12a and 12b (test unit), controllers 13a and 13b (calibration control unit), and switches 14a and 14b (switch unit). The DUT 50 is tested based on a signal obtained by applying a test signal to the DUT 50.

  The CPU 11 controls the test modules 12a and 12b in accordance with a test program created by the user, and causes at least one of power supply voltage supply to the DUT 50 and functional test of the DUT 50 to be performed. The test modules 12a and 12b include at least one of pin electronics for applying a test signal to the DUT 50 and receiving a signal from the DUT 50 and a power source supply unit for supplying a power voltage to the DUT 50 (both not shown). Under the control of the CPU 11, at least one of power supply voltage supply and function test for the DUT 50 is performed.

  The test modules 12a and 12b perform various calibrations according to the sequence control of the controllers 13a and 13b. Here, examples of calibration performed by the test modules 12a and 12b include calibration of a current value supplied to the DUT 50. In this calibration, a reference resistor with a known resistance value is used, a voltage drop due to a current flowing through the reference resistor is measured, and the current value is calibrated so that the voltage drop becomes a predetermined value.

  The controllers 13a and 13b are provided corresponding to the test modules 12a and 12b, respectively, and perform sequence control related to calibration of the corresponding test modules 12a and 12b. The controllers 13a and 13b perform open / close control of the switches 14a and 14b connected to the test modules 12a and 12b.

  Specifically, when performing the sequence control related to calibration of the corresponding test module 12a, the controller 13a opens the switch 14a so that the test module 12a is electrically disconnected from the DUT 50. On the other hand, when the test of the DUT 50 is performed by the corresponding test module 12a, the switch 14a is closed so that the test module 12a is connected to the DUT 50. Similarly, the controller 13b opens the switch 14b when performing the sequence control related to the calibration of the corresponding test module 12b, and closes the switch 14b when the test of the DUT 50 is performed by the corresponding test module 12b. To.

  Here, the semiconductor test apparatus 1 shown in FIG. 1 includes a plurality of test modules 12a and 12b and controllers 13a and 13b corresponding to the test modules 12a and 12b. There is a possibility that this will lead to an increase. For this reason, from the viewpoint of suppressing an increase in circuit scale and cost, the controllers 13a and 13b are preferably realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

  The switches 14a and 14b are provided for connecting or electrically disconnecting the test modules 12a and 12b from the DUT 50, and their open / close states are controlled by the controllers 13a and 13b, respectively. As the switches 14a and 14b, electronic switches using transistors or the like, or mechanical switches such as relays can be used.

  Next, the operation of the semiconductor test apparatus 1 having the above configuration will be described. Here, the case where the test of the DUT 50 is first performed using the test module 12a and the test module 12b is calibrated during the test will be described as an example. First, a signal indicating that the test is performed by the test module 12a is output from the CPU 11 to the controller 13a, and a signal indicating that the test module 12b is to be calibrated is output from the CPU 11 to the controller 13b. Accordingly, the switch 14a is closed by the control of the controller 13a, and the switch 14b is opened by the control of the controller 13b.

  Next, a control signal for instructing the test module 12a to start the test of the DUT 50 is output from the CPU 11, thereby starting the test of the DUT 50. When the test of the DUT 50 is started, a test signal or the like is applied from the test module 12a to the DUT 50 via the switch 14a. Then, the test module 12a receives a signal output from the DUT 50 by applying a test signal or the like, and performs pass / fail judgment.

  While the test of the DUT 50 by the test module 12a is being performed, the test module 12b is electrically disconnected from the DUT 50 by the switch 14b, and the test module 12b can be calibrated. For this reason, the calibration of the test module 12b is performed by the sequence control of the controller 13b (first step). For example, the current value is calibrated so that a voltage drop measured when a current is passed through a reference resistor with a known resistance value becomes a predetermined value. In addition to the current value and voltage value, the test signal application timing and pass / fail judgment timing may be calibrated. When the calibration of the test module 12b is completed, a calibration end signal indicating the end of calibration is output from the controller 13b to the CPU 11.

  When the test of the DUT 50 by the test module 12a ends, a test end signal indicating the end of the test is output from the test module 12a to the CPU 11. If the CPU 11 has received the calibration end signal from the controller 13b when this test end signal is input, the test module for testing the DUT 50 is switched under the control of the CPU 11 (second step). .

  That is, the CPU 11 outputs a signal indicating that the test is performed by the test module 12b to the controller 13b, and the CPU 11 outputs a signal indicating that the test module 12a is to be calibrated to the controller 13a. Thereby, the switch 14b is closed by the control of the controller 13b, while the switch 14a is opened by the control of the controller 13a, and the open / closed states of the switches 14a and 14b are switched. When the CPU 11 outputs a control signal that instructs the test module 12b to start the test of the DUT 50, the test of the DUT 50 is started.

  While the test of the DUT 50 by the test module 12b is being performed, the test module 12a is electrically disconnected from the DUT 50 by the switch 14a, and the test module 12a can be calibrated. For this reason, the calibration of the test module 12a is performed by the sequence control of the controller 13a. When the calibration of the test module 12a is completed, a calibration end signal indicating the end of calibration is output from the controller 13a to the CPU 11.

  When the test of the DUT 50 by the test module 12b ends, a test end signal indicating the end of the test is output from the test module 12b to the CPU 11. If the CPU 11 has received a calibration end signal from the controller 13a at the time when this test end signal is input, the controller 13a, 13b switches the open / close state of the switches 14a, 14b under the control of the CPU 11. Then, the DUT 50 is tested by the test module 12a after the calibration. Thereafter, the same operation is repeated.

  As described above, in the present embodiment, while the test of the DUT 50 is performed using one of the test modules 12a and 12b, the calibration of the other of the test modules 12a and 12b is performed in parallel with the test of the DUT 50. Therefore, the test modules 12a and 12b can be calibrated without interrupting the test of the DUT 50, and the time required for the calibration of the test modules 12a and 12b can be made substantially zero. As a result, the test efficiency does not decrease even if the test modules 12a and 12b are frequently calibrated in order to improve the test accuracy. Therefore, the time required for calibration of the test modules 12a and 12b can be shortened and the test accuracy can be improved. Improvement can be realized at the same time.

[Second Embodiment]
FIG. 2 is a block diagram showing a main configuration of a semiconductor test apparatus according to the second embodiment of the present invention. As shown in FIG. 2, the semiconductor test apparatus 2 of this embodiment includes a CPU 21, main units 22 a to 22 d, and a subunit 23, and tests a plurality of DUTs 50 a to 50 d at the same time.

  The CPU 21 controls the main units 22a to 22d and the subunit 23 according to the test program created by the user, and causes the plurality of DUTs 50a to 50d to perform at least one of power supply voltage supply and functional testing of the DUTs 50a to 50d. The main units 22a to 22d include a test module 24 (test unit), a controller 25 (configuration control unit), and a switch 26 (switch unit), and perform tests of the DUTs 50a to 50d under the control of the CPU 21, respectively. . Since the main units 22a to 22d have the same configuration, the internal configuration of the main unit 22a will be described here as a representative.

  The test module 24 of the main unit 22a includes at least one of pin electronics for applying a test signal to the DUT 50a and receiving a signal from the DUT 50a and a power source supply unit for supplying a power voltage to the DUT 50a (both not shown). Under the control of the CPU 21, at least one of power supply voltage supply and function test for the DUT 50 a is performed. Further, various calibrations similar to the calibration described in the first embodiment are performed according to the sequence control of the controller 25 of the main unit 22a.

  The controller 25 of the main unit 22a is provided corresponding to the test module 24 of the main unit 22a, and performs sequence control relating to calibration of the test module 24. Moreover, the opening / closing control of the switch 26 of the main unit 22a is performed. Specifically, the controller 25 opens the switch 26 of the main unit 22a when performing sequence control related to calibration of the test module 24 of the main unit 22a, and the test module 24 of the main unit 22a performs the test of the DUT 50a. When it is performed, the switch 26 of the main unit 22a is closed.

  The controller 25 is preferably realized by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), like the controllers 13a and 13b provided in the semiconductor test apparatus 1 shown in FIG. Further, the switch 26 can be an electronic switch using a transistor or a mechanical switch such as a relay, like the switches 14a and 14b provided in the semiconductor test apparatus 1 shown in FIG.

  The sub unit 23 includes a test module 27 (test unit), a controller 28 (calibration control unit), and a plurality of switches 29a to 29d (switch units), and any one of the main units 22a to 22d is calibrated. If so, test the DUT on behalf of the main unit being calibrated. The test module 27 is the same as the test module 24 included in the main units 22a to 22d, and the controller 28 is the same as the controller 25 included in the main units 22a to 22d.

  The switches 29a to 29d are for connecting the test module 27 to any one of the DUTs 50a to 50d, or for electrically disconnecting the test module 27 from the DUTs 50a to 50d. Is done. As these switches 29a to 29d, electronic switches using transistors or the like, or mechanical switches such as relays can be used.

  Next, the operation of the semiconductor test apparatus 2 having the above configuration will be described. First, a signal indicating that the test is performed by the test module 24 is output from the CPU 21 to the controller 25 of the main units 22a to 22d, and the test module 27 should be calibrated to the controller 28 of the subunit 23 from the CPU 21. A signal indicating that is output. Thereby, the switches 26 of the main units 22a to 22d are closed by the control of the controller 25 of the main units 22a to 22d, respectively, and all the switches 29a to 29d of the subunit 23 are opened by the control of the controller 28 of the subunit 23. Put into state.

  Next, the CPU 21 outputs control signals for instructing the test modules 24 of the main units 22a to 22d to start the tests of the DUTs 50a to 50d, thereby starting the tests of the DUTs 50a to 50d. Further, during the test of the DUTs 50a to 50d, the calibration of the test module 27 of the subunit 23 is performed by the controller 28 of the subunit 23 (first step). When calibration of the test module 27 is completed, a calibration end signal indicating the end of calibration is output from the controller 28 of the subunit 23 to the CPU 21.

  Now, assuming that the test of the DUT 50a by the test module 24 of the main unit 22a is completed, a test end signal indicating the end of the test is output from the test module 24 of the main unit 22a to the CPU 21. If the CPU 21 has received the calibration end signal from the controller 28 of the subunit 23 at the time when this test end signal is input, the test module for testing the DUT 50a is switched under the control of the CPU 21 ( Second step).

  That is, a signal indicating that the test is performed by the test module 27 is output from the CPU 21 to the controller 28 of the subunit 23, and the test module 24 of the main unit 22a is calibrated from the CPU 21 to the controller 25 of the main unit 22a. A signal indicating power is output. Thus, only the switch 29a is closed by the control of the controller 28 of the sub unit 23, while the switch 26 of the main unit 22a is opened by the control of the controller 25 of the main unit 22a. When the CPU 21 outputs a control signal instructing the test module 27 of the subunit 23 to start the test, the test of the DUT 50a is started.

  While the test of the DUT 50a is being performed by the test module 27 of the sub unit 23, the test module 24 of the main unit 22a is calibrated by the controller 25 of the main unit 22a. When calibration of the test module 24 of the main unit 22a is completed, a calibration end signal indicating completion of calibration is output from the controller 25 of the main unit 22a to the CPU 21.

  When the test of the DUT 50a by the test module 27 of the subunit 23 is completed, a test completion signal indicating the completion of the test is output from the test module 27 of the subunit 23 to the CPU 21. If the CPU 21 has received a calibration end signal from the controller 25 of the main unit 22a when this test end signal is input, the controller 25 of the main unit 22a and the controller 28 of the sub unit 23 under the control of the CPU 21. Thus, the open / close state of the switch 26 and the switch 29a is switched. Then, the DUT 50a is tested by the test module 24 of the main unit 22a after calibration.

  The operation when the test module 24 provided in the main unit 22a is calibrated has been described above. However, the above description also applies when the test module 24 provided in any of the main units 22b to 22d is calibrated. An operation similar to the operation is performed. Here, when the test module 24 of the main unit 22b is calibrated, the switch 29b is closed, and when the test module 24 of the main unit 22c is calibrated, the switch 29c is closed and the main unit 22d. When the test module 24 is calibrated, the switch 29d is closed, and the test module 27 of the subunit 23 performs tests on the DUTs 50b, 50c, and 50d, respectively.

  As described above, in the present embodiment, the subunit 23 is provided separately from the main units 22a to 22d for testing the DUTs 50a to 50d. When the test module 27 of the sub unit 23 is calibrated while the test of the DUTs 50a to 50d is being performed by the main units 22a to 22d, and any one test module 24 of the main units 22a to 22d is calibrated. Performs a DUT test using the test module 27 of the subunit 23 instead of the main unit being calibrated.

  Thereby, it is possible to calibrate the test module 24 provided in the main units 22a to 22d and the test module 27 provided in the subunit 23 without interrupting the test of the DUTs 50a to 50d, and it is necessary for these calibrations. The time can be apparently almost zero. For this reason, in the present embodiment, it is possible to simultaneously reduce the time required for calibration of the test module 24 and improve the test accuracy.

[Third Embodiment]
FIG. 3 is a block diagram showing a main configuration of a semiconductor test apparatus according to the third embodiment of the present invention. As shown in FIG. 3, the semiconductor test apparatus 3 of the present embodiment replaces the subunit 23 included in the semiconductor test apparatus 2 shown in FIG. 2 with the main unit 22 e, and establishes a connection relationship between the main units 22 a to 22 e and the DUTs 50 a to 50 d. It is the structure which provided the switching part 31 (switch part) which can be switched arbitrarily, and tests several DUT50a-50d simultaneously like the semiconductor test apparatus 2. FIG.

  The main unit 22e has the same configuration as the other main units 22a to 22d, and includes a test module 24, a controller 25, and a switch 26. The switching unit 31 includes a plurality of cross point switches, and the controller 25 provided in the main units 22a to 22e controls the plurality of cross point switches, thereby connecting the main units 22a to 22e and the DUTs 50a to 50d. Can be switched arbitrarily.

  That is, in the semiconductor test apparatus 2 shown in FIG. 2, the test targets of the main units 22a to 22d are fixed to the DUTs 50a to 50d, respectively, but in this embodiment, the test targets of the main units 22a to 22e are not fixed. Thus, for example, the DUT 50d can be tested with the main unit 22a, and the DUT 50b can be tested with the main unit 22e.

  In the semiconductor test apparatus 2 shown in FIG. 2, when any one of the main units 22a to 22d is calibrated, the DUT is used by using the subunit 23 in place of the calibrated main unit. The test was done. However, in the present embodiment, when any one of the main units 22a to 22e is calibrated, a DUT test using another main unit in place of the calibrated main unit is performed. Done.

  For example, when the DUT 50d is tested in the main unit 22a and the main unit 22a is calibrated, the main unit 22c tests the DUT 50d instead of the main unit 22a. Similarly, for example, when the DUT 50b is tested in the main unit 22e and the main unit 22e is calibrated, the main unit 22b tests the DUT 50b instead of the main unit 22e. The operation of the semiconductor test apparatus 3 according to the present embodiment is basically the same as that of the semiconductor test apparatus 2 shown in FIG.

  As described above, in this embodiment, when the main units 22a to 22e for testing the DUTs 50a to 50d are provided and any one of the test modules 24 of the main units 22a to 22e is calibrated, the calibration is performed. The DUT is tested using the test module 24 of another main unit instead of the main unit in which the test is performed. As a result, the test modules 24 provided in the main units 22a to 22e can be calibrated without interrupting the tests of the DUTs 50a to 50d, and the time required for these calibrations can be made substantially zero. . For this reason, as in the second embodiment, this embodiment can simultaneously reduce the time required for calibration of the test module 24 and improve the test accuracy.

  Although the semiconductor test apparatus and method according to the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and can be freely modified within the scope of the present invention. For example, in the third embodiment, the controller 25 provided in the main units 22a to 22e controls the switching unit 31, but the CPU 21 may directly control the switching unit 31, or A dedicated control device that performs control may be provided.

  Further, in the above-described embodiment, for the sake of simplicity, the case where only one DUT 50 is tested and the case where four DUTs 50a to 50d are simultaneously tested have been described. However, the number of DUTs that can be tested simultaneously is as follows. The number is not limited to four and can be set to an arbitrary number. If the maximum number of DUTs that can be simultaneously tested is n (n is an integer equal to or greater than 1), the semiconductor test apparatus 2 shown in FIG. 2 needs to be configured to include n main units and at least one subunit. There is. In addition, the semiconductor test apparatus shown in FIG. 3 needs to be configured to include at least (n + 1) main units.

It is a block diagram which shows the principal part structure of the semiconductor test apparatus by 1st Embodiment of this invention. It is a block diagram which shows the principal part structure of the semiconductor test apparatus by 2nd Embodiment of this invention. It is a block diagram which shows the principal part structure of the semiconductor test apparatus by 3rd Embodiment of this invention. It is a block diagram which shows the outline | summary of a structure of the conventional semiconductor test apparatus.

Explanation of symbols

1-3 Semiconductor test equipment 12a, 12b Test module 13a, 13b Controller 14a, 14b Switch 24 Test module 25 Controller 26 Switch 27 Test module 28 Controller 29a-29d Switch 31 Switching part 50 DUT
50a-50d DUT

Claims (6)

In a semiconductor test apparatus for testing the semiconductor device based on a signal obtained by applying a test signal to the semiconductor device,
A plurality of test units for testing the semiconductor device;
A calibration control unit that is provided corresponding to each of the plurality of test units and controls calibration of the corresponding test unit;
A semiconductor test apparatus comprising: a switch unit that switches a connection relationship between the plurality of test units and the semiconductor device.   The semiconductor test apparatus according to claim 1, wherein the test unit performs at least one of a supply voltage supply and a function test of the semiconductor device with respect to the semiconductor device.   When controlling the calibration of the corresponding test unit, the calibration control unit controls the switch unit so that the corresponding test unit is electrically disconnected from the semiconductor device, and the corresponding test unit controls the switch of the semiconductor device. 3. The semiconductor test apparatus according to claim 1, wherein when a test is performed, the switch unit is controlled so that the corresponding test unit is connected to the semiconductor device.   The specific one of the plurality of test units performs the test of the semiconductor device in place of the other test unit when another test unit is calibrated. The semiconductor test apparatus according to any one of claims 1 to 3.   2. When any one of the plurality of test units is calibrated, another test unit tests the semiconductor device instead of the test unit. The semiconductor test apparatus according to claim 3. In a semiconductor test method for testing the semiconductor device based on a signal obtained by applying a test signal to the semiconductor device,
A first step of performing a test of the semiconductor device and a calibration of the second test unit using a first test unit of the first and second test units for testing the semiconductor device;
And a second step of testing the semiconductor device using the calibrated second test unit instead of the first test unit.

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