JP4809515B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor, and more particularly to a field effect transistor having a via hole and a manufacturing method thereof.
[0002]
[Prior art]
In field effect transistors used for high-frequency and high-power applications, a via-hole structure is widely used to reduce source inductance. An example of this type of field effect transistor is disclosed in the document “Basics of GaAs Field Effect Transistors, page 213, 1992 (published by the Institute of Electronics, Information and Communication Engineers)”.
[0003]
FIG. 6 shows a sectional view of a field effect transistor having a conventional via hole structure. In FIG. 6, a source electrode 2, a gate electrode 3, and a drain electrode 4 are formed on the surface of a GaAs substrate 1 having source / drain regions (not shown). A ground electrode is formed on the back surface of the substrate 1. Further, a hole (via hole portion 6) penetrating from the back surface side to the front surface side of the substrate 1 is formed, and the ground electrode 5 is in contact with the source electrode through the via hole 6.
[0004]
In the field effect transistor having this structure, since the source is grounded through the via hole 6 formed so as to penetrate the substrate, the distance between the source electrode 2 and the ground electrode (earth) 5 can be shortened.・ Inductance can be reduced.
[0005]
[Problems to be solved by the invention]
However, in the via hole structure as described above, since a hole penetrating from the front surface to the back surface of the substrate is formed, the substrate having a thickness of about 600 μm is usually polished from the back side to about several tens of μm It needs to be thin. The thinned substrate has a weak mechanical strength, which leads to a decrease in yield due to wafer cracking, and is difficult to handle, requiring careful work by hand and increasing work time.
[0006]
[Means for Solving the Problems]
According to the present invention, an n- conductivity type semiconductor substrate, a p-type GaAs layer formed on the semiconductor substrate,
An n-type AlGaAs layer formed on the p-type GaAs layer, a buffer layer formed on the n-type AlGaAs layer , a semiconductor layer formed on the buffer layer, and formed on the semiconductor layer and a source electrode and a gate electrode, the source electrode and the insulating film formed on the semiconductor layer so as to cover the gate electrode, wherein so as to expose the source electrode first formed in an insulating film A contact hole is formed through the insulating film, the semiconductor layer, the buffer layer, the n-type AlGaAs layer, and the p-type GaAs layer so as to expose the semiconductor substrate through the surface of the insulating film. over first via-hole which is a first conductive layer by gold plating for electrically connecting the source electrode and the semiconductor substrate, so as to expose the gate electrode The second contact hole formed in the insulating film passes through the insulating film, the semiconductor layer, and the buffer layer so as to expose the n-type AlGaAs layer through the surface of the insulating film. A gold-plated second conductive layer that electrically connects the n-type AlGaAs layer and the gate electrode over the formed second via hole, and a ground electrode formed on the back surface of the semiconductor substrate. A field effect transistor is obtained.
[0007]
According to the present invention, a step of forming a p-type GaAs layer on an n- conductivity type semiconductor substrate, a step of forming an n-type AlGaAs layer on the p-type GaAs layer, and a step of forming on the n-type AlGaAs layer A step of forming a buffer layer; a step of forming a semiconductor layer on the buffer layer; a step of forming a source electrode and a gate electrode on the semiconductor layer; and the semiconductor so as to cover the source electrode and the gate electrode Forming an insulating film on the layer; forming a first contact hole in the insulating film to expose the source electrode; and forming a first contact hole in the insulating film to expose the gate electrode. Forming a contact hole of 2; and the insulating film, the semiconductor layer, the buffer layer, the n-type AlGaAs layer, and the p-type GaAs layer so as to expose the semiconductor substrate. Forming a first via hole penetrating, and forming a second via hole penetrating the insulating film, the semiconductor layer, and the buffer layer so as to expose the n-type AlGaAs layer; the over first via hole of the first through the surface of the insulating film from the contact hole, forming a first conductive layer by gold plating for electrically connecting the source electrode and the semiconductor substrate And a second conductive layer by gold plating for electrically connecting the n-type AlGaAs layer and the gate electrode from the second contact hole through the surface of the insulating film to the second via hole. A method of manufacturing a field effect transistor having a forming step and a step of forming a ground electrode on the back surface of the semiconductor substrate is obtained.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the sizes, shapes, and arrangement relationships of various components are merely shown to the extent that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples.
[0009]
"First embodiment"
With reference to FIG. 1, the manufacturing method of the field effect transistor in the 1st Embodiment of this invention is demonstrated.
[0010]
First, as shown in FIG. 1A, an undoped GaAs buffer layer 2 having a thickness of 1 μm, a GaAs / AlGaAs / InGaAs layer on an n-type (Si doped, 110 ¹⁹ cm ⁻³ ) GaAs substrate 1 having a thickness of 600 μm. The HEMT (High Electron Mobility Transistor) structure thin film 3 constituted by the above is sequentially grown by the MBE (Molecular Beam Epitaxy) method. The thickness of the HEMT structure portion is generally 200 nm or less. Subsequently, as shown in FIG. 1B, a passive element portion such as a wiring and a capacitor (insulating film 4) is formed in addition to the transistor portion having the gate electrode 6, the source electrode 5 and the drain electrode 7. An insulating film 4 is formed so as to cover these electrodes, wiring, and passive elements.
[0011]
As shown in FIG. 1C, a photoresist 8 is formed on the insulating film 4, and the photoresist 8 on the region where the via hole 9 is to be formed is removed by photolithography to form a resist pattern. Next, via holes 9 are formed by dry etching using CCl ₄ so as to reach the n-type GaAs substrate 1 from the substrate surface side.
[0012]
Subsequently, as shown in FIG. 1D, an AuGe / Ni / Au laminated film is deposited and lifted off, and an ohmic electrode for n-type GaAs is formed at the bottom of the via hole 9 (exposed portion of the n-type GaAs substrate 1). 10 is formed.
[0013]
As shown in FIG. 1E, after a contact hole 11 is formed in the insulating film 4 on the source electrode 5, a laminated film 12 of Ti / Au (thickness: 100 nm / 200 nm) is formed on the entire surface. Subsequently, after forming a resist pattern (not shown) by photolithography, an Au plating layer 14 is formed to a thickness of 1 μm by electroplating. After removing the resist pattern, the unnecessary portion of the Ti / Au laminated film 12 is removed by an ion milling method. In this way, conduction between the source electrode 5 and the via hole 9 is obtained.
[0014]
Finally, a Ti / Au (thickness: 100 nm / 200 nm) laminated film is formed on the back surface of the substrate 1 to form the ground electrode 13. In the first embodiment, the n-type GaAs substrate 1 is used as a part of the ground electrode 13.
[0015]
Although the HEMT has been described as an example of the basic element, the present invention can be applied to all elements such as a MESFET (Metal Semiconductor Field Effect Transistor) and an HBT (Heteropolar Transistor).
[0016]
Further, although 1 μm-thick undoped GaAs has been described as an example of the buffer layer, a similar via hole structure can be formed for any buffer structure such as a GaAs / AlGaAs laminated film. In addition, as an example of the via hole etching method, dry etching using CCl ₄ has been described as an example, but the same process can be performed by dry etching using other gas such as BCl ₃ or wet etching.
[0017]
In addition, as an example of the metal that connects the source electrode 5 and the via hole 9, a 1 μm thick Au plating layer formed on the Ti / Au laminated film by the electroplating method has been described. The forming method is not limited to this.
[0018]
As the substrate to be used, Si-doped n-type (110 ¹⁹ cm ⁻³ ) GaAs has been described as an example. The substrate doping amount is desirably high in order to reduce the influence of resistance, and is not limited to this concentration and dopant.
[0019]
As described above, in the field effect transistor according to the first embodiment, the n-type GaAs substrate 1 itself can be used as a part of the ground electrode 13 on the back surface. As a result, the via hole 9 only needs to penetrate the HEMT structure portion and the buffer layer portion, so that the etching depth can be reduced and the need for thinning the substrate is eliminated. Therefore, by maintaining the mechanical strength of the substrate, it is possible to prevent cracking of the wafer and to improve the yield. Moreover, since handling becomes easy, it can be expected to shorten the working time.
[0020]
“Second Embodiment”
A field effect transistor according to a second embodiment of the present invention will be described with reference to FIG.
[0021]
In FIG. 2, this field effect transistor is different from the first embodiment in that p-type GaAs 21 is used. The other points are the same as those of the first embodiment, and the same reference numerals are assigned to the same components.
[0022]
In FIG. 2, an undoped GaAs buffer layer 2 and a HEMT structure thin film 3 made of GaAs / AlGaAs / InGaAs are sequentially formed on a p-type (Zn-doped, 110 ¹⁹ cm ⁻³ ) GaAs substrate 21 having a thickness of 600 μm by the MBE method. To grow. Similar to the first embodiment, after forming the transistor part having the gate electrode 6, the source electrode 5 and the drain electrode 7 and the passive element part such as the wiring and the capacitor, it reaches the p-type GaAs substrate from the substrate surface side. A via hole 9 is formed as described above. Subsequently, an AuZn / Au laminated film is deposited and lifted off to form an ohmic electrode 10 for the p-type GaAs substrate at the bottom of the via hole 9.
[0023]
Thereafter, similarly to the first embodiment, an Au / Ti wiring 12 and an Au plating layer 14 for obtaining conduction between the source electrode 5 and the via hole 9 are formed, and Ti / Au is formed on the back surface of the substrate 21. A laminated film is formed as the ground electrode 13. In the second embodiment, the p-type GaAs substrate 21 is used as a part of the ground electrode 13.
[0024]
FIG. 3 shows a band diagram between the field effect transistor portion and the substrate in the case of the first embodiment and the case of the second embodiment. In the first embodiment, since an n-type GaAs substrate is used, the potential of the undoped GaAs buffer layer is raised, resulting in a curved band profile. The degree of bending of the band depends on the purity of the undoped GaAs buffer layer. The larger the band is bent, the shallower the threshold voltage of the field effect transistor and the lower the drain current. On the other hand, when the band curvature is small, the threshold voltage of the field effect transistor is deep and the drain current is large. The purity of the undoped GaAs buffer layer greatly depends on the state of the device during MBE growth. In the second embodiment, the potential in the undoped GaAs buffer layer monotonously increases toward the p-type GaAs substrate side, and since there is no inflection point, it is less affected by the purity in the buffer layer and is stable. It will be a thing.
[0025]
In the present embodiment, Zn-doped p-type (110 ¹⁹ cm ⁻³ ) GaAs has been described as an example of a substrate to be used. The substrate doping amount is desirably high in order to reduce the influence of resistance, and is not limited to this concentration and dopant.
[0026]
As described above, in the second embodiment, the p-type GaAs substrate 21 itself can be used as a part of the ground electrode 13 on the back surface. Since the p-type substrate has a higher resistivity at the same concentration than the n-type substrate, according to the second embodiment, the potential between the field effect transistor portion and the substrate is higher than that of the first embodiment. The distribution is stable, and the uniformity and controllability of field effect transistor characteristics can be improved.
[0027]
“Third Embodiment”
With reference to FIG. 4, the GaAs field effect transistor in 3rd Embodiment is demonstrated.
[0028]
4, this field effect transistor is different from the first embodiment in that an n-type AlGaAs etching stopper layer 22 is formed between an n-type GaAs 1 and an undoped GaAs buffer layer 3. The other points are the same as those of the first embodiment, and the same reference numerals are assigned to the same components.
[0029]
In FIG. 4, an n-type AlGaAs (Si doped, 110 ¹⁹ cm ⁻³ ) etching stopper layer 22 having a thickness of 1 μm is formed on an n-type (Si doped, 110 ¹⁹ cm ⁻³ ) GaAs substrate 1 having a thickness of 600 μm. A HEMT structure thin film 3 composed of a 1 μm undoped GaAs buffer layer 2 and a GaAs / AlGaAs / InGaAs layer is sequentially grown by the MBE method.
[0030]
In the third embodiment, the via hole 9 is etched by selective etching. The selective etching is performed under the condition that only GaAs is etched without etching AlGaAs, and dry etching using BCl ₃ or wet etching using citric acid / hydrogen peroxide solution. Can be performed.
[0031]
Thus, since the n-type AlGaAs etching stopper layer 22 is provided on the n-type GaAs substrate 1, the etching of the via hole 9 can be accurately performed with the n-type AlGaAs stopper layer by using selective etching. Can be stopped. The AlGaAs layer used as the etching stopper layer can be used as a part of the ground electrode 13 integrated with the n-type GaAs substrate 1 by doping n-type.
[0032]
As described above, in the third embodiment, the via hole etching depth can be accurately controlled. In the case of the first and second embodiments, it is necessary to perform over-etching at the time of etching to ensure that the via hole reaches the n-type or p-type substrate. Deepen. In order to form the wiring metal inside the via hole, the via hole is formed as shallow as possible.
[0033]
In the third embodiment, since the depth of the via hole can be accurately controlled, the via hole diameter can be reduced as compared with the first and second embodiments.
[0034]
“Fourth Example”
A field effect transistor according to the fourth embodiment will be described with reference to FIG.
[0035]
In the fourth embodiment, a p-type GaAs layer 2 (Be doped, 110 ¹⁹ cm ⁻³ ) having a thickness of 1 μm is formed on an n-type (Si doped, 110 ¹⁹ cm ⁻³ ) GaAs substrate 1 having a thickness of 600 μm. A HEMT structure thin film 5 composed of an n-type AlGaAs layer 3 (Si doped, 110 ¹⁹ cm ⁻³ ) having a thickness of 1 μm, an undoped GaAs buffer layer having a thickness of 1 μm, and a GaAs / AlGaAs / InGaAs layer is sequentially grown by the MBE method. .
[0036]
As in the first embodiment, after forming a gate electrode 58, a source electrode 57, and a transistor having a drain electrode, as well as passive elements such as wiring and capacitors, a via hole 59 of the source electrode 57 is formed. To do. The via hole is formed in the source electrode 57 using non-selective etching so as to reach the n-type GaAs substrate 51.
[0037]
An AuGe / Ni / Au laminated film is deposited and lifted off in the via hole 59 to form an ohmic electrode 63 for the n-type GaAs substrate 51, and then a contact hole 61 is formed in the insulating film 56 on the source electrode 57. . Thereafter, similarly to the first embodiment, a Ti / Au laminated metal wiring 64 and an Au plating layer 66 for obtaining electrical continuity between the source electrode 57 and the via hole 59 are formed.
[0038]
Furthermore, in the fourth embodiment, a via hole 60 for obtaining conduction between the gate electrode 58 and the n-type AlGaAs layer 53 is formed. The via hole 60 is formed so as to stop at the n-type AlGaAs layer 53 using selective etching. An AuGe / Ni / Au laminated film is deposited and lifted off in the via hole 60 to form an ohmic electrode 63 for n-type AlGaAs.
[0039]
Subsequently, after a contact hole 62 is formed in the insulating film 56 on the gate electrode 58, a Ti / Au laminated metal wiring 64 and an Au plating layer 66 are formed to obtain conduction between the gate electrode 58 and the via hole 60. .
[0040]
Finally, a Ti / Au laminated film is formed on the back surface of the n-type GaAs substrate 51 to form the ground electrode 65. In the third embodiment, the n-type GaAs substrate 51 is used as a part of the ground electrode 65. Furthermore, a structure in which a reverse pn junction diode is introduced between the gate electrode 58 and the ground electrode 65 can be realized.
[0041]
In a device using a field effect transistor, the transistor may be destroyed due to a surge applied to the gate electrode. In order to prevent this, a technique of introducing a diode between the gate electrode and the ground is often used. In this case, since the surge passes through the diode to the ground, the transistor portion can be protected from electrostatic breakdown. However, since it is necessary to dispose a diode simultaneously with the transistor on the substrate surface, there is a problem that the chip area cannot be reduced. In the fourth embodiment, a reverse pn junction diode is formed between a gate electrode and a ground electrode using a via hole structure, so that it is not necessary to form a diode on the substrate surface and the chip area is reduced. be able to.
[0042]
【The invention's effect】
As described above, according to the present invention, a via hole is formed from the surface side of a semiconductor layer having an active region and an insulating region, penetrating the insulating region and buffer layer of the semiconductor layer and reaching the semiconductor substrate. . Then, a conductive layer is formed to connect the semiconductor substrate and the electrode on the semiconductor layer through the via hole.
[0043]
According to the present invention, since it is not necessary to thin the substrate by polishing it from the back side, the strength of the substrate can be maintained. Therefore, cracking of the semiconductor substrate can be prevented and yield can be improved. Moreover, since handling becomes easy, the working time in the manufacturing process can be shortened.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a field effect transistor according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a field effect transistor according to a second embodiment of the present invention.
FIG. 3 is a graph showing a band diagram of a field effect transistor according to the first and second embodiments of the present invention.
FIG. 4 is a cross-sectional view showing a field effect transistor according to a third embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a field effect transistor according to a fourth embodiment of the present invention.
FIG. 6 is a cross-sectional view of a field effect transistor having a conventional via hole structure.
[Explanation of symbols]
1 n-type GaAs substrate 2 undoped GaAs buffer layer 3 HEMT structure thin film 4 insulating film 5 source electrode 6 gate electrode 7 drain electrode 8 photoresist 9 via hole 10 ohmic electrode 11 contact hole 12 Ti / Au wiring 13 ground electrode 14 Au plating layer 21 p-type GaAs substrate 22 n-type AlGaAs etching stopper layer

Claims (2)

an n- conductivity type semiconductor substrate;
A p-type GaAs layer formed on the semiconductor substrate;
An n-type AlGaAs layer formed on the p-type GaAs layer;
A buffer layer formed on the n-type AlGaAs layer ;
A semiconductor layer formed on the buffer layer;
A source electrode and a gate electrode formed on the semiconductor layer;
An insulating film formed on the semiconductor layer so as to cover the source electrode and the gate electrode ;
The insulating film, the semiconductor layer, and the buffer are exposed so as to expose the semiconductor substrate from the first contact hole formed in the insulating film so as to expose the source electrode, through the surface of the insulating film. A first conductive layer by gold plating for electrically connecting the semiconductor substrate and the source electrode over a first via hole formed through the layer, the n-type AlGaAs layer, and the p-type GaAs layer When,
The insulating film, the semiconductor layer, and the n-type AlGaAs layer are exposed from a second contact hole formed in the insulating film so as to expose the gate electrode, through the surface of the insulating film. A second conductive layer by gold plating for electrically connecting the n-type AlGaAs layer and the gate electrode across a second via hole formed through the buffer layer;
And a ground electrode formed on the back surface of the semiconductor substrate. forming a p-type GaAs layer on an n- conductivity type semiconductor substrate;
Forming an n-type AlGaAs layer on the p-type GaAs layer;
Forming a buffer layer on the n-type AlGaAs layer;
Forming a semiconductor layer on the buffer layer;
Forming a source electrode and a gate electrode on the semiconductor layer;
Forming an insulating film on the semiconductor layer so as to cover the source electrode and the gate electrode ;
Forming a first contact hole in the insulating film to expose the source electrode;
Forming a second contact hole in the insulating film to expose the gate electrode;
Forming a first via hole penetrating the insulating film, the semiconductor layer, the buffer layer, the n-type AlGaAs layer, and the p-type GaAs layer so as to expose the semiconductor substrate;
Forming a second via hole penetrating the insulating film, the semiconductor layer, and the buffer layer to expose the n-type AlGaAs layer;
Forming a first conductive layer by gold plating for electrically connecting the semiconductor substrate and the source electrode from the first contact hole through the surface of the insulating film to the first via hole; ,
A second conductive layer is formed by gold plating that electrically connects the n-type AlGaAs layer and the gate electrode from the second contact hole through the surface of the insulating film to the second via hole. Process,
And a step of forming a ground electrode on the back surface of the semiconductor substrate.

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