JP3974061B2 - Heterojunction field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a heterojunction field effect transistor, and more particularly to a high electron mobility transistor comprising an InGaAs electron transit layer.
[0002]
[Prior art]
A field effect transistor including a heterojunction has a characteristic that high-frequency operation is possible, and has become a key device that supports recent ultrahigh-speed communication systems. This type of transistor is required to further improve high-frequency characteristics, amplification characteristics, withstand voltage, and reduce power consumption.
[0003]
Reduction of parasitic resistance is effective for improving high-frequency characteristics and amplification characteristics and reducing power consumption. Parasitic resistance mainly consists of ohmic contact resistance that exists at the junction between the electrode metal and the semiconductor and resistance due to a potential barrier in the conduction band that exists at the junction between semiconductors having different electron affinities.
[0004]
FIG. 2 is a cross-sectional view showing a configuration of a conventional heterojunction field effect transistor. A buffer layer 2 made of GaAs or AIGaAs having a high resistance, an undoped InGaAs electron transit layer 3, an n-type AIGaAs electron supply layer 4, an undoped AlGaAs barrier layer 5, and a highly doped n-type GaAs contact. The layer 7 is laminated by an epitaxial growth method. The GaAs contact layer 7 is formed with a gold germanium alloy for making ohmic contact and an alloying region 8 of nickel, gold and GaAs, and a source electrode 9 and a drain electrode 10 are formed on the alloying region 8. The gate electrode 11 is formed on the AlGaAs barrier layer 5 from which the contact layer 7 has been removed by etching. This is a structure for improving high-frequency characteristics called a recess and withstand voltage.
[0005]
Parasitic resistance due to the heterojunction potential barrier in the structure of FIG. 2 will be described. FIG. 4A shows the energy of the conduction band and the Fermi level Ef in each layer of the AA cross section of FIG. Electrons injected from the source electrode 9 flow through the InGaAs electron transit layer 3 toward the drain electrode 10 via the n-type GaAs contact layer 6, the undoped InGaAs barrier layer 5, and the InGaAs electron supply layer 4. In this path, since the high potential barrier Ec ₂ exists at the interface between the n-type GaAs contact layer 7 and the undoped AlGaAs barrier layer 5 due to the difference in electron affinity, the parasitic resistance is high.
[0006]
Therefore, as shown in FIG. 3, a structure has been proposed in which an n-type AlGaAs layer 12 having an electron affinity located between the n-type GaAs contact layer 7 and the undoped AlGaAs barrier layer 5 is inserted (for example, Patent Documents). 1).
[0007]
FIG. 4B shows the energy of the conduction band and the Fermi level Ef in each layer of the AA cross section in the structure of FIG. Since the potential barrier Ec ₃ is lower than the Ec ₂ in FIG. 4A, the resistance due to the potential barrier can be lowered.
[0008]
Next, the ohmic resistance in the structure of FIG. 3 will be described. When an ohmic contact is made with n-type GaAs, generally, a gold germanium alloy, nickel, and gold are laminated, for example, heat treatment is performed at 400 ° C. for 1 minute to react with n-type GaAs to form an alloyed region. At this time, the alloy region of the gold germanium alloy, nickel, gold alloy and the n-type GaAs contact layer 7 reaches a thickness of 70 to 80 nm. In order to realize a low ohmic resistance, the lowermost surface of the alloying region 8 needs to be in the n-type GaAs contact layer 7 doped with a high concentration. Therefore, in consideration of process variations, the n-type GaAs contact layer 7 needs to have a thickness of at least about 100 nm in order to realize a low contact resistance.
[0009]
[Patent Document 1]
JP-A-6-252175
[Problems to be solved by the invention]
In forming the recess structure, it is important for securing a breakdown voltage to be a high resistance layer under the gate electrode. That is, it is necessary to completely remove the n-type GaAs contact layer 7 and the n-type AlGaAs layer 12 by etching. On the other hand, excessive etching leads to etching of the underlying AlGaAs barrier layer 5. The thickness of the AlGaAs barrier layer 5 determines the distance between the gate electrode 11 and the electron transit layer 3, and is a parameter that greatly affects the characteristics of the device. Therefore, in order to obtain the desired characteristics of the device, the etching is terminated when the n-type GaAs contact layer 7 and the n-type AlGaAs layer 12 are completely removed and the AlGaAs barrier layer 5 is not advanced. desirable.
[0011]
In order to control the etching with high accuracy, it is preferable that the GaAs contact layer 7 is as thin as possible. This is because the thinner the layer, the smaller the variation in thickness in the plane and between the wafers in the epitaxial growth, and the smaller the etching amount, the smaller the over-etching amount.
[0012]
However, since the thickness of the GaAs contact layer 7 formed by epitaxial growth is required to be at least about 100 nm in order to realize a low contact resistance, it is difficult to control the etching and the etching of the AlGaAs barrier layer 5 also proceeds. As a result, there is a problem in that the characteristics of the manufactured element vary.
[0013]
In addition, in such a structure where the n-type GaAs contact layer 7 is thick, electrons injected from the electrodes flow from the bottom surface of the alloy layer 8 toward the electron transit layer 3 in the vertical direction from the bottom surface and side surfaces of the alloy layer 8. Since the ratio of the lateral flow to the contact layer 7 increases, there is a problem that the current density at the recess end increases and the withstand voltage decreases.
[0014]
The present invention reduces the thickness of the GaAs contact layer, suppresses variation in device characteristics, improves yield, and suppresses a decrease in breakdown voltage while reducing contact resistance and parasitic resistance due to a potential barrier, An object is to provide a structure capable of improving the gain characteristics.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an InGaAs electron transit layer, an n-type AlGaAs electron supply layer formed on the electron transit layer, an undoped AlGaAs barrier layer formed on the electron supply layer, An n-type GaAs contact layer formed on the barrier layer, a recess structure gate electrode formed in a recess formed on the barrier layer by removing the contact layer, and an ohmic alloy formed on the contact layer A heterojunction field effect transistor comprising a region and a source electrode and a drain electrode formed on the alloying region, and having an n-type InGaP layer formed between the barrier layer and the contact layer , JP that you present ohmic resistance lower surface of the ohmic alloying region reach the n-type InGaP layer in junction with the n-type InGaP layer To.
[0016]
The ohmic alloyed region includes at least three metals of Au, Ge, and Ni.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. FIG. 1 is a sectional view of a HEMT (High Electron Mobility Transistor) showing an embodiment of the present invention.
[0018]
The HEMT shown in FIG. 1 has a GaAs substrate 1, a buffer layer 2 made of GaAs or AIGaAs having a high resistance, an undoped InGaAs electron transit layer 3, an n-type AIGaAs electron supply layer 4, an undoped AlGaAs barrier layer 5, and a thickness of 50 mm. A highly doped n-type InGaP layer 6 and a highly doped n-type GaAs contact layer 7 having a thickness of 50 nm are stacked by an epitaxial growth method. The n-type GaAs contact layer 7 is made of gold for making ohmic contact. A germanium alloy and an alloying region 8 of nickel, gold, and GaAs are formed. The lower surface of the alloy region 8 penetrates the GaAs contact layer 7 and reaches the n-type InGaP layer 6. Further, the source electrode 9 and the drain electrode 10 are formed on the alloying region 8, and the gate electrode 11 removes the GaAs contact layer 7 and the n-type InGaP layer 6 by etching in order to improve high frequency characteristics and breakdown voltage, A recess structure is formed on the undoped AlGaAs barrier layer 5.
[0019]
The n-type GaAs ohmic contact is obtained by, for example, sequentially laminating a gold germanium alloy, nickel, and gold, performing a heat treatment at 400 ° C. for 1 minute, and forming an alloyed region reacted with the n-type GaAs.
[0020]
Parasitic resistance due to the heterojunction potential barrier in the structure of FIG. 1 will be described. FIG. 4C shows the energy of the conduction band and the Fermi level Ef in each layer of the AA cross section of FIG. Electrons injected from the source electrode 9 flow through the InGaAs electron transit layer 3 toward the drain electrode via the n-type InGaP 6, the undoped Al GaAs barrier layer 5, and the n-type Al GaAs electron supply layer 4. In this path, the potential barrier Ec ₁ exists at the interface between the n-type GaAs contact layer 7 and the n-type InGaP6 due to the difference in electron affinity, but the potential barrier Ec ₁ is lower than its height Ec ₂ and is similar to Ec _3. The parasitic resistance due to the barrier is kept low.
[0021]
Further, according to the configuration of the present invention, the thickness of the n-type GaAs contact layer 7 is as thin as 50 nm compared to the conventional 100 nm. The controllability of the thickness of the undoped AlGaAs barrier layer 5 in the recess forming step by reducing the thickness of the GaAs contact layer 7 will be described below. For example, when the in-plane distribution of the growth layer thickness of epitaxial growth and the accuracy between the wafers are set to ± 3%, the thickness of the GaAs contact layer 7 grown by setting 100 nm is distributed from 97 to 103 nm. In the recess etching of the GaAs contact layer 7 and the n-type InGaP layer 6, for example, when the thickness of the n-type InGaP layer 6 is uniform and the etching rate of the lower AlGaAs barrier layer 5 is the same as that of GaAs, In order to remove the GaAs contact layer 7, it is necessary to carry out etching under a condition that the thickness is at least 103 nm. Under this etching condition, the lower undoped AlGaAs barrier layer 5 is etched by 6 nm at the thinnest part of the n-type GaAs contact layer 7. On the other hand, in the case of the configuration of the present invention, the thickness of the n-type GaAs contact layer 7 grown by setting 50 nm is distributed from 48.5 to 51.5 nm, and the n-type GaAs contact layer 7 is the thinnest part. However, the etching of the undoped AlGaAs barrier layer 5 can be suppressed to 3 nm at the maximum.
[0022]
Thus, since the thickness of the undoped AlGaAs barrier layer 5 under the recess structure gate electrode can be maintained with high accuracy, the uniformity of the characteristics of the fabrication element can be improved, and a high yield can be realized.
[0023]
According to the configuration of the present invention, the lower surface of the alloying region 8 penetrates the n-type GaAs contact layer 7 and reaches the n-type InGaP layer 6. Since InGaP can tolerate a carrier density that is about three times higher than that of AlGaAs, Ge doping and activation from the alloyed region 8 can be effectively performed and contact resistance can be reduced.
[0024]
Therefore, for example, when n-type AlGaAs is selected instead of n-type InGaP, a contact resistance as low as that of the present invention cannot be obtained.
[0025]
Furthermore, according to the present embodiment, since the n-type GaAs contact layer 7 is thinner than the conventional one, the bottom surface of the alloy layer 8 with respect to the flow of electrons from the bottom surface of the alloying region 8 toward the electron transit layer 3 in the vertical direction. In addition, since the rate of lateral flow from the side surface to the contact layer 7 is small, the current density at the recess edge is reduced, and the breakdown voltage can be improved.
[0026]
In the above example, the lower surface of the alloying region 8 remains in the n-type InGaP layer 6, but may penetrate the n-type InGaP layer 6 and reach the AlGaAs barrier layer 5.
[0027]
Although the HEMT has been described in the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made based on the gist of the present invention. For example, it can be applied to field effect transistors having other heterojunctions such as MESFET, and the optimum conditions of the thickness of the GaAs contact layer and InGaP are changed depending on the formation conditions of the ohmic contact alloy layer, and these are excluded from the scope of the present invention. Not what you want.
[Brief description of the drawings]
FIG. 1 is a diagram showing a cross-sectional structure of a high mobility transistor according to an embodiment of the present invention.
FIG. 2 is a diagram showing a cross-sectional structure of a conventional high mobility transistor.
FIG. 3 is a diagram showing a cross-sectional structure of a conventional high mobility transistor.
FIG. 4 shows the conduction band energy and Fermi level Ef of each layer in the AA cross section of FIGS.
[Explanation of symbols]
1 GaAs substrate, 2 undoped buffer layer, 3 undoped InGaAs electron transit layer, 4 n-type AlGaAs electron supply layer, 5 undoped AlGaAs barrier layer, 6 n-type InGaP layer, 7 n-type GaAs contact layer, 8 gold germanium alloy, gold, Alloying region of nickel and n-type GaAs, 9 source electrode, 10 drain electrode, 11 gate electrode, 12 n-type AlGaAs layer.

Claims (2)

An InGaAs electron transit layer;
An n-type AlGaAs electron supply layer formed on the electron transit layer;
An undoped AlGaAs barrier layer formed on the electron supply layer;
An n-type GaAs contact layer formed on the barrier layer;
A recess structure gate electrode formed in a recess formed on the barrier layer by removing the contact layer;
An ohmic alloying region formed in the contact layer ;
A source electrode and a drain electrode formed on the alloying region;
In a heterojunction field effect transistor comprising
An n-type InGaP layer formed between the barrier layer and the contact layer ;
The ohmic lower surface heterojunction field effect transistor, wherein the ohmic resistor is present in the junction between the n-type InGaP layer reaches the n-type InGaP layer of alloyed region.   2. The heterojunction field effect transistor according to claim 1, wherein the ohmic alloyed region includes three metals of Au, Ge, and Ni.

Images