CN117976621B - A through-hole gallium nitride high electron mobility transistor and its manufacturing method - Google Patents

Abstract

The invention relates to the technical field of transistors, in particular to a through-hole gallium nitride transistor with high electron mobility and a manufacturing method thereof, comprising the following steps: and manufacturing an etching barrier layer on the front surface of the wafer, patterning, sequentially etching from top to bottom to obtain deep holes, removing residues, and performing metallization hole filling. Because the key structures such as the source, the drain and the grid which influence the characteristics of the device are not manufactured, the cleaning has a very large process window, and the ultrasonic cleaning mode can be adopted to ensure that the hole wall and the hole bottom by-products are completely removed.

Description

A through-hole gallium nitride high electron mobility transistor and its manufacturing method

Technical Field

The present invention relates to the technical field of transistors, and in particular to a through-hole gallium nitride high electron mobility transistor and a manufacturing method thereof.

Background technique

GaN high electron mobility transistor (HEMT) has the technical characteristics of high electron mobility, high two-dimensional electron gas concentration, and high breakdown electric field. It has outstanding advantages in the field of high frequency and high voltage technology and has gradually become the preferred technology for RF/microwave power amplifiers.

The GaN HEMT process is divided into front-side process and back-side process. The front-side process mainly consists of ohmic contact, device isolation, Schottky contact, dielectric passivation and opening, wiring and other process steps; the back-side process mainly consists of wafer thinning, through-hole production, dicing road production and other process steps.

The front process is responsible for forming the gate, source, and drain electrodes and interconnecting the electrodes, while the back process interconnects the front device with the metal ground plane on the back. Vias are an essential element of microstrip transmission and a direct way for transistors to be grounded. Their importance is very prominent: the quality of the via process is directly related to whether the device function can be realized, the performance of the device, and whether the long-term reliability of the device can be achieved.

At present, the typical GaN HEMT back hole manufacturing process mainly consists of substrate etching, GaN/AlGaN etching, hole cleaning, hole metallization and other steps. Its key technical points include: through-hole etching depth and consistency control, hole bottom and hole wall byproduct cleaning. The through-hole etching process requires the etching of nearly 100 microns thick substrate crystals and one to two microns thick GaN/AlGaN layers in sequence. The thickness of the substrate material fluctuates by several microns or even ten microns, which poses a great challenge to the etching consistency. In addition, the substrate material is hard and brittle, and it is difficult to etch. High-density fluorine-based plasma etching is usually used. The etching bias power is large, and the physical and chemical reactions during the etching process are strong. General photoresists or dielectrics cannot withstand such long-term high-intensity consumption. Therefore, when etching the substrate, a metal hard mask is usually selected as an etching barrier layer, which also causes a large number of byproducts to be generated during the etching process and attached to the hole wall and bottom. In order not to affect the subsequent etching of the GaN/AlGaN layer, it must be removed in time. The etching of GaN/AlGaN layer usually adopts chlorine-based plasma, which also has strong etching ability for the front metal, so the etching depth needs to be precisely controlled to ensure that GaN/AlGaN is completely etched without causing excessive loss of the front metal layer. In the process of GaN/AlGaN etching, part of the back metal will inevitably be consumed. This process will form a large number of unstable byproducts at the bottom of the hole, which need to be removed before hole metallization.

In response to the above technical difficulties, the industry currently has the following countermeasures: through process design and process optimization, improve the etching selectivity of the substrate and GaN, so that the interface stops at the GaN layer after the substrate is etched and the GaN layer is less consumed. After removing the metal hard mask, use a customized cleaning agent to soak and clean the byproducts on the hole wall and bottom of the hole. If necessary, it is necessary to superimpose a certain period of ultrasonic cleaning to effectively remove them. Ultrasonic cleaning may cause damage to transistors and can only be used with restrictions. Such means have a narrow process window and extremely challenge the process control capability. In the subsequent GaN/AlGaN etching process, due to the consumption of a certain degree of barrier layer during substrate etching, the GaN thickness at different locations varies greatly, and the chlorine-based plasma has a low selectivity for GaN and front metal, which inevitably leads to certain differences in the consumption of front metal at each point. This process also involves the selection of the process window, that is, it is necessary to ensure that GaN/AlGaN is completely etched and to control the degree of over-etching. The above requirements have been incorporated into GJB548C-2021 "Test Methods and Procedures for Microelectronic Devices" Method 2010.2, and the requirements are becoming more and more stringent. At the same time, a large number of byproducts will be produced during the GaN/AlGaN etching process and attached to the bottom of the hole. Their properties are extremely unstable and must be completely removed before hole metallization. The above byproduct removal method is still customized cleaning agent immersion cleaning, and a certain degree of ultrasonic cleaning is superimposed when necessary. The problems it brings are almost the same as the byproduct cleaning process after substrate etching.

In general, the back-side via manufacturing process currently used has extremely high requirements for etching consistency, and the byproducts produced by the etching process are difficult to clean, and the cleaning methods are limited. The cleaning process is very likely to cause potential damage to the transistor, which may constitute the potential failure of the device. Due to the narrow process window, the requirements for the incoming material status and process control capabilities are extremely high. Various problems are inevitable in engineering practice, which restricts the improvement of the yield of GaN high electron mobility transistors and their circuits.

Summary of the invention

The purpose of the present invention is to provide a back-through hole gallium nitride high electron mobility transistor and a manufacturing method thereof, so as to solve the technical problems in the prior art that the back-through hole manufacturing process has extremely high requirements on etching consistency and the by-products generated in the etching process are difficult to clean.

The present invention discloses a method for manufacturing a through-hole gallium nitride high electron mobility transistor, comprising the following steps:

An etch stop layer is made on the front side of the wafer and patterned, and then deep holes are obtained by etching from top to bottom. The residue is then removed and the holes are filled with metal.

Since key structures that affect device characteristics, such as source, drain, and gate, have not yet been fabricated, the cleaning process here has a large process window, and ultrasonic cleaning can be used to ensure that byproducts on the hole wall and bottom are completely removed.

Furthermore, the deep hole is obtained by etching in-situ SiN, AlGaN/GaN and the substrate layer in sequence from top to bottom, and the substrate layer is etched to 80-110 μm.

Furthermore, the in-situ SiN, AlGaN/GaN and substrate layers are etched by ICP-RIE.

Furthermore, the substrate layer material may be silicon carbide, silicon, sapphire, gallium nitride and diamond.

Furthermore, a seed layer of metal is sputtered on the surface of the wafer and then a patterned etching stop layer is formed.

Furthermore, the seed layer metal is TiW/Au, wherein the thickness of TiW is 200-500 Å, and the thickness of Au is 1000-2000 Å.

Furthermore, the etching stop layer is patterned metal Ni with a thickness of 5-10 μm.

Furthermore, the metallization hole filling is specifically performed by seed layer sputtering, electroplating hole filling, metal grinding and polishing, and metal patterning.

Furthermore, the hole-filling metal is Au or Cu.

Furthermore, source/drain metal and gate metal are prepared after metal patterning.

Furthermore, after the gate metal is prepared, the remaining front side processes are continued.

Furthermore, the remaining front side processes include a second dielectric growth, field plate fabrication, a first metal wiring, a third dielectric growth, a second metal wiring and a front side protective layer.

Furthermore, after the front process is completed, the back process is carried out.

Furthermore, the backside process includes substrate thinning, backside metal fabrication and debonding.

Furthermore, the back wafer thinning process is divided into two stages: the first stage is to thin the substrate by grinding and polishing until the through-hole metal is slightly exposed, and the second stage is to introduce the corrosive liquid corresponding to the through-hole metal into the grinding and polishing liquid while continuing to thin the substrate until the substrate thickness is thinned to the target thickness. At the same time, the through-hole metal and the substrate are almost at the same level, which is convenient for subsequent processes.

Furthermore, the backside wafer is thinned to 75-100 μm.

A through-hole gallium nitride high electron mobility transistor is manufactured using the above method.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention completely avoids the damage to the transistor caused by the cleaning process of the through-hole etching byproducts by placing the through-hole process before the source, drain and gate are made. The cleaning process window is wide and the cleaning effect is fully guaranteed.

2. The present invention introduces a solid electroplating hole filling process, which improves the source current carrying capacity and effectively reduces the source resistance, which is beneficial to improving the high-frequency characteristics of the device;

3. The through-hole technology releases some stress in advance, which helps to improve the consistency between the device performance after the front process and the final device performance, and reduce the test screening cost;

4. The via-first technology does not increase the photolithography mask, and the number of process steps is equivalent to that of the via-last technology. After avoiding the technical deficiencies of the via-last technology, the via-first technology helps to improve the manufacturing yield of GaN high electron mobility transistors, thereby reducing their manufacturing costs.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only represent some embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

FIG1 is a GaN epitaxial structure before processing by the process of the present invention;

FIG2 shows the electroplating of an etching stop layer on the front side of a wafer and completion of patterning in the present invention;

FIG3 is a plasma etched deep hole;

Figure 4 shows metallization hole filling;

FIG5 is a diagram of source and drain metal patterning;

FIG6 is an in-situ SiN etching;

FIG7 shows the completion of source and drain metal fabrication;

FIG8 shows the growth of SiN for use as a protection and passivation layer;

FIG9 is a diagram for manufacturing a gate metal;

FIG10 shows the wafer after the front side process is completed and then flip-bonded to the carrier through the bonding material;

FIG11 is a diagram of substrate grinding and thinning;

Figure 12 shows the production of the back metal;

Figure 13 shows debonding.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

Example 1

A method for manufacturing a through-hole gallium nitride high electron mobility transistor using the above device in this embodiment, as shown in FIG. 1 to FIG. 13 , comprises the following steps:

A. As can be seen from Figure 1, from bottom to top, they are: substrate layer, AlGaN/GaN heterojunction layer and in-situ SiN layer. The thickness of the in-situ grown SiN layer is 10-30nm, and the growth method is MOCVD. The role is to protect the semiconductor surface. The seed layer metal is sputtered on the wafer surface, preferably TiW/Au, where the thickness of TiW is 200-500 Å and the thickness of Au is 1000-2000 Å; a patterned metal Ni is made as an etching stop layer with a thickness of 5~10μm. The patterning is mainly used to expose the specific position to be etched later. The method is to first electroplate the metal Ni on the entire surface, then use positive photoresist exposure and development to define the pattern, and then corrode the exposed metal Ni and the seed layer metal underneath; or use negative photoresist exposure and development and then electroplate the metal Ni, and remove the negative photoresist that blocks the hole after electroplating;

B. Etching in-situ SiN, preferably ICP-RIE etching, using F-based plasma, with an etching rate of 100-300 Å/min;

C. Etching AlGaN/GaN, preferably ICP-RIE etching, using Cl-based plasma, with an etching rate of 150-300 nm/min, and after etching, placing in deionized water for ultrasonic cleaning until by-products are completely removed;

D. Etch the substrate by ICP-RIE etching, using etching gas corresponding to the substrate material, etching rate 0.8-1.2μm/min, etching target depth 80-110μm, etching uniformity ±5%, and ultrasonic cleaning in deionized water after etching until by-products are completely removed;

E. Use nitric acid and hydrogen peroxide mixed solution to corrode metal Ni, with a corrosion rate of 0.5~1μm/min;

F. Use Au-specific KI etching solution to corrode Au;

G. TiW is corroded by heated hydrogen peroxide solution, and the heating temperature of hydrogen peroxide is 40-50°C. The ICP-RIE equipment for etching through holes has multiple chambers, and etching processes with different atmospheres are carried out in different chambers to avoid cross contamination. Since key structures that affect device characteristics such as source, drain, and gate have not yet been made, the cleaning here has a large process window, and ultrasonic cleaning can be used to ensure that byproducts on the hole wall and bottom are completely removed;

H. Sputtering the seed layer metal again, and then electroplating the metal to fill the deep hole, the hole filling metal is Au or Cu;

I. After the metal is polished, it is exposed and developed, and then the patterned metal is obtained by etching;

J. Evenly apply negative resist with a thickness of 1.6-2.0 μm, and obtain source and drain patterns after exposure and development;

K. Etching in-situ SiN, preferably ICP-RIE etching, using F-based plasma, with an etching rate of 100-150 Å/min;

L. After HCl cleaning, source and drain metals are evaporated, typically Ti/Al multilayer metals with a total thickness of 2500-3500 Å;

M. After stripping, enter the annealing furnace for rapid thermal annealing to form ohmic contact. The typical annealing conditions are 830-870℃, 20-60s;

N. Grow a layer of dielectric to protect the transistor surface. The dielectric is preferably silicon nitride. The growth method is PECVD. The dielectric thickness is 800-2000 Å.

O. Device isolation, preferably using a planar isolation method of ion implantation, the ions being F, B, N, etc.;

P. Open the dielectric to expose the source and drain metal patterns;

Q. To make the gate electrode, first use positive photoresist exposure and development, then etch SiN to define the gate foot, then use negative photoresist exposure and development, then evaporate the gate metal, and after peeling, the structure shown in Figure 9 is formed. The typical metal is Ni/Pt/Au, with a total thickness of 5000-8000 Å;

R. After completing the secondary dielectric process, field plate process, first-layer metal wiring process, third dielectric process, and second-layer metal wiring process, flip-bonding is performed and then transferred to the back-side process. The bonding between the wafer and the sapphire carrier is achieved through special materials such as paraffin, which can withstand high temperatures above 200°C and acid and alkali corrosion, and provide protection for the front-side devices;

S. Wafer thinning, thinning to 75-100μm, thinning is divided into two stages: the first stage is to thin the substrate by grinding and polishing until the through-hole metal is slightly exposed, and the second stage is to introduce the corresponding etching liquid of the through-hole metal into the grinding and polishing liquid while continuing to thin the substrate until the substrate thickness is thinned to the target thickness. At the same time, the through-hole metal and the substrate are almost at the same level, which is convenient for subsequent processes;

T. Sputtering seed layer, electroplating Au, thickness 5-8μm;

U. Make scribe lines, make back metal according to design requirements and interconnect with through-hole metal, and etch to form scribe lines for subsequent cutting and dicing;

V. Debonding: After the backside process is completed, the wafer will be debonded, and then transferred to the film, cut, and picked.

The above are the implementation methods listed in this embodiment, but this embodiment is not limited to the above optional implementation methods. Those skilled in the art can arbitrarily combine the above methods to obtain other various implementation methods. Anyone can derive other various forms of implementation methods under the inspiration of this embodiment. The above specific implementation methods should not be understood as limiting the scope of protection of this embodiment. The scope of protection of this embodiment shall be based on the definition in the claims, and the description can be used to interpret the claims.

Claims (6)

1. A method for manufacturing a through-hole gallium nitride transistor with high electron mobility is characterized in that: the method comprises the following steps:

Providing a wafer with a substrate layer, an AlGaN/GaN layer and an in-situ SiN layer structure from bottom to top, and sputtering seed layer metal on the surface of the wafer;

Manufacturing an etching barrier layer on the front surface of the wafer, patterning, sequentially etching the in-situ SiN layer, the AlGaN/GaN layer and the substrate layer from top to bottom to obtain deep holes, removing residues, and sputtering seed layer metal again;

Then electroplating metal to fill deep holes, performing exposure and development after metal polishing, obtaining patterned metal through corrosion, uniformly coating negative photoresist, and obtaining source-drain patterns after exposure and development;

Etching the in-situ SiN layer, evaporating source and drain metal after cleaning, and rapidly annealing by an annealing furnace after stripping to form ohmic contact;

Growing a layer of medium for protecting the surface of the transistor, isolating the device, and forming a hole in the medium to expose the source-drain metal pattern;

then firstly adopting positive photoresist to expose and develop, then etching a medium to define gate feet, then adopting negative photoresist to expose and develop, evaporating gate metal, and stripping to form gate metal;

and after the preparation of the gate metal is finished, continuing the residual front-side process and then transferring to the back-side process.

2. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the etching of the substrate layer is 80-110 mu m.

3. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the seed layer metal is TiW/Au, wherein the thickness of TiW is 200-500A, and the thickness of Au is 1000-2000A.

4. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the etching barrier layer is patterned metal Ni, and the thickness is 5-10 mu m.

5. A method of fabricating a through-hole gan high electron mobility transistor according to claim 1, wherein: the thinning process of the back wafer comprises two sections: the first section is to expose the substrate to the through hole metal through polishing, and the second section is to introduce etching liquid corresponding to the through hole metal into the polishing liquid while continuing to thin the substrate until the thickness of the substrate is thinned to the target thickness.

6. A through-hole gallium nitride high electron mobility transistor, characterized by: a method of fabricating a through-hole gan high electron mobility transistor according to any of claims 1-5.