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JP4735538B2 - Electronics - Google Patents

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Publication number
JP4735538B2
JP4735538B2 JP2006513612A JP2006513612A JP4735538B2 JP 4735538 B2 JP4735538 B2 JP 4735538B2 JP 2006513612 A JP2006513612 A JP 2006513612A JP 2006513612 A JP2006513612 A JP 2006513612A JP 4735538 B2 JP4735538 B2 JP 4735538B2
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hole
lead
electronic component
center
circuit board
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JPWO2005112531A1 (en
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善史 金高
直美 石塚
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447Lead-in-hole components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • H05K1/116Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10189Non-printed connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

本発明は、スルーホールを有する回路基板を用いた電子機器に関し、特に、挿入型の電子部品を無鉛はんだにてはんだ付け搭載するのに適した回路基板に挿入型電子部品を搭載してなる電子機器に関する。 The present invention relates to an electronic apparatus using the circuit board having a through hole, in particular, at an insertion type electronic component lead-free solder by mounting the insertion type electronic component on a circuit board suitable for mounting soldering Relates to electronic equipment.

回路基板上には、多くのリードレス化された電子部品が表面実装されるが、コネクタ、可変抵抗器などのいくつかの電子部品は、挿入型電子部品としてそのリードがスルーホールに挿入され、はんだ付けされる。図7(a)は、挿入型電子部品が実装される従来の回路基板の挿入型電子部品の実装部の構造を示す上面図であり、図7(b)は、図7(a)のA−A線による断面図である。なお、本明細書において、スルーホールとはプレーテッドスルーホールなどのように貫通孔の壁面が導電性膜によって被覆されているスルーホールのことをいう。   Many leadless electronic components are surface-mounted on a circuit board, but some electronic components such as connectors and variable resistors are inserted into through-holes as insertion-type electronic components, Soldered. FIG. 7A is a top view showing a structure of a mounting portion of an insertion type electronic component of a conventional circuit board on which the insertion type electronic component is mounted, and FIG. 7B is a diagram of A in FIG. It is sectional drawing by the -A line. In the present specification, the through hole refers to a through hole in which the wall surface of the through hole is covered with a conductive film, such as a plated through hole.

電子部品の実装用に使用される回路基板は、通常、次のような工程を経て作製される。ガラス布基材に、エポキシ樹脂、ポリイミド樹脂などの樹脂をしみこませ、半硬化させたプリプレグ又は紙基材にフェノール樹脂をしみこませ、半硬化させたプリプレグの積層体上に、銅箔を加圧加熱処理して貼り付けた銅張積層板を用い、銅箔をフォトエッチング法などによりパターニングして所定層数の内層パターンを有する配線基板を作製する。そして、プリプレグとの密着性を向上させるために、銅箔(内層パターン)表面に粗面化処理(黒化処理)を施した後、それらの配線基板と銅張積層板を銅箔が最外層となるようにプリプレグを介して積層し、加圧加熱して一体化させ、樹脂積層板2内に内層配線3を有する基板を作製する。   A circuit board used for mounting electronic components is usually manufactured through the following steps. A glass cloth base material is impregnated with a resin such as an epoxy resin or a polyimide resin, and a semi-cured prepreg or a paper base material is impregnated with a phenol resin, and a copper foil is pressed on the semi-cured laminate of the prepreg. Using a copper-clad laminate attached by heat treatment, the copper foil is patterned by a photoetching method or the like to produce a wiring board having a predetermined number of inner layer patterns. Then, in order to improve the adhesion to the prepreg, the surface of the copper foil (inner layer pattern) is subjected to a roughening treatment (blackening treatment), and then the copper foil is the outermost layer of the wiring board and the copper-clad laminate. Are laminated through a prepreg and integrated by pressurization and heating to produce a substrate having the inner layer wiring 3 in the resin laminate 2.

次いで、ドリル加工により貫通孔を開口し、内層配線とスルーホールとの接続性をよくするために、内層配線部の樹脂をクリーニング(デスミヤ)した後、活性化処理、無電解めっき、電解めっきを行って、スルーホール4を形成する。続いて、穴埋め法又はテンティング法によりスルーホールを保護し、最外層の銅層のパターニングを行って外層配線5を形成すると共に、基板表裏面のスルーホールの周囲にランド6を形成する。スルーホール4、外層配線5及びランド6は、パターンめっき法により形成することもできる。   Next, the through hole is opened by drilling, and in order to improve the connectivity between the inner layer wiring and the through hole, the resin of the inner layer wiring part is cleaned (desmear), and then activation treatment, electroless plating, and electrolytic plating are performed. As a result, the through hole 4 is formed. Subsequently, the through hole is protected by a hole filling method or a tenting method, the outermost layer copper layer is patterned to form the outer layer wiring 5, and the land 6 is formed around the through hole on the front and back surfaces of the substrate. The through hole 4, the outer layer wiring 5, and the land 6 can also be formed by a pattern plating method.

最後に、基板表裏面のはんだ付け部を除く領域にソルダーレジスト(図示せず)を形成して、多層回路基板1の作製工程が完了する。   Finally, a solder resist (not shown) is formed in the region excluding the soldered portions on the front and back surfaces of the substrate, and the manufacturing process of the multilayer circuit board 1 is completed.

以上は内層配線を有する多層回路基板の製造工程であるが、両面回路基板の場合には、両面銅張積層板を出発材料として貫通孔形成工程以降の工程を行うことにより形成することができる。   The above is the manufacturing process of the multilayer circuit board having the inner layer wiring, but in the case of the double-sided circuit board, it can be formed by performing the process after the through-hole forming process using the double-sided copper-clad laminate as a starting material.

図7において、電子部品実装後の電子部品の筐体部の中心を通る線をOにて示す。従来の回路基板においては、スルーホール4は、等間隔に配列されていた。即ち、電子部品の筐体部中心に最も近いリードが挿入される中央部スルーホール4a付近においても、電子部品の筐体部の最外端リードが挿入される最外端スルーホール4b付近においても等しいピッチで配列されていた。   In FIG. 7, a line passing through the center of the casing of the electronic component after mounting the electronic component is indicated by O. In the conventional circuit board, the through holes 4 are arranged at equal intervals. That is, even in the vicinity of the central through hole 4a where the lead closest to the center of the casing of the electronic component is inserted, and also in the vicinity of the outermost end through hole 4b where the outermost lead of the casing of the electronic component is inserted. They were arranged at an equal pitch.

このようにして作製された多層回路基板1を用いて、電子部品のはんだ付けを行う工程は、一般的には、チップ部品及びQFPになどの表面実装型部品を実装するリフロー工程を行った後、挿入型の電子部品を実装するフロー工程が行われる。   The process of soldering an electronic component using the multilayer circuit board 1 manufactured in this way is generally performed after a reflow process of mounting a surface mount type component such as a chip component and a QFP. A flow process for mounting the insertion type electronic component is performed.

電子部品をはんだ付けする場合のはんだ材料には、錫鉛系はんだが長い間用いられてきており、特にSnとPbの濃度比(質量%)がSn:Pb=60〜63%:40〜37%の共晶組成近傍である錫鉛共晶はんだが用いられてきた。錫鉛共晶はんだは延性に富む材料であったため、はんだ付け工程時などで多層回路基板1及び電子部品の筐体部の熱膨張・収縮の差によって発生する応力を錫鉛共晶はんだで緩和することが可能であった。   As a solder material for soldering electronic components, tin-lead solder has been used for a long time. Particularly, the concentration ratio (mass%) of Sn and Pb is Sn: Pb = 60 to 63%: 40 to 37. Tin-lead eutectic solder with a percent eutectic composition has been used. Since the tin-lead eutectic solder was a material with high ductility, the stress generated by the difference in thermal expansion and contraction of the multilayer circuit board 1 and the casing of the electronic component during the soldering process was alleviated with tin-lead eutectic solder. It was possible to do.

実開昭57−037276号公報Japanese Utility Model Publication No. 57-037276 特開2001−156420公報JP 2001-156420 A 特開2003−218534公報JP 2003-218534 A 特開平08−148790号公報JP 08-148790 A 特開平04−261087号公報Japanese Patent Laid-Open No. 04-261087 特開平03−009594号公報Japanese Patent Laid-Open No. 03-009594

しかしながら、近年、環境意識の高まりにより鉛による環境汚染が問題となり、鉛を含まない無鉛はんだへの転換が急速に進んでいる。この無鉛はんだは、錫を主成分とし、添加成分として、銀、銅、亜鉛、ビスマス、インジウム、アンチモン、ニッケル及びゲルマニウム等を含有しており、従来の錫鉛共晶はんだ(Sn63質量%、残りPb)と比べて、金属の引張り強度及びクリープ強度が強く、また延性が小さいという金属特性を持っている。また、溶融温度も錫鉛共晶はんだが183℃であるのに比べ、無鉛はんだは190℃〜230℃と高くなっている。そのため、はんだ付け工程時などの多層回路基板及び電子部品の筐体部の熱膨張及び収縮の差により発生する応力が大きくなり、かつはんだ自身での応力緩和が起こりにくいため、回路基板へかかる応力が大きくなり、特に最外端スルーホール部が破壊される現象が見受けられるようになった。従来の錫鉛共晶はんだでもスルーホール部が破壊される現象は見受けられたが、無鉛はんだへ転換したことでこの現象がより顕著になった。その状況について図8〜図10を参照してより具体的に説明する。   However, in recent years, environmental pollution due to lead has become a problem due to an increase in environmental awareness, and the conversion to lead-free solder containing no lead is rapidly progressing. This lead-free solder contains tin as a main component, and contains silver, copper, zinc, bismuth, indium, antimony, nickel, germanium, and the like as additive components. Compared with Pb), the metal has a metal property that the tensile strength and creep strength of the metal are strong and the ductility is small. Also, the melting temperature of the lead-free solder is as high as 190 ° C. to 230 ° C., compared to 183 ° C. for the tin-lead eutectic solder. As a result, the stress generated by the difference in thermal expansion and contraction between the multilayer circuit board and the electronic component housing during the soldering process is large, and the stress on the circuit board is less likely to be relaxed by the solder itself. In particular, a phenomenon that the outermost end through-hole portion is broken can be seen. Even though the conventional tin-lead eutectic solder had a phenomenon that the through-hole portion was destroyed, this phenomenon became more remarkable by switching to lead-free solder. The situation will be described more specifically with reference to FIGS.

図8は、図7に示す従来の多層回路基板1に、無鉛はんだを用いて電子部品をはんだ付けした状態を示す断面図である。なお、この断面図は、FR−4を基材とする回路基板に、筐体がポリアミドで、8ピン1列のコネクタを無鉛はんだ(Sn−3.0質量%Ag−0.5質量%Cu)を用いてはんだ付けした場合の断面写真を基に作図した図面である。   FIG. 8 is a cross-sectional view showing a state in which an electronic component is soldered to the conventional multilayer circuit board 1 shown in FIG. 7 using lead-free solder. This cross-sectional view shows a circuit board made of FR-4 as a base material, the housing is made of polyamide, and an 8-pin single-row connector is lead-free solder (Sn-3.0 mass% Ag-0.5 mass% Cu). ) Is a drawing based on a cross-sectional photograph when soldering using.

電子部品の筐体部材料の線膨張係数をα、回路基板の基板材料の線膨張係数をβとするとき、α>βのケースでは、図8に示されるように、筐体部7とリード8とを有する電子部品が多層回路基板1に実装されており、電子部品のリード8は、はんだフィレット9により多層回路基板1の銅層と電気的・機械的に結合されている。同図に示されるように、中央部スルーホール4aに挿入されたリード8は、多層回路基板1に対してほとんど垂直で、かつ中央部スルーホール4aの中心とリード8の中心がほぼ一致した状態ではんだ付けされている。しかし、最外端スルーホール4bに挿入されたリード8は、最外端スルーホール4bの中心から実装時の電子部品の筐体部7の中心方向から逆方向(外側方向)にずれた位置にはんだ付けされ、かつ図の上方に向かって電子部品の筐体部7の中心方向に曲げられた状態ではんだ付けされている。このように実装される理由は、電子部品の筐体部7と多層回路基板1の材質の違いによる熱膨張係数の差によるものである。   When the coefficient of linear expansion of the casing material of the electronic component is α and the coefficient of linear expansion of the substrate material of the circuit board is β, in the case of α> β, as shown in FIG. The electronic component lead 8 is electrically and mechanically coupled to the copper layer of the multilayer circuit board 1 by a solder fillet 9. As shown in the figure, the lead 8 inserted into the central through-hole 4a is almost perpendicular to the multilayer circuit board 1, and the center of the central through-hole 4a and the center of the lead 8 substantially coincide with each other. Soldered with. However, the lead 8 inserted into the outermost end through-hole 4b is displaced from the center of the outermost end through-hole 4b in the opposite direction (outward direction) from the center direction of the casing 7 of the electronic component during mounting. It is soldered and soldered in a state bent toward the center of the casing 7 of the electronic component toward the upper side of the figure. The reason for mounting in this way is due to the difference in thermal expansion coefficient due to the difference in material between the casing 7 of the electronic component and the multilayer circuit board 1.

図9は、電子部品が回路基板に搭載されてはんだ付けが行われる前の状態を示す断面図である。はんだ付け工程前には、最外端スルーホール4bを含む全てのスルーホールの中心とリード8の中心はほぼ一致している。この状態から予備加熱が行われ、はんだ槽への浸漬が行われると、電子部品の筐体部7の線熱膨張係数が多層回路基板1の線熱膨張係数よりも大きい場合、電子部品の筐体部7が多層回路基板1よりも大きく熱膨張し、また電子部品の筐体部7の中心から離れる箇所ほど、電子部品の筐体部7と多層回路基板1の熱膨張量の差が大きくなるため、最外端のリード8の中心は最外端スルーホール4bの中心から電子部品実装時の筐体部7の中心へ向かう方向と反対の方向にずれる。この状態でスルーホール内は溶融はんだで充填され、多層回路基板ははんだ槽から引き上げられる。はんだ付け工程直後では、温度が下がるにつれ電子部品の筐体部7は多層回路基板1よりも大きく熱収縮するため、リード8は図の上方に向かって、電子部品実装時の筐体部7の中心方向に曲げられた状態となる。   FIG. 9 is a cross-sectional view showing a state before electronic components are mounted on a circuit board and soldered. Before the soldering process, the centers of all the through holes including the outermost end through hole 4b and the centers of the leads 8 are substantially coincident. When preheating is performed from this state and immersion in a solder bath is performed, if the linear thermal expansion coefficient of the casing portion 7 of the electronic component is larger than the linear thermal expansion coefficient of the multilayer circuit board 1, the casing of the electronic component is The difference between the thermal expansion amounts of the electronic component casing 7 and the multilayer circuit board 1 increases as the body part 7 thermally expands more than the multilayer circuit board 1 and away from the center of the electronic component casing 7. Therefore, the center of the lead 8 at the outermost end is shifted in the direction opposite to the direction from the center of the outermost end through hole 4b toward the center of the casing 7 when the electronic component is mounted. In this state, the inside of the through hole is filled with molten solder, and the multilayer circuit board is pulled up from the solder bath. Immediately after the soldering process, as the temperature decreases, the housing part 7 of the electronic component is more thermally contracted than the multilayer circuit board 1, so that the leads 8 are directed upward in the figure toward the upper part of the housing part 7 when the electronic component is mounted. It is in a state bent in the center direction.

一方、α<βのケースでは、最外端スルーホール4bの中心から実装時の電子部品の筐体部7の中心方向にずれた位置ではんだ付けされて、かつ図の上方に向かって電子部品の筐体部7の中心方向と逆方向に曲げられた状態ではんだ付けされている。   On the other hand, in the case of α <β, the electronic component is soldered at a position shifted from the center of the outermost end through-hole 4b toward the center of the casing 7 of the electronic component during mounting, and upwards in the figure. Soldered in a state bent in the direction opposite to the center direction of the casing portion 7 of the case.

図10は、図8の左端の最外端スルーホール4bの部分を拡大して示す断面図である。図10(a)に示されるように、最外端のリード8は、最外端スルーホール4bの中心から電子部品実装時の筐体部7の中心方向と反対方向にずれてはんだ付けされるため、スルーホール−リード8間の電子部品筐体部中心方向と逆方向の領域(A部:図中斜線の付された領域)でのはんだ量が少なくなる。そして、リード8は図の上方に向かって筐体部7の中心方向に曲げられている。ここで、無鉛はんだは錫鉛共晶はんだに比べて、はんだ自身の応力緩和能力が低いため、リード8が曲げられることによって発生した応力を無鉛はんだで吸収する効果は著しく低い。このため、最外端スルーホール4bの電子部品実装時の筐体部中心と逆方向のスルーホール部のスルーホールコーナ部Bやスルーホール外壁面Cには大きな応力がかかることとなる。そのため、図10(b)に示すように、スルーホールコーナ部にコーナクラック11が発生したり、図10(c)に示すように、スルーホールめっき層が剥がれるスルーホール剥離12が発生しやすくなり、電子部品の電気的導通不良が起こることになる。   10 is an enlarged cross-sectional view of the leftmost outermost through hole 4b in FIG. As shown in FIG. 10A, the lead 8 at the outermost end is soldered by shifting from the center of the outermost end through-hole 4b in the direction opposite to the center direction of the housing part 7 when the electronic component is mounted. For this reason, the amount of solder in the region opposite to the center direction of the electronic component housing portion between the through hole and the lead 8 (A portion: the hatched region in the figure) is reduced. The lead 8 is bent in the center direction of the housing portion 7 upward in the figure. Here, since the lead-free solder has a lower stress relaxation capability than the tin-lead eutectic solder, the effect of absorbing the stress generated by bending the lead 8 with the lead-free solder is remarkably low. For this reason, a large stress is applied to the through-hole corner portion B and the through-hole outer wall surface C of the through-hole portion in the direction opposite to the center of the housing portion when the electronic component of the outermost end through-hole 4b is mounted. Therefore, as shown in FIG. 10 (b), a corner crack 11 is likely to occur in the through-hole corner portion, and as shown in FIG. 10 (c), a through-hole peeling 12 in which the through-hole plating layer is peeled off easily occurs. As a result, poor electrical continuity of electronic components occurs.

同様に、電子部品の筐体部材料の線膨張係数をα、回路基板の基板材料の線膨張係数をβとしたとき、α<βのケースでは、スルーホールとリード8との間の電子部品筐体部中心方向の領域でのはんだ量が少なくなるため、最外端スルーホール4bの電子部品実装時の筐体部中心方向のスルーホール部には大きな応力が印加されることとなる。このため、スルーホールコーナ部にコーナクラックが発生したり、スルーホールめっき層が剥がれるスルーホール剥離12が発生しやすくなる。このコーナクラック及びスルーホール剥離12により、電子部品の電気的導通不良が発生する。   Similarly, when the coefficient of linear expansion of the casing material of the electronic component is α and the coefficient of linear expansion of the substrate material of the circuit board is β, in the case of α <β, the electronic component between the through hole and the lead 8 is used. Since the amount of solder in the region in the center direction of the housing portion is reduced, a large stress is applied to the through hole portion in the center portion of the housing portion when the electronic component is mounted on the outermost end through hole 4b. For this reason, a corner crack is likely to occur in the through-hole corner portion, or through-hole peeling 12 in which the through-hole plating layer is peeled off easily occurs. Due to this corner crack and through-hole peeling 12, an electrical continuity failure of the electronic component occurs.

本発明の目的は、挿入型電子部品を無鉛はんだを用いて実装しても、スルーホールコーナクラック及びスルーホール剥離が発生することがない信頼性の高い回路基板を用いた電子機器を提供することにある。 An object of the present invention, even when the insertion type electronic component mounted with the lead-free solder, an electronic apparatus using a reliable circuit board never through hole corner cracks and through-holes peeling occurs There is.

本願第1発明に係る電子機器は、リード付きの電子部品のリードが挿入されはんだ付けされるスルーホールと、基板表裏面の前記スルーホールの周囲に前記スルーホールを介して電気的に接続されたランドとを有する。そして、この回路基板は、前記電子部品の筐体部材料の線膨張係数をα、前記回路基板の基板材料の線膨張係数をβとし、前記回路基板の前記電子部品の最外端リードが挿入される最外端スルーホールの中心とこの最外端スルーホールに最も近いスルーホールの中心との距離をP′、前記電子部品の中心に最も近いリードが挿入される中央部スルーホールの中心とこの中央部スルーホール最も近いスルーホールの中心との距離をPとして、
(α−β)(P′−P)>0
を満たす回路基板に、
リード付きの電子部品が搭載され、前記電子部品のリードが前記回路基板のスルーホールに挿入され、無鉛はんだによりはんだ付けされ、
前記電子部品の筐体部中心と前記最外端スルーホールの中心との距離をL、前記無鉛はんだの融点と常温(25℃)との差をΔTとして、
|P′−P|≧|α−β|×L×ΔT
を満たすことを特徴とする。
The electronic device according to the first aspect of the present invention is electrically connected to the through hole into which the lead of the electronic component with the lead is inserted and soldered, and the periphery of the through hole on the front and back surfaces of the substrate through the through hole. With land. In this circuit board, the linear expansion coefficient of the casing material of the electronic component is α, the linear expansion coefficient of the substrate material of the circuit board is β, and the outermost lead of the electronic component of the circuit board is inserted. P ′ is the distance between the center of the outermost through hole and the center of the through hole closest to the outermost through hole, and the center of the central through hole into which the lead closest to the center of the electronic component is inserted Let P be the distance from the center of the nearest through hole.
(Α−β) (P′−P)> 0
Circuit board that meets
An electronic component with a lead is mounted, the lead of the electronic component is inserted into the through hole of the circuit board, and soldered with lead-free solder,
The distance between the center of the casing of the electronic component and the center of the outermost through hole is L, and the difference between the melting point of the lead-free solder and room temperature (25 ° C.) is ΔT.
| P′−P | ≧ | α−β | × L × ΔT
It is characterized by satisfying .

また、本願第2発明に係る電子機器は、等間隔で配列されたリードを有するリード付きの電子部品のリードが挿入されはんだ付けされるスルーホールと、基板表裏面の前記スルーホールの周囲に前記スルーホールを介して電気的に接続されたランドとを有する。そして、この回路基板は、前記電子部品の筐体部材料の線膨張係数をα、前記回路基板の基板材料の線膨張係数をβとし、前記回路基板の前記電子部品の最外端リードが挿入される最外端スルーホールの中心とこの最外端スルーホールに最も近いスルーホールの中心との距離をP′、前記最外端スルーホールとこの最外端スルーホールに最も近いスルーホールとに挿入される前記電子部品のリードを結ぶ方向に配列されたリードのピッチをpとして、
(α−β)(P′−p)>0
を満たす回路基板に、
リード付きの電子部品が搭載され、前記電子部品のリードが前記回路基板のスルーホールに挿入され、無鉛はんだによりはんだ付けされ、
前記電子部品の筐体部中心と前記最外端スルーホールの中心との距離をL、前記無鉛はんだの融点と常温(25℃)との差をΔTとして、
|P′−p|≧|α−β|×L×ΔT
を満たすことを特徴とする。
The electronic device according to the second invention of the present application is characterized in that a lead of an electronic component with a lead having leads arranged at equal intervals is inserted and soldered around the through hole on the front and back surfaces of the substrate. And a land electrically connected through the through hole. In this circuit board, the linear expansion coefficient of the casing material of the electronic component is α, the linear expansion coefficient of the substrate material of the circuit board is β, and the outermost lead of the electronic component of the circuit board is inserted. P ′ is the distance between the center of the outermost through hole and the center of the through hole closest to the outermost through hole, and is the distance between the outermost through hole and the through hole closest to the outermost through hole. Let p be the pitch of leads arranged in the direction connecting the leads of the electronic component to be inserted,
(Α−β) (P′−p)> 0
Circuit board that meets
An electronic component with a lead is mounted, the lead of the electronic component is inserted into the through hole of the circuit board, and soldered with lead-free solder,
The distance between the center of the casing of the electronic component and the center of the outermost through hole is L, and the difference between the melting point of the lead-free solder and room temperature (25 ° C.) is ΔT.
| P′−p | ≧ | α−β | × L × ΔT
It is characterized by satisfying .

本発明により、電子部品の筐体部材料の線膨張係数をα、回路基板の基板材料の線膨張係数をβとしたとき、α>βのケースでは、スルーホールとリードとの間の電子部品筐体部中心方向と逆方向の領域でのはんだ量が少なくなることを抑制できるので、最外端スルーホールの電子部品実装時の筐体部中心方向と逆方向のスルーホール部にかかる応力を低減できる。また、α<βのケースでは、スルーホールとリードとの間の電子部品筐体部中心方向の領域でのはんだ量が少なくなることを抑制できるので、最外端スルーホールの電子部品実装時の筐体部中心方向のスルーホール部に印加される応力を低減できる。このため、スルーホールコーナ部に発生するコーナクラック及びスルーホールめっき層に発生するスルーホール剥離を防止でき、電子部品の電気的導通を維持できる。   According to the present invention, when the linear expansion coefficient of the casing material of the electronic component is α and the linear expansion coefficient of the substrate material of the circuit board is β, in the case of α> β, the electronic component between the through hole and the lead Since it is possible to suppress the amount of solder in the area opposite to the center direction of the casing, it is possible to suppress the stress applied to the through hole in the direction opposite to the center of the casing when mounting the electronic component of the outermost end through hole. Can be reduced. Also, in the case of α <β, it is possible to suppress a decrease in the amount of solder in the region in the central direction of the electronic component casing between the through hole and the lead, so when mounting the electronic component in the outermost end through hole The stress applied to the through hole portion in the central direction of the housing portion can be reduced. For this reason, it is possible to prevent corner cracks occurring in the through-hole corner portion and through-hole peeling occurring in the through-hole plating layer, and maintain electrical conduction of the electronic component.

本発明によれば、回路基板に電子部品を搭載し、はんだ付けするとき、最外端スルーホールでは最外端スルーホールの中心より電子部品の筐体部中心と逆方向の領域内に充填されるはんだ量が、最外端スルーホール以外のスルーホールの中心より電子部品の筐体部中心と逆方向の領域内に充填されるはんだ量より多くなる。これにより、はんだ付け工程時において、電子部品の筐体部と回路基板との熱膨張量の差により最外端リードが曲げられることで発生した熱応力を、最外端スルーホールに充填されたはんだで吸収することが可能になる。このため、最外端スルーホールの電子部品の筐体部中心と逆方向のコーナ部及びスルーホール内壁にかかる応力は小さくなる。これにより、最外端スルーホールのスルーホールコーナクラック及びスルーホール剥離の発生を抑制することができる。従って、本発明によれば、無鉛はんだによりはんだ付けを行っても、電子部品の電気的導通不良の発生が抑止され、接続信頼性の高いはんだ付けを行うことが可能になる。   According to the present invention, when an electronic component is mounted on a circuit board and soldered, the outermost through hole is filled in a region opposite to the center of the casing of the electronic component from the center of the outermost through hole. The amount of solder to be filled is larger than the amount of solder filled in the region opposite to the center of the casing of the electronic component from the center of the through hole other than the outermost end through hole. As a result, during the soldering process, the outermost end through-hole was filled with thermal stress generated by bending the outermost end lead due to the difference in thermal expansion between the casing of the electronic component and the circuit board. It can be absorbed by solder. For this reason, the stress applied to the corner portion and the inner wall of the through hole opposite to the center of the housing portion of the electronic component of the outermost end through hole is reduced. Thereby, generation | occurrence | production of the through-hole corner crack and through-hole peeling of an outermost end through-hole can be suppressed. Therefore, according to the present invention, even if soldering is performed using lead-free solder, the occurrence of poor electrical conduction of electronic components is suppressed, and soldering with high connection reliability can be performed.

(a)及び(b)は本発明の第1の実施形態に係る多層回路基板の夫々上面図及び断面図である。FIGS. 2A and 2B are a top view and a cross-sectional view, respectively, of the multilayer circuit board according to the first embodiment of the present invention. 本発明の第1の実施の形態の多層回路基板に電子部品を実装した状態を示す断面図である。It is sectional drawing which shows the state which mounted the electronic component in the multilayer circuit board of the 1st Embodiment of this invention. 図2の部分拡大図である。FIG. 3 is a partially enlarged view of FIG. 2. 本発明の第2の実施形態の多層回路基板を示す上面図である。It is a top view which shows the multilayer circuit board of the 2nd Embodiment of this invention. 本発明の第3の実施形態の多層回路基板を示す上面図である。It is a top view which shows the multilayer circuit board of the 3rd Embodiment of this invention. 本発明の第4実施形態の多層回路基板を示す上面図である。It is a top view which shows the multilayer circuit board of 4th Embodiment of this invention. (a)及び(b)は従来の多層回路基板の夫々上面図及び断面図である。(A) And (b) is the top view and sectional drawing of the conventional multilayer circuit board, respectively. 従来の多層回路基板に電子部品を実装した状態を示す断面図である。It is sectional drawing which shows the state which mounted the electronic component on the conventional multilayer circuit board. 従来の多層回路基板に電子部品を搭載し、はんだ付けを行う前の状態を示す断面図である。It is sectional drawing which shows the state before mounting an electronic component on the conventional multilayer circuit board, and performing soldering. (a)乃至(c)は従来例の問題点を示す断面図である。(A) thru | or (c) is sectional drawing which shows the trouble of a prior art example.

符号の説明Explanation of symbols

1 多層回路基板
2 樹脂積層板
3 内層配線
4 スルーホール
4a 中央部スルーホール
4b 最外端スルーホール
4c、4d 隣接スルーホール
5 外層配線
6 ランド
7 筐体部
8 リード
9 はんだフィレット
10 ソルダーレジスト
11 コーナクラック
12 スルーホール剥離
DESCRIPTION OF SYMBOLS 1 Multilayer circuit board 2 Resin laminated board 3 Inner layer wiring 4 Through hole 4a Center part through hole 4b Outermost end through hole 4c, 4d Adjacent through hole 5 Outer layer wiring 6 Land 7 Case part 8 Lead 9 Solder fillet 10 Solder resist 11 Corner Crack 12 Through hole peeling

次に、本発明の実施の形態について添付の図面を参照して詳細に説明する。   Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[第1の実施の形態]
図1(a)は、本発明の第1の実施の形態の回路基板を、部品搭載面側から見た上面図であり、図1(b)は、図1(a)のA−A線による断面図である。多層回路基板には、多くの表面実装型の電子部品又は挿入型の電子部品が実装されるが、図1は、一挿入型電子部品の実装位置の部分のみを示すものである。他の実施の形態を示す図も同様である。図1に示されるように、多層回路基板1は、樹脂積層板2を基板として形成されており、内部に内層配線3を有する。多層回路基板1の電子部品のリードの挿入位置にはスルーホール4(4a〜4d)が形成されており、基板表面裏面のスルーホールの周辺にはランド6が形成されている。基板表・裏面にはまた外層配線5が形成されている。
[First Embodiment]
FIG. 1A is a top view of the circuit board according to the first embodiment of the present invention as viewed from the component mounting surface side, and FIG. 1B is the AA line in FIG. It is sectional drawing by. Many surface-mounted electronic components or insertion-type electronic components are mounted on the multilayer circuit board, but FIG. 1 shows only a portion where the one-insertion-type electronic component is mounted. The same applies to drawings showing other embodiments. As shown in FIG. 1, a multilayer circuit board 1 is formed using a resin laminate 2 as a substrate, and has an inner layer wiring 3 inside. Through holes 4 (4a to 4d) are formed at the insertion positions of the electronic component leads of the multilayer circuit board 1, and lands 6 are formed around the through holes on the back surface of the substrate. Outer wiring 5 is also formed on the front and back surfaces of the substrate.

図1には、電子部品が実装された際のその筐体部の中心を通る中心線Oが鎖線にて示されている。スルーホール4の内、中心線Oに近いものが中央部スルーホール4a、最も離れて配置されたものが最外端スルーホール4b、中央部スルーホール4aに最も近い隣接するスルーホールが隣接スルーホール4c、最外端スルーホール4bに最も近い隣接するスルーホールが隣接スルーホール4dである。本実施の形態においては、多層回路基板の基材にはFR−4を用い、電子部品の筐体部の材質はポリアミドが想定されている。この場合、電子部品の筐体部材料の線膨張係数をα(ppm/℃)、多層回路基板の基板材料の線膨張係数をβ(ppm/℃)とすると、α>βとなる。本発明に従い、この場合、スルーホール間の間隔(ピッチ)は、最外端部において中央部より広くなる。即ち、最外端スルーホール4bとこれに最も近い隣接スルーホール4dとの中心間距離をP′、中央部スルーホール4aとこれに最も近い隣接スルーホール4cとの中心間距離をPとして、P′>Pとする。   In FIG. 1, a center line O passing through the center of the casing when an electronic component is mounted is indicated by a chain line. Of the through holes 4, the one near the center line O is the central through hole 4 a, the one farthest away is the outermost through hole 4 b, and the adjacent through hole closest to the central through hole 4 a is the adjacent through hole. 4c, the adjacent through hole closest to the outermost end through hole 4b is the adjacent through hole 4d. In the present embodiment, FR-4 is used as the base material of the multilayer circuit board, and the material of the casing of the electronic component is assumed to be polyamide. In this case, if the linear expansion coefficient of the casing material of the electronic component is α (ppm / ° C.) and the linear expansion coefficient of the substrate material of the multilayer circuit board is β (ppm / ° C.), then α> β. According to the present invention, in this case, the interval (pitch) between the through holes is wider at the outermost end than at the center. That is, the distance between the centers of the outermost end through hole 4b and the nearest adjacent through hole 4d is P ', and the distance between the centers of the center through hole 4a and the nearest adjacent through hole 4c is P, P '> P.

ここで、はんだが凝固する直前において最外端スルーホールの中央部より電子部品の筐体部の中心側に電子部品のリードが位置していることが望ましいことから、電子部品の筐体部中心と最外端スルーホール4bの中心との距離をL、電子部品の筐体部の線膨張係数をα(ppm/℃)、前記多層回路基板の線膨張係数β(ppm/℃)としたとき、
P′>(α−β)×L×ΔT+P (1)
とすることが望ましい。ここに、ΔTは、{はんだ付け工程時での電子部品の筐体部の最高温度(約200℃)−常温(約25℃)}である。ΔTは、(はんだ融点−常温)に置き換えてもよい。また、電子部品の筐体部材料の線膨張係数が、多層回路基板の基板材料の線膨張係数よりも小さい場合をも想定すると上式は、
|P′−P|≧|α−β|×L×ΔT (2)
となる。また、上記の式においてPの代わりに電子部品のリードのピッチを用いて最外端スルーホール4bとこれに最も近い隣接スルーホール4dとの中心間距離P′を決定し、中央部スルーホール4aとこれに最も近い隣接スルーホール4cとの中心間距離Pについては電子部品のリードピッチとしてもよい。
Here, since it is desirable that the lead of the electronic component is located closer to the center of the casing of the electronic component than the central portion of the outermost end through hole immediately before the solder solidifies, the center of the casing of the electronic component is desirable. And the center of the outermost through hole 4b is L, the linear expansion coefficient of the casing of the electronic component is α (ppm / ° C.), and the linear expansion coefficient β (ppm / ° C.) of the multilayer circuit board ,
P ′> (α−β) × L × ΔT + P (1)
Is desirable. Here, ΔT is {maximum temperature (about 200 ° C.) − Normal temperature (about 25 ° C.) of the casing of the electronic component during the soldering process}. ΔT may be replaced with (solder melting point−normal temperature). Assuming that the linear expansion coefficient of the casing material of the electronic component is smaller than the linear expansion coefficient of the substrate material of the multilayer circuit board, the above equation is
| P′−P | ≧ | α−β | × L × ΔT (2)
It becomes. Further, in the above formula, instead of P, the pitch of the lead of the electronic component is used to determine the center-to-center distance P ′ between the outermost end through hole 4b and the nearest adjacent through hole 4d, and the central through hole 4a. The distance P between the centers of the adjacent through-holes 4c closest to this may be the lead pitch of the electronic component.

このように構成された多層回路基板1に無鉛はんだによるフロー工程を実施して電子部品を実装する。フロー工程は例えば次のように行われる。
1.多層回路基板の所定の位置に電子部品を搭載、
2.多層回路基板の噴流はんだと接触する側にフラックスを塗布、
3.予備加熱、
4.溶融無鉛はんだを噴流するはんだ槽へ多層回路基板を浸漬、
5.冷却。
An electronic component is mounted on the multilayer circuit board 1 configured as described above by performing a flow process using lead-free solder. For example, the flow process is performed as follows.
1. Electronic components are mounted at predetermined positions on the multilayer circuit board.
2. Apply flux on the side of the multilayer circuit board that contacts the jet solder,
3. Preheating,
4). Immerse the multilayer circuit board in a solder bath that jets molten lead-free solder.
5. cooling.

また、フロー工程の主なプロセス条件は、部品搭載面側のランド6上にも無鉛はんだがあがり、はんだフィレットが形成できるように、例えば次のように設定される。
予備加熱温度:100℃〜120℃、
コンベア速度:0.8m/min〜1.2m/min、はんだ噴流:ダブルウェーブ、
はんだ槽温度:250℃±5℃。
Further, main process conditions of the flow process are set as follows, for example, so that lead-free solder can be raised on the component mounting surface side land 6 and a solder fillet can be formed.
Preheating temperature: 100 ° C. to 120 ° C.
Conveyor speed: 0.8 m / min to 1.2 m / min, solder jet: double wave,
Solder bath temperature: 250 ° C. ± 5 ° C.

図2は、図1に示した第1の実施の形態の多層回路基板に電子部品を実装した状態を示す断面図である。これは、基板材料としてFR−4(線膨張係数:10〜25ppm)を用いた多層回路基板に、電子部品として平面形状が長方形でポリアミド(線膨張係数:50〜85ppm)からなる筐体部7を有する8ピンのコネクタを、無鉛はんだ(Sn−3.0Ag−0.5Cu)を用いてはんだ付けした後の状態を撮影した断面写真に基づいて作成した図面である。図2に示されるように、多層回路基板1に、筐体部7とリード8とを有する電子部品が搭載され、スルーホール内及びランド6上にはんだフィレット9が形成されている。上記したように、本実施形態においては、スルーホールのうち、電子部品の最外端リードが挿入される最外端スルーホール4bと隣接スルーホール4dとの中心間距離P′が、電子部品の筐体部中心に最も近いリードが挿入される中央部スルーホール4aと隣接スルーホール4cとの中心間距離Pより大きい(すなわち、P′>P)ため、最外端スルーホール4bでは筐体部中心と逆方向の領域(図のA部)に充填される無鉛はんだ量が多くなる。その結果、はんだ付け工程時に電子部品のリードが曲げられることによって発生した応力を無鉛はんだで緩和する効果が得られる。この点について図3を参照してさらに詳しく説明する。   FIG. 2 is a cross-sectional view showing a state in which electronic components are mounted on the multilayer circuit board according to the first embodiment shown in FIG. This is because the case 7 is made of a multilayer circuit board using FR-4 (linear expansion coefficient: 10 to 25 ppm) as a substrate material, and a rectangular planar shape as an electronic component and made of polyamide (linear expansion coefficient: 50 to 85 ppm). It is drawing which created based on the cross-sectional photograph which image | photographed the state after soldering the 8-pin connector which has NO using lead-free solder (Sn-3.0Ag-0.5Cu). As shown in FIG. 2, an electronic component having a casing portion 7 and leads 8 is mounted on the multilayer circuit board 1, and solder fillets 9 are formed in the through holes and on the lands 6. As described above, in the present embodiment, among the through holes, the center-to-center distance P ′ between the outermost end through hole 4b into which the outermost end lead of the electronic component is inserted and the adjacent through hole 4d is determined by the electronic component. Since the distance P between the center through hole 4a into which the lead closest to the center of the casing is inserted and the adjacent through hole 4c is larger than the center distance P (that is, P '> P), the outermost end through hole 4b The amount of lead-free solder filled in the region opposite to the center (A portion in the figure) increases. As a result, an effect of relaxing the stress generated by bending the lead of the electronic component during the soldering process with lead-free solder can be obtained. This point will be described in more detail with reference to FIG.

図3は、図2の左端の最外端スルーホール4bの部分を拡大して示す断面図である。最外端スルーホール4bの中心位置が上記式(1)を満たすようになされているため、多層回路基板がはんだ槽に投入され、はんだが凝固する直前には、電子部品のリード8は最外端スルーホール4bの中心より右側、すなわち電子部品の筐体部中心寄りに位置している。その状態でまずはんだが凝固し始め、次いで多層回路基板と筐体部7とが収縮する。ここで多層回路基板の基板材料の線熱膨張係数βが筐体部7の線熱膨張係数αより小さい(α>β)ため、リードの上部は電子部品の中央部寄りに引っ張られる。そのため、リード8はその上部が左側に傾いて固定される。これにより、最外端スルーホール4bの筐体部7中心から離れる側の内壁とコーナ部は応力を受けることになるが、最外端スルーホール4bでは筐体部中心と逆方向の部分(図中A部にて示す)に充填される無鉛はんだ量が多くなっていることにより、最外端スルーホール4bの受けるこれらの応力は緩和される。その結果、図10(b)、(c)に示されるコーナクラック及びスルーホール剥離が発生することが抑制され、高い電気的導通信頼性を確保することが可能になる。   FIG. 3 is an enlarged cross-sectional view of the leftmost outermost through hole 4b in FIG. Since the center position of the outermost end through-hole 4b satisfies the above formula (1), the lead 8 of the electronic component is placed at the outermost position immediately before the multilayer circuit board is put into the solder bath and the solder is solidified. It is located on the right side from the center of the end through-hole 4b, that is, closer to the center of the casing of the electronic component. In this state, the solder starts to solidify first, and then the multilayer circuit board and the casing portion 7 contract. Here, since the linear thermal expansion coefficient β of the substrate material of the multilayer circuit board is smaller than the linear thermal expansion coefficient α of the casing portion 7 (α> β), the upper portion of the lead is pulled closer to the center portion of the electronic component. Therefore, the lead 8 is fixed with its upper portion inclined to the left side. As a result, the inner wall and the corner portion of the outermost end through hole 4b on the side away from the center of the casing portion 7 are subjected to stress, but the outermost end through hole 4b has a portion in the direction opposite to the center of the casing portion (see FIG. By increasing the amount of lead-free solder filled in the middle A portion), these stresses received by the outermost end through-hole 4b are alleviated. As a result, the occurrence of corner cracks and through-hole separation shown in FIGS. 10B and 10C is suppressed, and high electrical conduction reliability can be ensured.

また、電子部品の筐体部材料の線膨張係数をα(ppm/℃)、多層回路基板の基板材料の線膨張係数をβ(ppm/℃)としたとき、α<βのケースでは、電子部品の最外端リードが挿入される最外端スルーホール4bと隣接スルーホール4dとの中心間距離P′が、電子部品の筐体部中心に最も近いリードが挿入される中央部スルーホール4aと隣接スルーホール4cとの中心間距離Pより小さい(即ち、P′<P)ため、多層回路基板がはんだ槽に投入され、はんだが凝固する直前には、電子部品のリード8は最外端スルーホール4bの中心より電子部品筐体部の中心方向と逆方向寄りに位置している。その状態で、先ず、はんだが凝固し始め、次いで、多層回路基板と筐体部7とが収縮する。ここで、多層回路基板の基板材料の線膨張係数βが筐体部7の線膨張係数αより大きい(α<β)ため、リードの上部は電子部品の中央部と逆方向寄りに引っ張られる。このため、リード8はその上部が左側に傾いて固定される。これにより、最外端スルーホール4bの筐体部7中心方向の内壁とコーナ部は応力を受けることになるが、最外端スルーホール4bでは筐体部中心方向の部分に充填される無鉛はんだ量が多くなっていることにより、最外端スルーホール4bの受けるこれらの応力は緩和される。その結果、図10(b)、(c)に示されるコーナクラック及びスルーホール剥離が発生することが抑制され、高い電気的導通信頼性を確保することが可能になる。   In addition, when the linear expansion coefficient of the casing material of the electronic component is α (ppm / ° C.) and the linear expansion coefficient of the substrate material of the multilayer circuit board is β (ppm / ° C.), The central through hole 4a into which the lead P between the outermost end through hole 4b into which the outermost end lead of the component is inserted and the adjacent through hole 4d is closest to the center of the casing of the electronic component is inserted. Is smaller than the center-to-center distance P between the through hole 4c and the adjacent through hole 4c (that is, P '<P). It is located closer to the direction opposite to the center direction of the electronic component casing than the center of the through hole 4b. In this state, first, the solder starts to solidify, and then the multilayer circuit board and the housing part 7 contract. Here, since the linear expansion coefficient β of the substrate material of the multilayer circuit board is larger than the linear expansion coefficient α of the casing portion 7 (α <β), the upper portion of the lead is pulled toward the opposite direction to the central portion of the electronic component. For this reason, the lead 8 is fixed with its upper portion inclined to the left side. As a result, the inner wall and the corner of the outermost end through-hole 4b in the central direction of the casing 7 are subjected to stress, but the lead-free solder filled in the central portion of the casing at the outermost end through-hole 4b By increasing the amount, these stresses received by the outermost end through hole 4b are alleviated. As a result, the occurrence of corner cracks and through-hole separation shown in FIGS. 10B and 10C is suppressed, and high electrical conduction reliability can be ensured.

α>βのときには、P′>Pであるため、つまり、(α−β)>0、(P′−P)>0なので、(α−β)(P′−P)>0となる。また、α<βのときには、P′<Pであるため、つまり、(α−β)<0、(P′−P)<0なので、(α−β)(P′−P)>0となる。以上より、(α−β)(P′−P)>0を満たすことで、図10(b)、(c)に示されるコーナクラック及びスルーホール剥離が発生することが抑制され、高い電気的導通信頼性を確保することが可能となる。   When α> β, since P ′> P, that is, (α−β)> 0 and (P′-P)> 0, (α−β) (P′−P)> 0. Further, when α <β, P ′ <P, that is, (α−β) <0 and (P′−P) <0, so that (α−β) (P′−P)> 0 Become. As described above, by satisfying (α−β) (P′−P)> 0, the occurrence of corner cracks and through-hole separation shown in FIGS. It is possible to ensure conduction reliability.

[第2の実施の形態]
図4は、本発明の第2の実施の形態の回路基板を、部品搭載面側から見た部分上面図である。図4において、図1に示した第1の実施の形態の部分と同様の部分には同一の参照符号を付し重複する説明は省略する。本実施形態の多層回路基板が、図1に示した第1の実施形態のものと相違する点は、第1の実施形態ではスルーホール4の平面形状が円形であったが、本実施形態においては、実装される電子部品の筐体部の長手方向に長い長方形となっている点である。本実施形態においては、最外端スルーホール4bと隣接スルーホール4dとの中心間距離P′が、電子部品の筐体部中心に最も近いリードが挿入される中央部スルーホール4aと隣接スルーホール4cとの中心間距離Pより大きくなされていることに加え、スルーホールの平面形状が筐体部の長手方向に長い長方形になされたことにより、第1の実施形態の場合よりも更に高い応力緩和効果を得ることができる。
[Second Embodiment]
FIG. 4 is a partial top view of the circuit board according to the second embodiment of the present invention as viewed from the component mounting surface side. 4, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. The multi-layer circuit board of the present embodiment differs from that of the first embodiment shown in FIG. 1 in that the planar shape of the through hole 4 is circular in the first embodiment. Is a long rectangle in the longitudinal direction of the casing of the electronic component to be mounted. In the present embodiment, the center through-hole 4a and the adjacent through-hole into which the lead P closest to the center of the housing part of the electronic component is inserted with the center distance P 'between the outermost end through-hole 4b and the adjacent through-hole 4d. In addition to being larger than the center-to-center distance P with respect to 4c, the planar shape of the through-hole is a rectangle that is long in the longitudinal direction of the housing portion, so that the stress relaxation is higher than in the case of the first embodiment. An effect can be obtained.

第2の実施形態に変更を加え、スルーホールの平面形状を、筐体部の長手方向に長い楕円形、ひょうたん型、又は円を二つ割りにしてその間に長方形を挿入した形状等としてもよい。更には、正方形及び正六角形等の形状としてもよい。   By changing the second embodiment, the planar shape of the through hole may be an ellipse that is long in the longitudinal direction of the casing, a gourd shape, or a shape in which a circle is divided into two and a rectangle is inserted therebetween. Furthermore, it is good also as shapes, such as a square and a regular hexagon.

[第3の実施の形態]
図5は、本発明の第3の実施形態の回路基板を、部品搭載面側から見た部分上面図である。図5において、図1に示した第1の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態の多層回路基板の図1に示される第1の実施の形態のものと相違する点は、第1の実施の形態では、最外端スルーホール4bと隣接スルーホール4dとの中心間距離P′のみが他のスルーホール中心間距離より長くなされていたが、本実施の形態においては、電子部品実装時の筐体部中心から離れるに連れて徐々にスルーホール間距離が大きくなされる。即ち、図5に示されるように、筐体部中心に最も近いスルーホール間の距離をP1、筐体部中心から2番目、3番目のスルーホール間距離をP2として、
P1<P<P2<P′
になされている。
[Third Embodiment]
FIG. 5 is a partial top view of the circuit board according to the third embodiment of the present invention as viewed from the component mounting surface side. In FIG. 5, the same reference numerals are given to the same parts as those of the first embodiment shown in FIG. The difference between the multilayer circuit board of the present embodiment and that of the first embodiment shown in FIG. 1 is that the center of the outermost through hole 4b and the adjacent through hole 4d is different in the first embodiment. Although only the distance P ′ is longer than the distance between the other through-hole centers, in this embodiment, the distance between the through-holes is gradually increased as the distance from the center of the housing portion when mounting the electronic component is increased. The That is, as shown in FIG. 5, the distance between through holes closest to the center of the casing is P1, the distance between the second and third through holes from the center of the casing is P2,
P1 <P <P2 <P '
Has been made.

[第4の実施の形態]
図6は、本発明の第4の実施形態の回路基板を、部品搭載面側から見た部分上面図である。図4において、図1に示した第1の実施の形態の部分と同等の部分には同一の参照符号を付し重複する説明は省略する。本実施の形態の多層回路基板の図1に示される第1の実施の形態のものと相違する点は、第1の実施の形態では、搭載される電子部品がその筐体部の平面形状が長方形でそのリードがライン状に配列されていたのに対し、本実施の形態の回路基板に搭載される電子部品では、リードが筐体部中心から放射状に配列されている点である。
[Fourth Embodiment]
FIG. 6 is a partial top view of the circuit board according to the fourth embodiment of the present invention as viewed from the component mounting surface side. 4, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted. The difference between the multilayer circuit board of the present embodiment and that of the first embodiment shown in FIG. 1 is that in the first embodiment, the electronic component to be mounted has a planar shape of its casing. In contrast to the rectangular leads arranged in a line, in the electronic component mounted on the circuit board according to the present embodiment, the leads are arranged radially from the center of the casing.

本実施の形態においても、最外端スルーホール4bと、電子部品の筐体部中心と電子部品の最外端リードを結ぶ放射線上で最外端スルーホール4bと最も近い隣接スルーホール4dとの中心間距離P′が、中央部スルーホール4aと、電子部品の筐体部中心と電子部品の最外端リードを結ぶ放射線上で中央部スルーホールと最も近い隣接スルーホール4cとの中心間距離Pより大きいことにより、第1の実施形態の場合と同様の効果を得ることができる。なお、本実施形態と第2実施形態及び第3の実施形態と組み合わせることもできる。   Also in the present embodiment, the outermost end through-hole 4b and the adjacent through-hole 4d closest to the outermost end through-hole 4b on the radiation connecting the center of the casing of the electronic component and the outermost end lead of the electronic component. The center-to-center distance P ′ is the center-to-center distance between the central through hole 4a and the adjacent through hole 4c closest to the central through hole on the radiation connecting the center of the housing of the electronic component and the outermost lead of the electronic component. By being larger than P, the same effect as in the first embodiment can be obtained. It should be noted that this embodiment can be combined with the second embodiment and the third embodiment.

本発明によれば、無鉛はんだによるはんだ付けにおいて、電子部品の電気的導通不良の発生が抑制されるので、接続信頼性が高い回路基板を得ることができる。   According to the present invention, since the occurrence of poor electrical continuity of electronic components is suppressed in soldering with lead-free solder, a circuit board with high connection reliability can be obtained.

Claims (8)

リード付きの電子部品のリードが挿入されはんだ付けされるスルーホールと、
基板表裏面の前記スルーホールの周囲に前記スルーホールを介して電気的に接続されたランドと
を有し、
前記電子部品の筐体部材料の線膨張係数をα、前記回路基板の基板材料の線膨張係数をβとし、前記回路基板の前記電子部品の最外端リードが挿入される最外端スルーホールの中心と該最外端スルーホールに最も近いスルーホールの中心との距離をP′、前記電子部品の中心に最も近いリードが挿入される中央部スルーホールの中心と該中央部スルーホール最も近いスルーホールの中心との距離をPとして、
(α−β)(P′−P)>0
を満たす回路基板に、
リード付きの電子部品が搭載され、前記電子部品のリードが前記回路基板のスルーホールに挿入され、無鉛はんだによりはんだ付けされ、
前記電子部品の筐体部中心と前記最外端スルーホールの中心との距離をL、前記無鉛はんだの融点と常温(25℃)との差をΔTとして、
|P′−P|≧|α−β|×L×ΔT
を満たすことを特徴とする電子機器
Through-holes into which leads of electronic components with leads are inserted and soldered,
And a land electrically connected through the through hole around the through hole on the front and back surfaces of the substrate,
The linear expansion coefficient of the casing material of the electronic component is α, the linear expansion coefficient of the substrate material of the circuit board is β, and the outermost end through-hole into which the outermost lead of the electronic component of the circuit board is inserted P ′ is the distance between the center of the through hole and the center of the through hole closest to the outermost end through hole, and the center of the central through hole into which the lead closest to the center of the electronic component is inserted is closest to the central through hole Let P be the distance from the center of the through hole.
(Α−β) (P′−P)> 0
To be times circuit board meet,
An electronic component with a lead is mounted, the lead of the electronic component is inserted into the through hole of the circuit board, and soldered with lead-free solder,
The distance between the center of the casing of the electronic component and the center of the outermost through hole is L, and the difference between the melting point of the lead-free solder and room temperature (25 ° C.) is ΔT.
| P′−P | ≧ | α−β | × L × ΔT
An electronic device characterized by satisfying
等間隔で配列されたリードを有するリード付きの電子部品の前記リードが挿入されはんだ付けされるスルーホールと、
基板表裏面の前記スルーホールの周囲に前記スルーホールを介して電気的に接続されたランドと、
を有し、
前記電子部品の筐体部材料の線膨張係数をα、前記回路基板の基板材料の線膨張係数をβとし、前記回路基板の前記電子部品の最外端リードが挿入される最外端スルーホールの中心と前記最外端スルーホールに最も近いスルーホールの中心との距離をP′、前記最外端スルーホールと前記最外端スルーホールに最も近いスルーホールとに挿入される前記電子部品のリードを結ぶ方向に配列されたリードのピッチをpとして、
(α−β)(P′−p)>0
を満たす回路基板に、
リード付きの電子部品が搭載され、前記電子部品のリードが前記回路基板のスルーホールに挿入され、無鉛はんだによりはんだ付けされ、
前記電子部品の筐体部中心と前記最外端スルーホールの中心との距離をL、前記無鉛はんだの融点と常温(25℃)との差をΔTとして、
|P′−p|≧|α−β|×L×ΔT
を満たすことを特徴とする電子機器
A through-hole into which the lead of the electronic component with lead having leads arranged at equal intervals is inserted and soldered;
Lands electrically connected through the through holes around the through holes on the front and back surfaces of the substrate;
Have
The linear expansion coefficient of the casing material of the electronic component is α, the linear expansion coefficient of the substrate material of the circuit board is β, and the outermost end through-hole into which the outermost lead of the electronic component of the circuit board is inserted The distance between the center of the through hole and the center of the through hole closest to the outermost end through hole is P ′, and the distance between the outermost end through hole and the through hole closest to the outermost end through hole Let p be the pitch of the leads arranged in the direction connecting the leads,
(Α−β) (P′−p)> 0
To be times circuit board meet,
An electronic component with a lead is mounted, the lead of the electronic component is inserted into the through hole of the circuit board, and soldered with lead-free solder,
The distance between the center of the casing of the electronic component and the center of the outermost through hole is L, and the difference between the melting point of the lead-free solder and room temperature (25 ° C.) is ΔT.
| P′−p | ≧ | α−β | × L × ΔT
An electronic device characterized by satisfying
互いに隣接するスルーホールの中心間の距離は、前記電子部品の中心に最も近いリードが挿入される中央部スルーホールから前記電子部品の最外端リードが挿入される最外端スルーホールに向かって徐々に変化することを特徴とする請求項1又は2に記載の電子機器The distance between the centers of the through holes adjacent to each other is from the central through hole into which the lead closest to the center of the electronic component is inserted toward the outermost end through hole into which the outermost lead of the electronic component is inserted. The electronic apparatus according to claim 1, wherein the electronic apparatus changes gradually. 前記電子部品のリードは、ライン状又は前記電子部品が実装された際の前記電子部品の筐体部中心より放射線状に配列されていることを特徴とする請求項1乃至3のいずれか1項に記載の電子機器The lead of the electronic component is arranged in a line shape or a radial pattern from the center of the casing of the electronic component when the electronic component is mounted. The electronic device as described in. 前記スルーホールの平面形状は、円形、楕円形、正方形、長方形、又は、二つの半円の間に長方形を挟んだ形状であることを特徴とする請求項1乃至4のいずれか1項に記載の電子機器5. The planar shape of the through hole is a circle, an ellipse, a square, a rectangle, or a shape in which a rectangle is sandwiched between two semicircles. 6. Electronic equipment . 前記回路基板は、プリプレグと、銅を張り付けた積層板とを、夫々少なくとも1枚以上使用した複数層の構成を有することを特徴とする請求項1乃至5のいずれか1項に記載の電子機器6. The electronic device according to claim 1, wherein the circuit board has a multi-layer configuration using at least one prepreg and a laminated board on which copper is pasted. 6. . 前記回路基板の前記最外端のスルーホールの内壁と、このスルーホールに挿入された前記電子部品のリードとの間の前記リードの外面の全周に、無鉛はんだが存在していることを特徴とする請求項1乃至6のいずれか1項に記載の電子機器。Lead-free solder exists on the entire outer surface of the lead between the inner wall of the outermost through hole of the circuit board and the lead of the electronic component inserted into the through hole. The electronic device according to any one of claims 1 to 6 . 前記電子部品の中心部のスルーホールよりも、外側のスルーホールの方が、前記スルーホール内のはんだ量が多く、前記スルーホール内に挿入されたリードの周囲の全周にはんだが存在していることを特徴とする請求項1乃至7のいずれか1項に記載の電子機器。The outer through-hole has a larger amount of solder in the through-hole than the through-hole in the center of the electronic component, and solder exists around the entire periphery of the lead inserted into the through-hole. The electronic device according to claim 1 , wherein the electronic device is an electronic device.
JP2006513612A 2004-05-17 2005-05-17 Electronics Expired - Fee Related JP4735538B2 (en)

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JP4105148B2 (en) * 2004-12-10 2008-06-25 株式会社ケーヒン Printed board
CN111354683A (en) * 2018-12-21 2020-06-30 深南电路股份有限公司 Chip substrate and manufacturing method thereof, packaged chip and packaging method thereof

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JPS6465173A (en) * 1987-09-04 1989-03-10 Nippon Paint Co Ltd Preparation of aqueous dispersion of fine cationic gel particle
JPH08125323A (en) * 1994-10-27 1996-05-17 Matsushita Electric Works Ltd Hybrid integrated circuit board module
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JP2001156420A (en) * 1999-11-30 2001-06-08 Optrex Corp Printed-circuit board
JP2002252452A (en) * 2000-12-19 2002-09-06 Nec Corp Circuit board and electronic apparatus using it

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