JP4701487B2 - Method for manufacturing substrate for electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a substrate for an electro-optical device comprising a light-shielding layer having a predetermined pattern, an insulator layer, and a transistor element on the surface of the light-transmitting substrate, and the substrate for an electro-optical device manufactured by the manufacturing method. The present invention relates to an electro-optical device and an electronic apparatus including the electro-optical device substrate.
[0002]
[Prior art]
The SOI technology, in which a single crystal silicon thin film is formed on an insulating substrate and a semiconductor device is formed on the single crystal silicon thin film, has advantages such as higher element speed, lower power consumption, and higher integration. It is suitably used for an electro-optical device such as a device.
[0003]
When the SOI technology is applied to the electro-optical device as described above, a single crystal silicon substrate is bonded to a light transmissive substrate, a thin single crystal silicon layer is formed by polishing or the like, and the single crystal silicon layer is used for driving a liquid crystal, for example. Transistor elements such as MOSFETs are formed.
[0004]
By the way, in a projection display device such as a projector using a liquid crystal device, light is usually incident from one light-transmitting substrate side (the surface of the liquid crystal device) constituting the liquid crystal device. In general, a light shielding layer is provided on the light incident side of the transistor element in order to prevent light leakage current from entering the channel region of the transistor element formed on the surface of the substrate.
[0005]
However, even if a light-shielding layer is provided on the light incident side of the transistor element, if the substrate on which the transistor element is formed has light transmittance, the light incident on the liquid crystal device is incident on the substrate on which the transistor element is formed. The light may be reflected at the interface on the back surface and enter the channel portion of the transistor element as return light. This return light is a small percentage of the amount of light incident from the surface of the liquid crystal device, but in a device using a very powerful light source such as a projector, a light leakage current can be sufficiently generated. That is, the return light from the back surface of the substrate on which the transistor element is formed affects the switching characteristics of the element and degrades the device characteristics. Here, the surface on which the single crystal silicon layer is formed is the front surface of the substrate, and the opposite side is the back surface.
[0006]
Japanese Patent Application Laid-Open No. 10-293320 proposes a technique for forming a light-shielding layer corresponding to each transistor element on the surface of the substrate on which the transistor element is formed, and has a predetermined pattern on the substrate surface as described above. A method has been proposed in which a light-shielding layer is formed, an insulator layer is formed thereon, the surface of the insulator layer is flattened by polishing, and a single crystal silicon substrate is bonded onto the surface.
[0007]
[Problems to be solved by the invention]
However, in a general electro-optical device, transistor elements are formed on a substrate surface such that transistor elements are formed only in a display region (pixel portion) and transistor elements are not formed in a non-display region. Region) and regions that are not dense (regions that are not formed). Therefore, the light shielding layer provided corresponding to each transistor element is also distributed at the same density, and as a result, irregularities are formed on the surface of the insulator layer formed thereon, and the irregularities are also distributed. Even if the surface of the insulating layer is polished, the degree of polishing varies on the surface of the substrate. Even if the entire surface of the substrate is polished, the insulating layer becomes thicker at the portions where the convex portions are densely packed. There is a risk that the insulating layer becomes thin in the portion where the portion is not dense (the portion where the concave portion is dense), and the flatness of the surface of the insulating layer after polishing is low.
[0008]
For example, as illustrated in FIG. 15A, when a region 1010 where the light shielding layer 1003 is dense and a region 1020 where the light shielding layer 1003 is not dense exist on the surface of the substrate 1001, the light shielding layer 1003 is formed on the substrate 1001. On the surface of the insulating layer 1004, more concave portions are formed in the non-dense region 1020 than in the region 1010 where the light-shielding layer 1003 is dense. Note that in the region 1010 where the light-shielding layers 1003 are densely formed, fine unevenness is formed on the surface of the insulator layer 1004 in accordance with the pattern of the light-shielding layer 1003, but is omitted from the drawing for simplification. .
[0009]
As described above, when the surface of the insulator layer 1004 having uneven distribution is polished, the area of the convex portion in the surface of the insulator layer 1004 where the area of the convex portion is smaller (the region 1020 where the light-shielding layer 1003 is not dense) is larger. It is polished faster than a region having a large amount of light (region 1010 where the light shielding layer 1003 is densely packed). As a result, as shown in FIG. 15B, the insulator layer 1004 in the region 1020 where the light shielding layer 1003 is not densely polished is excessively polished, and the region 1010 where the light shielding layer 1003 is densely concentrated on the surface of the insulator layer 1004. A step is generated between the region 1020 and the non-performed region 1020, and the flatness of the surface of the insulator layer 1004 is low.
[0010]
As described above, when the flatness of the surface of the insulator layer is lowered, the following problems occur. First, voids are generated at the interface between the insulator layer and the single crystal silicon layer, and the characteristics of the transistor element formed in the region where the voids are present may be deteriorated. Secondly, the bonding strength between the insulator layer and the single crystal silicon layer is weakened, which may cause defects such as film peeling in the transistor element formation process after the formation of the single crystal silicon layer, thereby reducing the product yield. There is.
[0011]
Even if the surface of the insulator layer can be flattened, there is no method for detecting the end point of polishing, that is, the moment when the insulator layer is flattened, and the polishing process is controlled only by the polishing time. . However, since the polishing rate changes depending on the lot of polishing liquid used, the polishing machine, and the like, the time until the insulator layer is flattened changes depending on the polishing conditions at that time. Therefore, the surface of the insulator layer may not be flattened even after polishing for a certain time.
[0012]
Therefore, the present invention has been made to solve the above problems, and can planarize the surface of a light-transmitting substrate on which a single crystal silicon layer is bonded and a light shielding layer and an insulator layer are formed. And an electro-optical device substrate manufacturing method and an electro-optical device substrate capable of easily detecting an end point of polishing when polishing the insulator layer, and an electro-optical device including the electro-optical device substrate, and An object of the present invention is to provide an electronic apparatus including the electro-optical device.
[0013]
[Means for Solving the Problems]
  The present inventionThe method for manufacturing a substrate for an electro-optical device is a light-transmitting substrate.aboveA step of forming a light shielding layer and the light shielding layer;Is patterned at least in the transistor element formation regionAnd patterned light shielding layerA first portion having a protrusion due to the thickness of the patterned light shielding layer;Forming an insulator layer;Polishing the surface of the first insulator layer until the surface of the patterned light-shielding layer is exposed, and polishing the surface of the first insulator layer and the surface of the light-shielding layer where the surface is exposed. A step of forming a second insulator layer; and a surface of the second insulator layer.A step of bonding a single crystal silicon layer; and a step of forming a transistor element from the single crystal silicon layer.
  In the polishing step, the patterned light shielding layer has a polishing stop function.
[0014]
As described above, the inventor forms an insulator layer on the light-transmitting substrate on which the light-shielding layer is formed, and polishes the surface of the light-transmitting substrate on which the insulator layer is formed until the light-shielding layer surface is exposed. As a result, the surface of the light-transmitting substrate to which the single crystal silicon layer is bonded can be planarized, and the light shielding layer can have a polishing stop function by utilizing the different materials of the light shielding layer and the insulator layer. It was found that the end point of polishing can be easily detected.
[0015]
For example, when a CMP (Chemical Mechanical Polishing) method is used, a light-shielding layer made of metal or the like does not cause a chemical reaction with the polishing liquid, so that the light-transmitting substrate is polished immediately after the surface of the light-shielding layer is exposed. The frictional force between the pad and the light transmissive substrate is reduced. Further, the vibration of the substrate holder that holds the light transmissive substrate also changes. Therefore, the end point of polishing can be easily detected by detecting the frictional force between the polishing pad and the light transmissive substrate or the vibration of the substrate holder.
[0016]
In the present specification, “the light shielding layer has a polishing stop function” specifically means, as described above, “detecting the end point of polishing by detecting the moment when the surface of the light shielding layer is exposed”. It means that.
[0017]
In addition, since an oxide film is formed in advance on the surface of the single crystal silicon substrate used for bonding, the single crystal silicon substrate is directly bonded onto the surface of the light shielding layer made of metal or the like. Even if the transistor element is formed after the thin film is formed into a single crystal silicon layer, contamination from the light shielding layer to the transistor element is prevented.
[0018]
However, even when an oxide film is formed on the surface of the single crystal silicon substrate, if there is a risk of contamination from the light shielding layer to the transistor element, such as when the surface oxide film is very thin, the single crystal silicon substrate is attached. Before the alignment, it is desirable to form an insulator layer on the surface of the light shielding layer.
[0019]
According to the reference invention of this caseThe method for manufacturing a substrate for an electro-optical device includes a step of forming a light shielding layer on one surface of a light transmissive substrate, and patterning the light shielding layer to form at least one surface of the light transmissive substrate. A step of forming a light shielding layer corresponding to each transistor element, a step of forming a first insulator layer on the surface of the light-transmitting substrate on which the patterned light shielding layer is formed, A step of polishing the surface of the light-transmitting substrate on which the insulator layer is formed until the surface of the light-shielding layer is exposed, and a step of forming a second insulator layer on the surface of the light-transmitting substrate whose surface is polished And a step of bonding a single crystal silicon layer to the surface of the light transmissive substrate on which the second insulator layer is formed, and a step of forming a transistor element from the single crystal silicon layer. To do.
[0020]
In this way, the first insulator layer is formed on the light transmissive substrate on which the light shielding layer is formed, and the surface of the light transmissive substrate on which the first insulator layer is formed is polished until the surface of the light shielding layer is exposed. Then, after the surfaces of the light shielding layer and the first insulator layer are flattened, and then the second insulator layer is formed thereon, the second insulator layer has a flattened surface. Therefore, the surface of the light-transmitting substrate on which the single crystal silicon layer is bonded can be planarized. Furthermore, in this case, since the second insulator layer is formed between the light shielding layer and the transistor element, contamination from the light shielding layer to the transistor element can be completely prevented.
[0021]
  As explained above,The present inventionAccording to the method for manufacturing a substrate for an electro-optical device, since the surface of the light-transmitting substrate on which the single crystal silicon layer is bonded can be planarized, the light-transmitting substrate on which the light-shielding layer and the insulator layer are formed; It is possible to prevent the deterioration of the characteristics of the transistor element without generating a void at the boundary surface where the single crystal silicon layer is bonded. In addition, since the bonding strength between the light-transmitting substrate on which the light shielding layer and the insulator layer are formed and the single crystal silicon layer can be secured, it is possible to prevent defects such as film peeling in the process of forming the transistor element. , Can improve the product yield.
[0022]
The present inventionAccording to the method for manufacturing a substrate for an electro-optical device, a light-shielding layer having a predetermined pattern and a region where the light-shielding layer is not formed are formed on one surface of the light-transmitting substrate and have the same thickness as the light-shielding layer And an insulating layer having a planarized surface and a transistor element formed above the light-shielding layer, and the semiconductor layer constituting the transistor element is formed from a single crystal silicon layer. There can be provided a substrate for an electro-optical device.
[0023]
  Also,According to the reference invention of this caseAccording to the method for manufacturing the substrate for an electro-optical device, a second insulator layer is further provided on the surfaces of the light shielding layer and the insulator layer, and the transistor element is provided on the surface of the second insulator layer. The substrate for an electro-optical device can be provided.
[0024]
  Also,According to the reference invention of this caseAn electro-optical device substrate and another light-transmitting substrate disposed so as to face the surface on which the transistor element of the electro-optical device substrate is formed, and between the two light-transmitting substrates. An electro-optical device including the sandwiched electro-optical material layer can be provided.
[0025]
According to the reference invention of this caseElectro-optical device substrate and electro-optical device substrateAccording to the reference invention of this caseThe electro-optical device has a light-transmitting substrate in which a light-transmitting substrate on which a light-shielding layer and an insulating layer are formed and a single crystal silicon layer bonded to each other have no voids and a light-shielding layer and an insulating layer are formed. The single crystal silicon layer has a high bonding strength, and does not cause variations or defects in the characteristics of the transistor element, so that it has excellent performance.
[0026]
  Also,According to the reference invention of this caseBy providing the electro-optical device, it is possible to provide an electronic device with excellent performance.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments according to the present invention will be described in detail. In this embodiment, an active matrix type liquid crystal device using a TFT (transistor element) as a switching element will be described as an example of an electro-optical device. In the present embodiment, the step of forming the first interlayer insulating film on the surface of the light-transmitting substrate on which the first light shielding film (light shielding layer) is formed, and the structure of the first interlayer insulating film to be formed are particularly characteristic. It is a typical one.
[0028]
(Structure of electro-optical device)
First, the structure of an electro-optical device according to an embodiment of the present invention will be described by taking up a liquid crystal device. The electro-optical device (liquid crystal device) of the present embodiment includes a TFT array substrate (electro-optical device substrate) manufactured by the method of manufacturing the electro-optical device substrate of the present embodiment.
[0029]
FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms a pixel portion (display region) of a liquid crystal device. FIG. 2 is an enlarged plan view showing a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed. FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2. In FIG. 1 to FIG. 3, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawings.
[0030]
In FIG. 1, a plurality of pixels formed in a matrix that forms a pixel portion of a liquid crystal device includes a plurality of pixel electrodes 9 a formed in a matrix and a TFT (transistor element) 30 for controlling the pixel electrodes 9 a. Thus, the data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data line 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. . Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured.
[0031]
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode described later formed on a counter substrate described later.
[0032]
The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. In the normally white mode, incident light cannot pass through the liquid crystal part according to the applied voltage. In the normally black mode, incident light passes through the liquid crystal part according to the applied voltage. Light that has a contrast corresponding to the image signal is emitted from the liquid crystal device as a whole.
[0033]
Here, in order to prevent a display defect such as a decrease in contrast ratio and flicker called flicker due to a leak of the held image signal, the liquid crystal capacitance formed between the pixel electrode 9a and the counter electrode is connected in parallel. A storage capacity 70 is added. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the voltage is applied to the data line. Thereby, the holding characteristics are further improved, and a liquid crystal device with a high contrast ratio can be realized. In the present embodiment, in particular, in order to form such a storage capacitor 70, a capacitor line 3b having a low resistance using the same layer as the scanning line or a conductive light-shielding film is provided as will be described later.
[0034]
Next, referring to FIG. 2, the planar structure in the transistor element formation region (pixel portion) of the TFT array substrate will be described in detail. As shown in FIG. 2, in the transistor element formation region (pixel portion) on the TFT array substrate of the liquid crystal device, the outline is indicated by a plurality of transparent pixel electrodes 9a (dotted line portions 9a ′) in a matrix. ), And a data line 6a, a scanning line 3a, and a capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to a source region to be described later in the semiconductor layer 1a of the single crystal silicon layer through the contact hole 5, and the pixel electrode 9a is connected to the source layer in the semiconductor layer 1a through the contact hole 8. It is electrically connected to a drain region described later. Further, the scanning line 3a is arranged so as to face the channel region (the hatched region in the upper right in the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode.
[0035]
The capacitance line 3b is formed from a main line portion (that is, a first region formed along the scanning line 3a in a plan view) extending substantially linearly along the scanning line 3a and a portion intersecting the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) that protrudes forward (upward in the drawing) along the data line 6 a.
[0036]
A plurality of first light-shielding films (light-shielding layers) 11a are provided in the region indicated by the diagonal lines rising to the right in the drawing. More specifically, the first light-shielding film 11a is provided at a position where the TFT including the channel region of the semiconductor layer 1a is covered in the pixel portion as viewed from the substrate body side described later of the TFT array substrate. A main line portion that extends in a straight line along the scanning line 3a facing the main line portion of the line 3b, and protrudes from a portion intersecting the data line 6a to the adjacent step side (that is, downward in the figure) along the data line 6a. And a protruding portion. The tip of the downward projecting portion in each stage (pixel row) of the first light shielding film 11a overlaps the tip of the upward projecting portion of the capacitor line 3b in the next stage under the data line 6a. A contact hole 13 for electrically connecting the first light shielding film 11a and the capacitor line 3b to each other is provided at the overlapping portion. In other words, in the present embodiment, the first light shielding film 11a is electrically connected to the upstream or downstream capacitor line 3b through the contact hole 13.
[0037]
In this embodiment, the pixel electrode 9a, the TFT, and the first light shielding film 11a are provided only in the pixel portion (transistor element formation region).
[0038]
Next, a cross-sectional structure in the pixel portion of the liquid crystal device will be described with reference to FIG. As shown in FIG. 3, in the liquid crystal device, a liquid crystal layer 50 is sandwiched between the TFT array substrate 10 and a counter substrate 20 disposed to face the TFT array substrate 10.
[0039]
The TFT array substrate 10 is mainly composed of a substrate body 10A made of a light transmissive substrate such as quartz, a pixel electrode 9a formed on the surface of the liquid crystal layer 50, a TFT (transistor element) 30, and an alignment film 16. The counter substrate 20 is mainly composed of a substrate body 20A made of a transparent substrate such as transparent glass or quartz, a counter electrode (common electrode) 21 formed on the surface of the liquid crystal layer 50, and an alignment film 22. Has been.
[0040]
A pixel electrode 9a is provided on the surface of the substrate body 10A of the TFT array substrate 10 on the liquid crystal layer 50 side, and the alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided on the liquid crystal layer 50 side. Is provided. The pixel electrode 9a is made of a transparent conductive thin film such as ITO (indium tin oxide), and the alignment film 16 is made of an organic thin film such as polyimide.
[0041]
On the surface of the substrate body 10A on the liquid crystal layer 50 side, as shown in FIG. 3, pixel switching TFTs 30 that perform switching control of the pixel electrodes 9a are provided at positions adjacent to the pixel electrodes 9a.
[0042]
On the other hand, a counter electrode (common electrode) 21 is provided over the entire surface of the substrate body 20A of the counter substrate 20 on the liquid crystal layer 50 side, and a predetermined rubbing process or the like is provided on the liquid crystal layer 50 side. An alignment film 22 having been subjected to the alignment process is provided. The counter electrode 21 is made of a transparent conductive thin film such as ITO, and the alignment film 22 is made of an organic thin film such as polyimide.
[0043]
Further, on the surface of the substrate body 20A on the liquid crystal layer 50 side, as shown in FIG. 3, a second light shielding film 23 is provided in a region other than the opening region of each pixel portion. By providing the second light-shielding film 23 on the counter substrate 20 side in this way, incident light from the counter substrate 20 side causes the channel region 1a ′ of the semiconductor layer 1a of the pixel switching TFT 30 and the LDD (Lightly Doped Drain) regions 1b and 1c. Intrusion into the image can be prevented and contrast can be improved.
[0044]
Between the TFT array substrate 10 and the counter substrate 20, which are configured in this manner and arranged so that the pixel electrode 9 a and the counter electrode 21 face each other, a sealing material (illustrated) formed between the peripheral portions of both substrates. Liquid crystal (electro-optical material) is enclosed in a space surrounded by (approximately), and a liquid crystal layer (electro-optical material layer) 50 is formed.
[0045]
The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.
[0046]
Further, the sealing material is made of an adhesive such as a photo-curing adhesive or a thermosetting adhesive for bonding the TFT array substrate 10 and the counter substrate 20 at their peripheral portions, and both the substrates are inside. Spacers such as glass fibers and glass beads are mixed to make the distance between them a predetermined value.
[0047]
Further, as shown in FIG. 3, on the surface of the substrate body 10A of the TFT array substrate 10 on the liquid crystal layer 50 side, a first light shielding film (light shielding layer) 11a is provided at a position corresponding to each pixel switching TFT 30. ing. The first light shielding film 11a is preferably made of a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pd, which are preferably opaque high melting point metals.
[0048]
By configuring the first light shielding film 11a from such a material, the high temperature in the formation process of the pixel switching TFT 30 performed after the formation process of the first light shielding film 11a on the surface of the substrate body 10A of the TFT array substrate 10 is achieved. By the treatment, it is possible to prevent the first light shielding film 11a from being broken or melted.
[0049]
In the present embodiment, since the first light-shielding film 11a is formed on the TFT array substrate 10 in this way, the return light from the TFT array substrate 10 side is caused by the channel region 1a ′ or the LDD region 1b of the pixel switching TFT 30. 1c can be prevented, and the characteristics of the pixel switching TFT 30 as a transistor element can be prevented from deteriorating due to the generation of photocurrent.
[0050]
In addition, in the region where the first light shielding layer 11a is not formed immediately above the substrate body 10A, the first insulator layer has the same thickness as the first light shielding layer 11a and the surface is flattened. 12A is provided, and a second insulator layer 12B is provided on the surfaces of the first light shielding film 11a and the first insulator layer 12A. The second insulator layer 12B is formed over the entire surface of the substrate body 10A. A first interlayer insulating film 12 for electrically insulating the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a is formed by the first insulator layer 12A and the second insulator layer 12B. It is configured.
[0051]
Further, by providing the first interlayer insulating film 12 on the surface of the TFT array substrate 10 in this way, it is possible to prevent the first light shielding film 11a from contaminating the pixel switching TFT 30 and the like.
[0052]
In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, the semiconductor film 1a is extended to form the first storage capacitor electrode 1f, and further opposed thereto. The storage capacitor 70 is configured by using a part of the capacitor line 3b to be a second storage capacitor electrode.
[0053]
More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a, and an insulating film is formed on the capacitor line 3b that extends along the data line 6a and the scanning line 3a. The first storage capacitor electrode (semiconductor layer) 1f is disposed so as to be opposed to each other. In particular, since the insulating film 2 as a dielectric of the storage capacitor 70 is nothing but the gate insulating film 2 of the TFT 30 formed on the single crystal silicon layer by high-temperature oxidation, it can be a thin and high withstand voltage insulating film. The storage capacitor 70 can be configured as a large storage capacitor with a relatively small area.
[0054]
Further, as can be seen from FIGS. 2 and 3, in the storage capacitor 70, the first light shielding film 11a is connected to the first storage capacitor electrode 1f on the opposite side of the capacitor line 3b as the second storage capacitor electrode. By arranging the third storage capacitor electrode so as to face each other through the film 12 (see the storage capacitor 70 on the right side of FIG. 3), the storage capacitor is further provided. That is, in the present embodiment, a double storage capacitor structure in which storage capacitors are provided on both sides across the first storage capacitor electrode 1f is constructed, and the storage capacitor is further increased. By adopting such a structure, it is possible to improve a function of the liquid crystal device of the present embodiment that prevents flicker and burn-in in a display image.
[0055]
As a result, the space outside the opening area, that is, the area under the data line 6a and the area where the liquid crystal disclination occurs along the scanning line 3a (that is, the area where the capacitor line 3b is formed) is effectively used. Thus, the storage capacity of the pixel electrode 9a can be increased.
[0056]
In the present embodiment, the first light shielding film 11a (and the capacitor line 3b electrically connected thereto) is electrically connected to a constant potential source, and the first light shielding film 11a and the capacitor line 3b are Constant potential. Therefore, the potential fluctuation of the first light shielding film 11a does not adversely affect the pixel switching TFT 30 disposed opposite to the first light shielding film 11a. Further, the capacitor line 3 b can function well as the second storage capacitor electrode of the storage capacitor 70. As the constant potential source, a constant potential source such as a negative power source or a positive power source supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, etc.) for driving the liquid crystal device of this embodiment, Examples thereof include a ground power source and a constant potential source supplied to the counter electrode 21. In this way, if the power source such as a peripheral circuit is used, the first light shielding film 11a and the capacitor line 3b can be set to a constant potential without the need to provide a dedicated potential wiring or an external input terminal.
[0057]
Further, as shown in FIGS. 2 and 3, in the present embodiment, in addition to providing the first light shielding film 11a on the TFT array substrate 10, the first light shielding film 11a is formed in the previous stage or via the contact hole 13. It is configured to be electrically connected to the subsequent capacity line 3b. In the case of such a configuration, the data lines 6a are arranged along the edge of the opening region of the pixel portion as compared with the case where each first light shielding film 11a is electrically connected to the capacitor line of its own stage. There are few steps with respect to the other region where the capacitor line 3b and the first light shielding film 11a are formed. Thus, if there are few steps along the edge of the opening area of the pixel portion, the liquid crystal disclination (alignment failure) caused by the step can be reduced, so that the opening area of the pixel portion can be widened. Become.
[0058]
Further, in the first light shielding film 11a, the contact hole 13 is opened at the protruding portion protruding from the main line portion extending linearly as described above. Here, as the location of the contact hole 13 is closer to the edge, cracks are less likely to occur due to the fact that stress is more easily released from the edge. Therefore, the stress applied to the first light-shielding film 11a during the manufacturing process depends on how close to the tip of the protruding portion the contact hole 13 is opened (preferably, depending on how close the tip is to the tip of the margin). Is mitigated, cracks can be prevented more effectively, and the yield can be improved.
[0059]
The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, the dielectric film of the storage capacitor 70 and the gate insulating film 2 of the TFT 30 are made of the same high-temperature oxide film, and the first storage capacitor electrode 1f and the channel formation region 1a, the source region 1d, the drain region 1e, and the like of the TFT 30 are made of the same semiconductor layer 1a. For this reason, the laminated structure formed on the surface of the substrate main body 10A of the TFT array substrate 10 can be simplified. Further, in the manufacturing method of the liquid crystal device described later, the capacitor line 3b and the scanning line 3a are formed in the same thin film forming step. The dielectric film of the storage capacitor 70 and the gate insulating film 2 can be formed at the same time.
[0060]
Further, as shown in FIG. 2, the first light shielding film 11a extends along the scanning line 3a, and is divided into a plurality of stripes in the direction along the data line 6a. For this reason, for example, the first light shielding film 11a, the scanning line 3a, and the capacitor line 3b are formed as compared with the case where a grid-shaped light shielding film formed integrally around the opening region of each pixel portion is provided. In the laminated structure of the liquid crystal device of the present embodiment, which is composed of a polysilicon film, a metal film forming the data line 6a, an interlayer insulating film, etc., stress caused by heating and cooling during the manufacturing process due to the difference in physical properties of each film Can be relieved significantly. For this reason, it is possible to prevent the occurrence of cracks in the first light shielding film 11a and the like and to improve the yield.
[0061]
In FIG. 2, the linear main line portion of the first light shielding film 11 a is formed so as to substantially overlap the linear main line portion of the capacitance line 3 b, but the first light shielding film 11 a is formed in the channel of the TFT 30. If it is provided at a position covering the region and overlapped with the capacitor line 3b at any point so that the contact hole 13 can be formed, it has a light shielding function for the TFT 30 and a function for reducing the resistance of the capacitor line. it can. Therefore, for example, the first light-shielding film 11a is provided even in a longitudinal gap region along the scanning line between the adjacent scanning line 3a and the capacitor line 3b or a position slightly overlapping with the scanning line 3a. Also good.
[0062]
The capacitor line 3b and the first light-shielding film 11a are electrically connected to each other reliably and with high reliability through the contact hole 13 opened in the first interlayer insulating film 12, Such a contact hole 13 may be opened for each pixel, or may be opened for each pixel group including a plurality of pixels.
[0063]
When the contact hole 13 is opened for each pixel, the resistance of the capacitor line 3b can be reduced by the first light-shielding film 11a, and the degree of redundant structure between the two can be increased. On the other hand, when the contact hole 13 is opened for each pixel group composed of a plurality of pixels (for example, every 2 pixels or every 3 pixels), the sheet resistance, the driving frequency of the capacitor line 3b and the first light shielding film 11a, Taking into account the required specifications, etc., the benefits of the low resistance and redundant structure of the capacitor line 3b by the first light-shielding film 11a, the complexity of the manufacturing process by opening a large number of contact holes 13, or the liquid crystal device Since it is possible to properly balance the adverse effects such as the deterioration of the quality, it is very advantageous in practice.
[0064]
Further, the contact hole 13 provided for each pixel or each pixel group is formed under the data line 6a when viewed from the counter substrate 20 side. For this reason, the contact hole 13 is out of the opening region of the pixel portion, and is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed. Defects of the TFT 30 and other wirings due to the formation of the contact hole 13 can be prevented while effectively utilizing.
[0065]
In FIG. 3, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a channel region 1a ′ of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a and the scanning line 3a. Gate insulating film 2 that insulates scan line 3a from semiconductor layer 1a, data line 6a, low concentration source region (source side LDD region) 1b and low concentration drain region (drain side LDD region) 1c of semiconductor layer 1a, semiconductor layer 1a of high concentration source region 1d and high concentration drain region 1e.
[0066]
A corresponding one of the plurality of pixel electrodes 9a is connected to the high concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e are doped with an N-type or P-type dopant having a predetermined concentration depending on whether an N-type or P-type channel is formed in the semiconductor layer 1a. It is formed by doping. N-channel TFTs have the advantage of high operating speed and are often used as pixel switching TFTs 30 that are pixel switching elements.
[0067]
The data line 6a is composed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. A second contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are formed on the scanning line 3a, the gate insulating film 2 and the first interlayer insulating film 12, respectively. An interlayer insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5 to the source region 1b.
[0068]
Furthermore, on the data line 6a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1e is formed is formed. The pixel electrode 9a is electrically connected to the high concentration drain region 1e through the contact hole 8 to the high concentration drain region 1e. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured. The pixel electrode 9a and the high-concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same polysilicon film as the scanning line 3b.
[0069]
The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c. It may be a self-aligned TFT in which impurity ions are implanted at a high concentration using the (scanning line 3a) as a mask and high concentration source and drain regions are formed in a self-aligning manner.
[0070]
In addition, although a single gate structure in which only one gate electrode (scanning line 3a) of the pixel switching TFT 30 is disposed between the source-drain regions 1b and 1e is used, two or more gate electrodes are disposed therebetween. Also good. At this time, the same signal is applied to each gate electrode. If the TFT is constituted by a double gate or a triple gate or more in this way, a leakage current at the junction between the channel and the source-drain region can be prevented, and the off-state current can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.
[0071]
Here, in general, the single crystal silicon layer constituting the channel region 1a ′, the low concentration source region 1b, the low concentration drain region 1c, and the like of the semiconductor layer 1a has a photoelectric current due to the photoelectric conversion effect of silicon when light enters. However, in this embodiment, since the data line 6a is formed from a light-shielding metal thin film such as Al so as to cover the scanning line 3a from above, at least, the transistor characteristics of the pixel switching TFT 30 are deteriorated. Incident light can be prevented from entering the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a.
[0072]
Further, as described above, since the first light shielding film 11a is provided below the pixel switching TFT 30 (on the substrate body 10A side), at least the channel region 1a ′ and the LDD regions 1b, 1c of the semiconductor layer 1a. It is possible to prevent the return light from entering.
[0073]
In the present embodiment, since the capacitor line 3b provided in the adjacent upstream or downstream pixel is connected to the first light shielding film 11a, the first light shielding is applied to the uppermost or lowermost pixel. The capacitor line 3b for supplying a constant potential to the film 11a is required. Therefore, it is preferable to provide one extra capacity line 3b with respect to the number of vertical pixels.
[0074]
(Method for manufacturing electro-optical device)
Next, a method for manufacturing a liquid crystal device having the above structure will be described with reference to FIGS.
[0075]
First, a method for manufacturing the TFT array substrate 10 will be described as a method for manufacturing the substrate for an electro-optical device according to the present embodiment with reference to FIGS. 4 to 5 and FIGS. 6 to 11 are shown in different scales.
[0076]
First, based on FIG. 4 and FIG. 5, the process until the first light shielding film (light shielding layer) 11a and the first interlayer insulating film 12 are formed on the surface of the substrate body 10A of the TFT array substrate 10 will be described in detail. To do. 4 and 5 are process diagrams showing a part of the TFT array substrate in each process corresponding to the A-A 'cross section of FIG. 2, as in FIG.
[0077]
First, a substrate body (light transmissive substrate) 10A such as a quartz substrate or hard glass is prepared, and the substrate body 10A is preferably N.₂In an inert gas atmosphere such as (nitrogen), annealing is performed at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C., and pre-processing is performed so that distortion generated in the substrate body 10A is reduced in a high-temperature process performed later. It is desirable. That is, it is desirable to heat-treat the substrate body 10A at the same temperature or higher according to the maximum temperature processed in the manufacturing process.
[0078]
As shown in FIG. 4 (a), the entire surface of the substrate body 10A thus treated includes at least one of Ti, Cr, W, Ta, Mo, and Pd. The light shielding layer 11 is formed by depositing a metal silicide or the like to a film thickness of, for example, 150 to 200 nm by a sputtering method, a CVD method, an electron beam heating vapor deposition method, or the like.
[0079]
Next, after forming a photoresist on the entire surface of the substrate body 10A, the photoresist is exposed using a photomask having a pattern (see FIG. 2) of the first light-shielding film 11a to be finally formed. By developing the photoresist, as shown in FIG. 4B, a photoresist 207 having a pattern of the first light shielding film 11a to be finally formed is formed. In the present embodiment, since the first light shielding film 11a is formed only in the transistor element formation region (pixel portion), the photoresist 207 is formed only in the transistor element formation region.
[0080]
Next, the light shielding layer 11 is etched using the photoresist 207 as a mask, and then the photoresist 207 is peeled off to form a transistor element on the surface of the substrate body 10A as shown in FIG. The first light shielding film (light shielding layer) 11a having a predetermined pattern (see FIG. 2) is formed only in the region (pixel portion). The film thickness of the first light shielding film 11a is, for example, 150 to 200 nm.
[0081]
Next, as shown in FIG. 5A, the insulator layer 12X is formed on the entire surface of the substrate body 10A on which the first light-shielding film 11a is formed by sputtering, CVD, or the like. As a material of the insulator layer 12X, high insulating properties such as silicon oxide, silicon nitride, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), etc. Glass etc. can be illustrated. The film thickness of the insulator layer 12X is set to be at least thicker than the film thickness of the first light shielding film 11a, for example, about 400 to 1000 nm, and more preferably about 800 nm.
[0082]
Next, as shown in FIG. 5B, the surface of the first light shielding film 11a is exposed on the surface of the substrate body 10A on which the insulator layer 12X is formed by using a method such as a CMP (chemical mechanical polishing) method. Polish up to.
[0083]
When the surface of the substrate main body 10A is thus polished, the insulator layer 12X formed above the first light shielding film 11a is removed, and the first light shielding film 11a is formed in the region where the first light shielding film 11a is not formed. Only the first insulator layer 12A having the same thickness as the light shielding film 11a remains, and the surface of the substrate body 10A is flattened.
[0084]
Further, in this step, the end point of polishing can be easily detected by utilizing the different materials of the first light shielding film 11a and the insulating layer 12X (first insulating layer 12A). For example, when the CMP (Chemical Mechanical Polishing) method is used, the first light-shielding film 11a made of metal or the like does not cause a chemical reaction with the polishing liquid, so that the substrate body 10A is instantly exposed when the surface of the first light-shielding film 11a is exposed. The frictional force between the polishing pad that performs polishing and the substrate body 10A is reduced. Further, the vibration of the substrate holder that holds the substrate body 10A also changes. Therefore, the end point of polishing can be easily detected by detecting the frictional force between the polishing pad and the substrate body 10A or the vibration of the substrate holder.
[0085]
Thus, in this embodiment, since the end point of polishing can be detected by detecting the moment when the surface of the first light shielding film 11a is exposed, the first light shielding film 11a has a polishing stop function. ing.
[0086]
Next, as shown in FIG. 5C, the second surface is formed on the entire surface of the substrate body 10A on which the first light-shielding film 11a and the first insulator layer 12A are formed by sputtering, CVD, or the like. The insulator layer 12B is formed. Examples of the material of the second insulator layer 12B include silicon oxide, silicon nitride, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), and BPSG (boron phosphorus silicate glass). Examples thereof include highly insulating glass. The second insulator layer 12B may be made of a material different from that of the first insulator layer 12A. However, in order to simplify the manufacturing process, the second insulator layer 12B is made of the first insulator layer 12B. It is desirable that the insulating layer 12A be made of the same material.
[0087]
Further, since the second insulator layer 12A formed in this step is formed on the surfaces of the first light shielding film 11a and the first insulator layer 12A whose surfaces are planarized, the surfaces are planarized. It will be. As described above, the first interlayer insulating film 12 including the first insulator layer 12A and the second insulator layer 12B and having a flattened surface is formed.
[0088]
Next, a method of manufacturing the TFT array substrate 10 from the substrate body 10A on which the first interlayer insulating film 12 having a planarized surface is formed will be described with reference to FIGS. 6 to 11 are process diagrams showing a part of the TFT array substrate in each process corresponding to the A-A 'cross section of FIG. 2, as in FIG.
[0089]
FIG. 6A is a diagram showing a part of FIG. In FIGS. 6 to 11, the illustration of the first insulator layer 12 </ b> A and the second insulator layer 12 </ b> B constituting the first interlayer insulating film 12 is omitted for simplification.
[0090]
As shown in FIG. 6B, the substrate main body 10A shown in FIG. 6A on which the first interlayer insulating film 12 having a planarized surface is formed is bonded to the single crystal silicon substrate 206a.
[0091]
The thickness of the single crystal silicon substrate 206a used for bonding is, for example, 600 μm, and an oxide film layer 206b is formed on the surface of the single crystal silicon substrate 206a on the side to be bonded to the substrate body 10A in advance. Ion (H⁺) Is, for example, an acceleration voltage of 100 keV and a dose of 10 × 10¹⁶/ Cm²It is injected at. The oxide film layer 206b is formed by oxidizing the surface of the single crystal silicon substrate 206a by about 0.05 to 0.8 μm.
[0092]
For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be employed. In order to further increase the bonding strength, it is necessary to further increase the heat treatment temperature to about 450 ° C., but there is a large difference in the thermal expansion coefficient between the substrate body 10A made of quartz or the like and the single crystal silicon substrate 206a. Therefore, if it is heated as it is, defects such as cracks are generated in the single crystal silicon layer, and the quality of the manufactured TFT array substrate 10 may be deteriorated.
[0093]
In order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 206a once subjected to heat treatment for bonding at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, Further, it is desirable to perform a high temperature heat treatment. For example, using a KOH aqueous solution at 80 ° C., etching is performed so that the thickness of the single crystal silicon substrate 206a is 150 μm, and then bonding to the substrate main body 10A is performed, and heat treatment is performed again at 450 ° C. to increase the bonding strength. It is desirable to increase.
[0094]
Next, as shown in FIG. 6C, the single crystal silicon substrate 206a is attached to the substrate body 10A while leaving the oxide film 206b and the single crystal silicon layer 206 on the bonded surface side of the bonded single crystal silicon substrate 206a. Heat treatment for peeling from the substrate is performed. This substrate peeling phenomenon is caused by the fact that silicon bonds are broken at a certain layer near the surface of the single crystal silicon substrate 206a by hydrogen ions introduced into the single crystal silicon substrate 206a.
[0095]
The heat treatment can be performed, for example, by heating the two bonded substrates to 600 ° C. at a temperature rising rate of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon substrate 206a is separated from the substrate body 10A, and a single crystal silicon layer 206 of about 200 nm ± 5 nm is formed on the surface of the substrate body 10A. Note that the single crystal silicon layer 206 can be formed to have an arbitrary film thickness from 50 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 206a described above.
[0096]
In addition to the method described here, the thinned single crystal silicon layer 206 is obtained by polishing the surface of the single crystal silicon substrate to a thickness of 3 to 5 μm, and then further using a PACE (Plasma Assisted Chemical Etching) method. The ELTRAN (Epitaxial film) is a method in which the film thickness is etched to about 0.05 to 0.8 μm and the epitaxial silicon layer formed on the porous silicon is transferred onto the bonded substrate by selective etching of the porous silicon layer. It can also be obtained by the Layer Transfer method.
[0097]
Next, as shown in FIG. 6D, a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed by a photolithography process, an etching process, or the like. That is, in particular, in a region where the capacitor line 3b is formed under the data line 6a and a region where the capacitor line 3b is formed along the scanning line 3a, the first layer extending from the semiconductor layer 1a constituting the pixel switching TFT 30 is provided. One storage capacitor electrode 1f is formed.
[0098]
Next, as shown in FIG. 6E, the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 is placed at a temperature of about 850 to 1300 ° C., preferably about 1000 ° C. for about 72 minutes. By thermal oxidation, a relatively thin thermal silicon oxide film having a thickness of about 60 nm is formed, and the gate insulating film 2 for forming a capacitor is formed together with the gate insulating film 2 of the pixel switching TFT 30. As a result, the thickness of the semiconductor layer 1a and the first storage capacitor electrode 1f is about 30 to 170 nm, and the thickness of the gate insulating film 2 is about 60 nm.
[0099]
Next, as shown in FIG. 7A, a resist film 301 is formed at a position corresponding to the N-channel semiconductor layer 1a, and a dopant 302 of a V group element such as P is added to the P-channel semiconductor layer 1a at a low concentration. (For example, P ions are accelerated by 70 keV, 2 × 10¹¹/ Cm²Dope).
[0100]
Next, as shown in FIG. 7B, a resist film is formed at a position corresponding to a P-channel semiconductor layer 1a (not shown), and a group 303 element dopant 303 such as B is formed on the N-channel semiconductor layer 1a. At a low concentration (for example, an acceleration voltage of 35 keV for B ions, 1 × 10¹²/ Cm²Dope).
[0101]
Next, as shown in FIG. 7C, a resist film 305 is formed on the surface of the substrate 10 excluding the end of the channel region 1a ′ of each semiconductor layer 1a for each P channel and N channel. About 1 to 10 times the dose shown in FIG. 7A, a dose of about 1 to 10 times that of the step shown in FIG. A dopant 306 of a group III element such as B is doped.
[0102]
Next, as shown in FIG. 7D, in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, it corresponds to the scanning line 3a (gate electrode) on the surface of the substrate body 10A. A resist film 307 (wider than the scanning line 3a) is formed on the portion to be formed, and this is used as a mask to form a V group element dopant 308 such as P at a low concentration (for example, P ions at an acceleration voltage of 70 keV). 3 × 10¹⁴/ Cm²Dope).
[0103]
Next, as shown in FIG. 8A, a contact hole 13 reaching the first light shielding film 11a is formed in the first interlayer insulating film 12 by dry etching such as reactive etching, reactive ion beam etching, or wet etching. To do. At this time, opening the contact hole 13 or the like by anisotropic etching such as reactive etching or reactive ion beam etching has an advantage that the opening shape can be made substantially the same as the mask shape. However, if a hole is formed by combining dry etching and wet etching, these contact holes 13 and the like can be tapered, so that an advantage of preventing disconnection at the time of wiring connection can be obtained.
[0104]
Next, as shown in FIG. 8B, after the polysilicon layer 3 is deposited to a thickness of about 350 nm by a low pressure CVD method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive. . Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. Thereby, the conductivity of the polysilicon layer 3 can be increased.
[0105]
Next, as shown in FIG. 8C, the capacitance line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 2 by a photolithography process, an etching process, etc. using a resist mask. Thereafter, the polysilicon remaining on the back surface of the substrate body 10A is removed by etching with the surface of the substrate body 10A covered with a resist film.
[0106]
Next, as shown in FIG. 8D, in order to form a P-channel LDD region in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is covered with a resist film 309, and the scanning line 3a (gate First, a dopant 310 of a group III element such as B is used at a low concentration (for example, BF) using the electrode as a diffusion mask.₂Ions are accelerated at 90 keV, 3 × 10¹³/ Cm²The lightly doped source region 1b and the lightly doped drain region 1c of the P channel are formed.
[0107]
Subsequently, as shown in FIG. 8E, in order to form a P-channel high concentration source region 1d and a high concentration drain region 1e in the semiconductor layer 1a, a position corresponding to the N-channel semiconductor layer 1a is formed in a resist film. 309 and a state in which a resist layer is formed on the scanning line 3a corresponding to the P channel with a mask wider than the scanning line 3a (not shown), but also of a group III element such as B High concentration of dopant 311 (eg, BF₂Ions are accelerated at 90 keV, 2 × 10¹⁵/ Cm²Dope).
[0108]
Next, as shown in FIG. 9A, in order to form an N-channel LDD region in the semiconductor layer 1a, a position corresponding to the P-channel semiconductor layer 1a is covered with a resist film (not shown) and scanned. Using the line 3a (gate electrode) as a diffusion mask, a dopant 60 of a group V element such as P is used at a low concentration (for example, P ions are accelerated by 70 keV, 6 × 10 6¹²/ Cm²N-channel lightly doped source region 1b and lightly doped drain region 1c are formed.
[0109]
Subsequently, as shown in FIG. 9B, in order to form the N channel high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, a resist 62 is formed with a mask wider than the scanning line 3a. After forming on the scanning line 3a corresponding to the N channel, the dopant 61 of a V group element such as P is also used at a high concentration (for example, P ions are accelerated at a voltage of 70 keV, 4 × 10 4¹⁵/ Cm²Dope).
[0110]
Next, as shown in FIG. 9C, for example, by using a normal pressure or reduced pressure CVD method or TEOS gas so as to cover the capacitor line 3b and the scan line 3a together with the scan line 3a in the pixel switching TFT 30, A second interlayer insulating film 4 made of a silicate glass film such as NSG, PSG, BSG or BPSG, a silicon nitride film or a silicon oxide film is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0111]
Thereafter, an annealing process at about 850 ° C. is performed for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e.
[0112]
Next, as shown in FIG. 9D, the contact hole 5 for the data line 31 is formed by dry etching such as reactive etching or reactive ion beam etching or by wet etching. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.
[0113]
Next, as shown in FIG. 10A, on the second interlayer insulating film 4, a low resistance metal such as light-shielding Al or a metal silicide is formed on the second interlayer insulating film 4 by a sputtering process or the like as a metal film 6. The film is deposited to a thickness of 700 nm, preferably about 350 nm. Further, as shown in FIG. 10B, the data line 6a is formed by a photolithography process, an etching process, or the like.
[0114]
Next, as shown in FIG. 10 (c), a silicate glass film such as NSG, PSG, BSG, BPSG is used to cover the data line 6a by using, for example, normal pressure or low pressure CVD, TEOS gas, or the like. Then, a third interlayer insulating film 7 made of a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm, and more preferably 800 nm.
[0115]
Next, as shown in FIG. 11A, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high-concentration drain region 1e is formed by reactive etching or reactive ion beam. It is formed by dry etching such as etching.
[0116]
Next, as shown in FIG. 11B, a transparent conductive thin film 9 such as ITO is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. As shown in FIG. 11C, the pixel electrode 9a is formed by a photolithography process, an etching process, or the like. In the case where the liquid crystal device of the present embodiment is a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.
[0117]
Subsequently, after a polyimide alignment film coating solution is applied onto the pixel electrode 9a, the alignment film 16 (see FIG. 3) is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. ) Is formed.
[0118]
As described above, the TFT array substrate (electro-optical device substrate) 10 is manufactured.
[0119]
According to the method for manufacturing a substrate for an electro-optical device of this embodiment, the insulator layer 12X is formed on the substrate body (light transmissive substrate) 10A on which the first light shielding film (light shielding layer) 11a is formed, and the insulator layer is formed. The surface of the substrate main body 10A on which 12X is formed is polished until the surface of the first light-shielding film 11a is exposed, so that the first light-shielding film 11a has the same film thickness in a region where the first light-shielding film 11a is not formed. The surface of the substrate body 10A on which the first insulator layer 12A is formed and the first light shielding film 11a and the first insulator layer 12A are formed can be flattened and the polishing end point can be easily detected. it can.
[0120]
Further, the first insulator layer 12A and the second insulation layer 12A are formed on the surfaces of the first light shielding film 11a and the first insulator layer 12A whose surfaces are planarized, thereby forming the second insulator layer 12A and the second insulator layer 12A. Since the first interlayer insulating film 12 made of the body layer 12B and having a planarized surface can be formed, the surface of the substrate body 10A to which the single crystal silicon layer 206 is bonded can be planarized.
[0121]
In this way, the surface of the substrate body 10A to which the single crystal silicon layer 206 is bonded can be planarized, so that voids are generated at the boundary surface where the first interlayer insulating film 12 and the single crystal silicon layer 206 are bonded. Therefore, it is possible to prevent the deterioration of the characteristics of the TFT (transistor element) 30.
[0122]
In addition, since the bonding strength between the first interlayer insulating film 12 and the single crystal silicon layer 206 can be secured, it is possible to prevent the occurrence of defects such as film peeling in the process of forming the TFT (transistor element) 30. , Can improve the product yield.
[0123]
In the present embodiment, after the first insulator layer 12A is formed, a second insulator layer 12B is further provided on the surfaces of the first light shielding film 11a and the first insulator layer 12A. Since the TFT (transistor element) 30 is provided on the surface of the insulator layer 12B, contamination of the TFT (transistor element) 30 from the first light-shielding film 11a made of metal or the like can be completely prevented.
[0124]
Since the oxide film 206b is formed in advance on the surface of the single crystal silicon substrate 206a used for bonding, the single crystal silicon substrate 206a is directly formed on the surface of the first light shielding film 11a made of metal or the like. If the oxide film 206b can sufficiently prevent contamination from the first light-shielding film 11a to the TFT (transistor element) 30 even after bonding and forming the TFT (transistor element) 30, the first light-shielding film 11a and After forming the first insulator layer 12A, it is desirable to directly bond the single crystal silicon substrate 206a without forming the second insulator layer 12B, and the step of providing the second insulator layer 12B is unnecessary. Therefore, the manufacturing process can be simplified.
[0125]
In this case, the first light-shielding film (light-shielding layer) 11a having a predetermined pattern and the first light-shielding film 11a are not formed on one surface of the substrate body (light-transmissive substrate) 10A. A first insulator layer 12A having the same thickness as the first light-shielding film (light-shielding layer) 11a and having a flattened surface, and a TFT directly formed on the surface of the first light-shielding film 11a ( A TFT array substrate (substrate for an electro-optical device) including the transistor element 30 can be provided.
[0126]
In the present embodiment, the case where the first light shielding film 11a is provided only in the transistor element formation region (pixel portion) has been described. However, the present invention is not limited to this, and the first embodiment The light shielding film 11a may be provided in the non-formation region of the transistor element, and an effect equivalent to that of the present embodiment can be obtained. When the first light shielding film 11a is also provided in the non-transistor region, the pattern of the first light shielding film 11a in the non-transistor region may be the same pattern as in the transistor element formation region. The pattern may not be patterned, and any pattern may be used.
[0127]
Next, a manufacturing method of the counter substrate 20 and a method of manufacturing a liquid crystal device from the TFT array substrate 10 and the counter substrate 20 will be described.
[0128]
For the counter substrate 20 shown in FIG. 3, a light-transmitting substrate such as a glass substrate is prepared as the substrate body 20A, and the second light-shielding film 23 and a second light-shielding as a peripheral parting described later are formed on the surface of the substrate body 20A. A film is formed. The second light-shielding film 23 and the second light-shielding film as a peripheral parting described later are formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, and Al. These second light-shielding films may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist in addition to the above metal material.
[0129]
Thereafter, a counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO on the entire surface of the substrate main body 20A to a thickness of about 50 to 200 nm by sputtering or the like. Further, after an alignment film coating solution such as polyimide is applied to the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 5) is applied by rubbing in a predetermined direction so as to have a predetermined pretilt angle. 3). The counter substrate 20 is manufactured as described above.
[0130]
Finally, the TFT array substrate 10 and the counter substrate 20 manufactured as described above are bonded to each other with a sealing material so that the alignment films 16 and 22 face each other, and a method such as a vacuum suction method is used. A liquid crystal device having the above-described structure is manufactured by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals into the space to form a liquid crystal layer 50 having a predetermined thickness.
[0131]
(Overall configuration of liquid crystal device)
The overall configuration of the liquid crystal device of the present embodiment configured as described above will be described with reference to FIGS. 12 is a plan view of the TFT array substrate 10 as viewed from the counter substrate 20 side, and FIG. 13 is a cross-sectional view taken along the line H-H ′ of FIG. 12 including the counter substrate 20.
[0132]
In FIG. 12, a sealing material 52 is provided on the surface of the TFT array substrate 10 along the edge thereof. As shown in FIG. 13, the opposing surface has substantially the same contour as the sealing material 52 shown in FIG. The substrate 20 is fixed to the TFT array substrate 10 by the sealing material 52.
[0133]
As shown in FIG. 12, a second light shielding film 53 is provided on the surface of the counter substrate 20 in parallel with the inside of the sealing material 52, for example, as a peripheral parting made of the same or different material as the second light shielding film 23. ing.
[0134]
In the TFT array substrate 10, a data line driving circuit 101 and a mounting terminal 102 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 52. It is provided along two sides adjacent to one side. Needless to say, when the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side.
[0135]
In addition, the data line driving circuit 101 may be arranged on both sides along the side of the display region (pixel portion). For example, the odd-numbered data lines 6a are supplied with image signals from the data line driving circuit arranged along one side of the display area, and the even-numbered data lines 6a are arranged along the opposite side of the display area. An image signal may be supplied from the provided data line driving circuit. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured.
[0136]
Further, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the display area. Further, the second light shielding film 53 is used as a peripheral parting. A precharge circuit may be provided under the cover. In addition, at least one corner portion between the TFT array substrate 10 and the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20.
[0137]
Further, on the surface of the TFT array substrate 10, an inspection circuit or the like for inspecting the quality, defects, etc. of the liquid crystal device during the manufacturing or at the time of shipment may be formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the surface of the TFT array substrate 10, for example, the driving LSI mounted on the TAB (tape automated bonding substrate) is connected to the TFT array substrate 10. You may make it connect electrically and mechanically through the anisotropic conductive film provided in the periphery area | region.
[0138]
Further, for example, the TN (twisted nematic) mode, the STN (super TN) mode, and the D-STN (dual scan-STN) are respectively provided on the light incident side of the counter substrate 20 and the light output side of the TFT array substrate 10. ) Mode or the like, or a normally white mode / normally black mode, a polarizing film, a retardation film, a polarizing means, etc. are arranged in a predetermined direction.
[0139]
When the liquid crystal device of this embodiment is applied to a color liquid crystal projector (projection display device), three liquid crystal devices are used as RGB light valves, and each panel is for RGB color separation. Each color light separated through the dichroic mirror is incident as projection light. Therefore, in that case, as shown in the above embodiment, the counter substrate 20 is not provided with a color filter.
[0140]
However, even if an RGB color filter is formed together with the protective film in a predetermined region facing the pixel electrode 9a on which the second light shielding film 23 is not formed on the surface of the counter substrate 20 on the liquid crystal layer 50 side of the substrate body 20A. Good. With such a configuration, the liquid crystal device of the above embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector.
[0141]
Furthermore, a micro lens may be formed on the surface of the counter substrate 20 so as to correspond to one pixel. In this way, a bright liquid crystal device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that creates RGB colors using light interference may be formed by depositing multiple layers of interference layers having different refractive indexes on the surface of the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color liquid crystal device can be realized.
[0142]
In the liquid crystal device according to this embodiment, incident light is incident from the counter substrate 20 side as in the conventional case. However, since the TFT array substrate 10 is provided with the first light-shielding film 11a, the TFT array substrate 10 Incident light may be incident from the side and emitted from the counter substrate 20 side. That is, even when the liquid crystal device is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a and display a high-quality image. Is possible.
[0143]
Conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, it is necessary to separately arrange anti-reflection (AR) -coated polarizing means or to attach an AR film. However, in this embodiment, since the first light-shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a, such an AR film is formed. There is no need to use the polarized light means or the AR film, or to use the substrate obtained by AR-treating the TFT array substrate 10 itself.
[0144]
Therefore, according to the above embodiment, the material cost can be reduced, and it is very advantageous that the yield is not lowered due to dust, scratches, etc. when the polarizing means is attached. In addition, since the light resistance is excellent, even when a bright light source is used or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality degradation such as crosstalk due to light does not occur.
[0145]
In addition, since the liquid crystal device of the present embodiment includes the TFT array substrate (electro-optical device substrate) 10 manufactured by the method for manufacturing the substrate for an electro-optical device of the present embodiment, the first interlayer There is no void at the boundary surface where the insulating film 12 and the single crystal silicon layer 206 are bonded together, the bonding strength between the first interlayer insulating film 12 and the single crystal silicon layer 206 is strong, and the characteristics of the TFT (transistor element) 30 are improved. Excellent performance without variations and defects.
[0146]
(Electronics)
As an example of an electronic apparatus using the liquid crystal device (electro-optical device) of the above embodiment, a configuration of a projection display device will be described with reference to FIG.
[0147]
In FIG. 14, a projection display device 1100 is provided with three liquid crystal devices of the above-described embodiment, and is a schematic configuration diagram of an optical system of a projection liquid crystal device used as RGB liquid crystal devices 962R, 962G, and 962B. Show.
[0148]
A light source device 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display device of this example. The projection display device includes a color separation optical system 924 as color separation means for separating the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B); The three light valves 925R, 925G, and 925B as modulation means for modulating the color light beams R, G, and B, and the color synthesis prism 910 as color synthesis means for recombining the modulated color light beams are combined. A projection lens unit 906 is provided as projection means for enlarging and projecting the light beam onto the surface of the projection surface 100. Further, a light guide system 927 for guiding the blue light beam B to the corresponding light valve 925B is also provided.
[0149]
The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is divided into a plurality of partial light beams by the rectangular lens of the first lens plate 921. These partial light beams are superimposed in the vicinity of the three light valves 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has a non-uniform illuminance distribution within the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It can be illuminated.
[0150]
Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles and travel toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.
[0151]
Next, in the green reflection dichroic mirror 942, only the green light beam G out of the blue and green light beams B and G reflected by the blue-green reflection dichroic mirror 941 is reflected at right angles, and the green light beam G is emitted from the emitting portion 945. The light is emitted to the side of the combining optical system. The blue light beam B that has passed through the green reflecting dichroic mirror 942 is emitted from the emission part 946 of the blue light beam B to the light guide system 927 side. In this example, the distances from the light beam W emission part of the uniform illumination optical element to the color light emission parts 944, 945, and 946 in the color separation optical system 924 are set to be substantially equal.
[0152]
Condensing lenses 951 and 952 are disposed on the emission side of the emission portions 944 and 945 for the red and green light beams R and G of the color separation optical system 924, respectively. Therefore, the red and green light beams R and G emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.
[0153]
The collimated red and green light beams R and G are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are subjected to switching control according to image information by a driving unit (not shown), thereby modulating each color light passing therethrough. On the other hand, the blue light beam B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to the image information. The light valves 925R, 925G, and 925B in this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G disposed therebetween. , 962B.
[0154]
The light guide system 927 includes a condensing lens 954 arranged on the emission side of the emission part 946 of the blue light beam B, an incident-side reflection mirror 971, an emission-side reflection mirror 972, and an intermediate lens arranged between these reflection mirrors. 973 and a condenser lens 953 disposed on the front side of the light valve 925B. The blue light beam B emitted from the condenser lens 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. The optical path length of each color light beam, that is, the distance from the emission part of the light beam W to each liquid crystal device 962R, 962G, 962B is the longest for the blue light beam B, and therefore, the light amount loss of the blue light beam is the largest. However, the light loss can be suppressed by interposing the light guide system 927.
[0155]
The color light beams R, G, and B modulated through the light valves 925R, 925G, and 925B are incident on the color synthesis prism 910 and synthesized there. Then, the light synthesized by the color synthesis prism 910 is enlarged and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.
[0156]
In this example, since the liquid crystal devices 962R, 962G, and 962B are provided with the first light shielding film (light shielding layer) on the lower side of the TFT, the liquid crystal projector based on the projection light from the liquid crystal devices 962R, 962G, and 962B. The reflected light from the projection optical system, the reflected light from the surface of the TFT array substrate when the projected light passes through, a part of the projected light that penetrates the projection optical system after being emitted from other liquid crystal devices, etc. Even if light enters from the TFT array substrate side, it is possible to sufficiently shield the channel of the TFT for switching the pixel electrode.
[0157]
For this reason, even if a prism unit suitable for miniaturization is used in the projection optical system, a film for preventing return light is separately arranged between the liquid crystal devices 962R, 962G, 962B and the prism unit, or the polarizing means is used. Since it is not necessary to perform a return light prevention process, it is very advantageous in reducing the size and simplification of the configuration.
[0158]
In this embodiment, since the influence of the return light on the channel region of the TFT can be suppressed, the polarizing means 961R, 961G, and 961B subjected to the return light prevention process directly on the liquid crystal device need not be attached. Therefore, as shown in FIG. 15, the polarizing means is formed apart from the liquid crystal device. More specifically, one polarizing means 961R, 961G, 961B is attached to the prism unit 910, and the other polarizing means 960R, 960G. , 960B can be attached to the condenser lenses 953, 945, and 944. In this way, by attaching the polarizing means to the prism unit or the condenser lens, the heat of the polarizing means is absorbed by the prism unit or the condenser lens, and thus the temperature rise of the liquid crystal device can be prevented.
[0159]
Although not shown, an air layer is formed between the liquid crystal device and the polarizing unit by forming the liquid crystal device and the polarizing unit apart from each other, so a cooling unit is provided between the liquid crystal device and the polarizing unit. By sending air such as cold air into the liquid crystal, it is possible to further prevent the temperature of the liquid crystal device from rising and to prevent malfunction due to the temperature rise of the liquid crystal device.
[0160]
【The invention's effect】
As described above, according to the method for manufacturing a substrate for an electro-optical device of the present invention, an insulator layer is formed on a light-transmitting substrate on which a light shielding layer is formed, and the light-transmitting substrate on which the insulator layer is formed. By polishing the surface until the surface of the light shielding layer is exposed, the surface of the light-transmitting substrate to which the single crystal silicon layer is bonded can be flattened, and the light shielding layer has a polishing stop function so that the polishing end point can be obtained. Can be easily detected.
[0161]
In the case where there is a risk of contamination from the light shielding layer to the transistor element, it is desirable to form the second insulator layer on the surfaces of the light shielding layer and the insulator layer before the single crystal silicon substrate is bonded. .
[0162]
An electro-optical device substrate manufactured by the method for manufacturing an electro-optical device substrate according to the present invention and an electro-optical device including the electro-optical device substrate have light-transmitting properties in which a light shielding layer and an insulator layer are formed. There are no voids at the interface between the substrate and the single crystal silicon layer, and the light-transmitting substrate on which the light-shielding layer and the insulator layer are formed and the single crystal silicon layer have a strong bonding strength, which improves the transistor element characteristics. Excellent performance without variations and defects.
[0163]
In addition, by providing the electro-optical device of the present invention, an electronic apparatus with excellent performance can be provided.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like constituting a pixel unit in an electro-optical device according to an embodiment of the invention.
FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate in the electro-optical device according to the embodiment of the invention.
FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2;
4A to 4C are process diagrams showing a method for manufacturing a substrate for an electro-optical device according to an embodiment of the present invention.
FIGS. 5A to 5C are process diagrams illustrating a method for manufacturing an electro-optical device substrate according to an embodiment of the present invention.
6A to 6E are process diagrams showing a method for manufacturing an electro-optical device substrate according to an embodiment of the present invention.
FIGS. 7A to 7D are process diagrams showing a method for manufacturing a substrate for an electro-optical device according to an embodiment of the present invention.
FIGS. 8A to 8E are process diagrams showing a method for manufacturing a substrate for an electro-optical device according to an embodiment of the present invention.
9A to 9D are process diagrams showing a method for manufacturing a substrate for an electro-optical device according to an embodiment of the present invention.
FIGS. 10A to 10C are process diagrams showing a method for manufacturing an electro-optical device substrate according to an embodiment of the present invention.
FIGS. 11A to 11C are process diagrams showing a method for manufacturing a substrate for an electro-optical device according to an embodiment of the present invention. FIGS.
FIG. 12 is a plan view of the TFT array substrate of the electro-optical device according to the embodiment of the present invention as viewed from the counter substrate side together with each component formed on the TFT array substrate.
FIG. 13 is a cross-sectional view taken along the line H-H ′ of FIG.
FIG. 14 is a configuration diagram of a projection display device that is an example of an electronic apparatus using the electro-optical device according to the embodiment of the invention.
FIGS. 15A and 15B are diagrams for explaining a conventional problem. FIGS.
[Explanation of symbols]
1a ... Semiconductor layer
1a '... channel region
1b: low concentration source region (source side LDD region)
1c: Low concentration drain region (drain side LDD region)
1d ... High concentration source region
1e ... High concentration drain region
10 ... TFT array substrate
20 ... Counter substrate
10A, 20A ... substrate body (light transmissive substrate)
11a ... 1st light shielding film (light shielding layer)
12 ... 1st interlayer insulation film
12A ... 1st insulator layer
12B ... Second insulator layer
12X: Insulator layer
30 ... TFT for pixel switching (transistor element)
50 ... Liquid crystal layer (electro-optic material layer)
206 ... single crystal silicon layer

Claims (2)

Forming a light shielding layer on the light transmissive substrate ;
Patterning the light shielding layer at least in a transistor element formation region ;
Forming on the patterned light shielding layer a first insulator layer having a convex portion resulting from the thickness of the patterned light shielding layer ;
Polishing the surface of the first insulator layer until the surface of the patterned light shielding layer is exposed;
Forming a second insulator layer on the surface of the first insulator layer whose surface is polished and the light shielding layer where the surface is exposed;
Bonding a single crystal silicon layer to the surface of the second insulator layer ;
Forming a transistor element from the single crystal silicon layer. A method of manufacturing a substrate for an electro-optical device. 2. The method for manufacturing a substrate for an electro-optical device according to claim 1, wherein the patterned light shielding layer has a polishing stop function in the polishing step.

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