JP4222323B2 - Liquid crystal device and electronic device - Google Patents

Description

  The present invention belongs to the technical field of an active matrix driving type liquid crystal device driven by a thin film transistor (hereinafter referred to as TFT as appropriate), and is particularly used for a liquid crystal projector or the like, in which a light shielding film is provided below a TFT. It belongs to the technical field of equipment.

  Conventionally, when this type of liquid crystal device is used as a light valve in a liquid crystal projector or the like, projection light is generally incident from the side of the counter substrate disposed opposite to the TFT array substrate with the liquid crystal layer interposed therebetween. Here, when the projection light is incident on a channel region composed of an a-Si (amorphous silicon) film or p-Si (polysilicon) film of the TFT, a photocurrent is generated in this region due to a photoelectric conversion effect, The transistor characteristics of the TFT deteriorate. Therefore, a light shielding film made of a metal material such as Cr (chromium) or resin black is generally formed on the counter substrate at a position facing each TFT. This light shielding film defines the opening area of each pixel (that is, the area through which the projection light is transmitted), thereby improving the contrast and preventing color mixture of the color material in addition to shielding the TFT p-Si layer. Plays.

  In this type of liquid crystal device, a positive stagger type or coplanar type a-Si or p-Si TFT having a top gate structure (that is, a structure in which a gate electrode is provided above the channel on the TFT array substrate) is used. In this case, it is necessary to prevent a part of the projection light from entering the TFT channel from the TFT array substrate side as return light by the projection optical system in the liquid crystal projector. Similarly, after passing through the projection optical system after being emitted from reflected light from the surface of the TFT array substrate when the projection light passes through, or from other liquid crystal devices when a plurality of liquid crystal devices are used in combination for color, It is also necessary to prevent a part of the incoming projection light from entering the TFT channel from the TFT array substrate side as return light. For this reason, in Japanese Patent Application Laid-Open No. 9-127497, Japanese Patent Publication No. 3-52611, Japanese Patent Application Laid-Open No. 3-125123, Japanese Patent Application Laid-Open No. 8-171101, etc., a TFT is formed on a TFT array substrate made of a quartz substrate or the like. A liquid crystal device has also been proposed in which a light-shielding film is formed from, for example, an opaque refractory metal at an opposing position (that is, below the TFT).

On the other hand, in this type of liquid crystal device, by applying a scanning signal to the gate electrode, the time for holding the voltage in the pixel electrode is made longer than the time for supplying the image signal to the pixel electrode by making the TFT conductive. Therefore, in general, a storage capacitor is generally added to the pixel electrode so that the liquid crystal driving voltage can be applied for a sufficient time even when the duty ratio is small. In this case, a system in which a part of the capacitor line formed along the scanning line is configured as the other storage capacitor electrode is generalized.
In the liquid crystal device, there is a strong general demand for image quality improvement, and for this reason, it is important to increase the driving frequency of the liquid crystal device.

  However, in order to add a storage capacitor to the pixel electrode as described above, for example, when using a high temperature process having a process of exposing the substrate temperature to a high temperature such as 900 degrees, a capacitor line including one storage capacitor electrode is connected. Since it is formed of the same polysilicon film as the scanning line, it is difficult to reduce the resistance as compared with a wiring made of a low-resistance metal film such as Al. For this reason, the resistance and time constant of the capacitance line increase, and the capacitance of the capacitance line fluctuates due to the capacitive coupling with each data line in the capacitance line crossed under the plurality of data lines, thereby causing a transverse crosstalk. There is a problem that image degradation occurs due to ghosts and the like.

  More specifically, as shown in FIG. 20, when displaying an image 801 in which a black portion is drawn with high contrast against a gray background, other pixels are arranged on one row of pixel columns along the scanning line. When an image signal having a voltage (here, a voltage corresponding to black) that is partially different from a voltage of the image signal (here, a voltage corresponding to gray) is applied to the capacitor line due to such capacitive coupling Before the potential fluctuation becomes stable, writing to each pixel in the pixel row is performed. For this reason, in the image 802 that is actually displayed, a voltage shortage is caused in the left and right pixels of the pixel to which an image signal having a partially different voltage to be displayed in black, and the entire row to be displayed in gray becomes whitish. That is, horizontal crosstalk, ghost, etc. occur.

  In this case, in particular, the point in time when the image signal having a partially different voltage to be displayed in black is closer to the end point of writing for each scanning line, that is, the number of pixels to be displayed in black is one. When the scanning signal is supplied from one of the left and right sides on the scanning line, the closer the pixel is to the other side, or the closer the pixel is to the center when the scanning signal is supplied from both sides, the capacitive line by capacitive coupling. Since the writing to each pixel in the pixel row is performed before the potential fluctuation becomes stable, horizontal crosstalk, ghost, and the like are likely to occur remarkably.

  Such lateral crosstalk, ghosts, etc. are likely to occur because the time constant of the capacitance line relatively increases as the drive frequency increases, as in the case of so-called XGA, SXGA and other types of liquid crystal devices. . Further, when precharging is performed to supply a precharge signal of a predetermined voltage level to the data line in advance of the image signal so that the voltage of the image signal can be written to the data line with a small load, Since it is necessary to ensure a certain length of the horizontal blanking period, after image signals having partially different voltages are applied at a time close to the end of writing of each scanning line, It is impossible to secure a sufficient time until the fluctuation of the potential becomes stable. For this reason, there is a problem that the above-described lateral crosstalk, ghost, and the like are difficult to prevent when precharging.

In order to solve such problems as horizontal crosstalk and ghost, for example, a data line inversion driving method (1S inversion driving method) in which the polarity of the driving voltage applied to the liquid crystal is inverted for each data line, or for each pixel. The dot inversion driving method that inverts is effective, but according to these methods, the liquid crystal disclination (alignment failure) along the data lines and the scanning lines is strongly generated to cause display deterioration. Under the basic requirement of increasing the aperture ratio of the pixel region, these methods are not practical.
The present invention has been made in view of the above-described problems, and an object thereof is to provide a liquid crystal device capable of displaying a high-quality image with a relatively simple configuration using a storage capacitor and a light shielding film.

In order to solve the above problems, a liquid crystal device according to the present invention includes a liquid crystal sandwiched between a pair of substrates, a pixel electrode arranged in a matrix on one of the pair of substrates, A thin film transistor provided corresponding to the pixel electrode and electrically connected to the pixel electrode through a contact hole, a data line electrically connected to the thin film transistor, and a storage capacitor intersecting the data line and being connected to the pixel electrode And a light shielding film that extends so as to overlap the data line and covers at least a channel region of the semiconductor layer of the thin film transistor when viewed from the one substrate side, the light shielding film, the data line And a storage capacitor electrode of the storage capacitor is formed as a part of the semiconductor layer in a region where the capacitor line overlaps, and the contact hole is formed in a plane when viewed in plan. Over data lines and the light shielding film is characterized by being provided apart from the area to be stretched.

In the liquid crystal device according to the aspect of the invention, the storage capacitor may include a dielectric film made of the same insulating film as the gate insulating film of the thin film transistor.

In the electro-optical device according to the aspect of the invention, the light shielding film is formed below the semiconductor layer forming the thin film transistor via an interlayer insulating film, and the capacitor line and the light shielding film are formed on the interlayer insulating film. It is connected through an opened contact hole.

  According to this aspect, since the second storage capacitor electrode and the light shielding film are connected through the contact hole opened in the interlayer insulating film, a reliable and highly reliable electrical connection state is established between the two. realizable.

    According to a fourth aspect of the first invention, the contact hole is formed in a region overlapping the data line as viewed in a plan view.

  According to this aspect, the contact hole is opened under the data line. That is, the contact hole is provided in a portion of the first interlayer insulating film that is out of the pixel opening region and in which one electrode of the first storage capacitor extending from the thin film transistor and the semiconductor layer of the thin film transistor is not formed. Therefore, the pixel area can be effectively used.

  In a fifth aspect of the first invention, the second storage capacitor electrode and the light shielding film are connected to a constant potential source. According to this aspect, since the light shielding film is connected to the constant potential source, the light shielding film is set to a constant potential. Therefore, the potential fluctuation of the light shielding film does not adversely affect the thin film transistor disposed opposite to the light shielding film. Since the second storage capacitor electrode is also at a constant potential, it can function well as a storage capacitor electrode. In this case, the constant potential of the constant potential source may be equal to the ground potential, for example.

  A second aspect of the present invention is an electronic device including a substrate using a thin film transistor. According to this aspect, since the electronic apparatus includes the substrate using the thin film transistor according to the first invention described above, the reliability of the apparatus is high due to the redundant structure, and display deterioration such as lateral crosstalk is reduced. In addition, a high-quality image can be displayed by a substrate using a thin film transistor having excellent light-shielding performance against return light or the like.

  In a third aspect of the present invention, a liquid crystal is sandwiched between a pair of substrates, and one of the pair of substrates is a substrate using the thin film transistor of the first aspect of the invention. Device. According to this aspect, since the liquid crystal device includes the substrate using the thin film transistor of the first invention described above, the reliability of the device is high due to the redundant structure, and display deterioration such as lateral crosstalk is reduced. In addition, a high-quality image can be displayed by a substrate using a thin film transistor having excellent light-shielding performance against return light or the like.

  In one aspect of the third invention, at least one of the plurality of interlayer insulating films formed on the substrate is at least one of the thin film transistor, the data line, the scanning line, and the capacitor line. By forming the opposing portions in a concave shape, the side facing the liquid crystal of the film formed at the position closest to the liquid crystal among the plurality of interlayer insulating films is flattened.

  In this configuration, since the side facing the liquid crystal of the interlayer insulating film formed at the position closest to the liquid crystal is flattened, the surface of the interlayer insulating film formed at the position closest to the liquid crystal according to the degree of the flattening The disclination (defective alignment) caused by the unevenness of the liquid crystal can be reduced.

  The above operation and other advantages of the present invention will become apparent from the embodiments described later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
The configuration and operation of the first embodiment of the liquid crystal device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display area of a liquid crystal device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, etc. are formed, and FIG. 3 is a cross-sectional view taken along the line AA ′ of FIG. It is. FIG. 4 is a plan view showing a two-dimensional wiring layout of the light shielding film on the TFT array substrate together with peripheral circuits, and FIG. 5 is a timing chart of various signals related to precharging. In FIG. 3, the scales are different for each layer and each member in order to make each layer and each member recognizable on the drawing.

  In FIG. 1, a plurality of pixels formed in a matrix that constitutes the image display area of the liquid crystal device according to the present embodiment has a pixel electrode 9a and a plurality of TFTs 30 for controlling the pixel electrode 9a formed in a matrix. The data line 6a for supplying the image signal is electrically connected to the source region of the TFT 30. The image signals S1, S2,..., Sn to be written to the data line 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. good. Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. ing. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30 serving as a switching element for a certain period, the image signals S1, S2,. Write at the timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). . Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time when the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device with a high contrast ratio can be realized. As a method of forming the storage capacitor 70, it goes without saying that the capacitor line 3b which is a wiring for forming the capacitor may be provided, or the capacitor may be formed between the storage line 70 and the preceding scanning line 3a. Yes.

  In FIG. 2, on the TFT array substrate of the liquid crystal device, a plurality of transparent pixel electrodes 9a (outlined by dotted line portions 9a ') are provided in a matrix, and the vertical and horizontal boundaries of the pixel electrodes 9a A data line 6a, a scanning line 3a, and a capacitor line 3b are provided along each line. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a polysilicon film through the contact hole 5 and the pixel electrode 9a is connected to the source layer described later in the semiconductor layer 1a through the contact hole 8. Electrically connected to the drain region. In addition, the scanning line 3a is arranged so as to face a channel region (a hatched region in the lower right in the figure) described later in the semiconductor layer 1a. A first light-shielding film 11a in the pixel portion is provided in a region indicated by a diagonal line rising to the right in the drawing. That is, the first light shielding film 11a is provided in the pixel portion at a position where the TFT including the channel region of the semiconductor layer 1a, the data line 6a, the scanning line 3a, and the capacitor line 3b overlap each other when viewed from the TFT array substrate side. .

  As shown in FIG. 3, the liquid crystal device includes a TFT array substrate 10 that constitutes an example of one transparent substrate, and a counter substrate 20 that constitutes an example of the other transparent substrate disposed opposite thereto. Yes. The TFT array substrate 10 is made of, for example, a quartz substrate or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. The TFT array substrate 10 is provided with a pixel electrode 9a, and an alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a. The pixel electrode 9a is made of a transparent conductive thin film such as an ITO (Indium Tin Oxide) film. The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

  On the other hand, a counter electrode (common electrode) 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 that has been subjected to a predetermined alignment process such as a lapping process is provided below it. ing. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

  As shown in FIG. 3, the TFT array substrate 10 is provided with a pixel switching TFT 30 for switching control of each pixel electrode 9a at a position adjacent to each pixel electrode 9a.

  As shown in FIG. 3, the counter substrate 20 is further provided with a second light-shielding film 23 in a region other than the opening region of each pixel. Therefore, incident light does not enter the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 1 from the counter substrate 20 side. Further, the second light shielding film 23 has functions such as improvement of contrast and prevention of color mixture of color materials.

  A sealing material 52 (see FIGS. 18 and 19), which will be described later, is arranged between the TFT array substrate 10 and the counter substrate 20 which are configured in this manner and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other. Liquid crystal is sealed in the enclosed space, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film in a state where an electric field from the pixel electrode 9a is not applied.

  As shown in FIG. 3, a first light-shielding film 11a is provided in a mesh pattern along the pixel between the TFT array substrate 10 and each pixel switching TFT 30 at a position facing each pixel switching TFT 30. Yes. The first light shielding film 11a is preferably made of a simple metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb, which are preferably opaque high melting point metals.

  If composed of such a material, the first light-shielding film 11a is not destroyed or melted by the high-temperature treatment in the process of forming the pixel switching TFT 30 performed after the process of forming the first light-shielding film 11a on the TFT array substrate 10. You can Since the first light-shielding film 11a is formed, the return light from the TFT array substrate 10 side enters the channel region 1a ', the low concentration source region 1b, and the low concentration drain region 1c of the pixel switching TFT 30. This can be prevented, and the characteristics of the pixel switching TFT 30 are not deteriorated by the generation of the photocurrent.

  Further, a first interlayer insulating film 12 is provided between the first light shielding film 11 a and the plurality of pixel switching TFTs 30. The first interlayer insulating film 12 is provided to electrically insulate the semiconductor layer 1a constituting the pixel switching TFT 30 from the first light shielding film 11a. Further, the first interlayer insulating film 12 has a function as a base film for the pixel switching TFT 30 by being formed on the entire surface of the TFT array substrate 10. That is, the TFT array substrate 10 has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness during polishing of the surface of the TFT array substrate 10 and dirt remaining after cleaning. The first interlayer insulating film 12 can also prevent the first light shielding film 11a from contaminating the pixel switching TFT 30 and the like.

  In the present embodiment, the insulating thin film 2 serving as the gate insulating film is extended from a position facing the gate electrode formed of a part of the scanning line 3a and used as a dielectric film, and the semiconductor layer 1a is extended to be the first accumulation. A storage capacitor 70 is formed by using the capacitor electrode 1f and a part of the capacitor line 3b opposite to the capacitor electrode 1f as a second storage capacitor electrode. More specifically, the high-concentration drain region 1e of the semiconductor layer 1a extends below the data line 6a and the scanning line 3a, and an insulating thin film is formed on the capacitor line 3b that extends along the data line 6a and the scanning line 3a. 2 are arranged opposite to each other through a first storage capacitor electrode 1f. In particular, the insulating thin film 2 as a dielectric of the storage capacitor 70 can be a thin and high withstand voltage insulating film in the case of the gate insulating film of the TFT 30 formed on the polysilicon film by high temperature oxidation. It can be configured as a large storage capacity with a relatively small area.

  As a result, the storage capacity of the pixel electrode 9a is effectively utilized by effectively utilizing the space outside the opening area, that is, the area under the data line 6a and the area parallel to the scanning line 3a (that is, the area where the capacitor line 3b is formed). Can be increased.

  Particularly in the present embodiment, the capacitor line 3b and the first light shielding film 11a are electrically connected via the contact hole 13. For this reason, the resistance of the capacitor line 3b can be significantly lowered by the resistance of the first light shielding film 11a. In the present embodiment, the capacitor line 3b is formed of, for example, a polysilicon film having a sheet resistance value of about 25 Ω / □, so that the diagonal of 1.3 inches or 0. In the case of a small liquid crystal device of about 9 inches, it has a resistance of about 100 to 200 KΩ. However, since the first light shielding film 11a is formed of a conductive high melting point metal film, the scanning line in the capacitor line 3b The resistance in the direction along 3a is greatly reduced.

  As a result, the time constant of the capacitor line 3b can also be reduced from, for example, about several tens of microseconds to about several microseconds due to the presence of the first light shielding film 11a. Therefore, the capacitive coupling with the data lines 6a in the capacitive lines 3b crossed under the data lines 6a reduces the occurrence of lateral crosstalk, ghost, etc. due to the fluctuation of the potential of the capacitive line 3b. it can. That is, as shown in FIG. 20, when displaying an image 801 in which a black portion is drawn with high contrast against a gray background, the time point at which an image signal having a partially different voltage to be displayed in black is applied is scanned. Even at the time close to the end of writing for each line, the problem of display deterioration like the image 802 does not occur. In particular, even if the liquid crystal device is configured as a model having a high driving frequency such as XGA or SXGA as described above, the time constant of the capacitance line 3b is sufficiently small. Generation can be reduced.

  Therefore, there is no need to employ a method of inverting the polarity of the liquid crystal drive voltage for each data line 6a or for each pixel as described above in order to prevent such horizontal crosstalk and ghost. A scanning line inversion driving method (so-called 1H inversion driving method) in which the liquid crystal driving voltage is inverted for each scanning line 3a, which can reduce 50 disclinations and increase the pixel aperture ratio, can be employed.

  In the present embodiment, the first light-shielding film 11a (and the capacitor line 3b electrically connected thereto) is electrically connected to a constant potential source, and the first light-shielding film 11a and the capacitor line 3b are set to a constant potential. . Accordingly, it is possible to prevent the potential fluctuation of the first light shielding film 11a from adversely affecting the pixel switching TFT 30 disposed opposite to the first light shielding film 11a. The capacitor line 3b can function well as the second storage capacitor electrode of the storage capacitor 70. In this case, as the constant potential source, a constant potential source such as a negative power source or a positive power source supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, a sampling circuit, or the like) for driving the liquid crystal device. , A ground power source, a constant potential source supplied to the counter electrode 21, and the like. In this way, when the power supply of the peripheral circuit or the like is used, the first light shielding film 11a and the capacitor line 3b can be set to a constant potential without the need to provide a dedicated potential wiring or external circuit connection terminal.

  In FIG. 3, a pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, a scanning line 3a, a channel region 1a 'of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a, and scanning. An insulating thin film 2 that insulates the line 3a from the semiconductor layer 1a, a data line 6a, a low concentration source region 1b and a low concentration drain region 1c of the semiconductor layer 1a, a high concentration source region 1d and a high concentration drain region 1e of the semiconductor layer 1a. I have. In this embodiment, in particular, the data line 6a is composed of a light-shielding thin film such as a metal film such as Al 2 or an alloy film such as metal silicide.

  Further, on the scanning line 3a, the insulating thin film 2 and the first interlayer insulating film 12, a contact hole 5 leading to the high concentration source region 1d and a contact hole 8 leading to the high concentration drain region 1e are respectively formed. An insulating film 4 is formed. The data line 6a is electrically connected to the high concentration source region 1d through the contact hole 5. Further, a third interlayer insulating film 7 is formed on the data line 6 a and the second interlayer insulating film 4. The high concentration drain region 1e is electrically connected to the pixel electrode 9a through the contact hole 8. The pixel electrode 9a and the high concentration drain region 1e may be electrically connected by relaying the same Al film as the data line 6a or the same polysilicon film as the scanning line 3b.

  The pixel switching TFT 30 preferably has an LDD structure as described above, but may have an offset structure in which impurity ions are not implanted into the low concentration source region 1b and the low concentration drain region 1c, and the gate electrode as a mask. It may be a self-aligned TFT in which impurity ions are implanted at a high concentration and high concentration source and drain regions are formed in a self-aligning manner.

  In the present embodiment, a single gate structure in which only one gate electrode composed of a part of the scanning line 3a of the pixel switching TFT 30 is arranged between the source and drain regions is used. However, two or more gate electrodes are interposed between these gate electrodes. May be arranged. At this time, the same signal is applied to each gate electrode. If the TFT is configured with dual gates (double gates) or triple gates or more as described above, the leakage current between the channel and the source / drain region junction can be prevented, and the current during OFF can be reduced. If at least one of these gate electrodes has an LDD structure or an offset structure, the off-current can be further reduced and a stable switching element can be obtained.

  Here, in general, the polysilicon film forming the channel region 1a ′, the low concentration source region 1b, the low concentration drain region 1c, and the like of the semiconductor layer 1a has a photocurrent due to the photoelectric conversion effect of the polysilicon when light is incident thereon. In this embodiment, the data line 6a is formed of a light-shielding metal thin film such as Al so that the scanning line 3a is overlapped from the upper side. Incident light (that is, light from above in FIG. 3) can be effectively prevented from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a. Further, as described above, since the first light-shielding film 11a is provided below the pixel switching TFT 30, the channel region 1a ', the low concentration source region 1b, and the low concentration drain region 1c of at least the semiconductor layer 1a. It is possible to effectively prevent the return light (that is, the light from the lower side in FIG. 3) from entering. Next, the configuration of the peripheral circuit provided on the TFT array substrate 10 in the present embodiment will be described with reference to FIG.

  In FIG. 4, the liquid crystal device includes, as peripheral circuits, a data line driving circuit 101 for driving the data line 6a, a scanning line driving circuit 104 for driving the scanning line 3a, and a precharge signal having a predetermined voltage level on the plurality of data lines 6a. .., Sn before the supply of the image signals S1, S2,..., Sn, and a plurality of image signals S1, S2,. And a sampling circuit 301 for supplying data lines 6a.

  The scanning line drive circuit 104 pulse-sequentially applies scanning signals G1, G2,..., Gm to the scanning line 3a at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY and its inverted clock, and the like. Apply with.

  The data line driving circuit 101 is synchronized with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,..., Gm based on the power supplied from the external control circuit, the reference clock CLX, its inverted clock, and the like. Transfer signals X1, X2,..., Xn from the shift register as sampling circuit drive signals are supplied to the sampling circuit 301 through the sampling circuit drive signal line 306 for each data line 6a.

  The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6a, the precharge signal line 204 is connected to the drain or source of the TFT 202, and the precharge circuit drive signal line 206 is connected to the TFT 202. Connected to the gate electrode. In operation, power of a predetermined voltage necessary for writing a precharge signal (NRS) is supplied from an external power supply via the precharge signal line 204, and each data is supplied via the precharge circuit drive signal line 206. A precharge circuit drive signal (NRG) is supplied from the external control circuit so that the precharge signal (NRS) is written to the line 6a at a timing preceding the supply of the image signals S1, S2,. The precharge circuit 201 preferably supplies a precharge signal (NRS) (image auxiliary signal) corresponding to the image signals S1, S2,.

  The sampling circuit 301 includes a TFT 302 for each data line 6a, an image signal line 304 is connected to the drain or source electrode of the TFT 302, and a sampling circuit drive signal line 306 is connected to the gate electrode of the TFT 302. . When the image signals S1, S2,..., Sn are input via the image signal line 304, they are sampled. That is, when transfer signals X1, X2,..., Xn as sampling circuit drive signals are input from the data line drive circuit 101 via the sampling circuit drive signal line 306, the image signals S1, S2 from the image signal lines 304 respectively. ,..., Sn are sequentially applied to the data line 6a.

  As described above, in the present embodiment, the data lines 6a are selected for each line. However, the data lines 6a may be selected for a plurality of lines and simultaneously selected. For example, the image signals S 1, S 2, serial-parallel converted into a plurality of phases (for example, 3 phase, 6 phase, 12 phase,...) According to the writing characteristics of the TFT 302 constituting the sampling circuit 301 and the frequency of the image signal. ..., Sn may be supplied from the image signal line 304, and these may be sampled simultaneously for each group. In this case, it goes without saying that at least the number of image signal lines 304 is required for the number of serial-parallel conversions.

  Here, the precharge performed in the liquid crystal device of the present embodiment will be described with reference to FIG.

  As shown in FIG. 5, a clock signal (CLX) that defines a selection time t1 per pixel is input to the shift register of the data line driving circuit 101 as a reference for horizontal scanning, but a transfer start signal (DX ) Is input, transfer signals X1, X2,... Are sequentially supplied from the shift register. In each horizontal scanning period, the precharge circuit drive signal (NRG) is supplied to the precharge circuit 201 at a timing preceding the input of the transfer start signal (DX). More specifically, the clock signal (CLY) used as a reference for vertical scanning becomes a high level and the polarity of the image signal (VID) is inverted with respect to the voltage center value (VID center) of the signal. The precharge circuit drive signal (NRG) is set to the high level after elapse of time t3, which is a margin from precharge to precharge. On the other hand, the precharge signal (NRS) is set to a predetermined level having the same polarity as the image signal (VID) in the horizontal blanking period, corresponding to the inversion of the image signal (VID). Accordingly, precharge is performed at time t2 when the precharge circuit drive signal (NRG) is set to the high level. The precharge circuit is driven by a time t4 before the time when the horizontal blanking period ends and the effective display period starts, that is, a time period from the end of the precharge to the time when the image signal is written. The signal (NRG) is at a low level. As described above, the precharge circuit 201 supplies the precharge signal (NRS) to the plurality of data lines 6a prior to the image signal in each horizontal blanking period.

  In FIG. 5, the precharge is performed within the horizontal blanking period, but the fluctuation of the potential of the capacitive line 3b due to the capacitive coupling between the data line 6a and the capacitive line 3b described above becomes stable within the time t5. Therefore, if the timing of each signal is set so that the time t5 becomes longer, it can be considered that such potential fluctuation of the capacitance line 3b can be prevented. However, if this time t5 is made longer, then it becomes necessary to shorten the times t3, t2, and t4. Here, if the time t3 is made too short, the gate of the TFT 30 related to the preceding scanning line is turned on when the precharge circuit drive signal (NRG) becomes high level due to the gate delay of the TFT constituting the precharge circuit. Danger comes out. Further, if the time t2 is shortened, the precharge capability is lowered or a precharge circuit having a high charge supply capability is required. Furthermore, if the time t4 is shortened, the precharge signal and the image signal may be simultaneously applied to the data line 6a. Therefore, in order to satisfactorily precharge, it is not possible to easily increase the time t5 during the period (34) when stabilizing the potential fluctuation of the capacitive line 3b due to capacitive coupling. However, according to the present embodiment, the first light-shielding film 11a significantly lowers the resistance of the capacitance line 3b and greatly reduces the time constant, so that the time t5 relative to the time constant of the capacitance line 3b can be made relatively long. It can be done.

  Even when precharging is performed in this manner, in this embodiment, the horizontal blanking period for precharging is ensured for a sufficient length, and the fluctuation of the potential of the capacitive line 3b due to capacitive coupling is stabilized. The time t5 can be substantially sufficiently secured. As a result of the above, according to the present embodiment, even when the driving frequency is high, precharge and the above-described scanning line inversion driving can be performed satisfactorily, and lateral crosstalk, ghost, and the like due to capacitive coupling can be prevented. An extremely high quality image can be displayed.

  In addition to the above, according to the present embodiment, a redundant structure is realized in which the first light-shielding film 11a replaces the capacitor line 3b even if the capacitor line 3b is disconnected in the middle due to foreign matters or the like. That is, even if the capacitor line 3b is disconnected in the middle, there is no practical problem if both sides of the disconnected part are electrically connected to each other by the first light shielding film 11a via the contact hole 13. Therefore, according to the present embodiment, a liquid crystal device capable of displaying a high-quality image with a low defective product rate and high reliability can be realized.

  The capacitor line 3b and the scanning line 3a are made of the same polysilicon film, and the dielectric film of the storage capacitor 70 and the insulating thin film 2 that becomes the gate insulating film of the TFT 30 include the same high-temperature oxide film. The one storage capacitor electrode 1f, the channel region 1a ', the high concentration source region 1d, the high concentration drain region 1e, etc. of the TFT 30 are made of the same semiconductor layer 1a. For this reason, the laminated structure formed on the TFT array substrate 10 can be simplified. Further, in the liquid crystal device manufacturing method described later, the capacitor line 3b and the scanning line 3a can be simultaneously formed in the same thin film forming step, and the storage capacitor 70 dielectric films and insulating thin film 2 can be formed simultaneously.

  In the present embodiment, in particular, the capacitor line 3b and the first light shielding film 11a are electrically connected to each other reliably and with high reliability through the contact hole 13 formed in the first interlayer insulating film 12. However, such a contact hole 13 may be opened for each pixel or may be opened for each pixel group including a plurality of pixels.

  When the contact hole 13 is opened for each pixel, the resistance of the capacitor line 3b can be reduced by the first light shielding film 11a, and the degree of redundant structure between the two can be increased. On the other hand, when the contact hole 13 is opened for each pixel group composed of a plurality of pixels (for example, every two pixels or every three pixels), the sheet resistance, the driving frequency of the capacitor line 3b and the first light shielding film 11a, While taking into account the required specifications, etc., the benefits of the low resistance and redundant structure of the capacitor line 3b by the first light-shielding film 11a and the complicated manufacturing process by opening a large number of contact holes 13 or the liquid crystal device Since it is possible to properly balance the adverse effects such as the deterioration of the quality, it is very advantageous in practice.

  In this embodiment, in particular, the contact hole 13 provided for each pixel or each pixel group is opened under the data line 6a when viewed from the counter substrate 20 side. For this reason, the contact hole 13 is located outside the pixel opening region and is provided in the portion of the first interlayer insulating film 12 where the TFT 30 and the first storage capacitor electrode 1f are not formed. Thus, it is possible to prevent the TFT 30 and other wirings from being defective due to the formation of the contact hole 13.

  Next, a manufacturing process of the first embodiment of the liquid crystal device having the above configuration will be described with reference to FIGS. 6 to 9 are process diagrams showing each layer on the TFT array substrate side in each process corresponding to the AA ′ cross section of FIG. 2 as in FIG.

  As shown in step (1) in FIG. 6, a TFT array substrate 10 such as a quartz substrate, a hard glass substrate, or a silicon substrate is prepared. Here, the annealing is preferably performed in an inert gas atmosphere such as N 2 (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pre-processing is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process performed later. Keep it. That is, the TFT array substrate 10 is heat-treated in advance at the same temperature or higher in accordance with the temperature at which the high temperature treatment is performed at the maximum temperature in the manufacturing process.

  A metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal silicide is sputtered on the entire surface of the TFT array substrate 10 thus processed, and a film thickness of about 100 to 500 nm, preferably Forms a light-shielding film 11 having a thickness of about 200 nm.

  Subsequently, the first light shielding film 11a is formed by etching the light shielding film 11 as shown in step (2).

  Next, as shown in step (3), TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatrate) is formed on the first light shielding film 11a by, for example, atmospheric pressure or low pressure CVD. ) Gas, TMOP (tetra-methyl oxy-phosphate) gas, etc., NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), etc. A first interlayer insulating film 12 made of a silicate glass film, a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the first interlayer insulating film 12 is, for example, about 500 to 2000 nm.

  Next, as shown in step (4), a monosilane gas having a flow rate of about 400 to 600 cc / min on the first interlayer insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C., An amorphous silicon film is formed by low pressure CVD using disilane gas or the like (for example, CVD at a pressure of about 20 to 40 Pa). Thereafter, an annealing process is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the polysilicon film 1 has a thickness of about 50 to 200 nm, preferably Is solid phase grown to a thickness of about 100 nm.

  At this time, when an n-channel type pixel switching TFT 30 is formed as the pixel switching TFT 30 shown in FIG. 3, Vb such as Sb (antimony), As (arsenic), P (phosphorus), etc. is formed in the channel region. The impurity ions of group elements may be slightly doped by ion injection or the like. When the pixel switching TFT 30 is a p-channel type, a group III element impurity ion such as B (boron), Ga (gallium), or In (indium) may be slightly doped by ion implantation or the like. . Note that the polysilicon film 1 may be formed directly by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into a polysilicon film deposited by a low pressure CVD method or the like to make it amorphous (amorphized) and then recrystallizing it by annealing or the like. Next, as shown in step (5), a semiconductor layer 1a having a predetermined pattern as shown in FIG. 2 is formed. That is, in particular, in the region where the capacitor line 3b is formed under the data line 6a and the region where the capacitor line 3b is formed along the scanning line 3a, the first layer extending from the semiconductor layer 1a constituting the pixel switching TFT 30 is provided. One storage capacitor electrode 1f is formed.

  Next, as shown in step (6), by thermally oxidizing the first storage capacitor electrode 1f together with the semiconductor layer 1a constituting the pixel switching TFT 30 at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C. A relatively thin thermal oxide silicon film of about 30 nm is formed, and a high temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin thickness of about 50 nm by a low pressure CVD method or the like. An insulating thin film 2 that forms a dielectric film for forming a capacitor is formed together with the gate insulating film of the pixel switching TFT 30 having the structure (see FIG. 3). As a result, the semiconductor layer 1a and the first storage capacitor electrode 1f have a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating thin film 2 has a thickness of about 20 to 150 nm. The thickness is preferably about 30 to 100 nm. By shortening the high-temperature thermal oxidation time in this way, it is possible to prevent warping due to heat, particularly when using a large substrate of about 8 inches. However, the insulating thin film 2 having a single layer structure may be formed only by thermally oxidizing the polysilicon film 1.

Although not particularly limited in the step (6), the semiconductor layer portion to be the first storage capacitor electrode 1f is doped with, for example, P ions at a dose of about 3 × 10 ¹² / cm ² to reduce the resistance. Also good.

  Next, in step (7), a contact hole 13 reaching the first light shielding film 11a is formed in the first interlayer insulating film 12 by dry etching such as reactive ion etching, reactive ion beam etching, or wet etching. At this time, opening the contact hole 13 or the like by anisotropic etching such as reactive ion etching or reactive ion beam etching has an advantage that the opening shape can be made substantially the same as the mask shape. However, if a hole is formed by combining dry etching and wet etching, these contact holes 13 and the like can be tapered, so that an advantage of preventing disconnection at the time of wiring connection can be obtained.

  Next, as shown in step (8), after depositing the polysilicon film 3 by a low pressure CVD method or the like, P 2 is thermally diffused to make the polysilicon film 3 conductive. Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used.

  Next, as shown in step (9) of FIG. 7, the capacitor line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. The film thickness of the scanning line 3a and the capacitance line 3b is, for example, about 350 nm.

Next, as shown in step (10), when the pixel switching TFT 30 shown in FIG. 3 is an n-channel TFT having an LDD structure, the low concentration source region 1b and the low concentration drain region are first formed in the semiconductor layer 1a. In order to form 1c, impurity ions 60 of a V group element such as P or the like are used at a low concentration (for example, P ions of 1 to 3 × 10 ¹³ / cm 2) using a gate electrode serving as a part of the scanning line 3a as a diffusion mask. Dope with a dose of ² ). As a result, the semiconductor layer 1a under the scanning line 3a becomes a channel region 1a '. Due to the doping of the impurity ions, the capacitance line 3b and the scanning line 3a are also reduced in resistance.

Subsequently, as shown in step (11), in order to form the high-concentration source region 1d and the high-concentration drain region 1e constituting the pixel switching TFT 30 1, the resist layer 62 is formed with a mask wider than the scanning line 3 a. After the formation on the scanning line 3a, the impurity ions 61 of the V group element such as P are similarly doped at a high concentration (for example, P ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² ). Further, when the pixel switching TFT 30 is of a p-channel type, in order to form the low concentration source region 1b and the low concentration drain region 1c and the high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, B ( Doping using impurity ions of group III elements such as boron. For example, an TFT having an offset structure may be used without doping with low-concentration impurity ions, and an ion implantation technique using P ions, B ions, or the like using a gate electrode which is a part of the scanning line 3a as a mask. Thus, a self-aligned TFT may be used.

  The resistance of the capacitor line 3b and the scanning line 3a is further reduced by doping the impurities.

  Further, by repeating the step (10) and the step (11) again and performing impurity ions of group III elements such as B ions, a p-channel TFT can be formed. As a result, the data line driving circuit 101 and the scanning line driving circuit 104 having a complementary structure composed of n-channel TFTs and p-channel TFTs can be formed on the periphery of the TFT array substrate 10. Thus, if the semiconductor layer 1a constituting the pixel switching TFT 30 is formed of a polysilicon film, the data line driving circuit 101 and the scanning line driving circuit 104 are formed in substantially the same process when the pixel switching TFT 30 is formed. This is advantageous in manufacturing.

  Next, as shown in step (12), NSG, PSG, BSG, and the like using, for example, atmospheric pressure or reduced pressure CVD, TEOS gas, or the like so as to cover the capacitor line 3b together with the scanning line 3a in the pixel switching TFT 30. A second interlayer insulating film 4 made of a silicate glass film such as BPSG, a silicon nitride film or a silicon oxide film is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm.

  Next, in step (13), annealing is performed at about 1000 ° C. for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e, and then the contact hole 5 for the data line 6a is formed. It is formed by dry etching such as reactive ion etching or reactive ion beam etching or by wet etching. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.

  Next, as shown in step (14) of FIG. 8, a light-shielding low-resistance metal such as A1 or a metal silicide or the like is formed on the second interlayer insulating film 4 by sputtering or the like as a metal film 6. A data line 6a is formed by a photolithography process, an etching process, etc., as shown in step (15), with a thickness of 500 nm, preferably about 300 nm.

  Next, as shown in the step (16), a silicate glass film such as NSG, PSG, BSG, BPSG, etc. is used to cover the data line 6a by using, for example, atmospheric pressure or reduced pressure CVD or TEOS gas. A third interlayer insulating film 7 made of a silicon film, a silicon oxide film or the like is formed. The thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm.

  Next, in the step (17) of FIG. 9, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high-concentration drain region 1e is formed by reactive ion etching or reactive ion beam etching. It is formed by dry etching.

  Next, as shown in step (18), a transparent conductive thin film 9 such as an ITO film is deposited on the third interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm, and further in the step (18). 19), the pixel electrode 9a is formed. When the liquid crystal device is used for a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

  Subsequently, after applying a polyimide-based alignment film coating solution on the pixel electrode 9a, the alignment film 16 is rubbed in a predetermined direction so as to have a predetermined pretilt angle (see FIG. 3). Is formed. On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate or the like is first prepared, and the second light shielding film 23 and a third light shielding film (see FIGS. 18 and 19), which will be described later, are made of, for example, metallic chromium. After sputtering, it is formed through a photolithography process and an etching process. These second light-shielding films may be formed of a metal material such as Cr, Ni (nickel), and Al, or a material such as resin black in which carbon or Ti is dispersed in a photoresist.

  Thereafter, a transparent conductive thin film such as ITO is deposited on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 50 to 200 nm to form the counter electrode 21. Further, after applying a polyimide-based alignment film coating solution over the entire surface of the counter electrode 21, the alignment film 22 (see FIG. 3) is formed by performing a rubbing process so as to have a predetermined pretilt angle and in a predetermined direction. It is formed.

  Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together by the sealing material 52 so that the alignment films 16 and 22 face each other, and the space between the two substrates is obtained by vacuum suction or the like. In addition, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked to form a liquid crystal layer 50 having a predetermined thickness.

[Embodiment 2]
A second embodiment of the liquid crystal device according to the present invention will be described with reference to FIG.

  In the first embodiment described above, the first light-shielding film 11a is provided in a mesh pattern along the pixels, whereby the resistance of the capacitor line 3b can be reduced and the degree of the redundant structure is further increased. In the embodiment, the first light shielding film 11a is provided in a stripe shape (stripe shape). Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same components in the drawing, and descriptions thereof are omitted. FIG. 10 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed.

  In FIG. 10, the first light-shielding film 11a is composed of a plurality of striped (stripe-shaped) portions extending along the scanning line 3a. That is, the first light shielding film 11a is divided at a predetermined region facing the data line 6a. Accordingly, it is possible to promote a reduction in resistance of the capacitor line 3b electrically connected to the first light shielding film 11a, particularly in the direction along the scanning line 3a. In addition, the degree of redundant structure between the capacitor line 3b and the first light shielding film 11a can be increased.

  As a modification of the second embodiment, the first light-shielding film 11a is further provided in stripes at positions where the scanning line 3a and the capacitor line 3b overlap each other when viewed from the TFT array substrate 10 side, and the scanning line 3a A plurality of striped portions arranged along the line may be electrically connected to each other via the capacitor line 3b. Even with this configuration, the resistance of the capacitor line 3b can be reduced, and the degree of the redundant structure can be increased.

[Embodiment 3]
A third embodiment of the liquid crystal device according to the present invention will be described with reference to FIG.
In the first embodiment described above, the first light-shielding film 11a is provided in a mesh shape (lattice shape), whereby the resistance of the capacitor line 3b can be reduced and the degree of the redundant structure is further increased. In the embodiment, the first light-shielding film 11a is provided in a striped pattern and is not formed at a position facing the scanning line 3a except for a position covering the channel region 1a ′. Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same components in the drawing, and descriptions thereof are omitted. FIG. 12 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed.

  As shown in FIG. 11, first light-shielding films 11a are provided between the TFT array substrate 10 and the pixel switching TFTs 30 at positions facing the pixel switching TFTs 30, respectively.

  As shown in FIG. 11, in the present embodiment, the first light shielding film 11a is electrically connected to the capacitor line 3b provided in the adjacent preceding stage or subsequent stage via the contact hole 13. Therefore, compared with the case where each first light shielding film 11a is electrically connected to its own capacity line, the capacitor line 3b and the first light shielding are superimposed on the data line 6a along the edge of the opening region of the pixel portion. There are few steps with respect to the other area | region where the film | membrane 11a is formed. Thus, if there are few steps along the edge of the opening area of the pixel portion, the liquid crystal disclination (alignment failure) caused by the step can be reduced, so that the opening area of the pixel portion can be widened. Become.

  Further, as described above, the first light shielding film 11a has the contact hole 13 formed in the protruding portion protruding from the main line portion extending linearly. Here, the inventors of the present application have found that cracks are less likely to occur in the contact hole 13 due to the reason that stress is dissipated from the edge as it is closer to the edge. Therefore, in this case, depending on how close to the tip of the protruding portion the contact hole 13 is opened (preferably, depending on whether the contact hole 13 is close to the tip of the margin), the first light-shielding film 11a is formed during the manufacturing process. Such stress is relieved, cracks can be prevented more effectively, and the yield can be improved.

  Further, particularly in the present embodiment, the first light shielding film 11a is not formed at a position facing the scanning line 3a except for a position covering the channel region 1a ′. Accordingly, since there is practically no or no capacitive coupling between the first light shielding film 11a and each scanning line 3a, potential fluctuations in the first light shielding film 11a are caused by potential fluctuations in the scanning line 3a. As a result, there is no potential fluctuation in the capacitance line 3b.

  In the third embodiment, since the capacitor line 3b provided in the adjacent upstream or downstream pixel is connected to the first light shielding film 11a, the first light shielding is applied to the uppermost or lowermost pixel. The capacitor line 3b for supplying a constant potential to the film 11a is required. Therefore, it is preferable to provide one extra capacity line 3b with respect to the number of vertical pixels.

  In FIG. 11, the straight main line portion of the first light shielding film 11a is formed so as to substantially overlap the linear main line portion of the capacitor line 3b, but the first light shielding film 11a is formed in the channel of the TFT 30. If it is provided at a position that covers the region and overlaps with the capacitor line 3b at any point so that the contact hole 13 can be formed, the light shielding function for the TFT and the resistance reducing function for the capacitor line 3b can be exhibited. It is.

  Therefore, for example, the first light-shielding film 11a is provided even in a longitudinal gap region along the scanning line 3a between the adjacent scanning line 3a and the capacitance line 3b or a position slightly overlapping with the scanning line 3a. May be.

[Embodiment 4]
A fourth embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. In the first to third embodiments described above, the main line portion along the scanning line 3a and the capacitor line 3b in the first light shielding film 11a is formed substantially below the capacitor line 3b. In the sixth embodiment, Thus, the main line portion along the scanning line 3a and the capacitor line 3b is formed in a striped shape under the scanning line 3a and is not formed under the capacitor line 3b. Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same components in the drawing, and descriptions thereof are omitted. FIG. 12 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed.

  In FIG. 12, particularly in the liquid crystal device, the main line portion extending along the scanning line 3a of the striped first light shielding film 11a is disposed below the scanning line 3a. That is, the scanning line 3a is formed on the first light shielding film 11a in the main line portion via a first interlayer insulating film that is much thicker than the gate insulating film constituting the TFT in the pixel portion, for example. For this reason, even if an abnormally shaped portion such as an unintended projection in the manufacturing process is formed on the first light shielding film 11a, the projection or the like breaks through the first interlayer insulating film, whereby the first light shielding film 11a is formed. The possibility of shorting with the scanning line 3a can be extremely reduced.

  In the case where the semiconductor layer 1a, the insulating thin film 2 and the capacitor line 3b are further stacked on the protrusions formed on the first light shielding film 11a as in the first to third embodiments described above (FIG. 3). In consideration of the fact that this projection or the like breaks through the very thin insulating thin film 2 through the semiconductor layer 1a to increase the possibility that the semiconductor layer 1a and the capacitor line 3b are short-circuited. The configuration in which the first light-shielding film 11a is formed at a position facing 3a is more advantageous in improving the process yield.

  Therefore, from the viewpoint of improving the yield as described above, the region on the substrate where the first light shielding film 11a and the capacitor line 3b are opposed to each other is made as small as possible, and the first light shielding film 11a and the scanning line 3a are It is desirable to enlarge the regions on the substrate formed to face each other as much as possible. For this reason, in the fourth embodiment, as shown in FIG. 12, the minimum area required for electrically connecting the first light-shielding film 11a and the capacitor line 3b through the contact hole 13 and the channel area of the TFT 30 (in the figure, right In a region excluding the minimum necessary region for shielding light from the lower shaded portion), the first light shielding film 11a is disposed opposite to the scanning line 3a without being disposed opposite to the capacitor line 3b.

  As a result, according to the fourth embodiment, even if the first light-shielding film 11a is used to reduce the resistance of the capacitor line 3b, the capacitor line 3b and the semiconductor layer 1a disposed opposite to each other with the extremely thin insulating thin film 2 interposed therebetween. In practice, there is little or no possibility of short-circuiting, and ultimately the yield of the liquid crystal device can be improved.

[Embodiment 5]
A fifth embodiment of the liquid crystal device according to the present invention will be described with reference to FIG.
In the first to fourth embodiments described above, the contact hole 13 for electrically connecting the capacitor line 3b and the first light shielding film 11a has a quadrangular planar shape. In the fifth embodiment, this contact hole 13 has a rectangular shape. The planar shape of the hole is a circle such as a perfect circle or an ellipse. The other configurations are the same as those in the first to fourth embodiments. In this embodiment, the shape of the contact hole 13 in the third embodiment is modified, and the same components in the drawing are used. Are given the same reference numerals and their description is omitted. FIG. 13 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed.

  In FIG. 13, the contact hole 13 for electrically connecting the capacitor line 3b and the first light-shielding film 11a is configured so that the planar shape parallel to the substrate is circular. With this configuration, when a wet etching process is used in the manufacturing process to open the contact hole 13, the etching solution enters the interface between the first light shielding film 11 a and the first interlayer insulating film 12, The possibility of generating cracks can be reduced. That is, as in the third embodiment, if the contact hole 13 having a square portion such as a square shape is to be opened by wet etching, the etching solution is particularly likely to enter the corner portion and stress concentration also occurs. Therefore, cracks are likely to occur in the first light shielding film 11a and the like at this corner.

  On the other hand, when the contact hole 13 in the first embodiment is opened by the dry etching process, the very thin first contact hole 13 is formed due to the selection ratio between the first interlayer insulating film 12 and the first light shielding film 11a. 1 There is a high possibility that etching will penetrate through the light shielding film 11a. For this reason, the wet etching process using the circular contact hole 13 'as in the present embodiment is very advantageous in practice from the viewpoint of preventing penetration and cracking.

  As a result, according to the third embodiment, the reliability of the wiring near the contact hole can be improved, and the yield of the liquid crystal device can be improved. In addition, the shape of the contact hole of the present embodiment is modified from the shape of the contact hole of the configuration of the third embodiment as an example, but the present embodiment is different from the first embodiment, the second embodiment, and the fourth embodiment. Is also applicable.

[Embodiment 6]
A sixth embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. In the first and fifth embodiments described above, the first light-shielding film 11a is electrically connected to the previous-stage or rear-stage capacitor line 3b via the contact hole 13 or 13 '. The membrane is electrically connected to its own capacity line. Since other configurations are the same as those in the fifth embodiment, the same reference numerals are given to the same components in the drawing, and descriptions thereof are omitted. FIG. 14 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films, and the like are formed.

  In FIG. 14, the first light-shielding film 11a is provided at a position where the TFT including the channel region of the semiconductor layer 1a is covered in the pixel portion when viewed from the TFT array substrate side, and the linear main line of the capacitor line 3b. A main line portion extending linearly along the scanning line 3a facing the portion, and a projecting portion protruding from the portion intersecting the data line 6a along the data line 6a to the next stage side (ie, downward in the figure), And a projecting portion projecting forward from the portion intersecting with the data line 6a along the data line 6a (that is, upward in the drawing).

  The downward projecting portion of the first light shielding film 11 a covers the channel region and further extends downward to a position covering the contact hole 5. On the other hand, the upward projecting portion of the first light shielding film 11a is overlaid on the upward projecting portion of the capacitor line 3b below the data line 6a, and the first light shielding film 11a and the capacitor line 3b are near the tip of the overlap. A circular contact hole 13 ′ is provided to electrically connect the two. In other words, in the present embodiment, the first light-shielding film 11a in each stage (that is, the row of each pixel) is electrically connected to the capacitor line 3b in its own stage through the contact hole 13 ′.

  If configured in this manner, the level difference between the TFT 30, the capacitor line 3 b, and the first light-shielding film 11 a over the data line 6 a increases with respect to other regions, but the capacitor line 3 b and the first line can be relatively easily formed. It is possible to electrically connect the light shielding film 11a.

  Furthermore, with this configuration, the upward projecting portion of the first light shielding film 11a overlaps the first storage capacitor electrode 1f, so that the first storage capacitor electrode as the third storage capacitor electrode is utilized using the space below the data line 6a. There is also an advantage that the storage capacitor 70 formed between the light shielding film 11a and the first storage capacitor electrode 1f can be increased.

  In this embodiment as well, as in the case of the third embodiment, the contact hole may be square and the capacitor line of the own stage may be electrically connected to the light shielding film. In the third embodiment, since the capacitor line 3b provided in the pixel of the own stage and the first light shielding film 11a are connected, it is not necessary to provide an extra capacitor line 3b in the uppermost pixel or the lowermost pixel. This is advantageous.

[Embodiment 7]
A seventh embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. In the third or fourth embodiment described above, the first light shielding film 11a is formed along the scanning line 3a or the capacitor line 3b. However, in the present embodiment, the first light shielding film 11a is formed so as to cover the data line 6a. . In the drawings, the same components are denoted by the same reference numerals, and description thereof is omitted. FIG. 15 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films and the like are formed.

  As shown in FIG. 15, the first light shielding film 11a is connected through the contact hole 13 '. According to such a configuration, the distance from the first light shielding film 11a to the contact hole 8 for connecting the pixel electrode 9a and the semiconductor film 1a can be increased, so that the metal film forming the first light shielding film 11a can be formed. It is possible to prevent the capacitor line 3b and the semiconductor 1a from being short-circuited by the stress and becoming a point defect. The first light shielding film 11a may be fixed at a potential by connecting it to a constant potential line around the pixel region.

[Embodiment 8]
In the first to seventh embodiments described above, any flattening process is applied to the steps with respect to other regions in the stacked region in which the TFT 30, the scanning line 3 a, the capacitor line 3 b, the data line 6 a and the like are formed. However, in the eighth embodiment, the planarization process is performed by forming the first interlayer insulating film 12 in a concave shape. Since other configurations are the same as those in the first to seventh embodiments, the same reference numerals are given to the same components in the drawings, and description thereof will be omitted. FIG. 16 is a cross-sectional view taken along the line AA ′ of FIG. That is, the plan view of the liquid crystal device of the eighth embodiment is the same as that of the first to seventh embodiments.

  In FIG. 16, the first interlayer insulating film 12 ′ is formed such that portions facing the TFT 30, the data line 6 a, the scanning line 3 a, and the capacitor line 3 b are recessed in a concave shape. As a result, the side of the third interlayer insulating film 7 facing the liquid crystal layer 50 is flattened. Therefore, according to the fourth embodiment, since the side facing the liquid crystal layer 50 of the third interlayer insulating film 7 is flattened, depending on the unevenness of the surface of the third interlayer insulating film 7 according to the degree of the flattening. The disclination (orientation failure) of the liquid crystal caused can be reduced. As a result, according to the eighth embodiment, higher-quality image display can be performed, and the opening area of the pixel portion can be widened.

  As a method of forming the first interlayer insulating film 12 'in this way, the first interlayer insulating film 12 has a two-layer structure, a thin portion consisting of only one layer is used as a concave hollow portion, and a thick portion of two layers is formed into a concave shape. Thin film formation and etching may be performed so as to form the bank portion. Alternatively, the first interlayer insulating film 12 ′ may have a single layer structure, and a concave recess may be opened by etching. In these cases, when dry etching such as reactive ion etching or reactive ion beam etching is used, there is an advantage that a concave portion can be formed as designed. On the other hand, when wet etching is used alone or in combination with dry etching, the sidewall surface of the concave recess can be formed in a tapered shape as shown in FIG. Since the remaining of the polysilicon film, resist, etc. formed around the side wall can be reduced, there is an advantage that the yield is not lowered. A groove may be formed in the TFT array substrate 10, and wirings and TFTs 30 may be formed in the groove region and planarized.

  In the present embodiment, since the first interlayer insulating film 12 'is thin even in the portion where the first light-shielding film 11a is opposed to the first storage capacitor electrode 1f as the third storage capacitor electrode, the storage capacitor 70 1 in this portion is thin. Increased benefits are also obtained. Note that the planarization technique in the eighth embodiment as described above can be applied to any of the first to seventh embodiments.

[Embodiment 9]
A ninth embodiment of a liquid crystal device according to the present invention will be described with reference to FIG.
In the above-described eighth embodiment, the planarization process is performed by forming a concave recess in the first interlayer insulating film 12. However, in the ninth embodiment, the third interlayer insulating film is formed in a concave shape. Such a flattening process is performed. Since other configurations are the same as those in the first to eighth embodiments, the same reference numerals are given to the same components in the drawings, and description thereof will be omitted. FIG. 17 is a cross-sectional view corresponding to the cross section AA ′ of FIG. That is, the plan view of the liquid crystal device of the eighth embodiment is the same as that of the first to seventh embodiments.

  In FIG. 17, the third interlayer insulating film 7 ′ is formed such that portions facing the TFT 30, the data line 6 a, the scanning line 3 a, and the capacitor line 3 b are recessed in a concave shape. More specifically, a CMP (Chemical Mechanical Polishing) process is performed on the upper surface of the third interlayer insulating film 7 ′. As a result, the side of the third interlayer insulating film 7 'facing the liquid crystal layer 50 is flattened. Therefore, according to the fifth embodiment, it is possible to reduce the liquid crystal disclination (alignment failure) caused by the unevenness of the surface of the third interlayer insulating film 7 ′ according to the degree of planarization. As a result, according to the fifth embodiment, higher-quality image display can be performed, and the opening area of the pixel portion can be widened.

  In addition to such CMP treatment, SOG (spin-on glass) may be formed by spin coating or the like to planarize the upper surface of the third interlayer insulating film 7 ′.

  Furthermore, in the above-described eighth and ninth embodiments, the concave portions are formed in the first and third interlayer insulating films, respectively, but the concave portions may be formed in the second interlayer insulating film, and May combine these.

  In addition to these, the concave portion formed in the first, second, or third interlayer insulating film is not a portion facing the TFT 30, the data line 6a, the scanning line 3a, and the capacitor line 3b, but a concave portion. At least a portion facing the data line 6a having the largest total film thickness when any flattening process is not performed, so that the flattening process as in the eighth or ninth embodiment is performed. Also good. The planarization technique in the eighth and ninth embodiments as described above can be applied to any of the first to seventh embodiments.

(Overall configuration of liquid crystal device)
The overall configuration of each embodiment of the liquid crystal device configured as described above will be described with reference to FIGS. 18 is a plan view of the TFT array substrate 10 as viewed from the side of the counter substrate 20 together with the components formed thereon. FIG. 19 is a plan view of the TFT array substrate 10 including the counter substrate 20 shown in FIG. It is H 'sectional drawing.

  In FIG. 18, a sealing material 52 is provided on the TFT array substrate 10 along its edge, and in parallel with the inner side, for example, as a frame made of the same or different material as the second light shielding film 23. A third light shielding film 53 is provided. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 has two sides adjacent to the one side. It is provided along. Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuit 101 may be arranged on both sides along the side of the image display area. For example, the odd-numbered data lines 6a supply an image signal from a data line driving circuit arranged along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. Alternatively, an image signal may be supplied from a data line driving circuit arranged in this manner. If the data lines 6a are driven in a comb-like shape in this way, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be configured. Further, a plurality of wirings 105 are provided on the remaining side of the TFT array substrate 10 to connect between the scanning line driving circuits 104 provided on both sides of the image display area. Further, the third light shielding film 53 as a frame is provided. Alternatively, a precharge circuit 201 (see FIG. 4) may be provided behind. Further, at least one corner of the counter substrate 20 is provided with a conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20. Then, as shown in FIG. 19, the counter substrate 20 having substantially the same outline as the sealing material 52 shown in FIG. 18 is fixed to the TFT array substrate 10 by the sealing material 52.

  On the TFT array substrate 10 of the liquid crystal device in each of the embodiments described with reference to FIGS. 1 to 19 above, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during production or at the time of shipment. May be formed. Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate is connected to the peripheral portion of the TFT array substrate 10. You may make it connect electrically and mechanically through the anisotropic conductive film provided in this. Further, for example, a TN (Twisted Nematic) mode, a VA (Vertical Aligned) mode, and a PDLC (Polymer Dipersed Liquid Crystal) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the emission light of the TFT array substrate 10 exits. A polarizing film, a retardation film, a polarizing means, and the like are arranged in a predetermined direction according to an operation mode such as a mode, and a normally white mode / normally black mode.

  Since the liquid crystal device in each of the embodiments described above is applied to a color liquid crystal projector (projection type display device), three liquid crystal devices are used as RGB light valves, and each light valve has an RGB color. The light of each color decomposed through the decomposition dichroic mirror is incident as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the counter substrate 20 together with the protective film in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed. In this way, the liquid crystal device according to each embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflective type color liquid crystal television other than the liquid crystal projector. Further, a microlens may be formed on the counter substrate 20 so as to correspond to one pixel. In this way, a bright liquid crystal device can be realized by improving the collection efficiency of incident light. Furthermore, a dichroic filter that produces RGB colors by using interference of light may be formed by depositing several layers of interference layers having different refractive indexes on the counter substrate 20. According to this counter substrate with a dichroic filter, a brighter color liquid crystal device can be realized.

  In the liquid crystal device in each of the embodiments described above, incident light is incident from the counter substrate 20 side as in the prior art. However, since the first light shielding film 11a is provided, the incident light is incident from the TFT array substrate 10 side. Light may be incident and emitted from the counter substrate 20 side. That is, even when the liquid crystal device is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a. An image can be displayed. Here, conventionally, in order to prevent reflection on the back side of the TFT array substrate 10, it is necessary to separately arrange an anti-reflection (AR) anti-reflection (polarization means) or affix an AR film. there were. However, in each embodiment, the first light-shielding film 11a is formed between the surface of the TFT array substrate 10 and at least the channel region 1a ′ and the low concentration source region 1b and the low concentration drain region 1c of the semiconductor layer 1a. There is no need to use such AR-coated polarizing means or AR film, or to use an AR-treated substrate of the TFT array substrate 10 itself. Therefore, according to each embodiment, the material cost can be reduced, and it is very advantageous that the yield is not lowered due to dust, scratches, or the like when the polarizing means is attached. In addition, since the light resistance is excellent, even when a bright light source is used or polarization conversion is performed by a polarization beam splitter to improve light use efficiency, image quality degradation such as crosstalk due to light does not occur.

  In addition, the switching element provided in each pixel has been described as a positive stagger type or coplanar type polysilicon TFT, but other types of TFTs such as an inverted stagger type TFT or an amorphous silicon TFT can also be used. Each embodiment is effective.

(Electronics)
As an example of an electronic apparatus using the above liquid crystal device, a structure of a projection display device will be described with reference to FIG. In FIG. 21, a projection type display device 1100 is provided with three liquid crystal devices as described above, and shows a schematic configuration diagram of an optical system of a projection type liquid crystal device used as RGB liquid crystal devices 962R, 962G and 962B. The light source device 920 and the uniform illumination optical system 923 described above are employed in the optical system of the projection display device of this example. Then, the projection display device includes a color separation optical system 924 as color separation means for separating the light beam W 2 emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B), Three light valves 925R, 925G, and 925B as modulation means for modulating each color light beam R 1, G 2, and B, and a color composition prism 910 as color composition means for recombining the modulated color light beams are combined. A projection lens unit 906 is provided as projection means for enlarging and projecting the light beam onto the surface of the projection surface 100. Further, a light guide system 927 for guiding the blue light beam B 1 to the corresponding light valve 925 B is also provided.

  The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 are each provided with a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is divided into a plurality of partial light beams by the rectangular lens of the first lens plate 921. These partial light beams are superimposed in the vicinity of the three light valves 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has a non-uniform illuminance distribution within the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It can be illuminated.

  Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B 1 and the green light beam G 2 included in the light beam W 1 are reflected at right angles and travel toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission unit 944 of the red light beam R 1 to the color combining prism 910 side.

  Next, in the green reflecting dichroic mirror 942, only the green light beam G out of the blue and green light beams B 1 and G 2 reflected by the blue-green reflecting dichroic mirror 941 is reflected at right angles, and the color from the green light beam G emitting part 945 The light is emitted to the side of the combining optical system. The blue light beam B 1 that has passed through the green reflecting dichroic mirror 942 is emitted from the emission part 946 of the blue light beam B to the light guide system 927 side. In this example, the distances from the light beam emitting portion of the uniform illumination optical element to the light emitting portions 944, 945, and 946 of each color light beam in the color separation optical system 924 are set to be substantially equal.

  Condensing lenses 951 and 952 are disposed on the emission side of the emission portions 944 and 945 of the red and green light beams R 1 and G 2 of the color separation optical system 924, respectively. Therefore, the red and green light beams R 1 and G 2 emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.

  The collimated red and green light beams R 1 and G 2 are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are subjected to switching control according to image information by a driving unit (not shown), and thereby each color light passing therethrough is modulated. On the other hand, the blue light beam B is guided to the corresponding light valve 925B through the light guide system 927, where it is similarly modulated according to the image information. The light valves 925R, 925G, and 925B in this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal devices 962R and 962G disposed therebetween. , 962B.

  The light guide system 927 includes a condensing lens 954 arranged on the emission side of the emission part 946 of the blue light beam B 1, an incident side reflection mirror 971, an emission side reflection mirror 972, and an intermediate lens arranged between these reflection mirrors. 973 and a condensing lens 953 disposed on the front side of the light valve 925B. The blue light beam B 1 emitted from the condenser lens 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. The optical path length of each color light beam, that is, the distance from the emission part of the light beam W 1 to each of the liquid crystal devices 962R, 962G, 962B is the longest for the blue light beam B 1, and therefore the largest light loss of the blue light beam. However, the light loss can be suppressed by interposing the light guide system 927.

  The color light beams R, G, and B modulated through the light valves 925R, 925G, and 925B are incident on the color synthesis prism 910 and synthesized there. Then, the light synthesized by the color synthesis prism 910 is enlarged and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

  In this example, since the liquid crystal devices 962R, 962G, 962B are provided with a light shielding layer on the lower side of the TFT, the projection optical system in the liquid crystal projector based on the projection light from the liquid crystal devices 962R, 962G, 962B. Reflected light, reflected light from the surface of the TFT array substrate when the projected light passes through, part of the projected light that penetrates the projection optical system after being emitted from another liquid crystal device, etc. Even if the light is incident from the side, the light shielding for the channel of the switching TFT of the pixel electrode can be sufficiently performed.

  For this reason, even if a prism unit suitable for miniaturization is used in the projection optical system, a film for preventing return light is separately arranged between the liquid crystal devices 962R, 962G, 962B and the prism unit, or the polarizing means is used. Since it is not necessary to perform a return light prevention process, it is very advantageous in reducing the size and simplification of the configuration.

  In this embodiment, since the influence of the return light on the channel region of the TFT can be suppressed, the polarizing means 961R, 961G, and 961B subjected to the return light prevention process directly on the liquid crystal device need not be attached. Therefore, as shown in FIG. 18, the polarizing means is formed apart from the liquid crystal device. More specifically, one polarizing means 961R, 961G, 961B is attached to the color synthesizing prism 910, and the other polarizing means 960R, 960G and 960B can be attached to the condenser lenses 953, 945 and 944. In this way, by attaching the polarizing means to the prism unit or the condenser lens, the heat of the polarizing means is absorbed by the prism unit or the condenser lens, and thus the temperature rise of the liquid crystal device can be prevented.

  Although not shown, an air layer is formed between the liquid crystal device and the polarizing unit by forming the liquid crystal device and the polarizing unit apart from each other, so a cooling unit is provided between the liquid crystal device and the polarizing unit. By sending air such as cold air into the liquid crystal, it is possible to further prevent the temperature of the liquid crystal device from rising and to prevent malfunction due to the temperature rise of the liquid crystal device.

(The invention's effect)
According to the liquid crystal device of the present invention, the storage capacitor is provided to each of the plurality of pixel electrodes by the low resistance capacitance line using the plurality of light shielding films, so that the drive frequency of the liquid crystal device is increased. However, lateral crosstalk, ghosts, and the like caused by potential fluctuation of the capacitor line due to capacitive coupling between the data line and the capacitor line are reduced, and high-quality image display can be performed. Further, precharge and scanning line inversion driving can be performed satisfactorily. In addition to these, even if the capacitance line is disconnected due to foreign matter, the wiring by the light shielding film replaces the capacitance line, so that a redundant structure can be realized, and the occurrence of cracks related to the wiring by the light shielding film is reduced and the reliability is reduced. In addition, a liquid crystal device with a high yield rate can be realized.

3 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix-like pixels that form an image display area in the first embodiment of the liquid crystal device. 2 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding films, and the like are formed in the first embodiment of the liquid crystal device. FIG. It is AA 'sectional drawing of FIG. FIG. 3 is a block diagram of a pixel unit and peripheral circuits provided on the TFT array substrate in the first embodiment of the liquid crystal device. It is a timing chart of various signals concerning precharge. It is process drawing (the 1) which shows order for the manufacturing process of 1st Embodiment of a liquid crystal device later on. It is process drawing (the 2) which shows the manufacturing process of 1st Embodiment of a liquid crystal device later on in order. It is process drawing (the 3) which shows order for the manufacturing process of 1st Embodiment of a liquid crystal device later on. It is process drawing (the 4) which shows order for the manufacturing process of 1st Embodiment of a liquid crystal device later on. FIG. 10 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding film and the like are formed in a second embodiment of the liquid crystal device. It is a top view of a plurality of pixel groups which a TFT array substrate in which a data line, a scanning line, a pixel electrode, a light shielding film, etc. formed in a 3rd embodiment of a liquid crystal device adjoin. It is a top view of the several pixel group which the TFT array substrate in which the data line in 4th Embodiment of the liquid crystal device, the scanning line, the pixel electrode, the light shielding film, etc. formed was formed. It is a top view of the several pixel group which the TFT array substrate in which the data line in 5th Embodiment of the liquid crystal device, the scanning line, the pixel electrode, the light shielding film, etc. formed was formed. It is a top view of a plurality of pixel groups which a TFT array substrate in which a data line, a scanning line, a pixel electrode, a light shielding film, etc. formed in a 6th embodiment of a liquid crystal device adjoin. It is a top view of the several pixel group which the TFT array substrate in which the data line in 7th Embodiment of the liquid crystal device, the scanning line, the pixel electrode, the light shielding film, etc. were formed in is adjacent. It is AA 'sectional drawing of FIG. 2 in 8th Embodiment of a liquid crystal device. It is AA 'sectional drawing of FIG. 2 in 9th Embodiment of a liquid crystal device. It is the top view which looked at the TFT array substrate in each embodiment of a liquid crystal device from the counter substrate side with each component formed on it. It is HH 'sectional drawing of FIG. It is a conceptual diagram for demonstrating the display degradation by horizontal crosstalk. It is a block diagram of the projection type display apparatus which is an example of the electronic device using a liquid crystal device.

Claims (6)

A liquid crystal is sandwiched between a pair of substrates, and on one of the pair of substrates,
Pixel electrodes arranged in a matrix;
A thin film transistor provided corresponding to the pixel electrode and electrically connected to the pixel electrode through a contact hole;
A data line electrically connected to the thin film transistor;
A capacitance line that intersects the data line and provides a storage capacitance to the pixel electrode;
A light-shielding film extending so as to overlap the data line, and covering at least a channel region of the semiconductor layer of the thin film transistor when viewed from the one substrate side,
A storage capacitor electrode of the storage capacitor is formed as a part of the semiconductor layer in a region where the light shielding film, the data line, and the capacitor line overlap,
The liquid crystal device, wherein the contact hole is provided apart from a region where the data line and the light shielding film extend in a plan view.   The liquid crystal device according to claim 1, wherein the storage capacitor includes a dielectric film made of the same insulating film as a gate insulating film of the thin film transistor.   The light shielding film is formed below the semiconductor layer forming the thin film transistor via an interlayer insulating film, and the capacitor line and the light shielding film are interposed via a second contact hole opened in the interlayer insulating film. The liquid crystal device according to claim 1, wherein the liquid crystal device is connected.   The liquid crystal device according to claim 3, wherein the second contact hole is formed in a region overlapping the data line when viewed in a plan view.   The liquid crystal device according to claim 4, wherein the capacitor line and the light shielding film are connected to a constant potential source.   An electronic apparatus comprising the liquid crystal device according to claim 1.

Images