JP4693852B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP4693852B2 JP4693852B2 JP2008040749A JP2008040749A JP4693852B2 JP 4693852 B2 JP4693852 B2 JP 4693852B2 JP 2008040749 A JP2008040749 A JP 2008040749A JP 2008040749 A JP2008040749 A JP 2008040749A JP 4693852 B2 JP4693852 B2 JP 4693852B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- substrate
- semiconductor device
- pad
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 103
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 51
- 230000002093 peripheral effect Effects 0.000 claims description 40
- 239000011347 resin Substances 0.000 claims description 33
- 229920005989 resin Polymers 0.000 claims description 33
- 230000001681 protective effect Effects 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 description 20
- 239000009719 polyimide resin Substances 0.000 description 20
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000003825 pressing Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
そして、これら内、外多重状態で、断続的環状配列の接続端子と、内、外多重状態で、断続的環状配列のパッド間を、内、外多重状態で、断続的環状配列のバンプを介して接続した構成となっていた。
すなわち、上記従来例の構造においては、バンプ接続後に、基板と半導体チップ間に、固定用樹脂体を、半導体チップの外側から内側へと毛細管作用により流入させ、これにより半導体チップ下面と基板の上面間を、この固定用樹脂体により固定するようになっているが、固定用樹脂体の流入がスムーズに進行しない部分では、所謂空気の巻き込みによるボイドが形成されてしまう。
しかしながら、製造方法として、突起を形成するための工程を設ける必要が有り、コストアップになるという問題点があった。また、半導体チップと樹脂体の界面では最も密着強度が弱くなるため、界面に発生するボイドを抑制することが難しく、このボイドにより電気的接続状態が不安定になるという問題点があった。
また、前記突出部が形成される周辺の前記半導体チップ表面に凹凸を備えても良い。
また、前記凹凸を前記半導体チップ表面の下層部分にダミーメタルを設けることにより形成することが好ましい。
また、前記外周パッドの前記半導体チップ中心方向の端部は前記内周パッドの間に面することが好ましい。
また、前記流動が前記バンプの溶融と同時に発生し、前記樹脂の硬化が前記バンプの硬化と同時にされることが好ましい。
図1は本発明の半導体装置の断面図であり、図3におけるA−A部分に相当する断面図である。図2は本発明の半導体装置における固定用樹脂体挿入工程を説明する断面図、図3は本発明の半導体装置における半導体チップの裏面図である。図3においては表現保護膜7を省略している。また、図4は本発明の半導体装置における半導体チップの要部拡大図であり、パッドと突出部の構成を示す図である。図5は複数列の突出部を示す要部拡大図、図6は台形形状の突出部を示す断面図、図7は複数列の台形形状に形成された突出部を示す断面図、図8は底部に表面保護膜の凹凸が形成された突出部を示す断面図、図9は先端部に凹部が設けられた突出部を示す断面図である。
また、半導体チップ2の下面で、パッド4が形成される領域より内側の部分とパッド4の外周部分とは表面保護膜7により覆われており、さらに図1、図3に示すようにパッド4の内方部分の表面保護膜7部分は保護膜8により覆われている。
そして、この保護膜8形成時に、図3、図4に示す突出部9も同時に半導体チップ2の下面側に形成する。
また、図5は本発明の他の実施形態を示し、この実施形態では、突出部として複数列に形成される突出部9Aを設けたものである。1または複数のスリット10で突出部9Aが分割されることにより、ポリイミド樹脂の流れがよりスムーズになるとともに、硬化後はこのスリット10への樹脂の食いつき状態が、より固定強度を高めることになる。
2 半導体チップ
3 固定用樹脂体
4 パッド
5 接続端子
6 バンプ
7 表面保護膜
8 保護膜
9 突出部
9A 突出部
9B 突出部
9C 突出部
9D 突出部
9E 突出部
10 スリット
11 スリット
12 スリット
13 ダミーメタル
14 凹部
Claims (12)
- 基板上に半導体チップをフリップチップ実装した構造体であって、
前記半導体チップの実装面に環状配列された内周パッドと、
前記内周パッドより外周に環状配列された外周パッドと、
前記外周パッドの間に前記外周パッドより前記基板方向に突出する突出部と、
前記半導体チップの前記内周パッドおよび前記外周パッドとバンプを介して接続されるように前記基板上に形成される複数の接続端子と、
前記基板と前記半導体チップとを固定する固定用樹脂体と
を有し、前記突出部の前記半導体チップ中心方向の端部が前記外周パッド間の領域より前記半導体チップ中心方向に突出して形成され、前記突出部と前記基板との間に間隔があり、前記内周パッドの間には突出部が形成されていないことを特徴とする半導体装置。 - 前記内周パッドおよび前記外周パッドが2重環状で千鳥配置されることを特徴とする請求項1記載の半導体装置。
- 前記突出部が、隣接する前記外周パッドの隣接面に平行な方向の1または複数のスリットにより分割されることを特徴とする請求項1または請求項2のいずれかに記載の半導体装置。
- 前記突出部が、前記基板に近づく程細くなるように断面形状が台形であることを特徴とする請求項1〜請求項3のいずれかに記載の半導体装置。
- 前記突出部の先端部分に凹部を備えることを特徴とする請求項1〜請求項4のいずれかに記載の半導体装置。
- 前記突出部が形成される周辺の前記半導体チップ表面に凹凸を備えることを特徴とする請求項1〜請求項5のいずれかに記載の半導体装置。
- 前記凹凸を備える半導体チップ表面が表面保護膜であることを特徴とする請求項6記載の半導体装置。
- 前記凹凸を前記半導体チップ表面の下層部分にダミーメタルを設けることにより形成することを特徴とする請求項6または請求項7のいずれかに記載の半導体装置。
- 請求項1〜請求項8のいずれかに記載の半導体装置の製造方法であって、樹脂の形成に際し、
前記基板の前記半導体チップ搭載領域の中央部に前記固定用樹脂体を載置する工程と、
前記内周パッドおよび前記外周パッドと前記接続端子がバンプを介して1対1で接続されるように前記半導体チップを前記基板に加熱,加圧接続させる工程と
を有し、前記固定用樹脂体が前記半導体チップ下部の中央部から周辺部に流動することを特徴とする半導体装置の製造方法。 - 前記半導体チップが、前記内周パッドが形成される領域の内側の表面に保護膜を備え、前記突出部が前記保護膜と同時に形成されることを特徴とする請求項9記載の半導体装置の製造方法。
- 前記流動が前記バンプの溶融と同時に発生し、前記樹脂の硬化が前記バンプの硬化と同時にされることを特徴とする請求項9記載の半導体装置の製造方法。
- 前記外周パッドの前記半導体チップ中心方向の端部は前記内周パッドの間に面することを特徴とする請求項1記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008040749A JP4693852B2 (ja) | 2008-02-22 | 2008-02-22 | 半導体装置および半導体装置の製造方法 |
US12/372,760 US7977790B2 (en) | 2008-02-22 | 2009-02-18 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008040749A JP4693852B2 (ja) | 2008-02-22 | 2008-02-22 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009200270A JP2009200270A (ja) | 2009-09-03 |
JP4693852B2 true JP4693852B2 (ja) | 2011-06-01 |
Family
ID=40997491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008040749A Expired - Fee Related JP4693852B2 (ja) | 2008-02-22 | 2008-02-22 | 半導体装置および半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7977790B2 (ja) |
JP (1) | JP4693852B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005009358B4 (de) * | 2005-03-01 | 2021-02-04 | Snaptrack, Inc. | Lötfähiger Kontakt und ein Verfahren zur Herstellung |
FR2954588B1 (fr) * | 2009-12-23 | 2014-07-25 | Commissariat Energie Atomique | Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire |
US8476768B2 (en) * | 2011-06-28 | 2013-07-02 | Freescale Semiconductor, Inc. | System on a chip with interleaved sets of pads |
DE102012001346A1 (de) * | 2012-01-24 | 2013-07-25 | Giesecke & Devrient Gmbh | Verfahren zum Herstellen eines Datenträgers |
JP6152816B2 (ja) * | 2014-03-26 | 2017-06-28 | ソニー株式会社 | 半導体デバイス、表示パネル、表示装置、電子装置、および、半導体デバイスの製造方法 |
CN110211935A (zh) * | 2019-05-08 | 2019-09-06 | 华为技术有限公司 | 一种防止分层窜锡的封装及制造方法 |
CN111341746A (zh) * | 2020-03-13 | 2020-06-26 | 颀中科技(苏州)有限公司 | 植球结构及制备工艺 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11233544A (ja) * | 1998-02-18 | 1999-08-27 | Matsushita Electron Corp | 半導体装置 |
JP2001127198A (ja) * | 1999-10-28 | 2001-05-11 | Shinko Electric Ind Co Ltd | 表面実装用基板及び表面実装構造 |
JP2002203874A (ja) * | 2000-12-28 | 2002-07-19 | Toray Eng Co Ltd | チップの実装方法 |
JP2004221320A (ja) * | 2003-01-15 | 2004-08-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2007059703A (ja) * | 2005-08-25 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体チップとこれを回路基板に実装した半導体パッケージ、これらの製造方法 |
JP2007096096A (ja) * | 2005-09-29 | 2007-04-12 | Optrex Corp | 半導体装置 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5766982A (en) * | 1996-03-07 | 1998-06-16 | Micron Technology, Inc. | Method and apparatus for underfill of bumped or raised die |
US5726502A (en) * | 1996-04-26 | 1998-03-10 | Motorola, Inc. | Bumped semiconductor device with alignment features and method for making the same |
JP3349058B2 (ja) * | 1997-03-21 | 2002-11-20 | ローム株式会社 | 複数のicチップを備えた半導体装置の構造 |
US6965166B2 (en) * | 1999-02-24 | 2005-11-15 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure |
US7041533B1 (en) * | 2000-06-08 | 2006-05-09 | Micron Technology, Inc. | Stereolithographic method for fabricating stabilizers for semiconductor devices |
JP2003100801A (ja) * | 2001-09-25 | 2003-04-04 | Mitsubishi Electric Corp | 半導体装置 |
US7470564B2 (en) | 2002-10-28 | 2008-12-30 | Intel Corporation | Flip-chip system and method of making same |
US20050014313A1 (en) | 2003-03-26 | 2005-01-20 | Workman Derek B. | Underfill method |
JP4175197B2 (ja) * | 2003-06-27 | 2008-11-05 | 株式会社デンソー | フリップチップ実装構造 |
US7279359B2 (en) | 2004-09-23 | 2007-10-09 | Intel Corporation | High performance amine based no-flow underfill materials for flip chip applications |
JP4919630B2 (ja) | 2005-08-03 | 2012-04-18 | 大和ハウス工業株式会社 | 外壁パネルの製作方法 |
WO2007039959A1 (ja) * | 2005-10-05 | 2007-04-12 | Sharp Kabushiki Kaisha | 配線基板及びそれを備えた表示装置 |
JP5211493B2 (ja) * | 2007-01-30 | 2013-06-12 | 富士通セミコンダクター株式会社 | 配線基板及び半導体装置 |
US7521284B2 (en) * | 2007-03-05 | 2009-04-21 | Texas Instruments Incorporated | System and method for increased stand-off height in stud bumping process |
-
2008
- 2008-02-22 JP JP2008040749A patent/JP4693852B2/ja not_active Expired - Fee Related
-
2009
- 2009-02-18 US US12/372,760 patent/US7977790B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11233544A (ja) * | 1998-02-18 | 1999-08-27 | Matsushita Electron Corp | 半導体装置 |
JP2001127198A (ja) * | 1999-10-28 | 2001-05-11 | Shinko Electric Ind Co Ltd | 表面実装用基板及び表面実装構造 |
JP2002203874A (ja) * | 2000-12-28 | 2002-07-19 | Toray Eng Co Ltd | チップの実装方法 |
JP2004221320A (ja) * | 2003-01-15 | 2004-08-05 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2007059703A (ja) * | 2005-08-25 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体チップとこれを回路基板に実装した半導体パッケージ、これらの製造方法 |
JP2007096096A (ja) * | 2005-09-29 | 2007-04-12 | Optrex Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2009200270A (ja) | 2009-09-03 |
US20090212406A1 (en) | 2009-08-27 |
US7977790B2 (en) | 2011-07-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4693852B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5263895B2 (ja) | 半導体装置、及び半導体装置の製造方法 | |
US7517731B2 (en) | Semiconductor package | |
JP2012059832A5 (ja) | ||
WO2010070806A1 (ja) | 半導体装置とフリップチップ実装方法およびフリップチップ実装装置 | |
US20090023252A1 (en) | Method of manufacturing semiconductor device having a heat sink with a bored portion | |
JP2009259924A (ja) | 半導体装置の製造方法 | |
JP6467775B2 (ja) | 部品内蔵基板の製造方法 | |
JP4760361B2 (ja) | 半導体装置 | |
JP2007142017A (ja) | 半導体装置およびその製造方法 | |
US20090051048A1 (en) | Package structure and manufacturing method thereof | |
JP2015056540A (ja) | 半導体装置及びその製造方法 | |
JP2007201036A (ja) | 電子装置およびその製造方法 | |
JP4361828B2 (ja) | 樹脂封止型半導体装置 | |
JP2010205888A (ja) | 半導体装置 | |
JP6705741B2 (ja) | 半導体装置 | |
JP2006351935A (ja) | 半導体チップ実装基板及びそれを用いた半導体装置 | |
JP6467797B2 (ja) | 配線基板、配線基板を用いた半導体装置およびこれらの製造方法 | |
JP2008041857A (ja) | 配線基板、デバイス装置及びその製造方法 | |
JP2010114243A (ja) | 半導体装置 | |
CN114203644B (zh) | 半导体装置及半导体装置的制造方法 | |
JP2008091758A (ja) | 半導体装置およびその製造方法 | |
JP2020061449A5 (ja) | ||
JP2006278441A (ja) | 半導体装置およびその製造方法 | |
JP6858688B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100208 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100526 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100601 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100802 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100831 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101122 |
|
A911 | Transfer of reconsideration by examiner before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20101202 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110125 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110222 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140304 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |