JP4690554B2 - Flat panel display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flat display device, and more particularly to a flat display device in which a drive circuit and the like are arranged on a substrate on which pixels are formed.
[0002]
[Prior art]
A flat display device typified by a liquid crystal display device is used in a wide range of fields by making use of characteristics such as thinness, light weight, and low power consumption. Among them, a liquid crystal display device in which a TFT (thin film transistor) is arranged as a switching element for each pixel is widely used as a display device for information equipment terminals and thin televisions.
[0003]
Such a liquid crystal display device includes an array substrate on which electrodes and the like for operating liquid crystals are formed, and an external control circuit that supplies a control signal, a power supply potential, and the like to the array substrate. Conventionally, it has been difficult to form sophisticated and complicated drive circuits on an array substrate, and these drive circuits have been compensated by forming them on an external control circuit. However, in recent years, improvement of the array process and circuit technology has made it possible to build a drive circuit, a power supply circuit, and the like on the array substrate, thereby reducing cost and size.
[0004]
[Problems to be solved by the invention]
Currently, among the IC components included in the external control circuit, an array substrate having a charge pump circuit (voltage source circuit) is also made. However, since the pulse signal and power supply potential necessary for driving the charge pump circuit are still supplied from the external control circuit, the addition of a new array input pin and the generation of a dedicated pulse signal are a burden on the external control circuit. There is a problem that there is little effect of cost reduction and compactness by building a charge pump circuit on the substrate.
[0005]
An object of the present invention is to provide a flat display device that realizes cost reduction and compactness in a configuration in which a charge pump circuit is provided on an array substrate.
[0006]
Another object of the present invention is to provide a flat display device that achieves further low power consumption in addition to the above object.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the invention of claim 1 is characterized in that a plurality of scanning lines and a plurality of signal lines intersecting each other, switch elements arranged at intersections of both lines, and connected to the switch elements A first substrate including a pixel electrode; a second substrate including a counter electrode facing the pixel electrode; a display panel having a light modulation layer held between the first substrate and the second substrate; A signal line driving circuit for supplying a data signal to the signal line, a scanning line driving circuit for supplying a scanning signal to the scanning line, and a control signal and a power supply potential are supplied to the signal line driving circuit and the scanning line driving circuit. In the flat panel display device including the external control circuit, the voltage source circuit included in the external control circuit is disposed on the first substrate, and the signal line driving circuit or the Scan line drive circuit The same control signal as the control signal supplied is arranged to be supplied to the voltage source circuit, either one of the control signal supplied to the control signal and the scan line driver circuit is supplied to the signal line driver circuit Is selectively supplied to the voltage source circuit .
[0008]
As a preferred mode, the potential of the control signal is shifted to a predetermined level by a level shift circuit and supplied to the voltage source circuit.
[0010]
As a preferred mode, a control signal supplied to the scanning line driving circuit is supplied during standby when the voltage source circuit stops the boosting operation, and a control signal supplied to the signal line driving circuit when the boosting operation is performed. Supply.
[0011]
The invention of claim 2 is characterized in that Oite to claim 1, the control signal supplied to the voltage source circuit is fed via a frequency dividing circuit.
[0012]
As a preferred mode, a control signal whose potential is shifted by the level shift circuit is supplied to the frequency divider circuit.
[0013]
According to a third aspect of the present invention, in the first or second aspect , the same power supply potential as that supplied to the signal line driving circuit or the scanning line driving circuit is supplied to the voltage source circuit. Features.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a case where the flat display device according to the present invention is applied to an active matrix type liquid crystal display device in which a drive circuit is integrated on an array substrate will be described.
[0015]
[Embodiment 1]
FIG. 1 is a circuit configuration diagram of a liquid crystal display device 100 according to the first embodiment, and particularly shows a configuration of an array substrate and an external control circuit. A pixel portion 103 in which a plurality of pixels are formed, a scanning line driving circuit 104, and a signal line driving circuit 105 are arranged on the array substrate 101 shown in FIG.
[0016]
In the pixel portion 101, a plurality of signal lines S1, S2, S3... (Hereinafter, generically S) and a plurality of scanning lines G1, G2. A TFT 11 as a switch element is disposed at each intersection of both lines. The signal line S and the scanning line G are electrically insulated by an insulating film (not shown).
[0017]
The source electrode of the TFT 11 is connected to the signal line S, and the drain electrode is connected to the pixel electrode 12. Although not shown in FIG. 1, the counter electrode that forms a pair with the pixel electrode 12 is formed on a counter substrate (not shown). The array substrate 101 and the counter substrate are arranged at predetermined intervals so that their electrode surfaces face each other, and the periphery thereof is sealed with a sealing material. Then, the inside of both the substrates is filled with a liquid crystal material to be a light modulation layer.
[0018]
In the array substrate 101, the auxiliary capacitance 13 is connected in parallel to the pixel electrode 12 in order to maintain a potential relationship with a counter electrode (not shown). The auxiliary capacitor 13 forms a capacitor Cs between the pixel electrode 12 and auxiliary capacitor lines C1, C2,. The auxiliary capacitance line C is electrically connected to the auxiliary capacitance 13 of all pixels, and a constant voltage is applied from the external control circuit 102.
[0019]
A constant common voltage (Vcom) is applied from the external control circuit 102 to the counter electrode (not shown). The data signal written through the signal line S is held for one frame scanning period by the liquid crystal capacitor Clc and the capacitor Cs.
[0020]
The scanning line driving circuit 104 includes a timing circuit (shift register) and a buffer circuit (not shown), and based on the vertical clock signal CKV and the vertical start signal STV supplied as control signals from the external control circuit 102, the scanning lines G1, A scanning signal is sequentially output to G2... Every one horizontal scanning period.
[0021]
The signal line driver circuit 105 includes a timing circuit (shift register), a video bus, an analog switch circuit, and the like (not shown). The analog switch circuit is composed of TFTs, and each drain electrode is connected to signal lines S1, S2, S3. The timing circuit controls the analog switch circuit on the basis of the horizontal clock signal CKH and the horizontal start signal STH supplied as control signals from the external control circuit 102, and similarly applies a data signal supplied from the external control circuit 102 to a predetermined signal. The signal lines S1, S2, S3,... Are sampled at timing. The driving method of the signal line driver circuit may be a D / A conversion method in addition to the analog sample hold method.
[0022]
The scan line driver circuit 104 and the signal line driver circuit 105 are supplied with VDD1 and VDD2 as power supply voltages. Among these, VDD1 is supplied from the external control circuit 102, and VDD2 is supplied from the charge pump circuit 10 described later.
[0023]
The external control circuit 102 includes a control IC, a D / A converter, a level shifter, and the like (not shown), and appropriately converts and processes a reference clock signal and a digital data signal supplied from the outside, Control signals (CKV, CKH, STV, STH), power supply voltages (VDD1, VDD2), a common voltage, and the like are supplied to each drive circuit on the array substrate 101. The external drive circuit 102 and the array substrate 101 are electrically connected by an FPC (flexible wiring board) (not shown).
[0024]
A charge pump circuit 10 is disposed on the array substrate 101. In this charge pump circuit 10, the main circuit is disposed on the array substrate 101, and the output-side capacitor 15 provided between the output part of the circuit and the ground (GND) is disposed outside the array substrate 101. In FIG. 1, the output-side capacitor 15 is drawn outside the array substrate in order to make it easy to understand the relationship between the output part of the circuit and the ground, but the wiring from the output part of the circuit is externally controlled via the electrode pad 17. The output side capacitor 15 is formed inside the external control circuit 102 by being taken into the circuit 102. However, these capacitors are only required to be arranged outside the array substrate 101, and need not be arranged in the external control circuit 102 as in this embodiment.
[0025]
The output side capacitor 15 is connected to the auxiliary capacitor 13 of each pixel via the auxiliary capacitor line C. In this way, the output voltage can be further stabilized by connecting the auxiliary capacitors 13 attached to all the pixels and the output-side capacitors 15 arranged outside the array substrate 101. If the sum of the capacities Cs of the auxiliary capacitors 13 is sufficiently large when the screen is densified or enlarged, the capacity of the output-side capacitors 15 arranged outside the array substrate 101 can be reduced, Or the output side capacitor | condenser 15 itself can be made unnecessary.
[0026]
On the other hand, the charge pump circuit 10 is supplied with the power supply voltage VDDC for the charge pump circuit from the external control circuit 102. The VDDC is boosted to VDD2 and supplied to the scanning line driving circuit 104 and the signal line driving circuit 105. ing. Further, CKH (horizontal clock signal) of the control signals supplied from the external control circuit 102 to each drive circuit is supplied as a pulse signal necessary for driving the charge pump circuit 10. In this embodiment, the amplitude (potential) of CKH supplied from the external control circuit 102 is shifted to the same potential as VDD 1 by the level shift circuit 19 and input to the charge pump circuit 10.
[0027]
Note that CKH supplied from the external control circuit 102 may be directly input to the charge pump circuit 10. In this case, it is necessary to set the amplitude of CKH to an appropriate potential in advance.
[0028]
Here, the circuit configuration and operation of the charge pump circuit 10 will be briefly described. 2A is a circuit configuration diagram of the charge pump circuit 10, and FIG. 2B is an equivalent circuit diagram thereof. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.
[0029]
The charge pump circuit 10 includes two Nch TFTs 17 and 18, an input side capacitor 15 and an output side capacitor 16. Among these, the drain electrode side of the Nch TFT 17 is connected to the source electrode and the gate electrode of the Nch TFT 18.
[0030]
FIG. 3 is a timing chart showing the operation of the charge pump circuit 10. An example of the operation of the charge pump circuit 10 will be described with reference to FIG.
[0031]
First, the control signal (CKH) level-shifted to the amplitude VDD1 is input from the clock input unit 14. For example, a square wave having an amplitude of 10 V and a frequency of 1.5 MHz as shown in FIG. Further, for example, DC10V is input to the power input unit 21 as the power supply voltage VDDC, as in the case of VDD1.
[0032]
At the intermediate node pg, the following voltage is maintained according to the input waveform. That is, during a period when CKH is not input from the clock input unit 14, a voltage obtained by subtracting the threshold value Vth of the Nch TFT 17 from VDDC is maintained. For example, if the threshold voltage Vth of the Nch TFT 17 is 2V, the intermediate node pg is maintained at 8V (VDDC−Vth). Further, during the period in which CKH is input from the clock input unit 14, an amplitude waveform boosted by the boost ratio α is obtained. For example, when the step-up ratio α is 1, an amplitude waveform of 8 to 18 V (VDDC−Vth + αVDD1) is obtained as shown in FIG. The voltage of the output unit 22 is stepped up every time CKH is input to the clock input unit 14, and finally, an output voltage of VDDC-2Vth + αVDD1 is obtained. For example, in FIG. 3C, when the threshold voltage Vth of the Nch TFT 18 is 2V, an output voltage of 16V is obtained as VDD2 supplied to each drive circuit.
[0033]
According to the liquid crystal display device 100 configured as described above, since the charge pump circuit 10 is arranged on the array substrate 101, the external control circuit 102 can be made compact, and the external control circuit 102 has high functionality. Since no IC parts are required, the cost can be reduced. In particular, when the charge pump circuit 10 arranged in the external control circuit 102 is directly transferred onto the array substrate 101, a large-capacity capacitor cannot be formed on the array substrate 101. It becomes difficult to suppress the fluctuation of the output voltage of. However, according to the configuration of the first embodiment, the output voltage can be stabilized as in the case where the charge pump circuit 10 is arranged in the external control circuit 102.
[0034]
Since the CKH supplied from the external control circuit 102 is used as a pulse signal necessary for driving the charge pump circuit 10, the external control circuit 102 adds a new array input pin or a dedicated pulse signal. Can be reduced, and it is possible to sufficiently obtain the effects of cost reduction and downsizing by forming the charge pump circuit 10 on the array substrate 101.
[0035]
Therefore, in the liquid crystal display device 100 of the first embodiment, not only can the output voltage be stabilized as in the conventional case, but also the cost reduction and downsizing of the device can be realized.
[0036]
In the first embodiment, CKH is input as a pulse signal necessary for driving the charge pump circuit 10. Of the control signals supplied from the external control circuit 102, STH (horizontal start signal) is input. It may be.
[0037]
[Embodiment 2]
FIG. 4 is a circuit configuration diagram of the liquid crystal display device 110 according to the second embodiment, and the same components as those in FIG. Since the basic configuration of the liquid crystal display device 110 according to the second embodiment is the same as that of the first embodiment, description of each part will be omitted, and only characteristic parts will be described.
[0038]
In the liquid crystal display device 110 of the second embodiment, a frequency divider circuit 20 is connected between the charge pump circuit 10 and the level shift circuit 19. Assuming that CKH is supplied as a pulse signal necessary for driving the charge pump circuit 10, the frequency of the CKH is converted by the frequency dividing circuit 20 so as to be an optimum frequency for driving the charge pump circuit 10. Input to the charge pump circuit 10. For example, by converting the frequency of CKH to a low frequency of 1/64 by the frequency dividing circuit 20, it is possible to reduce the number of operations in the charge pump circuit 10 and reduce power consumption.
[0039]
Therefore, in the liquid crystal display device 110 of the second embodiment, as in the first embodiment, it is possible to stabilize the output voltage, reduce the cost and size of the device, and achieve further reduction in power consumption.
[0040]
[Embodiment 3]
In the first and second embodiments, an example in which CKH (or STH) supplied to the signal line driver circuit 105 is used as a pulse signal necessary for driving the charge pump circuit 10 is described. The supplied CKV (or STV) may be used (not shown).
[0041]
In addition, CKH (or STH) supplied to the signal line driver circuit 105 and CKV (or STV) supplied to the scanning line driver circuit 104 are used in combination so that any one of the pulse signals is selectively supplied. It may be. In general, since CKV and STV have lower frequencies than CKH and STH, CKV (or STV) is used during standby when the boosting operation in the charge pump circuit 10 is stopped, and CKH (or STV) is activated during the boost operation. It is effective to use STH). As a result, the number of operations in the charge pump circuit 10 can be reduced to reduce power consumption. Such switching of the pulse signal can be realized by a circuit configuration as shown in FIG. 5, for example.
[0042]
In FIG. 5, the sensor circuit 23 is a circuit that detects the operating state of the charge pump circuit 10, and can be configured by, for example, a differential amplifier circuit that inputs Vref and VDD2. The input switching circuit 24 is a circuit that switches the input pulse signal in accordance with the signal level output from the sensor circuit 23, and can be constituted by, for example, a clocked inverter circuit.
[0043]
While the charge pump circuit 10 is operating, the power supply voltage VDD2 output to each drive circuit is maintained at a predetermined voltage, but when the operation is stopped, the power supply voltage VDD2 is lowered. The sensor circuit 23 compares Vref and VDD2, and outputs (OUT) a high level signal if VDD2 ≧ Vref and a low level signal if VDD2 <Vref. The input switching circuit 24 switches the input to CKH (or STH) if the signal level output from the sensor circuit 23 is high, and switches the input to CKV (or STV) if the signal level is low. . By such an operation, CKV (or STV) is selected at the time of standby when the operation of the charge pump circuit 10 is stopped, and CKH (or STH) is selected at the time of activation during the boosting operation. Note that Vref of the sensor circuit 23 is input from the outside. At this time, for example, a desired voltage can be set by adjusting the potential by resistance voltage division.
[0044]
Also in the liquid crystal display device of the third embodiment, it is possible to stabilize the output voltage, reduce the cost and size of the device, and achieve low power consumption. In particular, when the frequency divider circuit 20 of the second embodiment is combined, further reduction in power consumption can be achieved.
[0045]
[Embodiment 4]
FIG. 6 is a circuit configuration diagram of the liquid crystal display device 120 according to the fourth embodiment, and the same components as those in FIG. Since the basic configuration of the liquid crystal display device 120 according to the fourth embodiment is the same as that of the first embodiment, description of each part will be omitted, and only characteristic parts will be described.
[0046]
In the liquid crystal display device 120 of Embodiment 4, VDD1 supplied to the scanning line driving circuit 104 and the signal line driving circuit 105 is used as a power supply voltage for the charge pump circuit. In this example, since the power supply for the charge pump circuit is shared with the power supply for the scanning line drive circuit 104 and the signal line drive circuit 105, the number of input power supplies to the array substrate 101 can be reduced.
[0047]
Therefore, in the liquid crystal display device 120 according to the fourth embodiment, the output voltage can be stabilized and the cost and the size of the device can be further reduced as in the first embodiment.
[0048]
Also in the fourth embodiment, when the frequency dividing circuit 20 of the second embodiment is combined, low power consumption can be achieved. Further, by adopting a configuration in which the pulse signal is selectively switched according to the operation state of the charge pump circuit 10 as in the third embodiment, further reduction in power consumption can be achieved.
[0049]
【The invention's effect】
As described above, in the first to third aspects of the invention, the control signal supplied to the scanning line driving circuit or the signal line driving circuit is supplied as a pulse signal necessary for driving the charge pump circuit (voltage source circuit). As a result, the burden of adding a new array input pin and generating a dedicated pulse signal in the external control circuit is reduced, and the effect of cost reduction and compactness by creating a charge pump circuit on the array substrate is reduced. You can get enough.
[0050]
In particular, if you be selectively supplied to the charge pump circuit to either one of the control signals which are respectively supplied with the previous SL signal line driving circuit to the scanning line driving circuit, suitable in accordance with the operation state of the charge pump circuit Since a control signal with a proper frequency can be selected, the number of operations in the charge pump circuit can be reduced to reduce power consumption.
[0051]
In particular, when the pulse signal is supplied via a frequency dividing circuit as in the invention of claim 2 , the frequency of the pulse signal can be converted to an optimum frequency, so that the charge pump circuit The number of operations can be reduced and low power consumption can be achieved.
[0052]
In particular, when the power supply voltage supplied to each drive circuit is supplied as the power supply voltage for the charge pump circuit as in the invention of claim 3 , the input to the array substrate (first substrate) is performed. Since the number of power supplies can be reduced, further cost reduction and downsizing of the apparatus can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a liquid crystal display device according to a first embodiment.
FIG. 2 is a circuit configuration diagram of the charge pump circuit shown in FIG.
FIG. 3 is a timing chart showing an operation of the charge pump circuit shown in FIG. 2;
4 is a circuit configuration diagram of a liquid crystal display device according to Embodiment 2. FIG.
FIG. 5 is a circuit configuration diagram of a circuit for switching a pulse signal.
6 is a circuit configuration diagram of a liquid crystal display device according to Embodiment 3. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Charge pump circuit, 11 ... TFT, 12 ... Pixel electrode, 13 ... Auxiliary capacity, 15 ... Input side capacity, 16 ... Output side capacity, 17, 18 ... Nch TFT, 19 ... Level shift circuit, 20 ... Frequency divider circuit, DESCRIPTION OF SYMBOLS 101 ... Array substrate, 102 ... External control circuit, 103 ... Pixel part, 104 ... Scanning line drive circuit, 105 ... Signal line drive circuit

Claims (3)

A plurality of scanning lines and a plurality of signal lines intersecting each other, a switch element disposed at each intersection of these lines, a first substrate including a pixel electrode connected to the switch element, and opposed to the pixel electrode A second substrate including a counter electrode, a display panel having a light modulation layer held between the first substrate and the second substrate, and a signal line driver circuit for supplying a data signal to the signal line A planar display device comprising: a scanning line driving circuit that supplies a scanning signal to the scanning line; and an external control circuit that supplies a control signal and a power supply potential to the signal line driving circuit and the scanning line driving circuit.
A voltage source circuit included in the external control circuit is disposed on the first substrate;
On the first substrate, the control signal supplied to the signal line driver circuit or the scanning line driver circuit is also supplied to the voltage source circuit ,
One of the control signal supplied to the signal line driver circuit and the control signal supplied to the scanning line driver circuit is configured to be selectively supplied to the voltage source circuit. Display device. The flat display device according to claim 1, wherein the control signal supplied to the voltage source circuit is supplied via a frequency divider circuit. 3. The flat display device according to claim 1, wherein a power supply potential supplied to the signal line driving circuit or the scanning line driving circuit is also supplied to the voltage source circuit.

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