JP4612153B2 - Flat panel display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flat display device, and more particularly to a flat display device in which a drive circuit and the like are arranged on a substrate on which pixels are formed.
[0002]
[Prior art]
A flat display device typified by a liquid crystal display device is used in a wide range of fields by making use of characteristics such as thinness, light weight, and low power consumption. Among them, a liquid crystal display device in which a TFT (thin film transistor) is arranged as a switching element for each pixel is widely used as a display device for information equipment terminals and thin televisions. In particular, in recent years, in order to expand the effective screen area on an array substrate of the same area and reduce the manufacturing cost, an active matrix type in which a drive circuit and a power supply circuit are arranged on the array substrate on which pixels are formed. Development of liquid crystal display devices is in progress.
[0003]
[Problems to be solved by the invention]
By the way, various clock signals, power supply voltages, and the like are supplied from an external control circuit arranged on the outside to the drive circuit and power supply circuit arranged on the array substrate. In the external control circuit, IC components such as a control IC, a D / A converter, a level shifter, a charge pump circuit (voltage source circuit) are arranged.
[0004]
Among these, in the charge pump circuit, a large-capacity capacitor is arranged in the clock input part and the output part in order to suppress fluctuations in the output voltage. However, in the current manufacturing process, it is difficult to form a large-capacity capacitor on the array substrate, so it is difficult to arrange the charge pump circuit on the array substrate. Therefore, it is difficult to make the external control circuit compact, and there is a problem that the cost becomes high because a high-functional IC component is required.
[0005]
On the other hand, the process of forming TFTs on a glass plate such as an array substrate is difficult to manufacture, and transistor characteristics often become unstable. For this reason, even when the charge pump circuit is formed on the array substrate, the transistor characteristics of the TFTs constituting the circuit become unstable, the threshold value varies, and the output voltage fluctuates. was there.
[0006]
In addition, when the TFT on the array substrate is formed of polycrystalline Si, the capability of the TFT is inferior to that of single crystal Si, so measures such as increasing the gate width are necessary to compensate for this. Become. For this reason, there is a problem in that the area required for the arrangement becomes large, and the frame becomes large accordingly.
[0007]
SUMMARY OF THE INVENTION A first object of the present invention is to provide a flat display device that realizes a compact external control circuit and low cost.
[0008]
A second object of the present invention is to provide a flat display device capable of stabilizing the output voltage from the charge pump circuit without being affected by the TFT manufacturing process.
[0009]
A third object of the present invention is to provide a flat display device capable of arranging a circuit such as a charge pump circuit on an array substrate without enlarging the frame.
[0010]
[Means for Solving the Problems]
  The first aspect of the present invention includes a plurality of scanning lines and a plurality of signal lines intersecting each other, a switching element disposed at each intersection of both lines, and a pixel electrode connected to the switching element. A second substrate including a counter electrode facing the pixel electrode, a display panel having a light modulation layer held between the first substrate and the second substrate, and data on the signal lines A signal line driving circuit for supplying a signal; a scanning line driving circuit for supplying a scanning signal to the scanning line; and an external control circuit for supplying a predetermined signal or potential to the signal line driving circuit and the scanning line driving circuit. In the flat display device provided, the voltage source circuit included in the external control circuitThe first thin film transistor and the second thin film transistor having different polarities are connected in series, and a clock signal used when driving the signal line driving circuit or the scanning line driving circuit is input through the first capacitor. A first input portion connected to the gate electrodes of the first thin film transistor and the second thin film transistor, and a second input portion for inputting an inverted clock signal of the clock signal through a second capacitor, The drain electrode of one thin film transistor and the source electrode of the second thin film transistor are connected to an intermediate connection point, the power supply voltage is connected to the source electrode of the first thin film transistor, and the output of the voltage source circuit A drain electrode of the second thin film transistor;A voltage source circuit disposed on the first substrate, a capacitance between the output of the voltage source circuit and the ground, andThe first capacity and the second capacityIs arranged outside the first substrate.
[0011]
As a preferred mode, in the configuration in which an auxiliary capacitor is connected in parallel with the pixel electrode, the auxiliary capacitor is included in a capacitor disposed between the output portion of the voltage source circuit and the ground. .
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a case where the flat display device according to the present invention is applied to an active matrix type liquid crystal display device in which a drive circuit is integrated on an array substrate will be described.
[0018]
[Embodiment 1]
First, as a first embodiment, a liquid crystal display device that realizes a compact external control circuit and low cost will be described.
[0019]
FIG. 1 is a circuit configuration diagram of the liquid crystal display device according to the first embodiment, and particularly shows a configuration of an array substrate and an external control circuit. A pixel portion 103 in which a plurality of pixels are formed, a scanning line driving circuit 104, and a signal line driving circuit 105 are arranged on the array substrate 101 shown in FIG.
[0020]
In the pixel portion 101, a plurality of signal lines S1, S2, S3... (Hereinafter, generically S) and a plurality of scanning lines G1, G2. A TFT 11 as a switch element is disposed at each intersection of both lines. The signal line S and the scanning line G are electrically insulated by an insulating film (not shown).
[0021]
The source electrode of the TFT 11 is connected to the signal line S, and the drain electrode is connected to the pixel electrode 12. Although not shown in FIG. 1, the counter electrode that forms a pair with the pixel electrode 12 is formed on a counter substrate (not shown). The array substrate 101 and the counter substrate are arranged at predetermined intervals so that their electrode surfaces face each other, and the periphery thereof is sealed with a sealing material. Then, the inside of both the substrates is filled with a liquid crystal material to be a light modulation layer.
[0022]
In the array substrate 101, the auxiliary capacitance 13 is connected in parallel to the pixel electrode 12 in order to maintain a potential relationship with a counter electrode (not shown). The auxiliary capacitor 13 forms a capacitor Cs between the pixel electrode 12 and auxiliary capacitor lines C1, C2,. The auxiliary capacitance line C is electrically connected to the auxiliary capacitance 13 of all pixels, and a constant voltage is applied from the external control circuit 102.
[0023]
A constant common voltage (Vcom) is applied from the external control circuit 102 to the counter electrode (not shown). The data signal written through the signal line S is held for one frame scanning period by the liquid crystal capacitor Clc and the capacitor Cs.
[0024]
The scanning line driving circuit 104 includes a timing circuit (shift register) and a buffer circuit (not shown), and based on the vertical clock signal CKV and the vertical start signal STV supplied from the external control circuit 102, the scanning lines G1, G2,. Output a sequential scanning signal to
[0025]
The signal line driver circuit 105 includes a timing circuit (shift register), a video bus, an analog switch circuit, and the like (not shown). The analog switch circuit is composed of TFTs, and each drain electrode is connected to signal lines S1, S2, S3. The timing circuit controls the analog switch circuit based on the horizontal clock signal CKH and the horizontal start signal STH supplied together with the data signal from the external control circuit 102, and sends the data signal to the signal lines S1, S2, S3,. Sampling to. The driving method of the signal line driver circuit may be a D / A conversion method in addition to the analog sample hold method.
[0026]
The external control circuit 102 includes a control IC, a D / A converter, a level shifter, and the like (not shown). The external control circuit 102 appropriately converts and processes an externally supplied reference clock signal, digital data signal, etc. An analog data signal, horizontal / vertical clock signal, start signal, power supply voltage (VDD1, VDD2), common voltage, and the like are output. The external drive circuit 102 and the array substrate 101 are electrically connected by an FPC (flexible wiring board) (not shown).
[0027]
A charge pump circuit 10 is disposed on the array substrate 101. The charge pump circuit 10 includes a main circuit disposed on the array substrate 101, an output side capacitor 15 provided between the output unit of the circuit and the ground (GND), and an input side capacitor provided in the clock input unit. 16 are both arranged outside the array substrate 101. In FIG. 1, the output-side capacitor 15 is drawn outside the array substrate in order to make it easy to understand the relationship between the output part of the circuit and the ground. The output side capacitor 15 is formed inside the external control circuit 102 by being taken into the circuit 102. However, these capacitors are only required to be arranged outside the array substrate 101, and need not be arranged in the external control circuit 102 as in this embodiment.
[0028]
The output side capacitor 15 is connected to the auxiliary capacitor 13 of each pixel via the auxiliary capacitor line C. In this way, the output voltage can be further stabilized by connecting the auxiliary capacitors 13 attached to all the pixels and the output-side capacitors 15 arranged outside the array substrate 101. If the sum of the capacities Cs of the auxiliary capacitors 13 is sufficiently large when the screen is densified or enlarged, the capacity of the output-side capacitors 15 arranged outside the array substrate 101 can be reduced, Or the output side capacitor | condenser 15 itself can be made unnecessary.
[0029]
Here, the circuit configuration and operation of the charge pump circuit 10 will be briefly described. 2A is a circuit configuration diagram of the charge pump circuit 10, and FIG. 2B is an equivalent circuit diagram thereof. In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.
[0030]
The charge pump circuit 10 includes two Nch TFTs 17 and 18, an input side capacitor 15 and an output side capacitor 16. Among these, the drain electrode side of the Nch TFT 17 is connected to the source electrode and the gate electrode of the Nch TFT 18.
[0031]
FIG. 3 is a timing chart showing the operation of the charge pump circuit 10. An example of the operation of the charge pump circuit 10 will be described with reference to FIG.
[0032]
First, a clock signal (CKU) having an amplitude VDD1 is input from the clock input unit 14. For example, a square wave having an amplitude of 10 V and a frequency of 1.5 MHz as shown in FIG. Further, for example, DC 10 V is input to the power input unit 21 as the power supply voltage VDD1.
[0033]
At the intermediate node pg, the following voltage is maintained according to the input waveform. That is, during a period when no clock signal is input from the clock input unit 14, a voltage obtained by subtracting the threshold value Vth of the Nch TFT 17 from VDD1 is maintained. For example, if the threshold voltage Vth of the Nch TFT 17 is 2V, the intermediate node pg is maintained at 8V (VDD2-Vth). Further, during the period when the clock signal is input from the clock input unit 14, an amplitude waveform boosted by the boost ratio α is obtained. For example, when the step-up ratio α is 1, an amplitude waveform of 8 to 18 V (VDD2−Vth + αVDD1) is obtained as shown in FIG. Then, the voltage of the output unit 22 is gradually increased as the clock signal is input to the clock input unit 14, and finally an output voltage of VDD2-2Vth + αVDD1 is obtained. For example, in FIG. 3C, when the threshold voltage Vth of the Nch TFT 18 is 2 V, 16 V is obtained as the output voltage.
[0034]
According to the liquid crystal display device 100 configured as described above, since the charge pump circuit 10 can be disposed on the array substrate 101, the external control circuit 102 can be made compact, and the external control circuit 102 can Since functional IC parts are not required, the cost can be reduced. In particular, when the charge pump circuit 10 arranged in the external control circuit 102 is directly transferred onto the array substrate 101, a large-capacity capacitor cannot be formed on the array substrate 101. It becomes difficult to suppress the fluctuation of the output voltage of. However, according to the configuration of the first embodiment, the output voltage can be stabilized as in the case where the charge pump circuit 10 is arranged in the external control circuit 102.
[0035]
Therefore, in the liquid crystal display device of Embodiment 1, not only can the output voltage be stabilized as in the conventional case, but also the external control circuit can be made compact and low in cost.
[0036]
[Embodiment 2]
Next, as a second embodiment, a liquid crystal display device will be described in which the output voltage can be stabilized without being affected by the TFT manufacturing process when the charge pump circuit is formed on the array substrate.
[0037]
Since the basic configuration of the liquid crystal display device according to the second embodiment is the same as that of the first embodiment, the description thereof will be omitted, and only the configuration of the charge pump circuit characteristic of the second embodiment will be described.
[0038]
FIG. 4 is a circuit configuration diagram of the charge pump circuit according to the second embodiment. The charge pump circuit 20 includes an Nch TFT 25, an Nch TFT 26, a Pch TFT 27, input side capacitors 29 and 32, and an output side 35.
[0039]
The Nch TFT 26 and the Pch TFT 27 are connected in series, and the drain electrode side of the Nch TFT 25 is connected to the respective gate electrodes of the Nch TFT 26 and the Pch TFT 27 through the intermediate node pg. A clock signal (CKU) is supplied from the clock input unit 28 to the gate electrodes of the Nch TFT 26 and the Pch TFT 27 via the input side capacitor 29. Further, an inverted clock signal (/ CKU) of the clock signal is input from the clock input unit 31 to the intermediate node ps that is an intermediate connection point between the Nch TFT 26 and the Pch TFT 27 via the input side capacitor 32.
[0040]
Also in the second embodiment, the capacitors arranged in the clock input unit and the output unit of the charge pump circuit 20 are arranged outside the array substrate. That is, the input side capacitors 29 and 32 shown in FIG. 4 and the output side capacitor 35 provided between the output unit 34 and the ground are both disposed outside the array substrate 101.
[0041]
FIG. 5 is a timing chart showing the operation of the charge pump circuit 20. An operation example of the charge pump circuit 20 will be described with reference to FIG.
[0042]
First, a clock signal (CKU) having an amplitude Vs is input from the clock input unit 28, and an inverted clock signal (/ CKU) having the same amplitude Vs is input from the clock input unit 31. For example, as shown in FIGS. 5A and 5B, a square wave having an amplitude of 10 V and a frequency of 1.5 MHz and its inverted square wave are input. Further, for example, DC 10 V is input to the input unit 33 as the power supply voltage VDD.
[0043]
At the intermediate node pg, the following voltage is maintained according to the input clock signal (CKU). That is, during a period when the clock signal (CKU) is not input, a voltage subtracted from VDD by the threshold value Vth of the Nch TFT 25 is maintained. For example, if the threshold Vth of the Nch TFT 25 is 2V, the intermediate node pg is maintained at 8V (VDD− | Vth |) as shown in FIG. Further, during the period in which the clock signal (CKU) is input, an amplitude waveform boosted by the boost ratio α is obtained. For example, when the step-up ratio α is 1, an amplitude waveform of 8 to 18 V (VDD + Vs− | Vth |) is obtained as shown in FIG. VDD is maintained at the intermediate node ps when the Nch TFT 26 is on, that is, during the period when the clock signal (CKU) is at Vs. For example, when the intermediate node pg is 18V and VDD is 10V, 10V is maintained. On the other hand, when the Nch TFT 26 is off, that is, in a period in which the clock signal (CKU) is GND, as shown in FIG. 5D, at the rising edge, only the amplitude (Vs) of the inverted clock signal (/ CKU). The potential is instantaneously raised, and then the potential drops. For example, when the amplitude of the inverted clock signal (/ CKU) is 10 V, the voltage is instantaneously raised to 20 V (VDD + Vs) at the rising edge, and then the potential gradually decreases. Then, a current flows from the intermediate node ps when the PchTFT 27 is on, that is, a period when the inverted clock signal (/ CKU) is Vs, and the voltage (VDD + Vs) at the intermediate node ps at this time is output to the output unit 34. Voltage. For example, when the intermediate node pg is 8V and the ps is 20V, 20V is obtained as the output voltage.
[0044]
In FIG. 4, when the threshold value Vth of the Nch TFT 26 becomes larger than, for example, a design value due to variations in transistor characteristics, VDD− | Vth | For this reason, only the output from the Nch TFT 26 cannot supply a necessary output voltage to the drive circuit, and the circuit cannot be operated normally. However, in the charge pump circuit 20 of the second embodiment, the potential is instantaneously raised by the amplitude of the inverted clock signal (/ CKU) regardless of the fluctuation of the threshold value Vth of the Nch TFT 26. By taking out the voltage (VDD + Vs) at the intermediate node ps as the output voltage, a stable output voltage can always be obtained.
[0045]
Therefore, in the liquid crystal display device of Embodiment 2, the output voltage from the charge pump circuit can be stabilized without being affected by the TFT manufacturing process.
[0046]
Also in the second embodiment, the charge pump circuit is arranged on the array substrate, and a large-capacity capacitor connected to the input / output unit is arranged outside the array substrate. By arranging a sufficiently large capacitor, the output voltage can be stabilized, and the external control circuit can be made compact and low in cost.
[0047]
[Embodiment 3]
Next, as a third embodiment, when a charge pump circuit is formed on an array substrate as in the second embodiment, an output voltage can be stabilized without being affected by a TFT manufacturing process. The display device will be described.
[0048]
Note that the basic configuration of the liquid crystal display device according to the third embodiment is the same as that of the first embodiment, and therefore the description thereof is omitted. Only the configuration of the charge pump circuit characteristic of the third embodiment will be described.
[0049]
FIG. 6 is a circuit configuration diagram of a charge pump circuit according to the third embodiment. The charge pump circuit 30 includes two diode circuits 36 and 38, an output side capacitor 42, and an input side capacitor 44. The diode circuit 36 includes an Nch TFT 136 and a Pch TFT 137 connected in series. The diode circuit 38 includes an Nch TFT 138 and a Pch TFT 139 that are also connected in series. Further, these two diode circuits 36 and 38 are connected in series. The charge pump circuit 30 is supplied with VDD as a power supply voltage from the outside, and the clock input unit 43 is supplied with a clock signal (CKU).
[0050]
Also in the charge pump circuit 30 of the third embodiment, both the output side capacitor 42 provided between the circuit output unit 41 and the ground (GND) and the input side capacitor 44 provided in the clock input unit 43 are both Arranged outside the array substrate 101.
[0051]
In the diode circuits 36 and 38 configured as described above, the threshold value of the two TFTs having different polarities constituting the circuit can be generally expressed as Vthn (NchTFT) + Vthp (PchTFT). Even if the threshold value of the Nch TFT or the Pch TFT deviates from the design value due to a variation in the manufacturing process, the value of Vthn + Vthp is constant. Therefore, a stable voltage can always be output from the charge pump circuit 30 without being affected by variations in the manufacturing process.
[0052]
For example, in one embodiment using the charge pump circuit 30 of FIG. 6, the same is true when Vthn = 2.5V and Vthp = −1.5V, and when Vthn = 1.5V and Vthp = −2.5V. Output voltage of.
[0053]
Incidentally, as a comparative example, the two diode circuits 36 and 38 of FIG. 6 are configured by Pch TFTs of the same channel and operated under the same conditions. When Vthn = 2.5V and Vthp = −1.5V, Vthn = 1.5V, Vthp = −2.5V, the output voltage is 2V smaller, and display unevenness may be visible on the screen.
[0054]
Therefore, also in the liquid crystal display device of Embodiment 3, the output voltages Vg1 and Vg2 from the charge pump circuit can be stabilized without being affected by the TFT manufacturing process.
[0055]
Also in the third embodiment, since the charge pump circuit is arranged on the array substrate and the large-capacity capacitor connected to the input / output unit is arranged outside the array substrate, the same as in the first embodiment. By arranging a sufficiently large capacitor, the output voltage can be stabilized, and the external control circuit can be made compact and low in cost.
[0056]
In the two diode circuits 36 and 38 shown in FIG. 6, the Nch TFT and the Pch TFT are connected in series. However, as shown in FIG. 7, the Nch TFT and the Pch TFT are connected in parallel, and these two diode circuits 46 are connected. The same effect can be obtained also when the configuration is made such that 47 and 47 are connected in series.
[0057]
Further, another charge pump circuit may be added to the circuit of FIG. 6 so that the power supply potential of the scanning line driver circuit 104 can be adjusted.
[0058]
FIG. 8 is a circuit configuration diagram showing an application example of the charge pump circuit according to the third embodiment. In FIG. 8, the configuration of the added charge pump circuit 40 is the same as that in which the arrangement of the Nch TFT and the Pch TFT of the two diode circuits 36 and 38 included in the charge pump circuit 30 is exchanged, and generates a negative voltage. is doing. The charge pump circuits 30 and 40 are used as a power source, and an operational amplifier 50 that is also composed of TFTs is arranged to adjust the output voltage. Here, the power supply voltage VDD supplied from the outside is used as the reference voltage. With such a circuit configuration, the influence of the TFT manufacturing process can be almost eliminated, and the output voltages Vg1 and Vg2 can be stabilized. Note that the operational amplifier 50 shown in FIG. 8 may be connected to the charge pump circuit of another embodiment.
[0059]
[Embodiment 4]
Next, as a fourth embodiment, a liquid crystal display device in which a circuit such as a charge pump circuit can be arranged on an array substrate without increasing the frame will be described.
[0060]
FIG. 9 is a circuit configuration diagram of the liquid crystal display device according to the fourth embodiment, and particularly shows a circuit arrangement on the array substrate. In FIG. 9, the same parts as those in FIG.
[0061]
As shown in FIG. 9, the charge pump circuit 200 is disposed in a region A facing the pixel unit 103 with respect to the region on the array substrate 101 where the scanning line driving circuit 104 is disposed. A clock signal and a power supply voltage to the charge pump circuit 200 are supplied through the external signal line 115 and the external power supply line 116, and an output voltage from the charge pump circuit 200 is supplied to the scan line driving circuit 104 and the internal voltage source lines 117 and 118. The signal is supplied to the signal line driver circuit 105. Although not shown, capacitors connected to the clock input unit and output unit of the charge pump circuit 200 are arranged outside the array substrate 101 as in the first embodiment.
[0062]
In the active matrix type liquid crystal display device as in Embodiment 4, it is often unnecessary to arrange the scanning line driving circuit 104 and the signal line driving circuit 105 on both sides with respect to the pixel portion 103, but the frame is to the outside. This is necessary on both sides of the pixel portion 103 due to problems such as attachment of the pixel portion 103. Therefore, for example, when the charge pump circuit 10 is arranged on the scanning line driving circuit 104 side as shown in FIG. 1, the frame must be enlarged, but when it is arranged in the area A secured in advance as shown in FIG. The charge pump circuit can be arranged without enlarging the frame.
[0063]
FIG. 10 is a circuit configuration diagram showing an example in which a bypass capacitor 201 is arranged instead of the charge pump circuit 200. Also in this case, the bypass capacitor 201 can be arranged on the array substrate 101 without increasing the frame.
[0064]
【The invention's effect】
  In the invention of claim 1,Since a necessary output voltage can be obtained regardless of variations in the TFT threshold value, the output voltage from the charge pump circuit can be stabilized without being affected by the TFT manufacturing process.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a liquid crystal display device according to a first embodiment.
FIG. 2 is a circuit configuration diagram of the charge pump circuit shown in FIG.
FIG. 3 is a timing chart showing an operation of the charge pump circuit shown in FIG. 2;
FIG. 4 is a circuit configuration diagram of a charge pump circuit according to a second embodiment.
FIG. 5 is a timing chart showing the operation of the charge pump circuit shown in FIG. 4;
FIG. 6 is a circuit configuration diagram of a charge pump circuit according to a third embodiment.
7 is a circuit configuration diagram showing another configuration example of the charge pump circuit shown in FIG. 6;
FIG. 8 is a circuit configuration diagram showing an application example of a charge pump circuit according to a third embodiment.
FIG. 9 is a circuit configuration diagram of a liquid crystal display device according to a fourth embodiment.
10 is a circuit configuration diagram showing another configuration example of a liquid crystal display device according to Embodiment 4. FIG.
[Explanation of symbols]
10, 20, 30, 40, 200 ... charge pump circuit, 11 ... TFT
12 ... Pixel electrode, 13 ... Auxiliary capacitance, 17, 25, 26 ... Nch TFT
18, 27 ... Pch TFT, 36, 38, 46, 47 ... Diode circuit
101 ... Array substrate, 102 ... External control circuit, 103 ... Pixel unit
104: Scanning line driving circuit, 105 ... Signal line driving circuit

Claims (1)

A plurality of scanning lines and a plurality of signal lines intersecting each other, a switch element disposed at each intersection of these lines, a first substrate including a pixel electrode connected to the switch element, the pixel electrode, A second substrate including opposing counter electrodes, a display panel having a light modulation layer held between the first substrate and the second substrate, and a signal line drive for supplying a data signal to the signal line In a flat display device comprising: a circuit; a scanning line driving circuit for supplying a scanning signal to the scanning line; and an external control circuit for supplying a predetermined signal and potential to the signal line driving circuit and the scanning line driving circuit.
In the voltage source circuit included in the external control circuit, a first thin film transistor and a second thin film transistor having different polarities are connected in series, and the signal line driving circuit or the scanning line driving circuit is driven through a first capacitor. A first input portion for inputting a clock signal used in the operation is connected to gate electrodes of the first thin film transistor and the second thin film transistor, and an inverted clock signal of the clock signal is supplied through a second capacitor. A second input portion for inputting is connected to an intermediate connection point where a drain electrode of the first thin film transistor and a source electrode of the second thin film transistor are connected, and a power supply voltage is connected to the source electrode of the first thin film transistor. And the output part of the voltage source circuit is configured as the drain electrode of the second thin film transistor,
The voltage source circuit is disposed on the first substrate, and a capacitor between the output part of the voltage source circuit and the ground, and the first capacitor and the second capacitor are disposed on the first substrate. A flat display device characterized by being arranged outside.

Images