JP4619074B2 - Plasma display device - Google Patents

Description

  The present invention relates to a plasma display device using a plasma display panel.

  In the plasma display apparatus, one field (or one frame) in a video signal is composed of a plurality of subfields each including an address period and a sustain period, so that gradation display is performed. During the address period, each discharge cell corresponding to each pixel of the plasma display panel is selectively discharged based on the input video signal, so that a lighting mode state where wall charges exist and a light-off mode state where wall charges do not exist Set to one of the states. In the sustain period, only the discharge cells set in the lighting mode state are repeatedly subjected to the sustain discharge for the number of times corresponding to the weight of the subfield, and the light emission state associated with the discharge is maintained. A reset period for initializing the state of all discharge cells is provided immediately before the address period of each subfield. In the reset period, first, a write reset discharge for causing wall charges to be formed in all the discharge cells is generated, and then an erase reset discharge for erasing the wall charges formed in all the discharge cells is generated. By doing so, all the discharge cells are initialized to the extinguishing mode. However, the light emission associated with a series of these reset discharges is not related to the display image, and is also generated simultaneously in all discharge cells, so that the contrast of the display image, particularly an image representing a dark scene is being displayed. Dark contrast is reduced. In view of this, there has been proposed a driving method in which the number of reset discharges is reduced to one in one field (or one frame) display period to suppress a reduction in contrast (see, for example, Patent Document 1).

However, if the number of reset discharges is set to one, a discharge delay occurs in the various discharges in the subsequent address period and sustain period. Therefore, various drive pulse pulses applied to the plasma display panel to cause various discharges. It is necessary to widen the width. Therefore, since the address period and the sustain period become longer as the pulse width is increased, it is difficult to increase the number of display gradations by increasing the number of subfields.
JP 11-65517 A

  The present invention has been made to solve such a problem, and an object thereof is to provide a plasma display device capable of increasing the number of display gradations.

A plasma display device according to a first aspect of the present invention is a display cell having a discharge space at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in the intersecting direction. A plasma display device equipped with a plasma display panel in which a magnesium oxide crystal that emits cathode luminescence having a peak in a wavelength range of 200 to 300 nm when excited by irradiation with an electron beam is provided in the display cell. A magnesium oxide layer formed on a surface in contact with the discharge space in each, and one field in the video signal is composed of a plurality of subfields, and one row electrode of the row electrode pair in an address period of each of the subfields A pixel corresponding to pixel data based on a video signal while applying a scanning pulse to In each of the subfields, an address means for selectively generating an address discharge in each display cell by applying a data pulse to the column electrode to form wall charges in the display cell, and the row electrode pair in each subfield. a sustain means for only a sustain discharge said display cells formed of the wall charges by applying a sustain pulse to each prior to before Symbol address period of the first subfield of the display period of the one field, all have a, and reset means allowed to rise to reset discharge in all the display cells by applying a reset pulse to said row electrode pairs, wherein the reset pulse, increasing the voltage is in a convex shape over time The leading edge that reaches the predetermined first voltage value and the voltage gradually decreases in a concave shape as time elapses. And a rear edge which lead to value.

  In driving a plasma display panel including a display cell formed with a magnesium oxide layer including a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence emission having a peak in a wavelength range of 200 to 300 nm. First, a reset discharge is generated in all display cells by applying a reset pulse to all the row electrodes. Next, an address discharge is selectively generated in each display cell by applying a scan pulse to one row electrode of the row electrode pair and applying a pixel data pulse corresponding to pixel data based on the video signal to the column electrode. Thus, wall charges are formed in the display cell. Then, by applying a sustain pulse to each row electrode, only the display cells in which wall charges are formed are subjected to a sustain discharge.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display device according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, a row electrode X drive circuit 51, a row electrode Y drive circuit 53, a column electrode drive circuit 55, and a drive control circuit 56.

In the PDP 50, column electrodes D _{1 to} D _m arranged to extend in the vertical direction (vertical direction) of the two-dimensional display screen, and row electrodes X ₁ to X _m arranged to extend in the horizontal direction (horizontal direction), respectively. X _n and row electrodes Y _{1 to} Y _n are formed. In this case, row electrode pairs (X ₁ , Y ₁ ), (X ₂ , Y ₂ ), (X ₃ , Y ₃ ),..., (X _n , Y _n ) that form pairs between adjacent ones. Are responsible for the first display line to the nth display line in the PDP 50. A display cell PC serving as a pixel is formed at each crossing portion (a region surrounded by an alternate long and short dash line in FIG. 1) between each display line and each of the column electrodes D _{1 to} D _m . That is, the PDP 50, display cells PC _{1, 1} to PC ₁ belonging to the first display _{line, m,} display cells PC ₂ belonging to the second display line, 1～PC2, _m, · · · ·, n-th display line display cell PC _n, 1~PC _n, each of _m is what is arranged in a matrix belonging to.

  FIG. 2 is a front view schematically showing the internal structure of the PDP 50 as viewed from the display surface side.

In FIG. 2, the crossing portions of each of the column electrodes D _{1 to} D ₃ of the PDP 50 and the first display line (Y ₁ , X ₁ ) and the second display line (Y ₂ , X ₂ ) are extracted and shown. Is. 3 is a view showing a cross section of the PDP 50 taken along the line V3-V3 in FIG. 2, and FIG. 4 is a view showing a cross section of the PDP 50 taken along the line W2-W2 in FIG.

As shown in FIG. 2, each row electrode X has a bus electrode Xb extending in the horizontal direction of the two-dimensional display screen and a T provided in contact with a position corresponding to each display cell PC on the bus electrode Xb. And a transparent electrode Xa having a letter shape. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the two-dimensional display screen, and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each display cell PC on the bus electrode Yb. Is composed of. The transparent electrodes Xa and Ya are made of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in FIG. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb are arranged on the back side of the front transparent substrate 10 whose front side is the display surface of the PDP 50. Is formed. At this time, the transparent electrodes Xa and Ya in each row electrode pair (X, Y) extend to the paired row electrode side, and the top sides of the wide portions pass through the discharge gap g1 having a predetermined width. Facing each other. On the back side of the front transparent substrate 10, there is a two-dimensional space between a pair of row electrodes (X ₁ , Y ₁ ) and a row electrode pair (X ₂ , Y ₂ ) adjacent to the row electrode pair. A black or dark light absorbing layer (light shielding layer) 11 extending in the horizontal direction of the display screen is formed. Further, a dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pair (X, Y). As shown in FIG. 3, on the back side of the dielectric layer 12 (the surface opposite to the surface in contact with the row electrode pair), the light absorbing layer 11 and bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are provided. A raised dielectric layer 12A is formed in a portion corresponding to the region where the and are formed. The surface of the dielectric layer 12 and the raised dielectric layer 12A includes a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak in the wavelength range of 200 to 300 nm. A magnesium oxide layer 13 is formed.

  On the other hand, on the rear substrate 14 arranged in parallel with the front transparent substrate 10, each of the column electrodes D is disposed at a position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). , Y). On the back substrate 14, a white column electrode protective layer 15 that covers the column electrode D is further formed. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 includes a horizontal wall 16A extending in the horizontal direction of the two-dimensional display screen at a position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and intermediate portions between the column electrodes D adjacent to each other. A ladder wall is formed by the vertical wall 16B extending in the vertical direction of the two-dimensional display screen at the position. A ladder-shaped partition wall 16 as shown in FIG. 2 is formed for each display line of the PDP 50, and a gap SL as shown in FIG. 2 exists between the partition walls 16 adjacent to each other. The ladder-shaped partition 16 partitions the display cell PC including the independent discharge space S and the transparent electrodes Xa and Ya. In the discharge space S, a discharge gas containing xenon gas is enclosed. A phosphor layer 17 is formed on the side surface of the horizontal wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protection layer 15 in each display cell PC so as to cover all of these surfaces as shown in FIG. . The phosphor layer 17 is actually composed of three types: a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light. As shown in FIG. 3, the magnesium oxide layer 13 is closed between the discharge space S and the gap SL of each display cell PC by contacting the horizontal wall 16A. On the other hand, as shown in FIG. 4, since the vertical wall 16B is not in contact with the magnesium oxide layer 13, there is a gap r1 therebetween. That is, the discharge spaces S of the display cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through the gap r1.

  Here, the magnesium oxide crystal forming the magnesium oxide layer 13 is a single crystal obtained by vapor phase oxidation of magnesium vapor generated by heating magnesium, for example, a wavelength region 200 excited by irradiation with an electron beam. It includes a vapor phase magnesium oxide crystal that performs CL emission having a peak within ˜300 nm (particularly, around 235 nm within 230 to 250 nm). This vapor phase magnesium oxide crystal has a multiple crystal structure in which cubic crystals as shown in the SEM photograph image of FIG. 5A are fitted to each other, or a cubic single crystal structure as shown in the SEM photograph image of FIG. 5B. , A magnesium single crystal having a particle size of 2000 angstroms or more is included. Such a magnesium single crystal is characterized by high purity and fine particles compared to magnesium oxide produced by other methods, and less aggregation of the particles, as will be described later. This contributes to the improvement of the discharge characteristics. In this example, a vapor phase magnesium oxide single crystal having an average particle size measured by the BET method of 500 angstroms or more, preferably 2000 angstroms or more is used. Then, the magnesium oxide layer 13 is formed by adhering such a magnesium oxide single crystal to the surface of the dielectric layer 12 as shown in FIG. 6 by spraying, electrostatic coating or the like. A thin film magnesium oxide layer is formed on the surfaces of the dielectric layer 12 and the raised dielectric layer 12A by vapor deposition or sputtering, and a magnesium oxide single crystal is deposited thereon to form a magnesium oxide layer 13. You may do it.

  The drive control circuit 56 supplies various control signals to drive the PDP 50 having the above structure in accordance with a light emission drive sequence employing a subfield method (subframe method) as shown in FIG. This is supplied to each of the circuit 53 and the column electrode drive circuit 55. In the light emission drive sequence shown in FIG. 7, the address process W, the sustain process I, and the erase process E are sequentially executed in each of the N subfields SF1 to SF (N) within one field (one frame) display period. . However, the reset process R is executed prior to the address process W only in the first subfield SF1.

  The row electrode X drive circuit 51 includes a reset pulse generation circuit and a sustain pulse generation circuit. The reset pulse generation circuit of the row electrode X drive circuit 51 generates a reset pulse (described later) to be applied to the row electrode X of the PDP 50 in the reset process R. The sustain pulse generation circuit of the row electrode X drive circuit 51 generates a sustain pulse (described later) to be applied to the row electrode X in the sustain process I. The row electrode Y drive circuit 53 includes a reset pulse generation circuit, a scan pulse generation circuit, and a sustain pulse generation circuit. The reset pulse generation circuit of the row electrode Y drive circuit 53 generates a reset pulse (described later) to be applied to the row electrode Y of the PDP 50 in the reset process R. The scan pulse generation circuit of the row electrode Y drive circuit 53 generates a scan pulse (described later) to be applied to the row electrode Y of the PDP 50 in the address process W. The sustain pulse generation circuit of the row electrode Y drive circuit 53 generates a sustain pulse (described later) to be applied to the row electrode Y in the sustain process I.

  The column electrode drive circuit 55 generates a pixel data pulse to be applied to the column electrode D of the PDP 50 in the address process W.

  FIG. 8 is a diagram showing application timings of various drive pulses applied to the column electrodes D and the row electrodes X and Y of the PDP 50 by extracting SF1 from the subfields SF1 to SF (N).

First, in the reset process R, as shown in FIG. 8, the row electrode Y drive circuit 53 causes the voltage on the row electrode Y to gradually rise in a convex shape over time and reach a positive peak voltage value Vry. a front edge, then slowly the voltage value applied simultaneously to the reset pulse RP _Y having a rear edge reaching the voltage value Vsel of a negative polarity is lowered concavely row electrodes Y ₁ to Y _n. The voltage value Vsel includes the voltage value on the row electrode Y when a negative-polarity scanning pulse (described later) is applied, and the voltage on the row electrode Y when no voltage is applied. The voltage between the values. The peak voltage value Vry is a voltage value larger than the voltage value on the row electrode Y when a sustain pulse described later is applied. The row electrode X driving circuit 51 applies a reset pulse RP _X having a negative voltage Vrx as shown in FIG. 8 to the row electrodes X _{1 to} X _{n over} the rising period of the voltage value in the reset pulse RPY.

Here, the occurrence between, all the display cells PC _{1, 1} to PC n, is weak write reset discharge between the row electrodes X and Y in the _m each reset pulse RP _X with reset pulse RP _Y is applied The After the end of the write reset discharge, a predetermined amount of wall charges is formed on the surface of the magnesium oxide layer 13 in the discharge space S of each display cell PC. That is, a positive charge is formed in the vicinity of the row electrode X on the surface of the magnesium oxide layer 13, and a negative charge is formed in the vicinity of the row electrode Y. Become. Thereafter, when the voltage of the reset pulse RP _Y gradually decreases from the peak voltage value Vry, a weak erase is performed between the row electrodes X and Y in each of the display cells PC _{1,1 to} PC _{n, m} during that time. A reset discharge occurs. Due to the erase reset discharge, the wall charges formed in all of the display cells PC _{1,1 to} PC _{n, m} disappear. That is, in the reset process R, all of the display cells PC _{1,1 to} PC _{n, m} are initialized to a so-called extinguishing mode in which the amount of wall charges does not reach a predetermined amount.

Next, in the address process W, the column electrode driving circuit 55 generates pixel data pulses for setting whether or not each display cell PC is caused to emit light in the subfield based on the input video signal. For example, the column electrode drive circuit 55 generates a pixel data pulse for each display cell PC with a high voltage when the display cell PC emits light and a low voltage when the display cell PC does not emit light. Then, the column electrode driving circuit 55, one display line such pixel data pulses (m in the number) per time, the pixel data pulse group DP _1, DP _2, · · ·, sequentially as DP _n, the column electrodes D ₁ to D _m Apply to. During this time, the row electrode Y drive circuit 53 sequentially applies negative scan pulses SP to the row electrodes Y _{1 to} Y _n in synchronization with the timing of the pixel data pulse groups DP _{1 to} DP _n . At this time, the address discharge is selectively generated only in the display cell PC to which the scanning pulse SP is applied and the high-voltage pixel data pulse is applied, and the magnesium oxide layer 13 and the fluorescence in the discharge space S of the display cell PC are generated. A predetermined amount of wall charges is formed on the surface of each body layer 17. On the other hand, since the address discharge as described above is not generated in the display cell PC to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, the wall charge formation state up to that time is maintained. That is, by executing the address process W, each display cell PC is either in a lighting mode state where a predetermined amount of wall charges are present or in a light-off mode state where there is no predetermined amount of wall charges based on the input video signal It is set to one side.

Next, in the sustain process I, each of the row electrode X drive circuit 51 and the row electrode Y drive circuit 53 alternately repeats positive sustain pulses IP _X and IP _Y to the row electrodes X _{1 to} X _n and Y ₁ to Y ₁ . Apply to Y _n . The number of times that the sustain pulses IP _X and IP _Y are applied depends on the luminance weighting in each subfield. At this time, each time the sustain pulses IP _X and IP _Y are applied, only the display cell PC set in the lighting mode state in which a predetermined amount of wall charges is formed undergoes a sustain discharge. Accordingly, the phosphor layer 17 emits light and an image is formed on the panel surface.

Next, in the erasing step E, the row electrode Y drive circuit 53 applies a positive erasing pulse EP to all the row electrodes Y _{1 to} Y _n simultaneously. By applying the erase pulse EP, an erase discharge is generated in all the display cells PC, and all the wall charges remaining in each display cell PC are extinguished.

  Here, as described above, the vapor-phase magnesium oxide single crystal contained in the magnesium oxide layer 13 formed in each display cell PC is excited by electron beam irradiation and has a wavelength region as shown in FIG. CL light emission having a peak within 200 to 300 nm (particularly, around 235 nm within 230 to 250 nm) is performed. At this time, as shown in FIG. 10, the peak intensity of CL emission increases as the particle diameter of the vapor-phase-process magnesium oxide crystal increases. That is, when forming a vapor phase magnesium oxide crystal, if the magnesium is heated at a temperature higher than usual, the particle size 2000 as shown in FIG. 5A or FIG. A relatively large single crystal of angstroms or more is formed. At this time, since the temperature at which magnesium is heated is higher than usual, the length of the flame in which magnesium and oxygen react with each other also becomes longer. Therefore, the temperature difference between the flame and the surroundings becomes large, and therefore, the group of vapor-phase magnesium oxide single crystals having a large particle size has a higher energy level corresponding to 200 to 300 nm (especially around 235 nm). It is presumed that many single crystals are contained.

  FIG. 11 shows a discharge probability when a magnesium oxide layer is not provided in the display cell PC, a discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and 200 to 300 nm (especially 230 to 250 nm) by electron beam irradiation. It is a figure which shows the discharge probability in each case when the magnesium oxide layer containing the gaseous-phase magnesium oxide single crystal which produces CL light emission which has a peak in the vicinity of 235 nm is provided. In FIG. 11, the horizontal axis represents the discharge pause time, that is, the time interval from when a discharge occurs until the next discharge occurs.

  In this way, the gas phase that emits CL having a peak at 200 to 300 nm (particularly around 235 nm within 230 to 250 nm) by irradiation with an electron beam as shown in FIG. 5A or 5B in the discharge space S of each discharge cell PC. When the magnesium oxide layer 13 including the magnesium oxide single crystal is formed, the discharge probability is increased as compared with the case where the magnesium oxide layer is formed by a conventional vapor deposition method. As shown in FIG. 12, the above-mentioned vapor-phase magnesium oxide single crystal is generated in the discharge space S as the intensity of CL emission having a peak particularly at 235 nm when irradiated with an electron beam increases. The discharge delay can be shortened.

Therefore, in order to achieve contrast improvement by suppressing the light emission accompanying the reset discharge not involved in displaying an image, the row electrodes are applied to the Y voltage transition of the reset pulse RP _Y as shown in FIG. 8, a voltage is convex with the passage of time Even if the reset discharge is weakened gently by the front edge portion that rises to the rear and the rear edge portion that falls concavely , the weak reset discharge can be stably generated in a short time. In particular, each display cell PC employs a structure in which a discharge is locally generated in the vicinity of the discharge gap between the T-shaped transparent electrodes Xa and Ya. Reset discharge is suppressed and strong erroneous discharge between the column electrode and the row electrode is also prevented.

In addition, since the discharge probability is increased (the discharge delay is reduced), the priming effect by the write reset discharge and the erase reset discharge in the reset process R is sustained for a long time, and therefore, it occurs in the address process W. The address discharge and the sustain discharge generated in the sustain process I are accelerated. As a result, the pulse width Wa of each of the pixel data pulse DP and the scanning pulse SP as shown in FIG. 8 applied to the column electrode D and the row electrode Y to cause the address discharge can be shortened. It is possible to reduce the processing time spent in this address process W by the amount. Further, the pulse width Wb of the sustain pulse IP _Y applied to the row electrode Y to cause the sustain discharge as shown in FIG. Can be shortened.

  Accordingly, it is possible to increase the number of subfields to be provided in one field (or one frame) display period by the amount of reduction of the processing time spent in each of the address process W and the sustain process I. Can be increased.

Further, as the PDP 50 in the above embodiment, the row electrode pairs (X ₁ , Y ₁ ), (X ₂ , Y ₂ ), (X ₃ , Y ₃ ),..., (X _n , Y _n ) are used. A structure in which the display cell PC is formed between the row electrode X and the row electrode Y that are paired with each other is adopted, but a structure in which the display cell PC is formed between all the adjacent row electrodes is adopted. May be. In short, between the row electrodes X ₁ and Y ₁ , between the row electrodes Y ₁ and X _2, between the row electrodes X ₂ and Y ₂ ,..., Between the row electrodes Y _n−1 and X _n , the row electrode X A structure in which a display cell PC is formed between _n and Y _n may be employed.

  The PDP 50 in the above embodiment employs a structure in which the row electrodes X and Y are formed on the front transparent substrate 10 and the column electrode D and the phosphor layer 17 are formed on the rear substrate 14. Alternatively, a structure in which the row electrodes X and Y are formed together with the column electrodes D and the phosphor layer 17 is formed on the back substrate 14 may be adopted.

It is a figure which shows schematic structure of the plasma display apparatus by this invention. It is a front view which shows typically the internal structure at the time of seeing PDP5 mounted in the plasma display apparatus of FIG. 1 from the display surface side. It is a figure which shows the cross section on the V3-V3 line | wire shown by FIG. It is a figure which shows the cross section on the W2-W2 line | wire shown by FIG. It is a figure which shows the magnesium oxide single crystal which has a cubic multiple crystal structure. It is a figure which shows the magnesium oxide single crystal which has a cubic multiple crystal structure. It is a figure which shows the form at the time of making a magnesium oxide single crystal powder adhere to the surface of a dielectric material layer and a raising dielectric material layer, and forming a magnesium oxide layer. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows the various drive pulses applied to PDP according to the light emission drive sequence shown in FIG. 7, and its application timing. It is a graph which shows the relationship between the particle size of magnesium oxide single crystal powder, and the wavelength of CL light emission. It is a graph which shows the relationship between the particle size of magnesium oxide single crystal powder, and the intensity | strength of CL light emission of 235 nm. The figure which shows the discharge probability when a magnesium oxide layer is not provided in the display cell, the discharge probability when a magnesium oxide layer is constructed by a conventional vapor deposition method, and the discharge probability when a magnesium oxide layer having a multiple crystal structure is constructed, respectively. It is. It is a figure which shows the correspondence of CL light emission intensity of a 235 nm peak, and discharge delay time.

Explanation of symbols

13 Magnesium oxide layer 50 PDP
51 row electrode X drive circuit 53 row electrode Y drive circuit 55 column electrode drive circuit 56 drive control circuit

Claims (3)

Plasma having mounted thereon a plasma display panel in which a display cell having a discharge space is formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes extending in the crossing direction. A display device,
A magnesium oxide layer that is excited by electron beam irradiation and emits cathodoluminescence light having a peak in a wavelength range of 200 to 300 nm, a magnesium oxide layer formed on a surface in contact with the discharge space in each of the display cells;
One field in the video signal is composed of a plurality of subfields, and in the address period of each of the subfields, a scanning pulse is applied to one row electrode of the row electrode pair and pixel data corresponding to pixel data based on the video signal Address means for selectively generating an address discharge in each of the display cells by applying a pulse to the column electrodes to form wall charges in the display cells;
In each of the subfields, sustain means for sustaining only the display cells in which the wall charges are formed by applying a sustain pulse to each of the row electrode pairs;
Prior before Symbol address period of the first subfield of the display period of the one field, and reset means allowed to rise to reset discharge in all the display cells by applying a reset pulse to all the row electrode pairs, I have a,
The reset pulse has a leading edge where the voltage gradually increases in a convex shape as time elapses and reaches a predetermined first voltage value, and the voltage gradually decreases in a concave shape as time elapses. A plasma display device having a trailing edge reaching a voltage value . The plasma display apparatus according to claim 1, wherein the first voltage value is larger than a voltage value on the row electrode when the sustain pulse is applied . The second voltage value is a voltage value between a voltage value on the row electrode when no voltage is applied to the row electrode and a voltage value on the row electrode when the scan pulse is applied. the plasma display apparatus of claim 1, wherein a is.