CN100479085C - Plasma display device and method of driving plasma display panel - Google Patents

Abstract

Provided are a plasma display and a driving method of a plasma display panel for improving contrast without degrading image quality. Each display unit formed on the plasma display panel has a magnesium oxide layer containing magnesium oxide crystals. The magnesium oxide crystal is excited by an electron beam irradiated thereon to emit cathode emission light having a peak in a wavelength range of 200 to 300 nm. In order to trigger reset discharges in all display cells, a reset pulse with a specific pulse waveform is applied to each row electrode pair of the plasma display panel. The voltage value of the reset pulse changes slowly over time to reach a peak voltage.

Description

Plasma display and method of driving plasma display panel

Background of the invention

1. Technical field

The present invention relates to a plasma display for displaying images and a method of driving a plasma display panel.

2. Description of related technologies

Various types of flat panel displays have been commercialized. One of them is an AC type (AC discharge type) plasma display panel. The plasma display panel has two substrates, namely, a front glass substrate and a rear glass substrate facing each other and disposed with a predetermined gap. The front glass substrate is the display surface of the plasma display panel. On the inner surface of the front glass substrate (ie, the surface facing the rear glass substrate), a plurality of row electrode pairs extending parallel to each other are formed as sustain electrode pairs. On the rear glass substrate, a plurality of column electrodes are formed as address electrodes extending perpendicular to the pair of row electrodes. A fluorescent material is coated on the rear glass substrate. A display unit that is a pixel is formed at an intersection of a row electrode pair and a column electrode when viewed from the display surface side. A multi-gray-scale (gradation) driving sequence using a sub-field method is performed for such a plasma display panel in order to produce a desired halftone display luminance that is faithful to an input video signal.

In the gradation drive sequence based on the subfield method, one field of a video signal is divided into a plurality of subfields, and a predetermined number of light emissions (or light emissions for a predetermined period of time) are assigned to each subfield. Display driving is performed for one field using these subfields. In each subfield, an address process and a sustain process are sequentially performed. During addressing, discharge is selectively performed between row and column electrodes in each display unit according to an input video signal to form (or erase) a predetermined amount of wall charges. This discharge is called selective discharge. During the sustain process, only those display cells having wall charges are forced to discharge repeatedly to maintain the light emission state associated with the discharge. Before the addressing process, an initialization process is performed at least in the first subfield. During the initialization process, a reset discharge is generated between two electrodes in each row electrode pair of all display cells to initialize the amount of wall charges left in all display cells.

The reset discharge is a relatively strong discharge and does not contribute at all to the image content to be displayed, so that the light emission associated with this discharge reduces the contrast of the image.

Another type of plasma display has been proposed (see FIG. 13 in Japanese Patent Laid-Open No. 2001-188509) to solve this problem. The plasma display uses T-shaped row electrodes for generating the discharge. A reset pulse is applied to the T-shaped row electrodes (see FIG. 7 in Japanese Patent Laid-Open No. 2001-188509), the voltage of which is slowly changed on the rising side to generate a weak reset discharge. Due to the weak reset discharge, the light emission luminance associated with the reset discharge is reduced so that the contrast is enhanced. In order to generate a reset discharge in all display cells using such a reset pulse, the peak voltage of the reset pulse must be relatively high.

However, the high peak voltage of the reset pulse produces a strong discharge not only between the two electrodes of each row electrode pair but also between the row and column electrodes. This results in lower contrast. Furthermore, the strong discharges generated between the row and column electrodes generate more wall charges than desired. This can cause erroneous selective discharge during the addressing process. As a result, the quality of the displayed image is reduced.

Summary of invention

An object of the present invention is to provide a plasma display capable of improving image contrast without degrading image quality.

Another object of the present invention is to provide a driving method of a plasma display panel capable of improving image contrast without sacrificing image quality.

According to a technical solution of the present invention, a plasma display with a plasma display panel is provided. The plasma display panel has a plurality of row electrode pairs extending in a row direction and a plurality of column electrodes extending perpendicular to the row electrode pairs. A display cell having a discharge space is formed at each intersection of a row electrode pair and a column electrode. A magnesium oxide layer is formed in each display cell. The magnesium oxide layer has magnesium oxide crystals that emit cathode emission (CL) light having a peak in a wavelength range of 200-300 nm when irradiated and excited by an electron beam. The plasma display also includes a reset device for applying reset pulses to the row electrode pairs, so as to generate reset discharges in the discharge spaces of all display units to initialize all display units. The reset pulse may be applied to every two electrodes of each row electrode pair, or to one of the two electrodes of each row electrode pair. A reset pulse initializes all display units. The plasma display also includes addressing means for sequentially applying scan pulses to one electrode of each row electrode pair, and applying a data pulse corresponding to an input video signal to each column electrode to selectively display A selective discharge is generated in the display space of the unit to set each display unit to a lit state or a non-lit state. The plasma display further includes sustain means for applying sustain pulses to the row electrode pairs to generate sustain discharges in the discharge spaces in those display cells that have been set to the light emitting state. At least part of the reset pulse slowly changes its voltage over time. The sustain pulse may be applied to every two electrodes of each row electrode pair, or to one of the two electrodes of each row electrode pair. This plasma display can increase image contrast without reducing image quality.

According to the second technical solution of the present invention, a method for driving a plasma display panel is provided. The plasma display panel includes a plurality of row electrode pairs extending in a row direction and a plurality of column electrodes extending perpendicular to the row electrode pairs. A display cell is formed at each intersection of a pair of row electrodes and a column electrode. The display unit has a magnesium oxide layer and a discharge space. The magnesium oxide layer faces the discharge space. The magnesium oxide layer has magnesium oxide crystals. The magnesium oxide crystal is excited by an electron beam irradiated thereon to emit cathode luminescence light having a peak in a wavelength range between 200 and 300 nm. A driving method of a plasma display panel includes applying a reset pulse to a pair of row electrodes. A reset pulse may be applied to every two electrodes in each row electrode pair or to one of the two electrodes in each electrode pair. The voltage value of the reset pulse changes slowly for at least a certain period of time. The reset pulse generates reset discharges in the discharge spaces of all display cells to initialize all display cells. The plasma display panel driving method further includes sequentially applying scan pulses to one electrode in each row electrode pair, and applying a data pulse corresponding to an input video signal to each column electrode, so that in the display space of each display unit Selective discharge is selectively generated. Selective discharge sets each display cell to either a light-emitting state or a non-light-emitting state. The driving method of the plasma display panel further includes applying sustain pulses to the pair of row electrodes to generate sustain discharges in discharge spaces in those display cells that have been set to a light emitting state. Sustain pulses may be applied to every two electrodes in each row electrode pair, or to one of the two electrodes in each electrode pair.

According to the third technical solution of the present invention, a device is provided, including a plasma display panel, a magnesium oxide layer, and a reset device. The plasma display panel includes a plurality of row electrode pairs extending in a row direction and a plurality of column electrodes extending in a column direction. A plurality of display cells each having a discharge space are formed at each intersection of a pair of row electrodes and a column electrode. The magnesium oxide layer has magnesium oxide crystals formed in each display cell. Magnesium oxide crystals are excited by electron beams irradiated thereon to emit cathode emission light. The cathode emission light has a peak in the wavelength range of 200 to 300 nm. The reset means applies reset pulses to all the row electrode pairs to generate reset discharges in the discharge spaces of all the display cells to initialize all the display cells. The reset pulse may be applied to every two electrodes of each row electrode pair, or to one of the two electrodes of each row electrode pair. The reset pulse has a voltage value that varies slowly over a certain period of time.

These and other objects, aspects and advantages of the present invention will become apparent to those skilled in the art from the following detailed description and appended claims when the present invention is read and understood in conjunction with the accompanying drawings.

Brief description of the drawings

Fig. 1 schematically shows the structure of a plasma display according to an embodiment of the present invention;

Figure 2 is a partially enlarged front view of the PDP to show the internal structure of the PDP;

Fig. 3 is a sectional view taken along line III-III of Fig. 2;

Fig. 4 is a sectional view taken along line IV-IV of Fig. 2;

Figure 5A shows an example of a magnesium oxide single crystal;

Figure 5B shows another example of a magnesium oxide single crystal;

Fig. 6 is a schematic diagram showing how to apply the magnesium oxide single crystal of the vapor phase method on the surface of the dielectric layer by spraying, electrostatic coating, etc.;

Figure 7 shows an exemplary light emission drive sequence employed in the plasma display shown in Figure 1;

FIG. 8 is a diagram showing the timing of driving pulses applied to the PDP according to the light emission driving sequence shown in FIG. 7;

Fig. 9 is a graph showing the relationship between the wavelength of CL light and the intensity of CL light observed when a magnesium oxide single crystal is irradiated with an electron beam;

FIG. 10 is a graph showing the relationship between the diameter of magnesium oxide single crystal particles and the light intensity of CL at 235 nm;

11 is a graph showing the discharge probability when the display unit is not formed with a magnesium oxide layer, the discharge probability when the display unit is formed with a magnesium oxide layer according to a conventional vapor deposition method, and when the display unit is formed with an oxide layer containing a single crystal of magnesium oxide. A graph of discharge probability for a magnesium layer wherein the magnesium oxide single crystal contains CL light emission with a peak in the range of 200-300 nm when irradiated with an electron beam;

Fig. 12 is a graph showing the relationship between the CL light emission intensity with its peak at 235 nm and the discharge delay time;

Fig. 13 is a sectional view taken along line XIII-XIII of Fig. 2 to show another embodiment of the present invention; and

FIG. 14 is a sectional view taken along line XIV-XIV shown in FIG. 2 for the modified embodiment of FIG. 13 .

Detailed description of the invention

The structure of a plasma display 48 according to an embodiment of the present invention will be described below with reference to FIG. 1 .

The plasma display 48 includes a plasma display panel (PDP) 50 , an X electrode driver 51 , a Y electrode driver 53 , an address driver 55 and a drive control circuit 56 .

The PDP 50 has column electrodes D ₁ -D _m respectively extending in the vertical direction of the two-dimensional display screen, and row electrodes X ₁ -X _n and row electrodes Y ₁ -Y _n respectively extending in the horizontal direction of the display screen. The pair of row electrodes (Y ₁ , X ₁ ), (Y ₂ , X ₂ ), (Y ₃ , X ₃ )...and (Y _n , X _n ) form the first display line, the second display line on the PDP 50 , the third display line... and the nth display line. In a region where each display line intersects with each of the column electrodes D ₁ -D _m (the region surrounded by the dashed-dotted line in FIG. 1 ), a display unit PC as a pixel is formed. In other words, on the PDP 50, the display cells _PC1,1 - _{PC1,m belonging to the first display line,} the display cells _PC2,1 - _{PC2,m belonging to the second display line, ...} and The display cells PC _n,1 - PC _n,m belonging to the nth display line.

FIG. 2 is a partially enlarged schematic view showing the internal structure of the PDP 50 when viewed from the front surface side (ie, the display surface side). Specifically, the intersections of the column electrodes D ₁ -D ₃ with the first display line (Y ₁ , X ₁ ) and the second display line (Y ₂ , X ₂ ) are shown. 3 is a cross-sectional view of the PDP 50 taken along line III-III of FIG. 2, and FIG. 4 is a cross-sectional view of the PDP 50 taken along line IV-IV of FIG.

As shown in FIG. 2 , each row electrode X includes a bus electrode Xb extending in the horizontal direction of the display screen and a plurality of T-shaped transparent electrodes Xa arranged in contact with the bus electrode Xb. The position of each T-shaped transparent electrode Xa is determined corresponding to each display unit PC. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the display screen and a plurality of T-shaped transparent electrodes Ya arranged in contact with the bus electrode Yb. The position of each T-shaped electrode Ya is determined corresponding to each display unit PC. The transparent electrodes Xa, Ya are composed of a conductive transparent film such as ITO, and the bus electrodes Xb, Yb are composed of, for example, a metal film. A row electrode X and a row electrode Y are formed on the back surface of the front transparent substrate 10, as shown in FIG. The front side of the front transparent substrate 10 is a display screen of the PDP 50 . In each row electrode pair (X, Y), the transparent electrode Xa (or Ya) extends towards the opposite row electrode Y (or X), and the heads (wide parts) of the "T" transparent electrodes Xa and Ya are connected to each other Facing each other, the distance therebetween is a discharge gap g1 of a predetermined length. On the back side of the front transparent substrate 10, a black or dark light-absorbing layer (light-shielding layer) 11 is formed so that it is formed between the first row electrode pair (X ₁ , Y ₁ ) and the second row electrode pair (X ₂ , Y ₂ ) between the display screens extending horizontally. The second row electrode pair is an adjacent row electrode pair of the first row electrode pair. On the back side of the front transparent substrate 10, a dielectric layer 12 is also formed to cover the pair of row electrodes (X, Y). On the back side of dielectric layer 12 (the surface opposite to the surface contacting the pair of row electrodes), raised dielectric layer 12A is formed at a position corresponding to light shielding layer 11 and adjacent to bus electrodes Xb and Yb, as shown in FIG. 3 . What is formed on the dielectric layer 12 and the raised dielectric layer 12A is a magnesium oxide layer 13, the magnesium oxide layer 13 includes magnesium oxide crystals that are excited by an electron beam irradiated thereon to perform cathodoluminescence, and the peak wavelength of the light emission is at 200 to the range of 300nm. The magnesium oxide crystals include vapor phase method magnesium oxide crystals produced by magnesium oxide vapor produced by heating magnesium in a vapor phase. The vapor phase magnesium oxide crystal has various crystal structures, among which solid crystals are suitable for each other, for example, as shown in the SEM photograph in FIG. 5A, or a solid single crystal structure as shown in the SEM photograph in FIG. 5B. Their average particle diameter is 500 angstroms or more, preferably 2000 angstroms or more (measured by the BET method). As shown in FIG. 6, a vapor-phase method magnesium oxide single crystal 13B is applied on the surface of the dielectric layer 12 by a spray method, an electrostatic coating method, or the like, so that the magnesium oxide layer 13 is formed. Alternatively, a thin film magnesium oxide layer may be formed on the surface of the dielectric layer 12 by vapor deposition or sputtering, and a vapor phase method of magnesium oxide single crystal may be applied on the thin film magnesium oxide layer to form the magnesium oxide layer 13 .

Referring back to FIGS. 2 and 3 , on the rear substrate 14 disposed in parallel with the front transparent substrate 10 , column electrodes D extending in a direction perpendicular to the pair of row electrodes (X, Y) are formed. The column electrode D extends below the transparent electrodes Xa and Ya. On the rear substrate 14, a white protective layer 15 for covering the column electrodes D is also formed. Spacers 16 are formed on the column electrode protection layer 15 . The spacer 16 includes a horizontal wall 16A and a vertical wall 16B, and the spacer 16 has a generally stepped shape. The horizontal wall 16A extends in the horizontal direction of the display screen at a position corresponding to each bus electrode Xb and Yb of the row electrode pair (X, Y). The vertical wall 16B extends in the vertical direction of the display screen between every two adjacent column electrodes D. As shown in FIG. For each display line of the PDP 50, there is a clearance SL between adjacent spacers 16 as shown in FIG. 2 . Also, the step-shaped spacers 16 define display cells PC each including an independent discharge space S and transparent electrodes Xa and Ya. Each display unit PC is defined by two adjacent horizontal walls 16A and two adjacent vertical walls 16B. The discharge space S is filled with a discharge gas including xenon gas. In each display cell PC, fluorescent material layer 17 is formed so as to cover the inner side surfaces of two horizontal walls 16A, the inner side surfaces of two vertical walls 16B, and the top surface of column electrode protective layer 15, as shown in FIG. The fluorescent material layer 17 includes three types of fluorescent materials; one for emitting red light, one for emitting green light, and one for emitting blue light. Between the discharge space S and the gap SL in each display cell PC, a horizontal wall 16A adjoins the magnesium oxide layer 13 so that the discharge space S is isolated from the gap SL, as shown in FIG. 3 . On the other hand, as shown in FIG. 4, the magnesium oxide layer 13 is not adjacent to the vertical wall 16B so that there is a gap r1 therebetween. In other words, the discharge spaces S of the display cells PC adjacent to each other in the horizontal direction of the display screen communicate with each other through the gap r1.

The drive control circuit 56 provides various control signals for driving the PDP 50 to the X electrode driver 51, the Y electrode driver 53 and the address driver 55 according to the light emission drive sequence, which adopts the subfield as shown in FIG. 7 method (sub-frame method). The X electrode driver 51, the Y electrode driver 53, and the address driver 55 generate various driving pulses (to be described later) for driving the PDP 50 according to the light emission driving sequence shown in FIG.

In the light emission driving sequence shown in FIG. 7, the addressing process W and the sustaining process I are performed in each subfield SF1-SF(N) within a display period of one field (one frame). The reset process R is performed only in the first subfield SF1 before the address process W. Referring to FIG.

8 is a diagram showing timings of applying drive pulses to the column electrode D and the row electrodes X, Y of the PDP 50 in the subfields SF1 and SF2 of the subfields SF1-SF(N).

During the addressing process W of each subfield, the address driver 55 generates pixel data pulses for setting whether to force each display unit PC to emit light in the subfield based on the input video signal. For example, the address driver 55 generates high voltage pixel data pulses when the display unit PC should emit light, and generates high and low voltage pixel data pulses when the display unit PC should not emit light. The address driver 55 generates pixel data pulses for each display cell PC. The address driver 55 then applies _m pixel data pulses for each display line to the column electrodes _D1 -Dm. The m pixel data pulses are a group of pixel data pulses DP. The address driver 55 sequentially applies pixel data pulse groups _DP1 , _DP2 ... and _DPn to the column electrodes _D1 - _Dm . At the same time, the Y electrode driver 53 supplies the negative polarity scan pulse SP to the row electrodes Y ₁ -Y _n synchronously with the timing of each pixel data pulse group DP ₁ -DP _n . A discharge (selective discharge) is generated only in the display unit PC supplied with the scan pulse SP and the high-voltage pixel data pulse to form A predetermined amount of wall charge. In the display cell PC supplied with the scan pulse SP but supplied with the low-voltage pixel data pulse, selective discharge is not generated so that the condition of the wall charge does not change, ie, the presence/absence of the sustain wall discharge.

In other words, by performing the addressing process W, each display cell PC is set to a light emitting state in which a predetermined amount of wall charges exist or a non-light emitting state in which a predetermined amount of wall charges does not exist according to an input video signal.

In the sustain process I of each subfield, the X electrode driver 51 and the Y electrode driver 53 respectively alternately and repeatedly apply positive polarity sustain pulses IPx and IPy to the row electrodes X ₁ -X _n and Y ₁ -Y _n . The number of times sustain pulses IPx and _IPY are applied depends on the luminance weighting in each subfield. Each time these sustain pulses IPx and _IPy are applied, a sustain discharge is generated only in the display cell in a light-emitting state (that is, formed with a predetermined amount of wall charges), and the phosphor layer 17 emits light associated with this discharge to display light on the panel An image is formed on the surface.

In the reset process R performed in the first subfield SF1 before the address process W, the X electrode driver 51 simultaneously applies a negative reset pulse RPx to the row electrodes X ₁ -X _n , as shown in FIG. 8 . While applying the reset pulse RPx, the Y electrode driver 53 simultaneously applies the first reset pulse RP _Y1 with positive polarity of the pulse waveform to the row electrodes Y ₁ -Y _n , whose voltage increases slowly with time and reaches the peak voltage, As shown in Figure 8. The peak voltage of the first reset pulse RP _Y1 is higher than the peak voltages of the sustain pulses IPx and IP _Y. With simultaneous application of the first reset pulse RP _Y1 and the reset pulse RPx of negative polarity, a first reset discharge is generated between row electrodes X and Y in each of all display cells PC _1,1 -PC _n,m . When the first reset discharge is completed, a predetermined amount of wall charges are formed on the surface of the magnesium oxide layer 13 in the discharge space S of each display cell PC. Specifically, positive charges are formed near the row electrode X and negative charges are formed near the row electrode Y on the surface of the magnesium oxide layer 13 . This condition is referred to as "wall charge formation" in this specification. Subsequently, the Y electrode driver 53 generates a second reset pulse RP _Y2 of negative polarity, whose voltage changes slowly on the rising side, as shown in FIG. 8 , and applies this pulse to all the row electrodes Y ₁ -Y _n at the same time. The peak voltage of the second reset pulse RP _Y2 is set within a range from the voltage value on the row electrode Y when the scan pulse SP is not applied in the address process W to the peak voltage value of the scan pulse SP. In response to the application of the second reset pulse RP _Y2 , a second reset discharge is generated between the row electrodes X and Y in each of all display cells _PC1,1 - _PCn,m . The second reset discharge destroys the wall charges formed in each of all display cells _PC1,1 - _PCn,m . In other words, through the reset process R, all the display cells PC _1,1 -PC _n,m are initialized to a non-light emitting state in which no wall charges exist. In the first and second reset discharges generated before the address discharge, a discharge is generated in each display cell PC. Since the magnesium oxide layer 13 is formed in the display cell PC, the priming effect generated by the reset discharge lasts for a longer time to allow faster addressing.

In the reset process R, the first reset pulse RP _Y1 is applied to the row electrode Y, and its voltage value changes slowly on the rising edge, so that a weak first reset discharge is generated between the T-shaped transparent electrodes Ya and Xa, so as to improve the contrast.

The magnesium oxide layer 13 formed in each display cell PC includes a relatively large vapor-phase magnesium oxide single crystal, as shown in FIG. 5A or 5B. When irradiated with an electron beam, this single crystal emits CL (cathodoluminescence) light having a peak in the wavelength range of 300-400nm and in the wavelength range of 200-300nm (especially around 235nm in the range of 230-250nm) Another CL light with a peak. Therefore, these single crystals are considered to have an energy level at 235 nm. As shown in FIG. 10, when the vapor-phase-processed magnesium oxide single crystal has a larger particle diameter, the CL light emission with a peak at 235 nm exhibits a higher peak intensity. Specifically, in the process of producing vapor-phase magnesium oxide crystals, if magnesium is heated at a temperature higher than the normal temperature, as shown in FIG. 5A or FIG. 5B, a relatively large particle diameter of 2000 Å or more Single crystals of were formed together with single crystals of vapor-phase magnesium oxide having an average particle diameter of 500 angstroms. The flame associated with the reaction of magnesium and oxygen also becomes longer due to heating the magnesium at higher than normal temperatures. As a result, a large temperature difference is generated between the glow and the surrounding environment, so that the group of vapor-phase magnesium oxide single crystals with large particle diameters is presumed to include various single crystals exhibiting high energy levels at 200-300 nm (especially at 235 nm). Compared to magnesium oxide produced by other methods, single crystals of vapor phase magnesium oxide are characterized by, for example, higher purity, finer particles, and less grain aggregation.

Therefore, it is believed that the vapor-phase magnesium oxide single crystal having an energy level at 235 nm traps electrons for a long time (several milliseconds) and emits electrons with the application of an electric field during selective discharge, so as to quickly trap initial electrons required for discharge. Therefore, when the magnesium oxide layer 13 as shown in FIG. There is always an amount of electrons sufficient to cause discharge in the discharge space S, resulting in a high possibility of discharge in the discharge space S.

11 is a graph showing discharge probabilities in three cases, namely, when no magnesium oxide layer is formed in the display cell PC, when a magnesium oxide layer is formed in the discharge cell PC by a conventional vapor deposition method, and When a magnesium oxide layer comprising a vapor phase magnesium oxide single crystal which generates CL light emission having a peak in the range of 200-300 nm upon electron beam irradiation is formed in the display unit PC. In FIG. 11 , the horizontal axis represents the discharge interval, that is, the time interval from the time when a discharge is generated to the time when a next discharge is generated. As shown in the figure, when each display unit PC has a magnesium oxide layer 13 comprising a vapor-phase magnesium oxide single crystal comprising a peak in the range of 200-300 nm when electron beams are irradiated, CL light emission increases the probability of discharge compared to a display cell having a magnesium oxide layer formed by a conventional vapor deposition method. As shown in Figure 12, when the vapor-phase MgO single crystal emits relatively high-intensity CL light, especially CL light with a peak at 235 nm when electron beams are irradiated, the vapor-phase MgO single crystal can reduce the generation of CL light in the discharge space S. the delay of the discharge.

Therefore, when a weak first reset discharge is generated by applying the first reset pulse RP _Y1 with a slow voltage change in the reset process R, even if the peak voltage value of the first reset pulse RP _Y1 is high, it is possible to reliably generate First reset discharge with low discharge intensity.

In the above-mentioned embodiment, although the magnesium oxide layer 13 comprising the magnesium oxide single crystal shown in FIG. A thin-film magnesium oxide layer 130 is provided between and 13 , as shown in FIGS. 13 and 14 .

The embodiment has been described in connection with the so-called selective writing and addressing method of driving the PDP 50 for a halftone image display. The selective writing and addressing method initializes the display units so that the wall charges remaining in all the display units are reduced to less than a predetermined amount (reset process R), and selectively forms in each display unit according to the input video signal equal to or greater than a predetermined amount of wall charges (addressing process W). However, the PDP 50 can be driven by a so-called selective erasing and addressing method to display halftone images. The selective erasing and addressing method forms wall charges equal to or greater than a predetermined amount in each of all display units (reset process R), and selectively subtracts the wall charges formed in each display unit according to pixel data. as small as less than a predetermined amount (addressing process W). Similar to the selective writing and addressing method, the selective erasing and addressing method can reliably generate the first reset discharge at a low discharge intensity during the reset process R.

In the illustrated embodiment, the reset pulse PRx is applied to the row electrode X at the same time as the first reset pulse RP _Y1 is applied to the row electrode _Y. However, it is possible to omit the reset pulse _PRx and set the row electrode X to ground potential. Another type of first reset pulse RP _Y1 may be applied to the row electrode Y. For example, the first reset pulse RP _Y1 may have a first portion in which the first reset pulse RP _Y1 steeply increases to a first predetermined voltage value lower than the discharge start voltage, and a subsequent portion in which In the part of , the voltage value of the first reset pulse RP _Y1 changes slowly with time to reach a peak voltage value. In other words, any suitable first reset pulse RP _Y1 can be used as long as the first reset pulse RP _Y1 exhibits a slow voltage change when a reset discharge should be generated.

Claims (21)

1, a kind of plasma display comprises:

Plasmia indicating panel, be included in a plurality of column electrodes of extending on the line direction to a plurality of row electrodes that on column direction, extend perpendicular to line direction, form a plurality of display units that each all has discharge space at each intersection point place of described a plurality of column electrodes pair and described a plurality of row electrodes;

Be formed on the double shielding layer in each described display unit, have magnesium oxide thin layer and the magnesium oxide single-crystal stratum granulosum that is deposited on this magnesium oxide thin layer, making can be by irradiation this magnesium oxide single-crystal stratum granulosum of electron beam excitation thereon, to be transmitted in the cathode luminescence that has peak value in 200 to the 300nm wave-length coverages, at least some particles in the described magnesium oxide single-crystal stratum granulosum have the particle diameter that is equal to, or greater than 2000 dusts; Described magnesium oxide single-crystal particle (13B) is exposed in the described discharge space (S) so that applying the first reset pulse (RP _Y1) time allow described magnesium oxide single-crystal particle (13B) to discharge electronics to described discharge space (S) apace;

Resetting means, be used for to each described column electrode (X, Y) one or two electrodes in apply reset pulse, so that in the described discharge space (S) of each described display unit (PC), produce reset discharge, make each described display unit (PC) initialization, described reset pulse comprises the described first reset pulse (RP _Y1) and the second reset pulse (RP _Y2), the described first reset pulse (RP _Y1) its voltage that slowly raises to be to produce wall electric charge, the described second reset pulse (RP in described discharge space (S) _Y2) slowly reduce its voltage in described discharge space (S), to eliminate described wall electric charge;

Device for addressing, be used for applying scanning impulse for successively an electrode of each described column electrode centering, and apply data pulse for each described row electrode corresponding to incoming video signal, optionally in the described display space of each described display unit, to produce the selectivity discharge, so that each described display unit is set to luminance or non-luminance; And

Holdout device is used for one or two electrodes to each described column electrode centering and applies and keep pulse, keeps discharge to produce in the described discharge space in being set to each described display unit of luminance.

2, plasma display according to claim 1, wherein each in two of each described column electrode centering column electrodes all is included in the extended body that extends on the line direction, and a plurality of excrescences that the column electrode towards coupling extends from described extended body on column direction, make between per two relative excrescences of each described column electrode centering, to form discharging gap.

3, plasma display according to claim 2, wherein the described excrescence of each described column electrode comprises wide head and described wide head is connected to doing of described extended body.

4, plasma display according to claim 1, wherein said magnesium oxide layer comprises the magnesium oxide monocrystal that obtains by magnesium oxide steam in vapour phase.

5, plasma display according to claim 1, wherein said magnesium oxide monocrystal are transmitted in the cathode luminescence that has peak value in 230 to 250nm the wave-length coverage.

6, plasma display according to claim 1, wherein said magnesium oxide layer are formed on and cover on the right dielectric layer of described column electrode.

7, plasma display according to claim 1, the crest voltage value of wherein said reset pulse is greater than the described crest voltage value of keeping pulse.

8, plasma display according to claim 1, wherein said reset pulse comprise first reset pulse and second reset pulse of its magnitude of voltage along with slow reduction of time that its magnitude of voltage slowly increased along with the time.

9, plasma display according to claim 8, wherein determine that by a described electrode and matched electrodes each described column electrode is right, the crest voltage value of described second reset pulse is between the crest voltage of magnitude of voltage that imposes on described matched electrodes when applying described scanning impulse for a described electrode and described scanning impulse.

10, a kind of driving method of Plasmia indicating panel, described Plasmia indicating panel be included in a plurality of column electrodes of extending on the line direction to a plurality of row electrodes that on column direction, extend perpendicular to described line direction, intersection point place at described a plurality of column electrodes pair and described a plurality of row electrodes forms a plurality of display units, each described display unit has double shielding layer and the discharge space that faces with each other, described double shielding layer has magnesium oxide thin layer and the magnesium oxide single-crystal stratum granulosum that is deposited on this magnesium oxide thin layer, making can be by irradiation this magnesium oxide single-crystal stratum granulosum of electron beam excitation thereon, to be transmitted in the cathode luminescence that has peak value in 200 to the 300nm wave-length coverages, at least some particles in the described magnesium oxide single-crystal stratum granulosum have the particle diameter that is equal to, or greater than 2000 dusts; Described magnesium oxide single-crystal particle (13B) is exposed in the described discharge space (S) so that applying the first reset pulse (RP _Y1) time allow described magnesium oxide single-crystal particle (13B) to discharge electronics to described discharge space (S) apace; Described method comprises:

Give each described column electrode to (X, Y) one or two electrodes in apply reset pulse, so that in the described discharge space (S) of each described display unit (PC), produce reset discharge, be used for the initialization of each described display unit (PC), described reset pulse comprises the described first reset pulse (RP _Y1) and the second reset pulse (RP _Y2), the described first reset pulse (RP _Y1) its voltage that slowly raises to be to produce wall electric charge, the described second reset pulse (RP in described discharge space (S) _Y2) slowly reduce its voltage in described discharge space (S), to eliminate described wall electric charge;

Apply scanning impulse for successively an electrode of each described column electrode centering, and apply corresponding to the video signal data pulse of importing for each described row electrode, so that optionally produce the selectivity discharge in the described display space in each described display unit, each described display unit is set to luminance or non-luminance; And

Apply for one or two electrodes of each described column electrode centering and keep pulse, keep discharge so that produce in the described discharge space in being set to each described display unit of luminance.

11, the driving method of Plasmia indicating panel according to claim 10, wherein said magnesium oxide layer comprises the magnesium oxide monocrystal that obtains by magnesium oxide steam in vapour phase.

12, the driving method of Plasmia indicating panel according to claim 11 wherein obtains described magnesium steam by heating magnesium.

13, a kind of device comprises:

Plasmia indicating panel, be included in a plurality of column electrodes of extending on the line direction to a plurality of row electrodes that on column direction, extend perpendicular to described line direction, form a plurality of display units that each all has discharge space at each intersection point place of described a plurality of column electrodes pair and described a plurality of row electrodes;

Be formed on the double shielding layer in each described display unit, have magnesium oxide thin layer and the magnesium oxide single-crystal stratum granulosum that is deposited on this magnesium oxide thin layer, making can be by irradiation this magnesium oxide single-crystal stratum granulosum of electron beam excitation thereon, to be transmitted in the cathode luminescence that has peak value in 200 to the 300nm wave-length coverages, at least some particles in the described magnesium oxide single-crystal stratum granulosum have the particle diameter that is equal to, or greater than 2000 dusts; Described magnesium oxide single-crystal particle (13B) is exposed in the described discharge space (S) so that applying the first reset pulse (RP _Y1) time allow described magnesium oxide single-crystal particle (13B) to discharge electronics to described discharge space (S) apace; And

Resetting means, be used for to each described column electrode (X, Y) one or two electrodes in apply reset pulse to produce reset discharge in the described discharge space (S) of each described display unit (PC), so that each described display unit (PC) initialization, described reset pulse comprises the described first reset pulse (RP _Y1) and the second reset pulse (RP _Y2), the described first reset pulse (RP _Y1) its voltage that slowly raises to be to produce wall electric charge, the described second reset pulse (RP in described discharge space (S) _Y2) slowly reduce its voltage in described discharge space (S), to eliminate described wall electric charge.

14, device according to claim 13, wherein each of two of each described column electrode centering column electrodes all is included in extended body that extends on the described line direction and a plurality of excrescences that the column electrode towards coupling extends from described extended body on described column direction, makes to form discharging gap between per two relative excrescences of each described column electrode centering.

15, device according to claim 14, wherein the described excrescence of each described column electrode comprises wide head and described wide head is connected to doing of described extended body.

16, device according to claim 13, wherein said magnesium oxide layer comprises the magnesium oxide monocrystal that obtains by magnesium oxide steam in vapour phase.

17, device according to claim 13, wherein said magnesium oxide monocrystal are transmitted in the cathode luminescence that has peak value in 230 to 250nm the wave-length coverage.

18, device according to claim 13 is wherein covering the described magnesium oxide layer of formation on the right dielectric layer of described column electrode.

19, device according to claim 13, the crest voltage value of wherein said reset pulse is greater than the described crest voltage value of keeping pulse.

20, device according to claim 13, wherein said reset pulse comprise first reset pulse and second reset pulse of its magnitude of voltage along with slow reduction of time that its magnitude of voltage slowly increased along with the time.

21, device according to claim 20, wherein determine that by a described electrode and matched electrodes each described column electrode is right, the crest voltage value of described second reset pulse is between the crest voltage of magnitude of voltage that imposes on described matched electrodes when applying described scanning impulse for a described electrode and described scanning impulse.

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