JP4608727B2 - Synchronization frequency discrimination circuit, image processing apparatus using the same, and synchronization frequency discrimination method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous frequency discriminating circuit that discriminates, for example, an asynchronous video synchronizing frequency, an image processing apparatus using the same, and a synchronous frequency discriminating method.
[0002]
[Prior art]
Generally, the image synchronization frequency is discriminated by using a free-run counter in a microcomputer (hereinafter referred to as a microcomputer) to count the interval of the synchronization signal to obtain an actual frequency.
[0003]
By the way, in the method of converting to an actual frequency in this way, in the case of an interlaced signal, an equivalent pulse is included in the vertical synchronization section and before and after that, so that the horizontal frequency near the vertical synchronization is avoided in order to avoid erroneous determination of the horizontal frequency due to the pulse. A method was used in which pulses were not used for counting.
In this method, generally, horizontal pulse capturing is started after a certain time (about 1 msec) after vertical synchronization is input.
[0004]
[Problems to be solved by the invention]
However, since the above-described method is a method in which horizontal pulse capturing is started after a certain time (about 1 msec) after vertical synchronization is input, a vertical synchronization signal is required as a horizontal frequency measurement start trigger. If a malfunction occurs in the vertical synchronization, there is a disadvantage of affecting the horizontal frequency measurement.
[0005]
Further, the conventional method in which the horizontal synchronization cannot be captured in the vertical synchronization section has a drawback in that it is limited by the vertical period because the horizontal synchronization capture time needs to be 1 V (one vertical synchronization section) or less.
Therefore, it is not suitable for a multi-scan system in which the synchronization frequency covers a wide range both horizontally and vertically.
[0006]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a synchronous frequency discriminating circuit that is not easily affected by equivalent pulses, disturbance noise, and the like, and that can independently determine horizontal / vertical. An object of the present invention is to provide an image processing apparatus and a synchronization frequency discrimination method using the same.
[0007]
[Means for Solving the Problems]
To achieve the above object, the present invention is input Image with equivalent pulse A synchronization frequency discriminating circuit for discriminating the frequency of a sync pulse, which is continuously input based on a plurality of buffers for storing a plurality of data and a reference frequency image A first means for obtaining the pulse interval of the synchronization pulse, and sequentially storing the obtained pulse interval data in the plurality of buffers; a second means for rearranging the data stored in each of the buffers according to the magnitude of the value; A third means for selecting buffer data excluding a buffer for storing data that is likely to contain erroneous data after rearrangement, and averaging the data value of the selected buffer; the reference frequency and the averaging And a fourth means for obtaining a frequency based on the data, The first means includes a clock generation unit that outputs a reference clock having a reference frequency, an edge detection unit that detects a falling or rising edge of the image synchronization pulse and outputs a synchronization edge signal, and the reference clock and A counter that counts the number of basic clocks from one edge of the input image synchronization pulse to the input of the next edge based on the synchronization edge signal, and the counter in response to the input image synchronization pulse The counter value data is sequentially stored in the plurality of buffers, and the third means is the buffer data rearranged by the second means, and is preset. Or a buffer for storing data that is likely to contain the above-mentioned erroneous data based on data given from the outside The output side switching unit that selects and reads the data of the buffer that has been read, the addition unit that adds the buffer data read by the output side switching unit, and the number of data that is read by selecting the addition value of the addition unit And an averaging unit that averages and outputs averaged data, and the fourth means obtains the frequency by dividing the reference frequency of the reference clock by the averaged data of the averaging unit. .
[0008]
The image processing apparatus of the present invention is Including a frequency discriminating circuit for discriminating and determining the frequency of an image synchronization pulse including an equivalent pulse to be input; A first circuit that generates image processing data based on the obtained frequency, and a second circuit that performs predetermined processing on the input image signal based on the image processing data from the first circuit; The frequency discrimination circuit has A plurality of buffers for storing a plurality of data and a pulse interval of image synchronization pulses continuously input based on a reference frequency are obtained, and the obtained pulse interval data is sequentially stored in the plurality of buffers. Means, second means for rearranging the data stored in each of the buffers according to the magnitude of the value, and data in the buffer excluding the buffer for storing data that is likely to contain erroneous data after the rearrangement. A third means for selecting and averaging the data values of the selected buffer; and a fourth means for obtaining a frequency based on the reference frequency and the averaged data. And the first means includes a clock generation unit that outputs a reference clock having a reference frequency, an edge detection unit that detects a falling or rising edge of the image synchronization pulse and outputs a synchronization edge signal, and Based on the reference clock and the synchronization edge signal, a counter that counts the number of basic clocks from one edge of the input image synchronization pulse to the input of the next edge, and responds to the input image synchronization pulse. An input side switching unit that sequentially stores the counter value data of the counter in the plurality of buffers, and the third means is data of the buffer rearranged by the second means, A database that stores data that is likely to contain the above-mentioned erroneous data based on data set in advance or given externally. An output side switching unit that selects and reads the buffer data excluding the buffer, an addition unit that adds the buffer data read by the output side switching unit, and selects and reads the addition value of the addition unit An averaging unit that divides by the number of data and averages and outputs the averaged data, and the fourth means divides the reference frequency of the reference clock by the averaged data of the averaging unit. Find the frequency .
[0009]
The image processing apparatus of the present invention is Including a frequency discriminating circuit for discriminating and determining the frequency of an image synchronization pulse including an equivalent pulse to be input; A first circuit that generates image processing data based on the obtained frequency, a second circuit that performs predetermined processing on the input image signal based on image processing data by the first circuit, and an image from the image signal A synchronization separation circuit that separates synchronization pulses and supplies them to the first circuit and the second circuit And the frequency discrimination circuit includes the frequency discrimination circuit, A plurality of buffers for storing a plurality of data and a pulse interval of image synchronization pulses continuously input based on a reference frequency are obtained, and the obtained pulse interval data is sequentially stored in the plurality of buffers. Means, second means for rearranging the data stored in each of the buffers according to the magnitude of the value, and data in the buffer excluding the buffer for storing data that is likely to contain erroneous data after the rearrangement. A third means for selecting and averaging the data values of the selected buffer; and a fourth means for obtaining a frequency based on the reference frequency and the averaged data. And the first means includes a clock generation unit that outputs a reference clock having a reference frequency, an edge detection unit that detects a falling or rising edge of the image synchronization pulse and outputs a synchronization edge signal, and Based on the reference clock and the synchronization edge signal, a counter that counts the number of basic clocks from one edge of the input image synchronization pulse to the input of the next edge, and responds to the input image synchronization pulse. An input side switching unit that sequentially stores the counter value data of the counter in the plurality of buffers, and the third means is data of the buffer rearranged by the second means, A database that stores data that is likely to contain the above-mentioned erroneous data based on data set in advance or given externally. An output side switching unit that selects and reads the buffer data excluding the buffer, an addition unit that adds the buffer data read by the output side switching unit, and selects and reads the addition value of the addition unit An averaging unit that divides by the number of data and averages and outputs the averaged data, and the fourth means divides the reference frequency of the reference clock by the averaged data of the averaging unit. Find the frequency .
[0010]
In the present invention, the second means performs a rearrangement process on the data stored in the buffer in ascending or descending order.
[0011]
In the present invention, the third means truncates a predetermined number of data on at least one of the minimum value side data and the maximum value side data, and averages the remaining data group.
[0012]
In the present invention, the image synchronization pulse includes a horizontal synchronization signal pulse.
[0013]
Also, the present invention is input Image with equivalent pulse A synchronization frequency determination method for determining the frequency of a synchronization pulse, which is continuously input based on a reference frequency image A first step of obtaining the pulse interval of the synchronization pulse and sequentially securing the obtained pulse interval data, a second step of rearranging the plurality of secured data according to the magnitude of the value, and error data after the rearrangement A third step of selecting data excluding data that is likely to be included, averaging the selected data values, and a fourth step of obtaining a frequency based on the reference frequency and the averaged data, The first step includes a step of detecting a falling edge or a rising edge of the image synchronization pulse to obtain a synchronization edge signal, a reference clock of a reference frequency and the synchronization edge signal based on the input A step of counting the number of basic clocks from one edge of an image synchronization pulse to the input of the next edge, and the counter value data of the counter in response to the input image synchronization pulse The third step is the data of the buffer rearranged in the second step, and is based on the data set in advance or given from the outside Select and read buffer data except for the buffer that stores data that is likely to contain erroneous data. And adding the read buffer data, and dividing the added value by the number of selected and read data and averaging to obtain averaged data, The step includes a step of obtaining a frequency by dividing the reference frequency of the reference clock by the averaged data. .
[0014]
In the present invention, in the second step, the data stored in the buffer is rearranged in ascending or descending order.
[0015]
In the present invention, in the third step, a predetermined number of data on at least one of the minimum value side data and the maximum value side data is rounded down, and the remaining data group is averaged.
[0016]
According to the present invention, the pulse intervals of synchronization pulses that are continuously input based on the reference frequency, for example, the pulse interval of the horizontal synchronization signal, are sequentially obtained, and the obtained data are sequentially stored in the buffers.
In the series of data stored in the buffer, erroneous data having a large count value due to lack of synchronization and the like, and erroneous data having a small count value due to equivalent pulses / noise, etc. are irregularly included. Are rearranged in ascending order (or descending order), for example. As a result, the erroneous data group can be collectively deleted by concentrating the erroneous data in the upper and lower limit areas of the buffer.
Then, averaged data of only the data value of the remaining buffer after deletion is obtained. For example, the frequency is obtained by dividing the reference frequency by this averaged data.
Thereby, it becomes possible to suppress the influence of disturbance.
In addition, since it is premised on that the equivalent pulse included in the horizontal synchronization is once taken into the buffer, the timing adjustment with the vertical synchronization signal is unnecessary, and the frequency can be discriminated independently in the horizontal / vertical directions.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of an image processing apparatus that employs a synchronous frequency discrimination circuit according to the present invention.
[0018]
As shown in FIG. 1, the image processing apparatus 10 includes an analog / digital (A / D) converter 11, a synchronization separation circuit 12, a system microcomputer 13 as a first circuit, a scan converter as a second circuit, and the like. It has a signal processing circuit 14 and a display 15.
[0019]
The A / D converter 11 converts the input analog image signal AIM into a digital signal and supplies it to the signal processing circuit 14.
[0020]
The synchronization separation circuit 12 separates the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC from the analog image signal AIM and supplies them to the system microcomputer 13 and the signal processing circuit 14.
[0021]
The system microcomputer 13 receives the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC from the synchronization separation circuit 12 and secures the pulse interval of the horizontal synchronization signal in the buffer as a data group, and ascending order (or (Descending order) is performed (after sorting), the data near the minimum and maximum is rounded down, the frequency is obtained by averaging the remaining data group, and the signal processing circuit 14 is based on the obtained frequency. Then, necessary image processing data is generated and supplied to the signal processing circuit 14.
[0022]
FIG. 2 is a functional block diagram for explaining the function of the synchronous frequency discrimination circuit portion in the system microcomputer 13.
[0023]
As shown in FIG. 2, the synchronous frequency discrimination circuit according to the present embodiment includes a clock generation unit 1311, an edge detection unit 1312, a counter 1313, an input side switching unit 1314, a buffer memory unit 1315, a sort unit 1316, and an output side switching unit. 1317, a switch switching unit 1318, an adding unit 1319, an averaging unit 1320, and a frequency unit 1321 are included.
For example these Among the elements, the function units of the clock generation unit 1311, the edge detection unit 1312, and the counter 1313 are realized by hardware, and the remaining function units are realized by software.
Further, the first means of the present invention includes a clock generation unit 1311, an edge detection unit 1312, a counter 1313, and an input side switching unit 1314, and the second means includes a sorting unit 1316, The means includes an output side switching unit 1317, a switch switching unit 1318, an adding unit 1319, and an averaging unit 1320, and the fourth means includes a frequency unit 1321.
[0024]
The clock generator 1311 receives an oscillation signal from the crystal oscillator XTAL and supplies a reference clock φ having a frequency of 1 MHz, for example, to the counter 1313 and the frequency generator 1321.
[0025]
The edge detection unit 1312 detects, for example, a falling edge of the horizontal synchronization signal H-SYNC, and supplies the synchronization edge signal S1312 to the counter 1313.
[0026]
The counter 1313 counts the number of reference clocks from the input synchronization edge to the input of the next edge based on the reference clock φ by the clock generation unit 1311 and the synchronization edge signal S1312 by the edge detection unit 1312.
[0027]
The input side switching unit 1314 sequentially stores the counter value data of the counter 1313 in the buffer memory unit 1315 by interruption of the input horizontal synchronization signal pulse.
[0028]
The buffer memory unit 1315 includes a plurality of buffers for storing a plurality of data. Have, input The counter value data of the counter 1313 is sequentially stored by the side switching unit 1314, the stored data is sorted by the sort unit 1316, and the sorted data is selectively read by the output side switching unit 1317.
The series of data stored in the buffer memory unit 1315 irregularly includes erroneous data having a large count value due to lack of synchronization or the like, and erroneous data having a small count value due to equivalent pulses / noise or the like.
Note that the buffer memory unit 1315 is configured by, for example, a RAM (Random Access Memory).
[0029]
The sorting unit 1316 sorts the counter value data of the counter 1313 in ascending order (or descending order) by the input side switching unit 1314 stored in the buffer memory unit 1315.
[0030]
Based on the selection signal S1318 from the switch switching unit 1318, the output side switching unit 1317 discards the data near the minimum and maximum after sorting, reads the remaining m data groups, and supplies them to the addition unit 1319.
[0031]
The switch switching unit 1318 is set in advance. Or Based on the data given from the outside, the cut data near the minimum and maximum after sorting in the buffer memory unit 1315 is cut off, and a selection signal S1318 for selecting data to be read is supplied to the output side switching unit 1317. The number m of data to be selected and read is supplied to the averaging unit 1320.
[0032]
The adding unit 1319 adds the m selection data read out via the output side switching unit 1317 and supplies the added value A to the averaging unit 1320.
[0033]
The averaging unit 1320 calculates the average data Av by dividing the addition value A by the adding unit 1319 by the number m of selection data by the switch switching unit 1318 and supplies the average data Av to the frequency unit 1321.
[0034]
The frequency converting unit 1321 calculates the discrimination frequency f by dividing the frequency (for example, 1 MHz) of the reference clock φ by the clock generating unit 1311 by the average data Av by the averaging unit 1320.
[0035]
The signal processing circuit 14 For example Based on the processing data supplied from the system microcomputer 13 based on processing data, the digital image signal by the A / D converter 11 is subjected to predetermined processing, for example, the digital signal is written to the image memory at a predetermined clock, and then written. Data is read out in synchronization with a clock having a frequency different from that of the writing clock, for example, and a video signal S14 that matches the number of vertical and horizontal pixels of the plasma display is generated and supplied to the display 15, for example.
[0036]
Next, the operation according to the above configuration will be described with reference to FIGS.
Here, FIG. 3 is a timing chart for explaining the operation, and FIG. 4 is a flowchart for explaining the operation.
[0037]
The analog image signal AIM is supplied to the A / D converter 11 and the synchronization separation circuit 12.
In the A / D converter 11, the input analog image signal AIM is converted into a digital signal and supplied to the signal processing circuit 14.
In the synchronization separation circuit 12, the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC are separated from the input analog image signal AIM and supplied to the system microcomputer 13 and the signal processing circuit 14.
[0038]
In the system microcomputer 13, for example, a horizontal synchronization signal H-SYNC having a frequency of 50 kHz as shown in FIG. 3A is input to the edge detection unit 1312.
The edge detector 1312 detects, for example, a falling edge of the horizontal synchronization signal H-SYNC, and supplies a synchronization edge signal S1312 to the counter 1313 (ST1).
The counter 1313 is supplied with a reference clock φ having a frequency of 1 MHz generated by the clock generator 1311 in addition to the synchronous edge signal S1312 by the edge detector 1312 (ST2).
Then, in the counter 1313, based on the reference clock φ by the clock generation unit 1311 and the synchronization edge signal S1312 by the edge detection unit 1312, as shown in FIG. The reference clock number t until it is input is counted.
[0039]
In parallel with this, as shown in FIG. 3C, the counter value data t of the counter 1313 is sequentially stored in the buffer memory unit 1315 through the input horizontal synchronization signal pulse interrupt via the input side switching unit 1314. .
At this time, as shown in FIG. 4, assuming that the total number of buffers is n (16 in the example of FIG. 3) and that the variable for setting the capture position is x, until the capture of data t into the buffer reaches x or more than the total number of buffers 2n. Repeated (ST4 to ST6).
[0040]
At this stage, the series of data stored in the buffer memory unit 1315 irregularly includes erroneous data having a large count value due to lack of synchronization or the like and erroneous data having a small count value due to equivalent pulses / noise or the like. Will be.
If the average value is calculated only from the data stored in the buffer at this stage,
Total data sum / number of buffers = 260/16 = 16.25
Therefore, the frequency calculation result is
1MHz / 16.25 = 61.5kHz
Thus, erroneous data such as an equivalent pulse has a great influence on the frequency calculation.
[0041]
Therefore, in this embodiment, the frequency calculation at this stage is not performed, and will be described below. Like However, it is necessary to perform frequency calculation after deleting some erroneous data near the maximum and minimum values to the buffer data, but normal data and erroneous data are irregularly mixed in the buffer. Therefore, it is difficult to extract data to be deleted.
[0042]
Therefore, next, in order to remove noise in the sorting unit 1316, as shown in FIG. Stored buffer data Are rearranged in ascending order (or descending order) (ST6).
This concentrates erroneous data near the upper and lower limits of the buffer, facilitating batch deletion of data.
[0043]
Here, in the switch switching unit 1318, based on data set in advance or given from the outside, the cut data near the minimum and maximum after sorting in the buffer memory unit 1315 is cut off, and the data to be read is selected. Selection signal S1318 is generated and supplied to the output side switching unit 1317. In addition, the number m of data selected and read from the switch switching unit 1318 is supplied to the averaging unit 1320.
Based on the selection signal S1318 from the switch switching unit 1318, the output-side switching unit 1317 truncates the data near the minimum and maximum after sorting, and the remaining m data groups are read out to the adding unit 1319. Supplied.
[0044]
In the example of FIG. 3, as shown in (e), 1 data near the maximum and 6 data near the minimum are deleted at a time, and the remaining 9 data are supplied to the adder 1319.
[0045]
Then, the adding unit 1319 performs an addition process on the m selection data read out via the output-side switching unit 1317, and the added value A is supplied to the averaging unit 1320 (ST7 to ST13).
[0046]
In the averaging unit 1320, the adding unit 1319 divides the added value A by the number m of selection data by the switch switching unit 1318 to calculate average data Av, which is supplied to the frequency unit 1321 (ST14).
In frequency converting section 1321, discrimination frequency f is calculated by dividing frequency 1 MHz of reference clock φ by clock generating section 1311 by average data Av by averaging section 1320 (ST15).
[0047]
In this way, the average value when 1 data near the maximum and 6 data near the minimum is deleted at once is
Remaining data sum / number of buffers = 165/9 = 18.33
The frequency calculation result is
1MHz / 18.33 = 54.5kHz
It becomes.
That is, each pulse interval of horizontal synchronization / vertical synchronization is secured in the buffer as a data group, and the secured data is rearranged in the ascending order (or descending order) (after sorting), and the sorted buffer data By calculating the frequency by truncating the data near the minimum and maximum and averaging the remaining data group, the frequency calculation accuracy is improved.
[0048]
Further, in this algorithm, the number of deletions of the maximum vicinity data (when synchronization is lost) and the deletion number of the minimum vicinity data (when equivalent pulses and noise are mixed) can be set independently and easily with respect to the buffer data.
For this reason, it is possible to switch the noise removal performance according to the type of signal (discriminating a VTR containing a lot of noise, a PC signal that requires frequency measurement accuracy, etc.), and the stability of the measured frequency It is also possible to change the noise removal level in real time by detecting.
FIG. 3F shows an average calculation result when the batch deletion area is changed to 2 data near the maximum and 8 data near the minimum. In this case, the average value is 20,
Horizontal frequency = 1MHz / 20.00 = 50.0kHz
Accordingly, the measurement result is a frequency calculation error of zero.
[0049]
Further, in the above processing, the equivalent pulse is stored in the buffer in the same manner as the normal synchronization signal, and then the deletion processing is performed, so that signal discrimination is possible without being affected by the vertical synchronization signal.
In other words, by performing the above processing, the conventional circuit does not capture the horizontal equivalent pulse itself into the buffer. Therefore, it is necessary to use a timing obtained by adding several milliseconds to the vertical synchronization signal as a horizontal capture trigger. When the signal is disturbed or when the synchronization itself is not input, the problem that the horizontal pulse is not captured normally is solved.
[0050]
In the system microcomputer 13, necessary image processing data is generated by the signal processing circuit 14 based on the frequency obtained by the above-described processing, and is supplied to the signal processing circuit 14.
[0051]
In the signal processing circuit 14, the digital image signal by the A / D converter 11 is written into the image memory with a predetermined clock based on the processing data supplied from the system microcomputer 13, and the next written data is, for example, a writing clock. The video signal S14 is read out in synchronization with clocks having different frequencies to match the number of pixels in the vertical and horizontal directions of the display 15, and supplied to the display 15.
[0052]
As described above, according to the present embodiment, the horizontal synchronization pulse interval is secured in the buffer as a data group by receiving the horizontal synchronization signal H-SYNC and the vertical synchronization signal V-SYNC by the synchronization separation circuit 12 and secured. Sort the data in ascending order (or descending order) (after sorting), truncate the data near the minimum and maximum, find the frequency by averaging the remaining data group, and find the frequency Since the system microcomputer 13 that generates necessary image processing data by the signal processing circuit 14 based on the above and supplies it to the signal processing circuit 14 is provided, the influence of disturbance can be suppressed.
That is, since the measurement start position of the horizontal synchronization pulse is not affected by the vertical synchronization, there is no restriction on the capture time, and the dynamic range of measurement accuracy can be widened.
Also, by rearranging the sync pulse width in ascending order, it becomes easier to specify the data to be discarded.
1) The noise removal level can be easily changed.
2) The noise removal level can be changed according to the signal type.
3) The noise removal level can be changed in real time.
There are advantages such as.
[0053]
Further, in this embodiment, since it is assumed that the equivalent pulse included in the horizontal synchronization signal is once taken into the buffer, timing adjustment with the vertical synchronization signal is not necessary, and frequency discrimination can be performed independently of horizontal / vertical. It becomes.
in this way , Since the horizontal / vertical synchronization discrimination is independent,
1) Measurement accuracy and noise resistance can be set individually.
2) It becomes easy to identify the faulty part at the time of disconnection / circuit failure of the synchronization signal.
There are advantages such as.
[0054]
【The invention's effect】
As described above, according to the present invention, since the measurement start position of the horizontal synchronization pulse is not affected by the vertical synchronization, there is no restriction on the capture time, and the dynamic range of measurement accuracy can be widened.
Also, by rearranging the sync pulse widths in ascending order, it is easy to specify the data to be discarded, so the noise removal level can be easily changed, the noise removal level can be changed according to the signal type, and the noise removal level is There is an advantage that it can be changed in real time.
[0055]
In addition, according to the present invention, since the horizontal / vertical synchronization determination is independent of each other, it is possible to individually set the measurement accuracy and the noise resistance, and it is possible to specify the faulty part at the time of the disconnection of the synchronization signal / circuit failure. There are advantages such as being easy.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an image processing apparatus employing a synchronous frequency discrimination circuit according to the present invention.
2 is a diagram for explaining a function of a synchronization frequency discrimination circuit portion in the system microcomputer of FIG. 1; FIG.
FIG. 3 is a timing chart for explaining the operation.
FIG. 4 is a flowchart for explaining an operation;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Image processing apparatus, 11 ... A / D converter, 12 ... Synchronous separation circuit, 13 ... System microcomputer, 14 ... Signal processing circuit, 15 ... Display, 1311 ... Clock generation part, 1312 ... Edge detection part, 1313 ... Counter , 1314 ... input side switching unit, 1315 ... buffer memory unit, 1316 ... sort unit, 1317 ... output side switching unit, 1318 ... switch switching unit, 1319 ... addition unit, 1320 ... averaging unit, 1321 ... frequency conversion unit.

Claims (15)

A synchronization frequency discrimination circuit for discriminating the frequency of an image synchronization pulse including an equivalent pulse to be input,
Multiple buffers to store multiple data,
First means for obtaining a pulse interval of image synchronization pulses continuously input based on a reference frequency, and sequentially storing the obtained pulse interval data in the plurality of buffers;
A second means for rearranging the data stored in each of the buffers according to the value size;
A third means for selecting buffer data excluding a buffer for storing data that is likely to contain erroneous data after sorting, and averaging data values of the selected buffer;
And a fourth means for determining a frequency based on the reference frequency and the averaged data,
The first means includes
A clock generator for outputting a reference clock of a reference frequency;
An edge detection unit for detecting a falling edge or a rising edge of the image synchronization pulse and outputting a synchronization edge signal;
Based on the reference clock and the synchronization edge signal, a counter that counts the number of basic clocks from the one edge of the input image synchronization pulse to the next edge input;
An input-side switching unit that sequentially stores counter value data of the counter in the plurality of buffers in response to the input image synchronization pulse,
The third means is
Except for the buffer data rearranged by the second means, which stores data that is likely to contain the erroneous data based on data set in advance or supplied from the outside An output side switching unit for selecting and reading out the buffer data;
An adder for adding the buffer data read by the output side switching unit;
An averaging unit that outputs the averaged data by dividing the added value of the adding unit by the number of data selected and read out, and an averaged data,
The fourth means is
A synchronous frequency discriminating circuit for obtaining a frequency by dividing the reference frequency of the reference clock by the averaged data of the averaging unit . The synchronous frequency discriminating circuit according to claim 1, wherein the second means rearranges the data stored in the buffer in ascending or descending order. The synchronous frequency discriminating circuit according to claim 1, wherein the third means truncates a predetermined number of data on at least one side of the minimum value side data and the maximum value side data, and averages the remaining data group. The synchronous frequency discriminating circuit according to claim 2, wherein the third means truncates a predetermined number of data on at least one side of the minimum value side data and the maximum value side data, and averages the remaining data group. A first circuit for generating image processing data based on the determined frequency, including a frequency determining circuit for determining and determining a frequency of an image synchronization pulse including an equivalent pulse to be input ;
A second circuit for performing predetermined processing on the input image signal based on the image processing data by the first circuit ,
The frequency discrimination circuit
Multiple buffers to store multiple data,
First means for obtaining a pulse interval of image synchronization pulses continuously input based on a reference frequency, and sequentially storing the obtained pulse interval data in the plurality of buffers;
A second means for rearranging the data stored in each of the buffers according to the value size;
A third means for selecting buffer data excluding a buffer for storing data that is likely to contain erroneous data after sorting, and averaging data values of the selected buffer;
And a fourth means for determining a frequency based on the reference frequency and the averaged data ,
The first means includes
A clock generator for outputting a reference clock of a reference frequency;
An edge detection unit for detecting a falling edge or a rising edge of the image synchronization pulse and outputting a synchronization edge signal;
Based on the reference clock and the synchronization edge signal, a counter that counts the number of basic clocks from the one edge of the input image synchronization pulse to the next edge input;
An input-side switching unit that sequentially stores counter value data of the counter in the plurality of buffers in response to the input image synchronization pulse,
The third means is
Except for the buffer data rearranged by the second means, which stores data that is likely to contain the erroneous data based on data set in advance or supplied from the outside An output side switching unit for selecting and reading out the buffer data;
An adder for adding the buffer data read by the output side switching unit;
An averaging unit that outputs the averaged data by dividing the added value of the adding unit by the number of data selected and read out, and an averaged data,
The fourth means is
An image processing apparatus for obtaining a frequency by dividing the reference frequency of the reference clock by the averaged data of the averaging unit. A first circuit for generating image processing data based on the determined frequency, including a frequency determining circuit for determining and determining a frequency of an image synchronization pulse including an equivalent pulse to be input ;
A second circuit for performing predetermined processing on the input image signal based on the image processing data by the first circuit;
A synchronization separation circuit that separates an image synchronization pulse from an image signal and supplies the image synchronization pulse to the first circuit and the second circuit ;
The frequency discrimination circuit
Multiple buffers to store multiple data,
First means for obtaining a pulse interval of image synchronization pulses continuously input based on a reference frequency, and sequentially storing the obtained pulse interval data in the plurality of buffers;
A second means for rearranging the data stored in each of the buffers according to the value size;
A third means for selecting buffer data excluding a buffer for storing data that is likely to contain erroneous data after sorting, and averaging data values of the selected buffer;
And a fourth means for determining a frequency based on the reference frequency and the averaged data ,
The first means includes
A clock generator for outputting a reference clock of a reference frequency;
An edge detection unit for detecting a falling edge or a rising edge of the image synchronization pulse and outputting a synchronization edge signal;
Based on the reference clock and the synchronization edge signal, a counter that counts the number of basic clocks from the one edge of the input image synchronization pulse to the next edge input;
An input-side switching unit that sequentially stores counter value data of the counter in the plurality of buffers in response to the input image synchronization pulse,
The third means is
Except for the buffer data rearranged by the second means, which stores data that is likely to contain the erroneous data based on data set in advance or supplied from the outside An output side switching unit for selecting and reading out the buffer data;
An adder for adding the buffer data read by the output side switching unit;
An averaging unit that outputs the averaged data by dividing the added value of the adding unit by the number of data selected and read out, and an averaged data,
The fourth means is
An image processing apparatus for obtaining a frequency by dividing the reference frequency of the reference clock by the averaged data of the averaging unit. The image processing apparatus according to claim 5 , wherein the second means performs rearrangement processing on the data stored in the buffer in ascending order or descending order. The image processing apparatus according to claim 5 , wherein the third means truncates a predetermined number of data on at least one side of the minimum value side data and the maximum value side data, and averages the remaining data group. The image processing apparatus according to claim 7, wherein the third means truncates a predetermined number of data on at least one of the minimum value side data and the maximum value side data, and averages the remaining data group. The image processing apparatus according to claim 5 , wherein the image synchronization pulse includes a horizontal synchronization signal pulse. The image processing apparatus according to claim 8, wherein the image synchronization pulse includes a horizontal synchronization signal pulse. A synchronization frequency determination method for determining a frequency of an image synchronization pulse including an equivalent pulse to be input,
A first step of obtaining a pulse interval of image synchronization pulses continuously input based on a reference frequency and sequentially securing the obtained pulse interval data;
A second step of rearranging the plurality of secured data according to the magnitude of the value;
After sorting, a third step of selecting data excluding data likely to contain erroneous data and averaging the selected data values;
A fourth step of determining a frequency based on the reference frequency and the averaged data ,
The first step is
Detecting a falling or rising edge of the image synchronization pulse to obtain a synchronization edge signal;
Counting the number of basic clocks from one edge of an input image synchronization pulse to the next input based on a reference clock of a reference frequency and the synchronization edge signal;
Sequentially storing counter value data of the counter in the plurality of buffers in response to the input image synchronization pulse,
The third step is
The buffer data rearranged in the second step, except for the buffer that stores data that is likely to include the erroneous data based on data set in advance or given from the outside. Selecting and reading buffer data; and
Adding the read buffer data;
Dividing the added value by the number of selected and read data and averaging to obtain averaged data,
The fourth step is
A method for discriminating a synchronization frequency , comprising: calculating a frequency by dividing a reference frequency of the reference clock by the averaged data . The synchronization frequency determination method according to claim 12, wherein in the second step, rearrangement processing is performed on the data stored in the buffer in ascending order or descending order. 13. The synchronization frequency determination method according to claim 12, wherein in the third step, a predetermined number of data on at least one side of the minimum value side data and the maximum value side data is discarded, and the remaining data group is averaged. The synchronization frequency determination method according to claim 13, wherein in the third step, a predetermined number of data on at least one side of the minimum value side data and the maximum value side data is discarded, and the remaining data group is averaged.

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