JP2871746B2 - Clock signal regeneration circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a video signal processing circuit such as a video tape recorder (hereinafter abbreviated as VTR), and reproduces a clock signal based on a synchronization signal. It is about.

2. Description of the Related Art In a digital signal processing circuit such as a TBC (time base collector) of a VTR, a write pulse to a memory generally resets a memory address by a reference signal obtained based on a horizontal synchronization signal or a burst signal. A reset pulse is generated, and a clock that is phase-locked with a reference signal is generated by a voltage-controlled oscillator (hereinafter abbreviated as VCO) of a PLL circuit, which is used as a write clock to a memory. In this PLL circuit, if a skew for a certain period or more occurs at the time of head switching, the operation of the phase comparator is prohibited for a predetermined period based on the information of the head switching signal and the vertical synchronization signal, and the 1 / n frequency dividing circuit is used. The reset or the preset is configured to be performed based on the input signal.

Problems to be Solved by the Invention However, when the VTR is reproduced, the PTR having the above-described conventional configuration is used.
When the LL circuit is used, a large skew for a certain period of time or more when switching heads can be handled. Takes a certain amount of time. To shorten the time, it is sufficient to increase the response speed of the PLL, but if it is increased too much, it has the adverse effect of weakening against noise, so there is a limit. In other words, after the discontinuity of the reference signal of the input signal
A certain period of time, for example, several H periods (H = horizontal scanning cycle) is required until the PLL circuit is pulled in stably, during which time the output of the PLL circuit, that is, the output of the VCO used for the write clock, etc., is guaranteed. Had the problem of not being able to.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a clock signal generation circuit that guarantees the output of a VCO.

Means for Solving the Problems In order to solve the above problems, a clock signal reproducing circuit according to the present invention comprises: a voltage controlled oscillator for outputting a clock signal having a frequency corresponding to an input level; and the clock signal. A frequency divider for dividing and outputting 1 / n (n is a positive integer) and a synchronizing signal are input, and the synchronizing signal interval is counted in fixed clock units based on the synchronizing signal. Is averaged, and based on the average data, a window signal is generated in a time zone in which the next synchronization signal occurs,
A synchronizing signal extracting means for extracting and outputting only a synchronizing signal at a correct time interval using the window signal as a gate signal, and a synchronizing signal output from the synchronizing signal extracting means and the clock signal divided by the frequency divider. The phase comparator compares the phases of the synchronization signal and the clock signal, and outputs a phase signal whose output is held for a normal time and a phase signal whose output is held for a long time. Selecting means for inputting the output synchronization signal, selecting and outputting two phase signals of the phase comparator output in accordance with a time interval at which the synchronization signal is extracted, and the phase selected by the selection means A low-pass filter that receives a phase signal of the comparator, changes the gain when the phase signal changes abruptly, and outputs the gain to the voltage-controlled oscillator.

According to the configuration described above, the synchronization signal extracting means counts the time interval of the synchronization signal in fixed clock units to determine whether or not the synchronization signal as the input signal is a correct time interval, and averages the counted data. Data is created, a window signal (pulse) is generated in a region where the next synchronization signal is generated based on the average data, and only synchronization signals at correct time intervals are extracted, and the extracted synchronization signal is sent to a phase comparator. input.

When a small skew or a small dropout occurs and a synchronization signal is not extracted due to deviation from the window signal, the phase signal in the previous state is input to the low-pass filter as the output of the phase comparator. Therefore, a PL consisting of a phase comparator, a low-pass filter, a voltage-controlled oscillator, and a frequency divider
Since no disturbance is applied to the L loop, a stable clock signal can be obtained.

When the state changes in the special search mode and the output signal of the phase comparator output to the low-pass filter changes in a short time, the low-pass filter increases the gain and increases the change in the voltage output to the voltage-controlled oscillator. Thus, the PLL loop is quickly pulled to a stable point.

When a large skew occurs during head switching or when a dropout occurs for a long time, the synchronizing signal is not extracted from the synchronizing signal extracting means for a long time. And switches to a phase signal that is held for a long time and inputs it to the low-pass filter. Therefore, since no disturbance is given to the PLL loop, a stable clock signal can be obtained.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock signal reproducing circuit showing one embodiment of the present invention.

A synchronization signal a is input from an input terminal 1 to a synchronization signal discrimination extraction circuit (DISCRI) 2.

DISCRI2, as shown in FIG. 2, counts the time interval of the input synchronization signal a with a fixed clock in a synchronization signal interval counting circuit (DET) 10 and averages it based on the count data j counted in DET10. Synchronization signal interval data creation circuit (AV
E) An average data k is created at 11, and a window signal 1 is created at a window generation circuit (WINDOW) 12 based on the average data k. As shown in a waveform diagram of FIG. 5, a gate circuit (GATE) is created. Synchronization signal a that does not enter the window at 13
Is inhibited so as not to be output, and only the synchronization signal a in the window is output as the output synchronization signal b of DISCRI2.

The output synchronization signal b of DISCRI2 is, as shown in FIG.
The phase comparator output switching signal generation circuit (SELA) 3 and one input terminal of the phase comparator (PC) 4 are input. SELA3
Generates a switching signal f for switching between a phase signal d and a phase signal e of the output of the PC4, which will be described later, in accordance with a time interval at which the output synchronization signal b is extracted, and outputs a phase comparator output switching switch (SWA).
5, and as shown in FIG. 5, SWA5 switches the phase signal d and phase signal e of PC4 according to this switching signal f, and
The signal is output to a low-pass filter (LPF) 6 as an output signal g. The LPF output signal h of the LPF 6 is input to a voltage controlled oscillator (VCO) 7, and the VCO 7 is a clock signal i having a frequency corresponding to the input.
Is generated and output from the output terminal 9, and the clock signal i
Is input to a 1 / n frequency divider 8 (n is a positive integer) and is divided, and the frequency-divided signal c divided by 1 / n is input to the other input terminal of PC4.

As shown in FIG. 3, PC4 has two phase comparators, that is, a phase comparator (PCA) 21 whose output holding function is a normal one.
And a phase comparator (PCB) 22 for holding the output for a long period of time. Both the PCA 21 and the PCB 22 receive the output synchronizing signal b and the frequency-divided signal c, and as shown in FIG. , And a phase signal d whose normal output is held and a phase signal e whose output is held for a long time are sampled and held by the output synchronizing signal b and output to the SWA5.

The LPF 6 is composed of an active filter as shown in FIG. 4, and the switching signal generation circuit (SELB) 17 switches the resistance of the resistance switching switch (SWB) 16 according to the SWA output signal g input from the SWA 5. Create a resistor (R ₁ ) 14 with SWB16
And the resistance (R ₂ ) 15 (R ₁ > R ₂ ), and if the output signal g changes suddenly, select the resistance (R ₂ ) 15 with SWB16 and increase the gain of the active filter to increase the LPF output signal h. ing. In FIG. 4, reference numeral 18 denotes a capacitor, 19 denotes a resistor (R ₃ ), and 20 denotes an operational amplifier.

With the above configuration, when a small skew or a small dropout occurs, no synchronization signal is output from the window by DISCRI2, and no disturbance is given to the PLL loop by the output holding function of PC4. Therefore, the PLL output (clock signal i) is output stably.

When the state is changed in the special search mode, the output of the PC 4 changes in a short period of time even though the synchronization signal a is in the window. This is realized by increasing the active gain and increasing the output signal h to the VCO 7 in the LPF 6.

Furthermore, if a large skew occurs during head switching or a large dropout occurs and the synchronization signal is not extracted from DISCRI2 for a long period of time, the output of SWA5 is switched by SELA3 and the holding function is switched from the normal PCA21 phase signal d to the PCB22 with long-term holding function. By switching to the phase signal e of
No disturbance is applied to the LL loop, and the PLL output (clock signal i) is output stably.

In this way, even when a skew or dropout occurs, or in the special search mode, a stable PLL output can be obtained with a quick pull-in, and a great effect can be obtained by using it in a signal processing circuit such as a VTR. Can be.

Effects of the Invention As described above, according to the present invention, the synchronization signal extracting means extracts only synchronization signals at correct time intervals, thereby
PL even when small skew or small dropout occurs
Since no disturbance is given to the L loop, a stable PLL output (clock signal) can be obtained. Further, when the output signal of the phase comparator changes in a short time such as in the special search mode, the PLL loop can be quickly stabilized by changing the gain of the low-pass filter to increase the response speed. Further, when a large skew or a large dropout occurs, any disturbance is given to the PLL loop by switching the output of the phase comparator from the phase signal held for a long time to the phase signal held for a long time. Because there is no PLL, a stable PLL output can be obtained. As described above, a stable PLL output can be obtained with a quick pull-in, and a great effect can be obtained by using the same in a signal processing circuit such as a VTR.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock signal reproducing circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a synchronous signal discriminating / extracting circuit of FIG. 1, and FIG. 3 is a block diagram of a phase comparator of FIG. FIG. 4 is a block diagram of the low-pass filter of FIG. 1,
FIG. 5 is a main part waveform diagram of the clock signal reproducing circuit of FIG. 1,
FIG. 6 is a waveform diagram of the phase comparator of FIG. 1 ... input terminal, 2 ... synchronization signal discrimination extraction circuit, 3 ...
Phase comparator output switching signal generation circuit, 4... Phase comparator,
5: phase comparator output switching switch, 6: low-pass filter, 7: voltage-controlled oscillator, 8: 1 / n frequency divider, 9
…… Output terminal, 10… Sync signal interval counting circuit, 11… Average sync signal interval data creation circuit, 12… Window generation circuit, 13… Gate circuit, 14… Resistance, 15… Resistance, 16
…… Resistance switching switch, 17 …… Switching signal generation circuit, 18…
... capacitors, 19 ... resistors, 20 ... operational amplifiers, 21 ...
Phase comparator, 22 ... phase comparator, a ... synchronization signal, b ...
... output synchronization signal, c ... frequency-divided signal, d, e ... phase signal,
f: switch signal, g: SWA output signal, h: LPF output signal, i: clock signal, j: count data, k: average data, l: window signal, m: switch signal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/91-5/95

Claims (1)

(57) [Claims] 1. A voltage controlled oscillator for outputting a clock signal having a frequency corresponding to an input level, the clock signal being input, and dividing the clock signal by 1 / n (n is a positive integer) and outputting it. A frequency divider and a synchronization signal are input, the synchronization signal interval is counted in fixed clock units based on this synchronization signal, the counted synchronization signal intervals are averaged, and the next synchronization signal is generated based on this average data. Synchronizing signal extracting means for generating and outputting only a synchronizing signal at a correct time interval using the window signal as a gate signal, and a synchronizing signal output from the synchronizing signal extracting means, The clock signal divided by the frequency divider is input and the phases of these synchronization signals and the clock signal are compared, and a phase signal whose output is held for a normal time and a phase signal whose output is held for a long time are output. That the phase comparator, the inputs of the synchronizing signal output from the synchronization signal extraction means, 2 of the phase comparator output according to the time interval that the synchronizing signal is extracted
Selecting means for selecting and outputting two phase signals, and inputting the phase signal of the phase comparator selected by the selecting means,
A clock signal reproducing circuit comprising: a low-pass filter that changes the gain when the phase signal changes suddenly and outputs the same to the voltage-controlled oscillator.