JPH0435183A - Horizontal synchronizing signal detector - Google Patents

Abstract

PURPOSE:To detect time axis fluctuation surely and stably by detecting a horizontal synchronizing signal surely and stably even in a reproduced video signal including much noise with deteriorated S/N. CONSTITUTION:A gate pulse generating circuit 15 reproduces a reproduction video signal at a horizontal synchronizing signal period of 63.55musec in the NTSC system by the speed correction of the VTR. Moreover, for example, no synchronizing signal exists at a front edge part of a gate pulse in a gate circuit 13, it is discriminated that the synchronizing signal is missing and a correction pulse is generated based on the front edge of the gate pulse and outputted to correct the synchronizing signal almost in the regular position.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a video tape recorder (hereinafter abbreviated as VTR).
The present invention relates to a horizontal synchronization signal detection device for detecting a horizontal synchronization signal including time axis fluctuations from a reproduced signal.

Conventional technology In recent years, with the rapid development of semiconductor technology, large-scale digital circuits have been converted to LSIs, and A/Ds that can operate at video rates have become available.
, D/A converters can be realized at low cost, and consumer VT
Even in R, etc., it is possible to implement a time base variation correction device (time base collector) etc. using digital memory. This time axis fluctuation correction device corrects time axis fluctuations in a reproduced video signal caused by relative speed fluctuations between a tape and a cylinder in a VTR.

In order to correct the time axis fluctuation of the reproduced video signal, the time axis fluctuation must be detected from the reproduced signal. This time axis variation is generally detected using a synchronization signal of the reproduced signal.

Hereinafter, a conventional synchronization signal detection device will be explained with reference to FIG.

A reproduced video signal inputted from an input terminal 1 is separated into a synchronization signal by a synchronization separation circuit 2, and is inputted to a gate circuit 3 as well as an equalization pulse removal circuit 5. After the equalization pulse is removed from the synchronization signal input to the equalization pulse removal circuit 5, the synchronization signal is sent to a phase comparator (PC) 6. The signal is input to a so-called automatic frequency control oscillator 10 consisting of a low pass filter (LPF) 7° and a voltage control oscillator (VCO) 8. The output signal from the voltage controlled oscillator 8 of the automatic frequency controlled oscillator 10 is input to the gate width adjustment circuit 9, and the output signal is input to the gate circuit 3. The synchronization signal gated by the gate circuit 3 is output to an output terminal 4.

The specific operation of the conventional horizontal synchronization signal detection device configured as described above will be explained using FIGS. 5 and 6. However, FIG. 6 is an output waveform diagram of each circuit in FIG. 5, and the same signals are given the same symbols.

A reproduction signal a inputted from an input terminal 1 is separated into a synchronization signal by a synchronization separation circuit 2. The equalization pulse removal circuit 5 removes the equalization pulse near the vertical synchronization signal from the separated synchronization signal, and outputs it as a horizontal synchronization signal pulse C to the phase comparator 6.
is output to. Further, the output pulse d from the voltage controlled oscillator 8 whose free-running oscillation frequency is near the horizontal synchronizing signal period (fh=15.734 KHz) is input to the phase comparator 6. Since the phase difference voltage from the phase comparator 6 passes through the low-pass filter 7 and is fed back to the voltage controlled oscillator 8,
The output pulse d from the voltage controlled oscillator 8 always operates in phase synchronization with the horizontal synchronizing signal pulse C. The output pulse d from the voltage controlled oscillator 8 synchronized with the horizontal synchronization signal pulse C is adjusted by the gate width adjustment circuit 9 to a gate pulse e that is gated for a period of 2 to 3 μsec before and after the trailing edge of the synchronization signal. It is input to circuit 3. The synchronizing signal S is input to a gate circuit 3, gated with a gate pulse e, and outputted to an output terminal 4 as an output pulse f. Since the gate pulse e is outputted from the automatic frequency control oscillator 10, it is outputted with a stable horizontal synchronization signal period and is not easily affected by noise. Therefore, even if there is noise at a position far enough from the trailing edge of the synchronizing signal as shown in A in FIG. 5A, it can be easily gated and removed.

By optimally selecting the gate width of the gate pulse e, the response characteristics of the automatic frequency control oscillator 10 can be adjusted as described in 2 below.
It is possible to stably detect the trailing edge of the synchronization signal, which is not easily affected by the video signal portion, and to detect time axis fluctuations.

Problems to be Solved by the Invention However, in the conventional configuration as described above, when the S/N of the reproduced video signal is unstable and there is noise near the trailing edge of the synchronization signal (B in Fig. 5a), ),
A plurality of pulses are detected in the vicinity of a regular synchronizing signal pulse in the synchronizing signal pulse f gated by the gate circuit 3, resulting in a problem that time axis fluctuations are erroneously detected.

In view of this, the present invention has been developed to ensure that the trailing edge of the synchronization signal is detected even when synchronization signal pulses are missing due to poor S/N ratio of the reproduced video signal, or when there is thin pulse-like noise between the synchronization signal pulses. An object of the present invention is to provide a horizontal synchronization signal detection device that can detect horizontal synchronization signals.

Means for Solving the Problem In order to achieve this object, the horizontal synchronization signal detection device (claim 1) of the present invention includes a synchronization separation means for separating a synchronization signal from a reproduced video signal, and a gate for generating a gate pulse. a pulse generating means, a gate means for gating the trailing edge of the synchronization signal by the gate pulse to output a synchronization signal pulse, and a clock generation means for generating a clock phase-synchronized with the synchronization signal pulse output from the gate means; head switching detection means for inputting a head switching signal and outputting a detection signal for detecting a period from a head switching point to a predetermined period to the gate pulse generation means; 1 horizontal synchronization period counter counts, the count output is decoded to generate a first gate pulse, and the counter is reset by the trailing edge of the synchronization signal pulse, and the period of the detection signal output from the switching detection means. This device generates and outputs a second gate pulse whose decoded value is changed, and is constructed by the following two means.

Further, the horizontal synchronization signal detection device (claim 2) of the present invention includes:
synchronization separation means for separating a synchronization signal from a reproduced video signal;
gate pulse generation means for generating a gate pulse; gate means for gating the trailing edge of the synchronization signal by the gate pulse to output a synchronization signal pulse; and generating a clock phase-synchronized with the synchronization signal pulse output from the gate means. head switching detection means for inputting a head switching signal and outputting a detection signal to the gate pulse generation means for detecting a period from a head switching point to a predetermined period; switching detection means for accumulating the number of times a synchronization signal does not exist within a gate pulse and outputting a switching detection signal according to the accumulated value; and PLL means for generating a signal synchronized in frequency and phase with the synchronization signal by a PLL circuit. , switching means for switching and outputting a synchronization signal from the gate means and an output signal from the PLL means according to a detection signal from the switching detection means, and the gate pulse generation means converts the clock into one horizontal line. A synchronization period counter decodes the count output and the count output to generate a first gate pulse, and the counter is reset by the trailing edge of the synchronization signal pulse, and only the period of the detection signal output from the switching detection means is decoded. It generates and outputs a second gate pulse whose value has been changed, and is constructed by the above-described means.

Function: The horizontal synchronization signal detection device of the present invention gates the synchronization signal separated by the synchronization separation means using the gate pulse generated by counting one horizontal synchronization period from the synchronization signal pulse output from the gate means using the gate pulse generation means. It is designed to detect pulses, and when a synchronizing signal pulse is missed, the counter self-resets to generate the next gate pulse to ensure stable operation.Moreover, it is designed to prevent skews that occur when switching heads. By widening the gate pulse width to a width that can sufficiently absorb the skew (approximately 20 μsec or less), malfunctions due to skew are prevented, and the gate pulse width is widened at least once per vertical period. As a result, even in the case of malfunctions caused by gate pulses, it is reset every vertical phase period.

Furthermore, when the chances of the synchronizing signal missing from the gate pulse increase due to noise or the like, the horizontal synchronizing signal detection device of the present invention determines the S/H state of the reproduced video signal based on the number of times the synchronizing signal has missed, and if the number of times has increased. If so, use PL that is resistant to noise.
It is designed to switch to a horizontal pulse consisting of an L circuit.

Embodiment A first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a block diagram of a horizontal synchronization signal detection device in a first embodiment of the present invention.

In FIG. 1, a reproduced video signal inputted from an input terminal 11 is separated from a synchronization signal by a synchronization separation circuit 12 and outputted to a gate circuit 13. The output signal from the gate circuit 13 is sent to the gate pulse generation circuit 15 and the clock generation circuit 1.
6 and is also output to the output terminal 14. The head switching signal input from the input terminal 17 is input to the head switching detection circuit 18. The detection signal from the head switching detection circuit 18 and the clock from the clock generation circuit 16 are input to the gate pulse generation circuit 15 , and its output signal is input to the gate circuit 13 .

The specific operation of this embodiment will be explained below in Figures 1 and 2.
This will be explained with reference to the figures. However, the waveform diagram in FIG. 2 shows the output waveforms of each circuit in FIG. 1, and the same components are given the same reference numerals.

The reproduced video signal g input from the input terminal 11 is separated from the synchronization signal by the synchronization separation circuit 12 and outputted to the gate circuit 13 . The gate pulse 1 from the gate pulse generating circuit 15 is also input to the gate circuit 13, and the trailing edge of the synchronizing signal is generated by this gate pulse i, and a synchronizing signal pulse j including the gate is output. The output synchronizing signal pulse j is input to the gate pulse generation circuit 15 and also to the clock generation circuit 16. The clock and clock generation circuit 16 generates a clock whose phase is synchronized with this synchronization signal j, and inputs it to the gate pulse generation circuit 15. The head switching signal inputted to the input terminal 17 is inputted to a head switching detection circuit 18, and a head switching detection signal 1 is outputted to the gate pulse generation circuit 15.

In the gate pulse generation circuit 15, a counter reset at the trailing edge of the synchronization signal pulse j counts one horizontal synchronization period clock, and the count output is decoded to generate a gate pulse i, which generates the synchronization signal. When the pulse j is missing (C in FIG. 2), the counter is reset by self-reset, and the gate pulse i is output again after one horizontal synchronization period. Furthermore, at locations where skew exists, such as the head switching point (D in FIG. 2), malfunction of the gate circuit 13 due to the skew is prevented by widening the width of the gate pulse i. In order to sufficiently absorb this skew, it is desirable that the gate width be approximately 40 μsec or more and 80 μsec or less based on the horizontal synchronizing signal.

Next, a specific embodiment of the gate pulse generation circuit 15 will be described with reference to FIG. However, Figures 1 and 2
Signals that are the same as those in the figure are given the same symbols.

Clock generation circuit 16 input to first input terminal 19
The clock m from is input to the counter 21. The counter 21 receives a reset signal 0 obtained by ANDing the synchronizing signal pulse j from the second input terminal 20 and the self-reset n output from the counter 21 using an AND gate 22 .

From this reset signal 0, the clock m is set to 1 by the counter 21.
The horizontal synchronization period is counted and count data p is output to the decoder 22. The decoder 22 outputs a gate pulse l to the output terminal 23 based on the counter data p. The head switching detection signal l from the head switching detection circuit 18 is also input to the decoder 22 from the third input terminal 24, and the period decode value of this head switching detection signal 1 is changed to change the gate pulse width. There is.

According to the present invention, the separated synchronization signals are
By always accurately counting one horizontal synchronization period and using the gate pulse created, a stable trailing edge of the horizontal synchronization signal can always be obtained even when the S/N of the reproduced video signal is poor and affected by noise. It is something.

In the gate pulse generation circuit 15, the horizontal synchronizing signal period of the reproduced video signal is adjusted to NTSC by speed correction of the VTR.
In this method, data is reproduced at a cycle of 63.55 μsec. At this time, there is jitter (time axis fluctuation component) in the actually reproduced signal, and it is thought that this causes a variation in the period of the horizontal synchronizing signal of about 200 to 300 nsec. Furthermore, if the width of the gate pulse is too large, the detection error will increase if noise is introduced into the gate pulse, and for example, when time axis detection is performed and jitter is corrected, horizontal striped noise will result. Therefore, it is desirable that the width of the gate pulse be within the range of 63.00 μsec to 64.00 μsec from the horizontal synchronizing signal.

In addition, if the signal system is CCIR system, similarly, the gate pulse width is 63 degrees 50 μsec from the horizontal synchronization signal.
Second, a range of 64.50 μsec or less is desired.

In addition, in the gate circuit 13, for example, if there is no synchronization signal at the leading edge of the gate pulse, it is determined that the synchronization signal is missing, and a correction pulse is generated and output based on the leading edge of the gate pulse. This allows the synchronization signal to be corrected to a nearly normal position.

A second embodiment of the present invention will be described with reference to FIG. FIG. 4 shows a block diagram showing a second embodiment of the present invention. In this figure, the same numbers as those in FIG. 1 are given the same numbers.

In FIG. 4, a reproduced video signal inputted from an input terminal 11 is separated from a synchronization signal by a synchronization separation circuit 12 and outputted to a gate circuit 13. The output signal from the gate circuit 13 is sent to the gate pulse generation circuit 25 and the clock generation circuit 1.
6 is input. The head switching signal input from the input terminal 17 is input to the head switching detection circuit 18.

The detection signal from the head switching detection circuit 18 and the clock from the clock generation circuit 16 are input to the gate pulse generation circuit 25 , and its first output signal is input to the gate circuit 13 . The configuration below is similar to that of the first embodiment. The difference from FIG. 1 is that the synchronization signal from the synchronization separation circuit 12 is transferred to a phase comparator (PC) 28.
Low pass filter (LPF) 27. The signal is input to a PLL circuit consisting of a voltage controlled oscillator (VCO) 28, a so-called automatic frequency control oscillator 29, and an output signal from the voltage controlled oscillator 28 synchronized with a synchronization signal is input to a switching circuit 30. Further, the output signal from the gate circuit 13 is also input to the switching circuit 30. A second output signal from the gate pulse generation circuit 25 is input to the switching control circuit 31, and the output from the switching control circuit 31 allows the output from the voltage controlled oscillator 28 and the output signal from the gate circuit 13 to be combined. It is switched and output to the output terminal 32.

The detailed operation of the horizontal synchronizing signal detecting device configured as described above will be described below with reference to FIG. 4.

The reproduced video signal inputted from the input terminal 11 is separated from the synchronizing signal by the synchronizing signal separation circuit 12 and sent to the gate circuit 1.
3 is output. The gate circuit 13 also receives the gate I pulse from the gate pulse generation circuit 25, and uses this gate pulse to gate the trailing edge of the synchronization signal and output a synchronization signal pulse. Gate pulse generation circuit 25
A self-reset signal that is generated when the synchronizing signal pulse is lost is also output from , and is input to the switching control circuit 31 . The output synchronizing signal pulse is input to the gate pulse generation circuit 25 and the clock generation circuit 16 as well as to the switching circuit 30.

The clock generation circuit 16 generates a clock phase-synchronized with this synchronization signal pulse, and the gate pulse generation circuit 25
is being entered. The head switching signal input to the input terminal 17 is input to the head switching detection circuit 18, which outputs the head switching detection signal to the gate pulse generation circuit 25. In the gate pulse generation circuit 25, a counter that is reset at the trailing edge of the synchronization signal pulse counts and outputs one horizontal synchronization period clock, and the count output is decoded to generate a gate pulse. The counter is reset by the reset, and a gate pulse is output again after one horizontal synchronization period. Furthermore, at locations where skew exists, such as at head switching points, malfunction of the gate circuit 13 due to skew is prevented by widening the width of the gate pulse.

On the other hand, the synchronization signal separated by the synchronization separation circuit 12 is input to the phase comparator 26 in the automatic frequency control oscillator 29, and a horizontal pulse synchronized in frequency and phase with this synchronization signal is output from the voltage control oscillator 28, and the switching circuit 30 is entered. Therefore, the synchronizing signal pulse from the gate circuit 13 and the horizontal pulse from the automatic frequency control oscillator 29 are input to the switching circuit 30. \This switching circuit 30 is switched by a switching control signal from a switching control circuit 31,
It is output to the output terminal 32. The switching control circuit 31 integrates the number of outputs of the self-reset signal, and when it is below a predetermined set value, it outputs a synchronizing signal pulse from the gate circuit 13, and when it is above a predetermined set value, it outputs a synchronizing signal pulse from the automatic frequency control oscillator 2.
It outputs a control signal that outputs a horizontal pulse from 9.

As described above, according to the present invention, an accurate and stable horizontal synchronization signal is output by gating the trailing edge of the synchronization signal with a gate pulse generated stably for one horizontal synchronization period, and a self-reset signal is output. When the number of times increases, it is determined that the S/N is quite poor, and by switching to the horizontal pulse from the PLL circuit that can output stably against noise, it operates stably even when the S/H is quite poor. It is possible to provide a horizontal synchronization detection device that can perform =20.

As described in ``Effects of the Invention'', the present invention is capable of reliably and stably detecting a horizontal synchronizing signal even in a reproduced video signal with poor S/N ratio and containing a lot of noise. It has been able to detect reliable and stable time axis fluctuations, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a horizontal synchronizing signal detection device in a first embodiment of the present invention, FIG. 2 is an operating waveform diagram in the same embodiment, and FIG. 3 is a block diagram of a gate pulse generation circuit in the same embodiment. FIG. 4 is a block diagram of a horizontal synchronizing signal detecting device according to a second embodiment of the present invention, FIG. 5 is a block diagram of a conventional horizontal synchronizing signal detecting device, and FIG. 6 is an operating waveform of the conventional example shown in FIG. It is a diagram. 11.17...Input terminal, 12...Horizontal synchronization separation circuit, 13...Gate circuit, 14.32.
...output terminal, 15...gate pulse generation circuit,
16... Clock generation circuit, 18... Head switching control circuit, 29... Automatic frequency control oscillator, 3
0...Switching circuit, 31...Switching control circuit.

Claims (2)

[Claims] (1) Synchronization separation means for separating a synchronization signal from a reproduced video signal, gate pulse generation means for generating a gate pulse, and gate means for gating the trailing edge of the synchronization signal using the gate pulse and outputting a synchronization signal pulse. a clock generating means for generating a clock phase-synchronized with the synchronization signal pulse outputted from the gate means; inputting a head switching signal and generating a detection signal for detecting a period from the head switching point to a predetermined period in response to the gate pulse; head switching detection means for outputting to the generation means; the gate pulse generation means counts the clock with a one horizontal synchronization period counter, decodes the count output and generates the first gate pulse; A horizontal synchronization signal detection device that resets a counter by the trailing edge of a synchronization signal pulse and generates a second gate pulse whose decode value is changed only during the period of the detection signal output from the head switching detection means. (2) synchronization separation means for separating a synchronization signal from a reproduced video signal; gate pulse generation means for generating a gate pulse; and gate means for gating the trailing edge of the synchronization signal using the gate pulse and outputting a synchronization signal pulse. a clock generating means for generating a clock phase-synchronized with the synchronization signal pulse outputted from the gate means; inputting a head switching signal and generating a detection signal for detecting a period from the head switching point to a predetermined period in response to the gate pulse; head switching detection means for outputting an output to the generating means; switching control means for integrating the number of times a synchronization signal does not exist within a gate pulse from the synchronization signal and the gate pulse, and outputting a switching control signal in accordance with the integrated value; PLL means for generating a signal synchronized in frequency and phase with the synchronization signal by a PLL circuit; and switching and outputting the synchronization signal pulse from the gate means and the output signal from the PLL means using a control signal from the switching control means. switching means, the gate pulse generating means counts the clock with a one horizontal synchronization period counter, decodes the count output to generate a first gate pulse, and generates a first gate pulse by a trailing edge of the synchronization signal pulse. A horizontal synchronizing signal detection device that resets a counter and generates a second gate pulse whose decoded value is changed only during the period of the detection signal output from the switching detection means.