JP4576408B2 - Limiter amplifier circuit - Google Patents

Description

  The present invention relates to a limiter amplifier circuit having excellent response to a high-speed burst signal.

  As an optical transmission system that enables high-speed data transmission, a passive optical network (PON) system that time-multiplexes a packet of data signals for each subscriber is known. In this system, an optical receiving circuit is used to receive a burst signal.

  FIG. 15 is a diagram illustrating a conventional optical receiver circuit. The photodiode 100 converts a minute optical signal into a current signal. A transimpedance amplifier (TIA: Trans Impedance Amplifier) 101 converts this current signal into a voltage signal and amplifies it. The limiter amplifier circuit 102 amplifies the output signal of the transimpedance amplifier 101 to a constant amplitude.

  FIG. 16 is a diagram illustrating an output signal of the transimpedance amplifier of the optical receiver circuit of FIG. A DC offset occurs in each of the positive phase output IP and the negative phase output IN of the transimpedance amplifier. The DC offset of the input signal is multiplied by the gain of the transimpedance amplifier. Although the magnitude of the DC offset varies depending on individual differences of the transimpedance amplifiers, when the DC offset is large, there is a problem that the burst responsiveness of the limiter amplifier circuit is degraded and good responsiveness cannot be obtained.

  FIG. 17 is a diagram illustrating a conventional optical receiver circuit having an AC coupling configuration. Coupling capacitors C1 and C2 are provided between the transimpedance amplifier and the limiter amplifier circuit. Thereby, the influence of the DC offset of the optical receiver circuit of FIG. 15 can be eliminated.

  FIG. 18 is a diagram showing the positive phase output of the transimpedance amplifier of the optical receiver circuit of FIG. 17, and FIG. 19 is a diagram showing the negative phase output. There is a problem that it takes time until the DC level changes due to the time constant determined by the coupling capacitors C1 and C2 and the input impedance 50Ω of the limiter amplifier circuit 102, and an appropriate DC offset is obtained.

  Therefore, a limiter amplifier circuit is proposed in which an offset adjustment circuit is provided without using a coupling capacitor (see, for example, Patent Document 1). The offset adjustment circuit detects the DC component of the positive-phase input signal and the DC component of the negative-phase input signal by the peak detection circuit, negatively feeds back the voltage difference to the differential amplifier circuit, and performs differential amplification according to this potential difference. The DC offset voltage of the differential output signal of the circuit is adjusted. Thereby, good responsiveness can be obtained.

JP 2006-311210 A

  However, the conventional limiter amplifier circuit provided with the offset adjustment circuit has a problem that the DC output levels of the positive phase output signal and the negative phase output signal become equal when no differential input signal is input.

  When the burst signal speed is 1 Gb / s (GPON / GEPON), the response of the peak detection circuit can be ignored. However, in the future 10 Gb / s (10G-PON) high-speed signal, the response of the peak detection circuit becomes a problem. A peak detection circuit having a high hold performance using a MOS transistor with little leakage cannot follow a change in the DC level of the differential input signal, and thus cannot operate normally.

  The present invention has been made in order to solve the above-described problems. The first object of the present invention is to obtain a good response and to output a positive phase when no differential input signal is input. A limiter amplifier circuit capable of preventing the DC output levels of the signal and the negative-phase output signal from becoming equal is obtained.

  A second object of the present invention is to provide a limiter amplifier circuit that can obtain a good response to a high-speed burst signal and can perform a normal operation.

A limiter amplifier circuit according to the present invention includes a first differential amplifier circuit that amplifies a differential input signal composed of a positive phase input signal and a negative phase input signal, and a differential output signal of the first differential amplifier circuit. The DC offset voltage of the differential output signal of the first differential amplifier circuit is determined according to the voltage difference between the second differential amplifier circuit to be amplified and the DC component of the positive phase input signal and the DC component of the negative phase input signal. The DC offset of the differential output signal of the second differential amplifier circuit according to the DC component and the reference voltage of one signal of the differential output signal of the first offset adjustment circuit to be adjusted and the second differential amplifier circuit A second offset adjustment circuit that adjusts the voltage, the reference voltage is adjusted to a predetermined value, and when the differential input signal is input, the second offset adjustment circuit is connected to the second differential amplifier circuit. No DC offset is added to the DC offset voltage of the differential output signal If the differential input signal is not input for adding a DC offset to DC offset voltage of the differential output signal of the second differential amplifier circuit. Other features of the present invention will become apparent below.

  According to the present invention, good responsiveness can be obtained, and when the differential input signal is not input, it is possible to prevent the DC output levels of the positive phase output signal and the negative phase output signal from becoming equal.

  FIG. 1 is a block diagram showing a limiter amplifier circuit according to an embodiment of the present invention. The differential amplifier circuit 11 (first differential amplifier circuit 11) amplifies a differential input signal composed of a normal phase input signal IP and a negative phase input signal IN. The differential amplifier circuits 12 and 13 (second differential amplifier circuit 12) amplify the differential output signal of the differential amplifier circuit 11.

  The first offset adjustment circuit 14 includes a first peak detection circuit 15, a second peak detection circuit 16, and a differential amplifier circuit 17 (third differential amplifier circuit). The first peak detection circuit 15 detects and holds the direct current component of the positive phase input signal IP. The second peak detection circuit 16 detects and holds the direct current component of the negative phase input signal IN. The differential amplifier circuit 17 provides the differential amplifier circuit 11 with a voltage difference between the DC component of the positive phase input signal IP and the DC component of the negative phase input signal IN detected by the first and second peak detection circuits 15 and 16. Negative feedback is performed, and the DC offset voltage of the differential output signal of the differential amplifier circuit 11 is adjusted according to this potential difference.

  The second offset adjustment circuit 18 includes a third peak detection circuit 19 and a differential amplifier circuit 20 (fourth differential amplifier circuit). The third peak detection circuit 19 detects and holds the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated. The differential amplifier circuit 20 applies the voltage difference between the DC component of one of the differential output signals of the differential amplifier circuit 12 detected by the third peak detection circuit 19 and the reference voltage REF to the differential amplifier circuit 12. Feedback is performed, and the DC offset voltage of the differential output signal of the differential amplifier circuit 12 is adjusted according to this potential difference.

  FIG. 2 is a circuit diagram showing a pre-stage portion of the limiter amplifier circuit of FIG. The differential amplifier circuit 11 includes transistors Q1 to Q6, load resistors R1 and R2, and constant current circuits I1 to I4. The pair of transistors Q1 and Q2 (first differential transistors) receive differential input signals IP and IN from bases (input terminals), respectively. A pair of load resistors R1, R2 (first load resistors) are respectively connected between the collectors (output terminals) of the pair of transistors Q1, Q2 and the constant voltage terminal VCC (first constant voltage terminal). . A constant current circuit I1 is connected between the emitters of the commonly connected transistors Q1 and Q2 and the constant voltage terminal VEE.

  The collectors of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively. A constant current circuit I2 is connected between the emitters of the commonly connected transistors Q3 and Q4 and the constant voltage terminal VEE. The collectors of the transistors Q5 and Q6 are connected to the constant voltage terminal VCC, and the bases are connected to the collectors of the transistors Q1 and Q2, respectively. Constant current circuits I3 and I4 are connected between the emitters of the transistors Q5 and Q6 and the constant voltage terminal VEE, respectively. Differential output signals POS and NEG of the differential amplifier circuit 11 are output from the emitters of the transistors Q6 and Q5.

  The first peak detection circuit 15 includes a first bipolar transistor Q7, a second bipolar transistor Q8, load resistors R3 and R4, a constant current circuit I5, a diode D, and a capacitor C. A signal is input from the base of the first bipolar transistor Q7. The second bipolar transistor Q8 forms a differential pair with the first bipolar transistor, and outputs the output signal of the first peak detection circuit 15 from the base. Load resistors R3 and R4 are connected between the collectors of the first and second bipolar transistors Q7 and Q8 and the constant voltage terminal VCC. A constant current circuit I5 is connected between the emitters of the first and second bipolar transistors Q7 and Q8 connected in common and the constant voltage terminal VEE. The diode D is connected between the collector and the base of the second bipolar transistor Q8. The capacitor C is connected between the base of the second bipolar transistor Q8 and the constant voltage terminal VEE (second constant voltage terminal). The second and third peak detection circuits 16 and 19 have the same configuration.

  A diode D and a capacitor C are connected in series between the collector of the second bipolar transistor Q8 and the power source VEE to extract a DC component. As a result, a charge corresponding to the DC component of the signal is accumulated in the capacitor C via the diode D. Here, by providing a discharge path by connecting the base of the second bipolar transistor Q8 between the capacitor C and the diode D, a potential corresponding to a change in the DC level of the differential input signal can be obtained.

  In the first peak detection circuit 15 on the positive phase input side, the high level is increased by the input amplitude when the differential input signal is input than when the differential input signal is not input. On the other hand, the high level of the second peak detection circuit 16 on the reverse phase input side does not change. Therefore, even if the same peak detection circuit is used, the response of the second peak detection circuit 16 on the reverse phase input side is delayed. In order to improve the symmetry of the first and second peak detection circuits 15 and 16, a differential amplifier circuit 17 is provided.

  The differential amplifier circuit 17 includes transistors Q9 to Q12, load resistors R5 to R8, and constant current circuits I6 to I8. The transistors Q9 and Q10 receive the output signals of the first and second peak detection circuits 15 and 16 from the bases, respectively. A pair of load resistors R5 and R6 are connected between the collectors of the transistors Q9 and Q10 and the constant voltage terminal VCC, respectively. The emitters of the transistors Q9 and Q10 are connected to one ends of resistors R7 and R8, respectively. A constant current circuit I6 is connected between the other ends of the commonly connected resistors R7 and R8 and the constant voltage terminal VEE. The bases of the transistors Q11 and Q12 are connected to the collectors of the transistors Q9 and Q10, respectively, and the collectors of the transistors Q11 and Q12 are connected to the constant voltage terminal VCC. Constant current circuits I7 and I8 are connected between the emitters of the transistors Q11 and Q12 and the constant voltage terminal VEE, respectively. The differential output signal of the differential amplifier circuit 17 is output from the emitters of the transistors Q11 and Q12 to the bases of the transistors Q3 and Q4 of the differential amplifier circuit 11, respectively. As a result, the differential amplifier circuit 17 draws out a current corresponding to the voltage difference between the output signal of the first peak detection circuit 15 and the output signal of the second peak detection circuit 16 from the pair of load resistors R1 and R2. .

  FIG. 3 is a circuit diagram showing a rear stage portion of the limiter amplifier circuit of FIG. The differential amplifier circuit 12 includes transistors Q13 to Q18, load resistors R9 and R10, and constant current circuits I9 to I12. The pair of transistors Q13 and Q14 (second differential transistors) input the differential output signals POS and NEG of the differential amplifier circuit 11 from the bases (input terminals), respectively. A pair of load resistors R9 and R10 (second load resistors) are connected between the collectors (output terminals) of the pair of transistors Q13 and Q14 and the constant voltage terminal VCC (first constant voltage terminal), respectively. . A constant current circuit I9 is connected between the emitters of the commonly connected transistors Q13 and Q14 and the constant voltage terminal VEE.

  The collectors of the transistors Q15 and Q16 are connected to the collectors of the transistors Q13 and Q14, respectively. A constant current circuit I10 is connected between the emitters of the commonly connected transistors Q15 and Q16 and the constant voltage terminal VEE. The collectors of the transistors Q17 and Q18 are connected to the constant voltage terminal VCC, and the bases are connected to the collectors of the transistors Q13 and Q14, respectively. Constant current circuits I11 and I12 are connected between the emitters of the transistors Q17 and Q18 and the constant voltage terminal VEE, respectively. The differential output signal of the differential amplifier circuit 12 is output from the emitters of the transistors Q18 and Q17.

  The differential amplifier circuit 20 includes transistors Q19 to Q22, load resistors R11 to R14, and constant current circuits I13 to I15. The transistor Q19 receives the output signal of the third peak detection circuit 19 from the base, and the transistor Q20 receives the reference voltage REF from the base. A pair of load resistors R11 and R12 are connected between the collectors of the transistors Q19 and Q20 and the constant voltage terminal VCC, respectively. The emitters of the transistors Q19 and Q20 are connected to one ends of resistors R13 and R14, respectively. A constant current circuit I13 is connected between the other ends of the commonly connected resistors R13 and R14 and the constant voltage terminal VEE. The bases of the transistors Q21 and Q22 are connected to the collectors of the transistors Q19 and Q20, respectively, and the collectors of the transistors Q21 and Q22 are connected to the constant voltage terminal VCC. Constant current circuits I14 and I15 are connected between the emitters of the transistors Q21 and Q22 and the constant voltage terminal VEE, respectively. The differential output signal of the differential amplifier circuit 20 is output from the emitters of the transistors Q21 and Q22 to the bases of the transistors Q15 and Q16 of the differential amplifier circuit 12, respectively. As a result, the differential amplifier circuit 20 extracts a current corresponding to the voltage difference between the output signal of the third peak detection circuit 19 and the reference voltage REF from the pair of load resistors R9 and R10.

  Since the first offset adjustment circuit 14 is an AC coupling input, the DC offset voltage of the differential output signal of the differential amplifier circuit 11 can be adjusted following the change in the DC level of the differential input signal. Thereby, favorable responsiveness can be obtained.

  Further, when the reference voltage REF is adjusted to a predetermined value and the second offset adjustment circuit 18 receives a differential input signal (packet signal) (when there is an input signal amplitude), the second offset adjustment circuit 18 When no DC offset is added to the DC offset voltage of the differential output signal and no differential input signal (packet signal) is input (when there is no input signal amplitude), the differential output signal of the differential amplifier circuit 12 A DC offset is added to the DC offset voltage. Thus, when no differential input signal is input, the DC level is adjusted so that the positive phase output signal of the limiter amplifier circuit is low and the negative phase output signal is high. Therefore, it is possible to prevent the DC output levels of the positive-phase output signal and the negative-phase output signal of the limiter amplifier circuit from becoming equal when no differential input signal is input.

  Further, the differential output signal of the differential amplifier circuit 13 is saturated. Thereby, the second offset adjustment circuit 18 can detect the presence / absence of a packet (signal input) without depending on the input amplitude.

  In the transition period of the differential input signal, a delay corresponding to the response time of the first and second offset adjustment circuits 14 and 18 occurs. In contrast, in the present embodiment, the circuit constants of the first and second peak detection circuits 15 and 16 of the first offset adjustment circuit 14 and the third peak detection circuit 19 of the second offset adjustment circuit 18 are as follows. The circuit constants of the differential amplifier circuit 17 of the first offset adjustment circuit 14 and the differential amplifier circuit 20 of the second offset adjustment circuit 18 are equal. As a result, the response time of the first offset adjustment circuit 14 and the second offset adjustment circuit 18 can be easily matched, so that the offset is released from the state in which the offset is added in the transition period of the differential input signal. The response time can be made substantially the same by the first and second offset adjustment circuits 14 and 18. Therefore, good response can be obtained even for a high-speed burst signal, and normal operation can be performed.

  FIG. 4 is a waveform diagram showing a simulation result of the differential input signal of the limiter amplifier circuit. FIG. 5 is a waveform diagram showing simulation results of output signals of the first and second peak detection circuits. FIG. 6 is a waveform diagram showing a simulation result of the differential output signal of the third differential amplifier circuit. FIG. 7 is a waveform diagram showing a simulation result of the differential output signal of the first differential amplifier circuit. Since the limiter amplifier circuit according to the present embodiment is an AC coupled input, the DC level (high level) of the differential input signal changes depending on the capacitance value (100 pF in the simulation). On the other hand, a first offset adjustment circuit is constituted by a peak detection circuit having a discharge path. Thereby, as shown in FIG. 7, the first offset adjustment circuit takes a response time of 3 ns. After 3 ns, it can cope with the DC level change of the differential input signal.

  FIG. 8 is a waveform diagram showing the simulation result of the output signal of the third peak detection circuit. FIG. 9 is a waveform diagram showing a simulation result of the differential output signal of the fourth differential amplifier circuit. FIG. 10 is a waveform diagram showing a simulation result of the differential output signal of the second differential amplifier circuit. The second offset adjustment circuit adjusts the DC level so that when the differential input signal is not input, the positive phase output signal of the second differential amplifier circuit is low and the negative phase output signal is high. Then, by making the circuit constants of the first offset adjustment circuit and the second offset adjustment circuit the same, the response times of the first offset adjustment circuit and the second offset adjustment circuit can be easily matched.

  FIG. 11 is a waveform diagram showing a simulation result of the differential output signal of the limiter amplifier circuit. 12 to 14 are enlarged views of the circled portion of FIG. 11, and the inputs are 30 mVpp, 100 mVpp, and 300 mVpp, respectively. The circuit constants of the first offset adjustment circuit and the second offset adjustment circuit are made equal. From this simulation result, it was confirmed that the limiter amplifier circuit according to the present embodiment can respond at high speed even when the operation speed is 10 Gb / s (10 times).

It is a block diagram which shows the limiter amplifier circuit which concerns on embodiment of this invention. FIG. 2 is a circuit diagram showing a front stage portion of the limiter amplifier circuit of FIG. 1. FIG. 2 is a circuit diagram showing a rear part of the limiter amplifier circuit of FIG. 1. It is a wave form diagram which shows the simulation result of the differential input signal of a limiter amplifier circuit. It is a wave form diagram which shows the simulation result of the output signal of a 1st, 2nd peak detection circuit. It is a wave form diagram which shows the simulation result of the differential output signal of a 3rd differential amplifier circuit. It is a wave form diagram which shows the simulation result of the differential output signal of a 1st differential amplifier circuit. It is a wave form diagram which shows the simulation result of the output signal of a 3rd peak detection circuit. It is a wave form diagram which shows the simulation result of the differential output signal of a 4th differential amplifier circuit. It is a wave form diagram which shows the simulation result of the differential output signal of a 2nd differential amplifier circuit. It is a wave form diagram which shows the simulation result of the differential output signal of a limiter amplifier circuit. It is the figure which expanded the part enclosed with the circle of FIG. It is the figure which expanded the part enclosed with the circle of FIG. It is the figure which expanded the part enclosed with the circle of FIG. It is a figure which shows the conventional optical receiver circuit. FIG. 16 is a diagram illustrating an output signal of a transimpedance amplifier of the optical receiving circuit in FIG. 15. It is a figure which shows the conventional optical receiver circuit of AC coupling structure. It is a figure which shows the positive phase output of the transimpedance amplifier of the optical receiver circuit of FIG. It is a figure which shows the reverse phase output of the transimpedance amplifier of the optical receiver circuit of FIG.

Explanation of symbols

11 differential amplifier circuit (first differential amplifier circuit)
12, 13 Differential amplifier circuit (second differential amplifier circuit)
14 First offset adjustment circuit 15 First peak detection circuit 16 Second peak detection circuit 17 Differential amplifier circuit (third differential amplifier circuit)
18 Second offset adjustment circuit 19 Third peak detection circuit 20 Differential amplifier circuit (fourth differential amplifier circuit)
C Capacitance D Diode Q1, Q2 First differential transistor Q13, Q14 Second differential transistor Q7 First bipolar transistor Q8 Second bipolar transistor R1, R2 First load resistance R9, R10 Second load resistance

Claims (5)

A first differential amplifier circuit for amplifying a differential input signal composed of a normal phase input signal and a negative phase input signal;
A second differential amplifier circuit for amplifying a differential output signal of the first differential amplifier circuit;
A first offset adjustment circuit that adjusts a DC offset voltage of a differential output signal of the first differential amplifier circuit according to a voltage difference between a DC component of the positive phase input signal and a DC component of the negative phase input signal. When,
A second offset for adjusting a DC offset voltage of the differential output signal of the second differential amplifier circuit according to a DC component of one signal of the differential output signal of the second differential amplifier circuit and a reference voltage Adjustment circuit ,
When the reference voltage is adjusted to a predetermined value and the differential input signal is input, the second offset adjustment circuit converts the DC offset voltage to the DC offset voltage of the differential output signal of the second differential amplifier circuit. A limiter amplifier circuit characterized by adding a DC offset to a DC offset voltage of a differential output signal of the second differential amplifier circuit when no offset is added and the differential input signal is not inputted . 2. The limiter amplifier circuit according to claim 1 , wherein a differential output signal of the second differential amplifier circuit is saturated. The first differential amplifier circuit includes:
A pair of first differential transistors that respectively input the differential input signals from input terminals;
A pair of first load resistors respectively connected between an output terminal of the pair of first differential transistors and a first constant voltage terminal;
The second differential amplifier circuit includes:
A pair of second differential transistors that respectively input differential output signals of the first differential amplifier circuit from input terminals;
A pair of second load resistors respectively connected between an output terminal of the pair of second differential transistors and a first constant voltage terminal;
The first offset adjustment circuit includes:
A first peak detection circuit for detecting and holding a DC component of the positive phase input signal;
A second peak detection circuit for detecting and holding a DC component of the negative phase input signal;
A third differential amplifier circuit for extracting a current corresponding to a voltage difference between an output signal of the first peak detection circuit and an output signal of the second peak detection circuit from the pair of first load resistors; Have
The second offset adjustment circuit includes:
A third peak detection circuit for detecting and holding a DC component of one of the differential output signals of the second differential amplifier circuit;
Claims, characterized in that a current corresponding to the voltage difference between the output signal and the reference voltage of the third peak detecting circuit, and a fourth differential amplifier circuit is pulled out from the second load resistor of the pair The limiter amplifier circuit according to 1 or 2 . The circuit constants of the first and second peak detection circuits and the third peak detection circuit are equal, and the circuit constants of the third differential amplifier circuit and the fourth differential amplifier circuit are equal. The limiter amplifier circuit according to claim 3 . The first to third peak detection circuits are:
A first bipolar transistor that receives a signal from a base;
A second bipolar transistor that forms a differential pair with the first bipolar transistor and outputs a signal from a base;
A diode connected between a collector and a base of the second bipolar transistor;
5. The limiter amplifier circuit according to claim 1, further comprising a capacitor connected between a base of the second bipolar transistor and a second constant voltage terminal.

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