JPH09289495A - Amplifier for burst signal and optical receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the amplifier which can accurately regenerate a signal at any time in various operation environment and the optical receiving circuit which uses it. SOLUTION: First and second maximum value holding circuits 12 and 13 have the same circuit constitution, and variations which are generated inside are also equal in size and have the same direction. Further, a differential amplifier 14 has its amplification factor set to 0.5 and a variation generated inside is the same as a variation generated in the differential amplifier 11. Output variations generated by the maximum value holding circuits 12 and 13 owing to temperature variation are canceled by the differential amplifier 14. At this time, the variation generated in the differential amplifier 11 is also canceled. Then the output variation generated in the differential amplifier 14 is equalized in value to the output variation generated in the differential amplifier 11 to superpose the variation with a signal input on a reference input supplied to a differential amplifier 15. Consequently, the differential amplifier 15 can be supplied with the reference input which accurately follows up the DC level of the signal input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier and an optical receiver circuit using the same, and more particularly to an amplifier for amplifying a burst signal (a signal that appears intermittently) and an amplifier for such an amplifier. The optical receiver circuit used.

[0002]

2. Description of the Related Art Conventionally, a signal amplifier in an optical receiving circuit that handles a continuous signal is constructed by AC coupling, and a threshold level of a comparator for determining 1 or 0 is given by detecting an average value of the signal. The scheme has been taken.

In an optical receiving circuit that handles a small amount of received optical power, it is necessary to amplify a signal up to several mV, and a circuit configuration that can suppress output fluctuations due to temperature fluctuations and power supply voltage fluctuations is essential.

This AC coupling system is widely used because the bias of each stage amplifier is relatively unlikely to be affected by fluctuations in power supply voltage and temperature, and stable operation as an amplifier can be easily realized. Has been done.

However, in recent years, in the fields such as optical subscriber systems and optical interconnections, there is an increasing need to handle burst signals that intermittently exchange optical signals, and an optical receiving circuit corresponding thereto is required. There is.

In particular, in the optical subscriber system, it is necessary to consider the application range, for example, the outdoor use, and it is possible to guarantee stable operation in a wider temperature range than the conventional one. The need is growing.

In a conventional AC-coupled optical receiver circuit, when a burst signal is received, the average value of the received signal fluctuates greatly at the beginning of the burst signal, and accurate signal reproduction is impossible near the beginning of the burst signal. There is a point.

Therefore, a DC coupling method is required for a receiver that handles burst signals, but the DC coupling method has a problem that the bias is easily affected by temperature fluctuations and power supply voltage fluctuations. Hereinafter, this will be described in more detail.

Conventionally, as an optical receiving circuit based on the DC coupling system, an optical receiving circuit disclosed in Japanese Patent Laid-Open No. 6-310967 (hereinafter referred to as a first conventional example) and Japanese Patent Publication No. 7-
The optical receiving circuit disclosed in Japanese Patent No. 107943 (hereinafter referred to as the second
(Hereinafter referred to as the "conventional example"), an optical receiver circuit shown in U.S. Pat. No. 5,430,766 (hereinafter referred to as the third conventional example), and the like.

In the first conventional optical receiving circuit, the output signal of the preamplifier to which the photodiode is connected is used as the signal input of the next-stage comparator, and the first peak detecting section for detecting and holding the maximum value of the output of the preamplifier. Pulse signal and the output signal of the second peak detection unit that detects and holds the minimum value of the output of the preamplifier, and the intermediate value generated by resistance division is used as the reference input of the comparator in the next stage. The signal can be reproduced.

Further, in the second conventional optical receiving circuit, the output signal of the first transimpedance type preamplifier to which the photodiode is connected is used as the signal input of the next stage comparator, and the minimum value of the output of the first preamplifier is used. Resistance division between the output signal of the peak detection unit that detects and holds the output signal and the output signal of the second preamplifier (preamplifier to which the photodiode is not connected) for outputting the maximum value of the first preamplifier output signal. The pulse signal can be reproduced by using the intermediate value generated by the above as a reference input of the comparator in the next stage.

[0012]

In the optical receiving circuits of the first and second conventional examples, the temperature fluctuation of the peak detecting section directly affects the input of the comparator in the next stage with respect to the temperature fluctuation. There is a problem that it is difficult to use in a wide temperature range. In addition, when noise is mixed in the signal line, there is a risk that the peak detection unit will hold an incorrect peak value in response to the noise, and in this case also there is a problem that accurate signal reproduction becomes difficult. To do.

On the other hand, the third conventional optical receiving circuit is composed of a preamplifier using a differential amplifier and a comparator for receiving a differential output from the differential amplifier to obtain a digital output. In the optical receiving circuit of the third conventional example, in order to determine the reference input level of the differential amplifier which constitutes the preamplifier, the output of the peak detecting section on the + terminal side of the differential output signal is fed back and used. There is. Therefore, if there is a temperature change or a power supply voltage change, the output change of the peak detection unit affects the preamplifier output, which makes it difficult to accurately reproduce the signal in a wide temperature range.
Further, when noise is mixed in the signal line, there is a risk that the peak detection unit may hold an erroneous peak value in response to the noise, and also in this case, it is difficult to accurately reproduce the signal. Exists.

By the way, in an optical communication system such as a passive double star configuration in which a plurality of terminals are connected to an exchange through a star coupler, each terminal is temporally separated by the TDMA method to perform signal transmission. Even in such a case, the light emission levels of the respective terminals at the timing of originally not transmitting may be summed up to become a level that cannot be ignored with respect to the signal level. In addition, if a configuration is adopted in which different signals are exchanged at multiple wavelengths by using wavelength multiplexing technology, and if the wavelength-multiplexed light isolation is insufficient in the optical module, the optical signal of the unnecessary wavelength is It is conceivable that the light may go around the conversion element and adversely affect the background light.

In the third conventional optical receiving circuit, in order to avoid the influence of the background light as described above, two peak detecting portions for detecting and holding the respective maximum values of the differential outputs of the preamplifier are provided, The feedback control is realized in which the difference between the outputs of these two peak detectors is taken and the current source is controlled so as to eliminate the difference. However, in such a configuration, two feedback loops are used, and there is a problem that it is difficult to optimally set the time constant.

Therefore, it is an object of the present invention to operate under various operating environments (for example, ambient temperature fluctuations, power supply voltage fluctuations, noise from power sources, etc., or background light. (3) also provides an amplifier and a light receiving circuit using the same, which can always reproduce a signal accurately.

[0017]

Means for Solving the Problems and Effects of the Invention The present invention has the following features in order to achieve the above-mentioned objects. A first aspect of the present invention is an amplifier for amplifying an input burst signal, which amplifies the burst signal, and the amplification result appears vertically symmetrical with respect to an offset voltage which is an output voltage when there is no input. A first amplifier circuit that outputs a differential output including first and second outputs, and a first peak value holding circuit that detects and holds the peak value of the first output of the first amplifier circuit And a second peak value holding circuit for detecting and holding a peak value of the second output of the first amplifier circuit (however, a peak value in the same direction as the peak value detected by the first peak value holding circuit). And a second amplifier circuit that generates a reference voltage that follows the DC level of the first output of the first amplifier circuit by differentially amplifying the outputs of the first and second peak value holding circuits. I have it.

In the first aspect of the invention, since the first and second peak value holding circuits both detect the peak value in the same direction, the output fluctuation also appears in the same direction. Therefore, when the outputs of the first and second peak value holding circuits are differentially amplified by the second amplifier circuit, mutual output fluctuations are canceled out and an accurate reference voltage is obtained. Therefore, even when power supply voltage fluctuations or temperature fluctuations occur, fluctuations in the peak detector can be absorbed, and the burst signal can be accurately amplified with a simple configuration.

A second invention is the same as the first invention,
The amplification factor of the second amplifier circuit is set to around 0.5, and the offset voltage, which is the output voltage when the differential input of the second amplifier circuit is not input, is the offset voltage of the first amplifier circuit. Is set to be almost equal to.

In the second aspect of the invention, the amplification factor of the second amplifier circuit is set to 0.5, and the offset voltage thereof is set to be equal to the offset voltage of the first amplifier circuit. The level of the reference voltage output from the amplifier circuit is accurately adjusted to the position of the center of the signal amplitude of the first output in the first amplifier circuit.

A third invention is the same as the second invention,
The first and second amplifier circuits are characterized in that their respective circuit configurations and circuit constants are determined in association with each other so that the fluctuations in the outputs due to the respective internal circuits become equal to each other.

According to the structure of the third invention, a fluctuation equivalent to the fluctuation of the output generated in the first amplifier circuit appears in the same direction in each of the first and second peak value holding circuits. It is superimposed on the reference voltage in the second amplifier circuit.
Here, the variation of the output generated in the first amplifier circuit is
Since it is canceled when the differential amplification is performed by the second amplification circuit, equivalently, the reference voltage output from the second amplification circuit includes only the fluctuation amount of the output generated in the first amplification circuit. become. Then, since the first and second amplifier circuits are configured so that the output fluctuations are equal to each other, the reference voltage accurately follows the fluctuation of the signal output from the first amplifier circuit. Become.

A fourth invention is the same as the above-mentioned third invention,
The first and second peak value holding circuits have the same circuit configuration.

According to the fourth aspect of the invention, the fluctuations generated in the first and second peak value holding circuits are the same, and differential amplification is performed in the second amplifier circuit.
Those fluctuations can be made almost zero.

A fifth invention is the same as the above-mentioned fourth invention,
The first and second peak value holding circuits respectively include the first and second peak value holding circuits.
The first and second maximum value holding circuits for detecting and holding the maximum values of the first and second outputs of the amplifier circuit.

A sixth invention is the same as the above-mentioned third invention,
The first amplification circuit includes at least first and second transistors whose emitters are commonly connected to each other, a first current source connected to commonly-connected emitters of the first and second transistors, and a first current source. A second amplifier circuit including a first resistor interposed between the collector of the first transistor and the power supply line, and a second resistor interposed between the collector of the second transistor and the power supply line. Is interposed between at least the third and fourth transistors, a third resistor whose one end is connected to the emitter of the third transistor, and the collector of the third transistor and the power supply line. And a fourth resistor having a resistance value equal to that of the resistor
A fifth resistor connected to the emitter of the second transistor and having a resistance value equivalent to that of the third resistor, and a fifth resistor connected between the collector of the fourth transistor and the power supply line, and a resistor equivalent to the second resistor. A sixth resistor having a value and the other ends of the third and fifth resistors have the same configuration as the first current source, and the value of the current flowing therethrough is also the first current. A second current source having a value equal to the value of the current flowing through the source.

A seventh invention is the above-mentioned first invention,
The first amplifier circuit receives the burst signal as a signal input, receives a fixed voltage temporarily set for the DC level of the burst signal as a reference input, and differentially amplifies the burst signal based on the fixed voltage. Includes a differential amplifier.

An eighth invention is the same as the above-mentioned first invention,
A first amplifier circuit receives a first output of the first amplifier circuit as a signal input, receives a reference voltage output from the second amplifier circuit as a reference input, and differentially amplifies the first output based on the reference voltage. The amplifier circuit of 3 is further provided.

A ninth aspect of the invention is the same as the first aspect of the invention.
Receiving the first output of the first amplifier circuit as a signal input, the reference voltage output from the second amplifier circuit as a reference input, and discriminating the first output using the reference voltage as a threshold value. Therefore, a comparator for shaping the output of the first amplifier circuit into a digital waveform is further provided.

A tenth aspect of the present invention is an optical receiving circuit for receiving and amplifying an optical burst signal, wherein a photoelectric conversion element for converting the received optical burst signal into a current signal and a current signal from the photoelectric conversion element. Is converted into a voltage signal and amplified, and the amplification result is output in the form of a differential output including first and second outputs that appear symmetrically up and down with respect to an offset voltage that is an output voltage when there is no input. A first amplifier circuit, a first peak value holding circuit that detects and holds a peak value of a first output of the first amplifier circuit, and a peak value of a second output of the first amplifier circuit (however, , A second peak value holding circuit for detecting and holding a peak value in the same direction as the peak value detected by the first peak value holding circuit and the outputs of the first and second peak value holding circuits. By amplifying, the first output of the first amplifier circuit And a second amplifier circuit for generating a reference voltage to follow the the DC level.

In the tenth aspect of the invention, since the first and second peak value holding circuits detect the peak values in the same direction, the output fluctuations also appear in the same direction. for that reason,
If the outputs of the first and second peak value holding circuits are differentially amplified by the second amplifier circuit, mutual output fluctuations are canceled out and an accurate reference voltage is obtained. Therefore, fluctuations in the peak value holding circuit due to temperature fluctuations and power supply voltage fluctuations can be absorbed, and the burst signal can be accurately amplified with a simple configuration.

In an eleventh aspect based on the tenth aspect, the amplification factor of the second amplifier circuit is set to around 0.5, and the differential input of the second amplifier circuit is not input. The offset voltage, which is the output voltage, is set to be substantially equal to the offset voltage of the first amplifier circuit.

In the eleventh aspect of the invention, the amplification factor of the second amplifier circuit is set to 0.5, and the offset voltage thereof is set to be equal to the offset voltage of the first amplifier circuit. The level of the reference voltage output from the amplifier circuit is accurately adjusted to the position of the center of the signal amplitude of the first output in the first amplifier circuit.

In a twelfth aspect based on the eleventh aspect, the first and second amplifying circuits have respective circuit configurations and circuit constants so that the fluctuations in the outputs caused by the respective internal circuits become equal to each other. Is determined in association with each other.

According to the structure of the twelfth aspect of the present invention, the fluctuation amount equivalent to the fluctuation amount of the output generated in the first amplifier circuit is the first fluctuation amount.
And the second peak value holding circuit respectively appear in the same direction, and thus are superimposed on the reference voltage in the second amplifier circuit. Here, the variation of the output generated in the first amplifier circuit is
Since it is canceled when differential amplification is performed in the second amplifier circuit, equivalently speaking, the reference voltage output from the second amplifier circuit includes only the fluctuation of the output generated in the first amplifier circuit. Will be included. Then, since the first and second amplifier circuits are configured so that the output fluctuations are equal to each other, the reference voltage accurately follows the fluctuation of the signal output from the first amplifier circuit. Become.

In a thirteenth aspect based on the twelfth aspect, the first and second peak value holding circuits have the same circuit configuration.

According to the structure of the thirteenth aspect of the invention, the fluctuations generated in the first and second peak value holding circuits are the same, and the fluctuations are caused by performing differential amplification in the second amplifier circuit. Minutes can be close to zero.

In a fourteenth aspect based on the thirteenth aspect, the first and second peak value holding circuits are respectively
It includes first and second maximum value holding circuits that detect and hold the maximum values of the first and second outputs of the first amplifier circuit.

In a fifteenth aspect based on the twelfth aspect, the first amplifying circuit includes at least a first differential amplifier, first and second emitter followers, and first and second feedback circuits. The first differential amplifier is composed of a resistor and a first and a second emitter whose emitters are commonly connected.
The first transistor, the first current source connected to the commonly connected emitters of the first and second transistors, and the first resistor interposed between the collector of the first transistor and the power line. A current signal including a second resistor inserted between the collector of the second transistor and the power supply line and output from the photoelectric conversion element is given to the base of the first transistor and supplied to the base of the first transistor. The inverting output of the first differential amplifier obtained from the collector is output via the first emitter follower, and the non-inverting output of the first differential amplifier obtained from the collector of the second transistor is the second inverted output of the second differential amplifier. The output of the first emitter follower is output to the base of the first transistor via the first feedback resistor, and the output of the second emitter follower is output. Is fed back to the base of the second transistor via the second feedback resistor, and the second amplifier circuit has a base connected to a third transistor receiving the output of the first peak value holding circuit. A fourth transistor for receiving the output of the second peak value holding circuit,
A third resistor interposed between the collector of the third transistor and the power supply line and having a resistance value equivalent to that of the first resistor;
A fourth resistor interposed between the collector of the fourth transistor and the power supply line and having a resistance value equivalent to that of the second resistor;
A fifth resistor whose one end is connected to the emitter of the third transistor, a sixth resistor whose one end is connected to the emitter of the fourth transistor, and the other end of each of the fifth and sixth resistors A second current source connected to the first current source, having a configuration equivalent to that of the first current source, and having a value of a current flowing therethrough equal to that of the current flowing to the first current source; A third emitter follower having the same structure as the second emitter follower and receiving the signal output from the collector of the fourth transistor;
Includes an emitter follower.

In a sixteenth aspect based on the tenth aspect, a reset signal is applied to the first and second maximum value holding circuits each time reception of the optical burst signal is completed each time. The second maximum value holding circuit is characterized in that, in response to the reset signal, each output voltage is set to be substantially equal to the offset voltage of the first amplifier circuit.

According to the sixteenth aspect of the invention, since the output voltages of the first and second maximum value holding circuits are reset every time the reception of the optical burst signal is completed every time, the optical burst signal to be received is received. Even if there is a considerable level difference between the two, it is possible to reproduce the signal accurately.

A seventeenth invention is the above tenth invention, wherein the first output of the first amplifier circuit is received as a signal input, and the reference voltage output from the second amplifier circuit is received as a reference input. It further comprises a third amplifier circuit that differentially amplifies the first output based on a reference voltage.

In an eighteenth aspect of the present invention based on the seventeenth aspect, the output of the third amplifier circuit is discriminated by using the level of the reference input as a threshold value to discriminate the output of the third amplifier circuit. The comparator further includes a comparator for shaping the output level of the comparator, and the reference input level of the comparator is the output level of the third amplifier circuit when the optical burst signal is not input.
It is characterized in that it is set to a level to which an offset for the noise amplitude is added.

According to the eighteenth aspect of the invention, since the low level is always output as a digital output when the optical burst signal is not input, it is possible to prevent malfunction of the clock recovery circuit connected in the subsequent stage. can do.

In a nineteenth aspect based on the tenth aspect, the first output of the first amplifier circuit is received as a signal input, and the reference voltage output from the second amplifier circuit is received as a reference input. It further comprises a comparator that shapes the output of the first amplifier circuit into a digital waveform by discriminating the first output using the reference voltage as a threshold value.

A twentieth aspect of the present invention is an optical receiving circuit for receiving and amplifying an optical burst signal, which is a photoelectric conversion element for converting the received optical burst signal into a current signal, and a current signal from the photoelectric conversion element. A preamplifier circuit that converts the voltage into a voltage signal and amplifies it, a reference voltage generation circuit that generates a reference voltage, and a main amplifier circuit that amplifies the output of the preamplifier circuit. The output of the circuit is received as a signal input, the output of the reference voltage generation circuit is received as a reference input, the signal input is differentially amplified based on the reference input, and the amplification result is the offset voltage that is the output voltage when there is no input. First and second that appear vertically symmetrical with respect to the voltage
A first amplifier circuit for outputting in the form of a differential output including the output of the first amplifier, a first peak value holding circuit for detecting and holding a peak value of the first output of the first amplifier circuit, A second peak value holding circuit for detecting and holding a peak value of the second output of the amplifier circuit (however, a peak value in the same direction as the peak value detected by the first peak value holding circuit); And a second amplifier circuit that generates a reference voltage that follows the DC level of the first output of the first amplifier circuit by differentially amplifying the output of the second peak value holding circuit.

In the twentieth aspect of the invention, since the first and second peak value holding circuits included in the main amplifier circuit detect the peak values in the same direction, their output fluctuations also appear in the same direction. Therefore, when the outputs of the first and second peak value holding circuits are differentially amplified by the second amplifier circuit, mutual output fluctuations are canceled out and an accurate reference voltage is obtained. Therefore, fluctuations in the peak value holding circuit due to temperature fluctuations and power supply voltage fluctuations can be absorbed, and the burst signal can be accurately amplified with a simple configuration.

In a twenty-first aspect based on the twentieth aspect, the amplification factor of the second amplifier circuit is set to around 0.5, and the differential input of the second amplifier circuit is not input. The offset voltage, which is the output voltage, is set to be substantially equal to the offset voltage of the first amplifier circuit.

In the twenty-first aspect of the invention, the amplification factor of the second amplifier circuit is set to about 0.5 and the offset voltage is set to be substantially equal to the offset voltage of the first amplifier circuit. The level of the reference voltage output from the second amplifier circuit is accurately adjusted to the center position of the signal amplitude of the first output in the first amplifier circuit.

In a twenty-second aspect of the invention based on the twenty-first aspect, the first and second amplifier circuits have respective circuit configurations and circuit constants so that the fluctuations in the outputs caused by the respective internal circuits become equal to each other. Is determined in association with each other.

According to the twenty-second aspect of the present invention, the fluctuation amount equivalent to the fluctuation amount of the output generated in the first amplifying circuit is the first fluctuation amount.
And the second peak value holding circuit respectively appear in the same direction, and thus are superimposed on the reference voltage in the second amplifier circuit. Here, the variation of the output generated in the first amplifier circuit is
Since it is canceled when differential amplification is performed in the second amplifier circuit, equivalently speaking, the reference voltage output from the second amplifier circuit includes only the fluctuation of the output generated in the first amplifier circuit. Will be included. Then, since the first and second amplifier circuits are configured so that the output fluctuations are equal to each other, the reference voltage accurately follows the fluctuation of the signal output from the first amplifier circuit. Become.

In a twenty-third aspect of the invention based on the twenty-second aspect, the first and second peak value holding circuits have the same circuit configuration.

According to the twenty-third aspect of the invention, the fluctuations produced in the first and second peak value holding circuits are the same, and the second amplification circuit performs the differential amplification to make those fluctuations. Minutes can be close to zero.

In a twenty-fourth aspect based on the twenty-third aspect, the first and second peak value holding circuits are respectively
It includes first and second maximum value holding circuits that detect and hold the maximum values of the first and second outputs of the first amplifier circuit.

The twenty-fifth invention is characterized in that, in the twenty-fourth invention, the reference voltage generating circuit is constituted by a fixed voltage source.

In a twenty-sixth aspect of the invention based on the twenty-fourth aspect, the reference voltage generating circuit detects the maximum value and the minimum value of the output signal from the preamplifier circuit, and outputs an intermediate value. And

In a twenty-seventh aspect based on the twenty-second aspect, the first amplifying circuit has a first transistor for receiving the output of the preamplifying circuit at its base, and an output of the reference voltage generating circuit for its base. The second transistor to receive and the first
A first resistor inserted between the collector of the transistor and the power supply line, a second resistor inserted between the collector of the second transistor and the power supply line, a first current source, and A third resistor interposed between the emitter of the first transistor and the first current source, and a third resistor interposed between the emitter of the second transistor and the first current source and equivalent to the third resistor And a fourth resistor having a resistance value of, the second amplifier circuit has a third transistor for receiving the output of the first peak value holding circuit at its base, and a second peak value holding circuit for its base. A fourth transistor that receives the output of the third transistor, a fifth resistor that is interposed between the collector of the third transistor and the power supply line, and has a resistance value equivalent to that of the first resistor, and a collector of the fourth transistor. Is inserted between the power supply line and the 6 and resistor having a value, the second first includes a current source equivalent configuration, and the value of the current flowing therethrough is equal to the value of the current flowing through the first current source
Current source, a seventh resistor interposed between the emitter of the third transistor and the second current source, and having a resistance value equivalent to that of the fifth resistor; It includes an eighth resistor interposed between the second current source and the sixth resistor and having a resistance value equivalent to that of the sixth resistor.

In a twenty-eighth aspect of the invention based on the twentieth aspect, a reset signal is applied to the first and second maximum value holding circuits each time reception of the optical burst signal is completed each time. The second maximum value holding circuit is characterized in that, in response to the reset signal, each output voltage is set to be substantially equal to the offset voltage of the first amplifier circuit.

According to the twenty-eighth aspect of the present invention, the output voltages of the first and second maximum value holding circuits are reset every time the reception of the optical burst signal is completed every time, so that the received optical burst signal is received. Even if there is a considerable level difference between the two, it is possible to reproduce the signal accurately.

In a twenty-ninth aspect of the invention based on the twentieth aspect, the main amplifying circuit includes the first and second amplifying circuits and the first amplifying circuit.
And a second peak value holding circuit as one set, and a plurality of sets of amplifier units are cascade-connected to form a multi-stage configuration.
The first amplifying circuit in the amplifying unit in the second and subsequent stages receives the first output of the first amplifying circuit in the amplifying unit in the preceding stage as a signal input, and refers to the output of the second amplifying circuit in the amplifying unit in the preceding stage. Receive as input.

A thirtieth invention is characterized in that, in the twenty-ninth invention, the amplification factor of the first-stage amplification section in the main amplification circuit is set to be lower than that of the second-stage and subsequent amplification sections. And

According to the thirtieth aspect of the present invention, the amplification factor of the first-stage amplification section in the main amplification circuit is set lower than the amplification rate of the second-stage and subsequent amplification sections. Even if the output of the reference voltage generator slightly deviates from the signal component due to the wider area and temperature fluctuations or power supply voltage fluctuations, the reference voltage level can be set accurately at 1/2 the signal position. Becomes Further, the signal can be amplified to a sufficient level in the second and subsequent amplification units.

A thirty-first invention is the thirtieth invention, wherein the first output of the first amplifier circuit in the final stage amplifier section of the main amplifier circuit is received as a signal input and is output from the second amplifier circuit. A comparator for receiving the reference voltage as a reference input and discriminating the first output using the reference voltage as a threshold value to shape the output of the first amplifier circuit into a digital waveform.

In a thirty-second aspect based on the thirty-first aspect, the reference input level of the comparator is set to the output level of the second amplifying circuit in the amplifying section at the final stage when no optical burst signal is input. It is characterized in that it is set to a level to which an offset for the noise amplitude is added.

According to the thirty-second aspect of the invention, since the low level is always output as a digital output when no optical burst signal is input, malfunction of a clock recovery circuit or the like connected in the subsequent stage is prevented. can do.

[0066]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a block diagram showing the configuration of a burst signal amplifier according to the first embodiment of the present invention. In FIG. 1, the amplifier of the present embodiment includes three differential amplifiers 11, 14 and 15 and two maximum value holding circuits 12 and 13.

A burst signal to be amplified is given as a signal input to the differential amplifier 11, and a fixed voltage (for example, generated by a constant voltage source (not shown)) is provided as a reference input.
Is given. The fixed voltage as the reference input is set to a value such that the differential amplifier 11 can always amplify the signal input in the linear amplification region. The differential amplifier 11 differentially amplifies the signal input based on the applied reference input. From the differential amplifier 11, the amplification result is taken out in the form of differential output, that is, in the form of non-inverted output and inverted output. The maximum value holding circuit 12 detects and holds the maximum value of the non-inverted output of the differential amplifier 11. Maximum value holding circuit 13
Has the same circuit configuration as the maximum value holding circuit 12, and detects and holds the maximum value of the inverted output of the differential amplifier 11. The output of the maximum value holding circuit 12 is given to the differential amplifier 14 as a signal input, and the output of the maximum value holding circuit 13 is given as a reference input. The amplification factor of the differential amplifier 14 is 0.
5 is set. Further, the differential amplifier 14 is configured such that the output voltage when the differential input is not input is the same as the output voltage when the differential input is not input in the differential amplifier 11. The output of the differential amplifier 14 is a non-inverted output. The non-inverted output of the differential amplifier 11 is given as a signal input to the differential amplifier 15, and the output of the differential amplifier 14 is given as a reference input. The amplification factor of the differential amplifier 15 is set to a predetermined value.

FIG. 2 is a diagram showing an example of a circuit configuration of the differential amplifier 11 in FIG. In FIG. 2, a current source 27 is connected to each emitter of the transistors 21 and 22 that are commonly connected. A resistor 23 is connected to the collector of the transistor 21, and a resistor 24 having the same resistance value as the resistor 23 is connected to the collector of the transistor 22. A signal input is supplied to the base of the transistor 21, and a reference input is supplied to the base of the transistor 22. The signal extracted from the collector of the transistor 21 is impedance-converted by an emitter follower composed of the transistor 25 and the current source 28, and then is output as an inverted output. The signal extracted from the collector of the transistor 22 is supplied to the transistor 26 and the current source 29.
After being subjected to impedance conversion by an emitter follower composed of and, it is derived as a non-inverted output.

FIG. 3 is a diagram showing an example of the circuit configuration of the differential amplifier 14 in FIG. In FIG. 3, a resistor 36 is connected to the emitter of the transistor 31, and a resistor 33 is connected to the collector. A resistor 37 is connected to the emitter of the transistor 32, and a resistor 34 is connected to the collector. Resistors 36 and 37 are connected to current source 38. The resistors 33 and 34 have resistance values equivalent to those of the resistors 23 and 24, respectively. Transistor 3
The signal extracted from the collector of 2 is the transistor 3
After being subjected to impedance conversion by an emitter follower composed of 5 and a current source 39, it is derived as a non-inverted output. A signal input is supplied to the base of the transistor 31, and a reference input is supplied to the base of the transistor 32.

The resistors 36 and 37 are used as local negative feedback resistors. If the transconductance of the transistors 31 and 32 is sufficiently large, the resistance 36
By setting the resistance values of and to be the same as that of the resistors 33 and 34, the amplification factor as a differential amplifier becomes 0.5.

The current source 38 has the same structure as the current source 27 of FIG. 2, and the current value flowing therethrough is also the same. Further, the current source 39 has the same configuration as the current sources 28 and 29 of FIG. 2, and the current value flowing therein is also the same.

FIG. 4 is a waveform diagram showing signals of respective parts in the embodiment of FIG. In FIG. 4A, the waveform 41
Reference numerals 42 and 42 show signal waveforms of the non-inverted output and the inverted output of the differential amplifier 11, respectively. Also, FIG.
In (a), waveforms 44 and 45 are output waveforms of the maximum value holding circuits 12 and 13, respectively.
Further, in FIG. 4A, the waveform 43 indicates the differential amplifier 1
The offset voltage is 1, that is, the output voltage when there is no differential input. In addition, in FIG.
6 shows an output waveform of the differential amplifier 14. Also,
In FIG. 4B, a waveform 47 indicates the offset voltage of the differential amplifier 14, that is, the output voltage when there is no differential input. The operation of the amplifier shown in FIG. 1 will be described below with reference to FIG.

In the differential amplifier 11, when the differential input is not input (that is, when there is no potential difference between the signal input and the reference input), the current set by the current source 27 is (1 / 2) is shunted to resistors 23 and 24, respectively. Therefore, the offset voltage (waveform 43) of the differential amplifier 11 when there is no differential input is lower than the power supply voltage by the sum of the potential drop in the resistor 23 or 24 and the base-emitter potential in the transistor 25 or 26. Determined as voltage.

Similarly, the offset voltage (waveform 47) of the differential amplifier 14 when there is no differential input is the potential drop amount due to (1/2) of the current value determined by the current source 38 flowing through the resistor 34. And the sum of the base-emitter potential of the transistor 35 is determined as a voltage lower than the power supply voltage.

When the current values of the current sources 27 and 38 are the same and the resistance values of the resistors 23, 24 and 34 are the same, the offset voltage (waveform 43) of the differential amplifier 11 and the offset of the differential amplifier 14 are set. Voltage (waveform 4
7) has the same value.

Non-inverting output of differential amplifier 11 (waveform 41)
The inverted output (waveform 42) appears at vertically symmetrical positions with the offset voltage (waveform 43) interposed therebetween. The differential amplifier 14 takes a difference between the output of the maximum value holding circuit 12 (waveform 44) and the output of the maximum value holding circuit 13 (waveform 45), and a potential obtained by multiplying the difference by 0.5 is input. The output voltage is added to the offset voltage (waveform 47) and output. Therefore, the output of the differential amplifier 14 (waveform 4
6) is located at the center of the signal amplitude of the non-inverted output (waveform 41) of the differential amplifier 11.

When there are temperature fluctuations and power supply voltage fluctuations,
The current flowing through the current source 27 varies. This allows
The non-inverted output and the inverted output of the differential amplifier 11 are changed in proportion to the potential drop by the resistors 23 and 24 in proportion to the current change. This variation appears in the plus direction or the minus direction with respect to both the inverting output and the non-inverting output of the differential amplifier 11. Therefore, in the maximum value holding circuits 12 and 13, each of the outputs fluctuates in the same direction in response to the fluctuation of the input.
At this time, although the variation due to the internal configuration is also added, the maximum value holding circuits 12 and 13 have the same configuration,
The fluctuation due to the internal structure appears as fluctuation in the same direction. Then, the variation in the same direction is
All will be canceled by.

In the differential amplifier 14, the current flowing through the current source 38 fluctuates, and the non-inverting output fluctuates by the potential drop due to the resistor 34 in proportion to the current fluctuation. However, since the current source 38 has the same configuration and the same current value as the current source 27, the fluctuation that occurs occurs in the differential amplifier 11
It becomes almost the same as the case of. The resistance value of the resistor 34 is
Since the resistances are the same as the resistances of the resistors 23 and 24, the variation due to the potential drop is also the same as that of the differential amplifier 11. Therefore, the fluctuation of the non-inverted output of the differential amplifier 11 supplied to the differential amplifier 15 as a signal input and the differential amplifier 14 supplied to the differential amplifier 15 as a reference input.
The non-inverted output fluctuation amount becomes almost the same value, and the reference input level is always set near the center of the signal amplitude appearing at the signal input. As a result, it is possible to always perform stable amplification even when there is a temperature change or a power supply voltage change.

As described above, in the first embodiment, the output variation generated in the maximum value holding circuits 12 and 13 due to the temperature variation and the power source voltage variation is differentially amplified by the differential amplifier 14. It will be canceled. At this time, the output fluctuation generated in the differential amplifier 11 is also canceled. Therefore, by setting the output fluctuation generated in the differential amplifier 14 to the same value as the output fluctuation generated in the differential amplifier 11, the fluctuation equivalent to the signal input is superimposed on the reference input given to the differential amplifier 15. There is. As a result, the differential amplifier 15 can be provided with a reference input that accurately follows the DC level of the signal input, and stable amplification can always be performed.

Note that, in general, a comparator is arranged after the differential amplifier 15, and the analog signal is converted into a digital signal by the comparator. However, when the level of the signal input to the differential amplifier 11 is high, a signal of a sufficient level can be obtained from the differential amplifier 11, so that the differential amplifier 15 does not perform signal amplification, and Non-inverting output and differential amplifier 14
Alternatively, the non-inverted output of the above may be directly input to the comparator. The comparator converts the analog signal into a digital signal by discriminating the non-inverting output of the differential amplifier 11 using the non-inverting output of the differential amplifier 14 as a threshold value.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
3 is a block diagram showing a configuration of an optical receiving circuit according to the embodiment of FIG. In FIG. 5, the optical receiving circuit of the present embodiment includes a photoelectric conversion element 51, a preamplifier 52, two maximum value holding circuits 55 and 56, and two differential amplifiers 54 and 5.
7, a comparator 59, and a reference voltage source 58.

The photoelectric conversion element 51 is composed of, for example, a photodiode, and converts the received optical signal into a current signal. When the photoelectric conversion element 51 is composed of a photodiode, its cathode is connected to the power supply line and its anode is connected to the input terminal of the preamplifier 52. The preamplifier 52 converts the current signal output from the photoelectric conversion element 51 into a voltage signal. This preamplifier 52
The amplification result of is extracted in the form of a differential output.

The maximum value holding circuit 55 detects and holds the maximum value of the non-inverted output of the preamplifier 52. The output of the maximum value holding circuit 55 is given as a signal input to a differential amplifier 57 described later. The maximum value holding circuit 56 has the same circuit configuration as the maximum value holding circuit 55, and detects and holds the maximum value of the inverted output of the preamplifier 52. Maximum value holding circuit 56
The output of is supplied as a reference input to a differential amplifier 57 described later. A reset signal is externally applied to maximum value holding circuits 55 and 56.

The differential amplifier 54 is supplied with the non-inverted output of the preamplifier 52 as a signal input and the output of the differential amplifier 57 as a reference input. Comparator 59
Discriminates the output signal of the differential amplifier 54 by using the reference voltage supplied from the reference voltage source 58 as a threshold value to shape the signal waveform into a digital waveform.

FIG. 6 is a circuit diagram showing an example of the configuration of preamplifier 52 in FIG. In FIG. 6, transistors 61 and 62 and current source 63 form a differential amplifier. The emitters of the transistors 61 and 62 are commonly connected and connected to a current source. The output of the photoelectric conversion element 51 is supplied to the base of the transistor 61. The resistor 611 is inserted between the collector of the transistor 61 and the power supply line, and the resistor 621 is inserted between the collector of the transistor 62 and the power supply line. Transistor 6
4 and the current source 66 form a first emitter follower circuit, and the transistor 65 and the current source 67 form a second emitter follower circuit. The inverted output of the differential amplifier obtained from the collector of the transistor 61 is supplied to the output terminal 69 via the first emitter follower circuit. The non-inverting output of the differential amplifier obtained from the collector of the transistor 62 is supplied to the output terminal 68 via the second emitter follower circuit. The output of the first emitter follower is the feedback resistor 5
It is fed back to the base of the transistor 61 via 3 and the output of the second emitter follower is fed back to the base of the transistor 62 via the feedback resistor 531.

FIG. 7 is a circuit diagram showing an example of the configuration of differential amplifier 57 in FIG. In FIG. 7, the output of the maximum value holding circuit 55 is supplied to the base of the transistor 71, and the output of the maximum value holding circuit 56 is supplied to the base of the transistor 72. Power line and transistor 71
A resistor 711 is inserted between the power supply line and the collector of the transistor 72. A resistor 712 is provided at the emitter of the transistor 71.
Of the resistor 722 is connected to the emitter of the transistor 72, and the other ends of the resistors 712 and 722 are connected to the current source 73. The collector of transistor 72 is also connected to the base of transistor 74. The emitter of this transistor 74 is
The transistor 74 and the current source 76 are connected to the current source 76 to form an emitter follower circuit. Further, an output terminal 77 is prepared so as to be connected to the emitter of the transistor 74.

In the configuration as described above, the preamplifier 5
The second current source 63 and the current source 73 of the differential amplifier 57 have the same configuration and are set so that the current values flowing through them are also the same. Resistors 611 and 621
And the resistors 711 and 721 have the same resistance value. The resistors 712 and 722 have the same resistance value as the resistors 711 and 721. Resistors 712, 72
2 has a local feedback effect, and when the transconductances of the transistors 71 and 72 are sufficiently large, the resistors 712 and 722 are set equal to the resistors 711 and 721, so that the amplification factor of the differential amplifier 57 is increased. It becomes 0.5.

FIG. 8 shows the maximum value holding circuit 55 shown in FIG.
It is a figure which shows the more detailed structure of. In FIG. 8, the maximum value holding circuit 55 includes an operational amplifier 81 and an operational amplifier 81.
, A capacitor 85 for accumulating electric charges for holding a peak value, a buffer circuit 83 configured by a source follower, and the like, a capacitor that is turned on in response to a reset signal, and is grounded. And a switch circuit 84 forming a discharge path 82.

FIG. 9 is a circuit diagram of the optical receiver circuit shown in FIG.
FIG. 6 is a waveform diagram showing signals of respective parts when an optical burst signal is input. In FIG. 9, a waveform 581 shows the waveform of the reset signal applied to the maximum value holding circuits 55 and 56. The waveform 681 shows the waveform of the signal at the output terminal 68 of the preamplifier 52, and the waveform 691 shows the signal waveform at the output terminal 69 of the preamplifier 52. A waveform 551 shows an output signal waveform of the maximum value holding circuit 55, and a waveform 561 shows an output signal waveform of the maximum value holding circuit 56. A waveform 771 shows an output signal waveform at the output terminal 77 of the differential amplifier 57. A waveform 541 shows an output signal waveform of the differential amplifier 54, and a waveform 591 shows a reference input level of the comparator 59. Also, the waveform 592 is the comparator 5
9 shows the output signal waveform of No. 9. The operation of the optical receiving circuit shown in FIGS. 5 to 8 will be described below with reference to FIG.

In the preamplifier 52, the collector current of the transistor 61 and the collector current of the transistor 62 are the same when there is no optical signal to be received. Two
The current will flow. The offset voltage, which is the output potential of the preamplifier 52 in the non-input state, is
And 69 have the same voltage, which is a value lowered from the power supply potential by the sum of the potential drop in the resistor 611 or 621 and the base-emitter potential difference in the transistor 64 or 65.

On the other hand, when no differential input is made in the differential amplifier 57, the collector currents of the transistors 71 and 72 are the same, and half the current of the current source 73 flows through the transistors 71 and 72. . The offset voltage of the differential amplifier 57 is a value lowered from the power supply potential by the sum of the potential drop in the resistor 721 and the base-emitter potential difference in the transistor 74.

When the current source 63 and the current source 73 have the same current value and the resistors 611 and 621 and the resistor 721 have the same resistance value, the output terminal 68 of the preamplifier 52 when the optical signal is not input. And the offset output level at the output terminal 77 of the differential amplifier 57 when the differential input is not input are the same.

When the optical burst signal is input, the non-inverted output signal at the output terminal 68 of the preamplifier 52 is output in the form of addition from the level when there is no input, as shown by the waveform 681, and at the output terminal 69. The inverted output signal is output in the form of being subtracted from the level when there is no input, as indicated by the waveform 691. At this time, the output of the maximum value holding circuit 55 follows the maximum value of the non-inverted output of the preamplifier 52, as shown by the waveform 551. On the other hand, the output of the maximum value holding circuit 56 holds the level when there is no input, as indicated by the waveform 561.

The differential amplifier 57 receives the waveform 5 as a signal input.
The potential shown at 51 is applied and the waveform 561 is used as a reference input.
When the potential shown in (1) is applied, the amplification factor is 0.5, and therefore the potential obtained by multiplying the difference by 0.5 is added to the output level at the time of no input and output. Therefore, the output of the differential amplifier 57 has a waveform 771. The output waveform 771 of the differential amplifier 57 is at an almost intermediate level of the output waveform 681 of the preamplifier 52, so that the output of the differential amplifier 54 is
The waveform 541 is obtained.

Here, in the actual circuit, noise components such as thermal noise and shot noise generated in the photoelectric conversion element and the electric circuit are superimposed on the output signal shown by the waveform 541. Therefore, the reference input level 591 of the comparator 59 is set to a value with an offset that exceeds the peak values of these noise components. As a result, the noise component is removed. That is, when the signal input is the waveform 541 and the reference input level is the waveform 591, the output of the comparator 59 is as shown by the waveform 592, and when there is no input, the digital output from the comparator 59 is always at the low level and the optical signal is received. The digital output can be set to the high level only when As a result, the burst signal can be reproduced.

Next, the operation when there is a temperature change or a power supply voltage change will be described. When the current source 63 and the current source 73 have the same configuration and the same current value, the preamplifier 52 and the differential amplifier 57 can have the same current variation with respect to the power source voltage variation and the temperature variation. The same applies when the current sources 66 and 67 and the current source 76 have the same configuration and the same current value.

The offset potential in the preamplifier 52 when there is no optical signal to be received is as described above. When an optical signal is input to the preamplifier 52,
The output looks like this: That is, the non-inverted output at the terminal 68 of the preamplifier 52 has a signal amplitude in which the potential difference according to the input optical power of the optical signal is added to the higher potential side with respect to the offset potential when there is no input. On the other hand, the inverted output at the terminal 69 of the preamplifier 52 has a signal amplitude in a form in which the potential difference according to the input optical power is subtracted from the offset potential when there is no input to the side where the potential is low.

The output variation of the preamplifier 52 when there is a temperature variation or a power source voltage variation is the sum of the variation as a DC component (variation in offset voltage) and the variation as an AC component (variation in signal amplitude). Become. The fluctuation of the offset voltage which is the fluctuation as the DC component is the sum of the fluctuation of the potential drop in the resistors 611 and 621 due to the fluctuation of the current source 63 and the fluctuation of the base-emitter potential of the transistors 64 and 65. The fluctuation of the signal amplitude, which is the fluctuation as the AC component, is caused by the fluctuation of the gain-frequency characteristic of the preamplifier 52 due to the fluctuation of the power supply voltage and the fluctuation of the temperature.

The output fluctuations of the maximum value holding circuits 55 and 56 due to temperature fluctuations or power supply voltage fluctuations are the same by making the respective configurations the same. The output fluctuation of the differential amplifier 57 in the presence of temperature fluctuations and power supply voltage fluctuations is the fluctuation of the offset voltage of the differential amplifier 57 plus the fluctuations of the output of the maximum value holding circuit 55 and the maximum value holding circuit 56. It was done. The variation of the offset voltage in the differential amplifier 57 is the sum of the potential drop in the resistor 721 due to the current variation of the current source 73 and the variation in the base-emitter potential difference in the transistor 74, and the current source 73 and the current source 63. When and have the same configuration and the same current value, and the resistors 611 and 621 and the resistor 721 have the same resistance value, the fluctuation is the same as the DC component in the preamplifier 52.

Maximum value holding circuits 55 and 56 follow the maximum value including the same fluctuation, respectively, and differential amplifier 57
Since the difference component between the output of the maximum value holding circuit 55 and the output of the maximum value holding circuit 56 is amplified, if the variation is the same,
The variation is canceled by the differential amplifier 57.

As a result, the output waveform 7 of the differential amplifier 57
71 always indicates the center value of the amplitude of the signal appearing at the non-inverting output of the preamplifier 52. As a result, even if there is a temperature fluctuation or a power supply voltage fluctuation, the reference input level that follows the level fluctuation of the signal input in the differential amplifier 54 is always obtained, and the comparator 59 can always output the burst signal accurately. Becomes

By the way, the maximum value holding circuits 55 and 56.
Is a charge corresponding to the input signal voltage, as shown in FIG.
By charging the capacitor 82, the maximum value of the input signal voltage is held. In the conventional maximum value holding circuit, after receiving and reproducing the burst signal,
The electric charge accumulated in the capacitor 82 is gradually discharged according to a certain time constant. Therefore, when the small-amplitude optical burst signal is received after the large-amplitude optical burst signal is received, the input signal voltage corresponding to the small-amplitude optical burst signal may be lower than the residual voltage of the capacitor 82. In such a case, the output voltage of the maximum value holding circuit becomes higher than the maximum value of the input signal voltage, and the maximum value cannot be detected.

Therefore, in the optical receiving circuit of the second embodiment, the reset signal 581 is given to the maximum value holding circuits 55 and 56 each time reception and reproduction of the burst signal are completed. This reset signal 5
In response to 81, the switch circuit 84 of FIG. 8 is turned on, and the electric charge accumulated in the capacitor 82 is forcibly discharged. As a result, the outputs 551 and 561 of the maximum value holding circuits 55 and 56 are forcibly reset to the offset voltage which is the output level when the optical signal to the preamplifier 52 is not input. As a result, the signal can be regenerated even if the small-amplitude optical burst signal is received after the large-amplitude optical burst signal is received.

When the light receiving level of the photoelectric conversion element 51 is sufficiently high, a signal of a sufficient level can be obtained from the preamplifier 52. Therefore, the preamplifier 52 does not perform signal amplification. 52 output and differential amplifier 57
You may make it input the output of the above into a comparator directly. In this case, the comparator discriminates the output of the preamplifier 52 by using the output of the differential amplifier 57 as a threshold value, thereby converting the analog signal into a digital signal.

(Third Embodiment) FIG. 10 is a block diagram showing the arrangement of an optical receiving circuit according to the third embodiment of the present invention. In FIG. 10, the optical receiving circuit of the present embodiment is
The photoelectric conversion element 51, the preamplifier 101, and the feedback resistor 1
02, the reference voltage generation unit 103, the main amplification unit 104,
And a comparator 105.

In the present embodiment, as the main amplification section 104,
A configuration is shown in which the first and second amplification units 104a and 104b having the same configuration are connected in cascade. First
Of the maximum value holding circuit 1042a.
And 1043a and two differential amplifiers 1041a and 1044a. Similarly, the second amplifier 104b
Are two maximum value holding circuits 1042b and 1043b.
And two differential amplifiers 1041b and 1044b.

The photoelectric conversion element 51 is composed of a photodiode, for example, and converts the received optical signal into a current signal. When the photoelectric conversion element 51 is composed of a photodiode, its cathode is connected to the power supply line and its anode is connected to the input terminal of the preamplifier 101. The preamplifier 101 converts the current signal output from the photoelectric conversion element 51 into a voltage signal.

The reference voltage generator 103 has a configuration described later to generate an output at a DC level which is approximately the center of the amplitude of the output signal of the preamplifier 101. This reference voltage generator 10
The output of 3 is the differential amplifier 10 in the first amplifier 104a.
41a is supplied as a reference input.

The output of the preamplifier 101 is the differential amplifier 1
041a is supplied as a signal input. Differential amplifier 1
The non-inverted output and inverted output of 041a are supplied to maximum value holding circuits 1042a and 1043a, respectively.

Maximum value holding circuits 1042a and 1043
The outputs of a are supplied to the differential amplifier 1044a as a signal input and a reference input, respectively. Maximum value holding circuits 1042a and 1043a have the same circuit configuration. Maximum value holding circuits 1042a and 1043a
A reset signal is externally applied to the. The non-inverted output of the differential amplifier 1041a is the second amplification unit 104 of the next stage.
It is supplied as a signal input to the differential amplifier 1041b in b. The non-inverting output of the differential amplifier 1044a is supplied to the differential amplifier 1041b as a reference input.

The non-inverted output and the inverted output of the differential amplifier 1041b are supplied to maximum value holding circuits 1042b and 1043b, respectively. Maximum value holding circuit 1042b
And the outputs of 1043b are respectively the differential amplifier 10
44b is provided as a signal input and a reference input.
Maximum value holding circuits 1042b and 1043b have the same circuit configuration. A reset signal is externally applied to maximum value holding circuits 1042b and 1043b.

The non-inverted output of the differential amplifier 1041b is supplied to the comparator 105 at the next stage as a signal input. The non-inverting output of the differential amplifier 1044b is supplied to the comparator 105 as a reference input. The comparator 105 shapes the optical reception signal waveform into a digital waveform by discriminating the signal input using the reference input as a threshold value.

FIG. 11 shows the differential amplifier 10 of FIG.
It is a circuit diagram which shows an example of a structure of 41a. It should be noted in advance that the differential amplifier 1041b also has the same circuit configuration as the differential amplifier 1041a. In FIG. 11, the collector of the transistor 111 is connected to the power supply line via the resistor 1131. In addition, the transistor 112
The collector of is connected to the power supply line through the resistor 1132. The emitter of the transistor 111 is connected to the current source 115 via the resistor 1141. The emitter of the transistor 112 is connected to the current source 11 via the resistor 1142.
5 is connected. The signal input from the preamplifier 101 is
It is supplied to the base of the transistor 111. The reference input from the reference voltage generator 103 is supplied to the base of the transistor 112.

The collector output of the transistor 111 is supplied to the base of the transistor 116. The collector output of the transistor 112 is supplied to the base of the transistor 117. Each collector of transistors 116 and 117 is connected to a power supply line. The emitter of the transistor 116 is connected to the current source 118. The emitter of the transistor 117 is connected to the current source 119. The transistor 116 and the current source 118 form a first emitter follower circuit, and the transistor 117 and the current source 119 form a second emitter follower circuit. The output of the first emitter follower circuit obtained from the emitter of the transistor 116 is the differential amplifier 1
The inverted output of 041a is given to the circuit in the subsequent stage. The output of the second emitter follower circuit obtained from the emitter of the transistor 117 is given to the subsequent circuit as the non-inverting output of the differential amplifier 1041a.

In the above structure, the resistor 1141
And the resistor 1142 have the same resistance value. Resistance 1
The local feedback action works by the 141 and the resistor 1142, and by appropriately selecting these resistance values,
The amplification factor of the differential amplifier 1041 can be set appropriately.

FIG. 12 shows the differential amplifier 10 of FIG.
It is a circuit diagram which shows an example of a structure of 44a. It should be noted in advance that the differential amplifier 1044b also has the same circuit configuration as the differential amplifier 1044a. In FIG. 12, the collector of the transistor 121 is connected to the power supply line via the resistor 1231. In addition, the transistor 122
The collector of is connected to the power supply line via the resistor 1232. The emitter of the transistor 121 is connected to the current source 125 via the resistor 1241. The emitter of the transistor 122 is connected to the current source 12 via the resistor 1242.
5 is connected. The output of the maximum value holding circuit 1042a is supplied to the base of the transistor 121 as a signal input. The output of the maximum value holding circuit 1043a is supplied to the base of the transistor 122 as a reference input.

The collector output of the transistor 122 is supplied to the base of the transistor 126. The collector of the transistor 126 is connected to the power supply line, and the emitter of the transistor 126 is connected to the current source 127. These transistors 126
The current follower 127 forms an emitter follower circuit. The output of the emitter follower circuit obtained from the emitter of the transistor 126 is the differential amplifier 104.
It is given to the subsequent circuit as a non-inverting output of 4a.

In the configuration as described above, the resistor 1241
And the resistor 1242 are connected to the resistors 1231 and 12 respectively.
It has the same resistance value as 32. Resistors 1241 and 12
A local feedback effect acts on 42, and when the transconductance of the transistors 121 and 122 is sufficiently large, the amplification factor of the differential amplifier 1044a becomes
0.5. This also applies to the differential amplifier 1044b.

Further, in the above-mentioned structure, the current source 115 of the differential amplifier 1041a and the differential amplifier 1041.
The current sources 125 of 4a have the same configuration as each other, and are designed so that the current values flowing through them are also the same. Also, the resistors 1131 and 1132 and the resistor 123.
1 and 1232 have the same resistance value. Further, the current sources 118 and 119 applied to the emitter follower of the differential amplifier 1041a, and the differential amplifier 1
Current source 127 applied to 044a emitter follower
Have the same configuration as each other and are designed so that the current values flowing through them are also the same. As a result, the differential amplifier 1041a and the differential amplifier 1044a have the same offset voltage which is the output level when there is no input, and further, even when there are power supply voltage fluctuations and temperature fluctuations, the fluctuations of the offset voltages are the same. It becomes possible to

FIG. 13 shows a more detailed structure of maximum value holding circuit 1042 (or 1043) in FIG. In FIG. 13, the maximum value holding circuit 1042
(Or 1043) is an operational amplifier 131, a diode 132 for receiving the output of the operational amplifier 131, a capacitor 133 for accumulating charges for holding a peak value, a buffer circuit 134 including a source follower and the like.
And a switch circuit 135 which is turned on in response to the reset signal and forms a discharge path of the capacitor 133 between the ground and the ground.

FIG. 14 is a diagram showing a more detailed structure of the reference voltage generator 103 in FIG. 14, the constant voltage output unit 141 has the same configuration as the preamplifier 101 and the feedback resistor 102 in FIG. 10, and outputs a constant voltage equal to the output of the preamplifier 101 when there is no input. When an optical signal is input, the preamplifier 10
The output of 1 changes from the output level at the time of no input to the lower side. The output of the constant voltage output unit 141 is the preamplifier 10
Since the output is equal to the output of 1 when there is no input, the constant voltage output unit 141
From, the maximum value of the output of the preamplifier 101 is output.

The minimum value holding circuit section 142 detects and holds the minimum value of the input signal. This minimum value holding circuit unit 142
An operational amplifier 1421, a diode 1422 having a cathode connected to the output of the operational amplifier, a capacitor 1423 for accumulating electric charges for holding a minimum value, a buffer circuit 1424 configured by a source follower, and the like, and turned on in response to a reset signal. , Capacitor 1423 between power line
And a switch circuit 1425 that forms a discharge path of.

The output of the constant voltage output section 141 is supplied to one end of the resistor 143, and the output of the minimum value holding circuit section 142 is supplied to one end of the resistor 144. Resistors 143 and 144
Have the same resistance value. Resistors 143 and 144
Are connected to each other, and the output of the reference voltage generation unit 103 is obtained from this connection unit. With this configuration, the preamplifier 102 can be connected to the reference voltage generator 103.
A constant voltage value having the level at the center of the output signal amplitude of is output.

FIG. 15 is a circuit diagram of the first amplifying section 1 shown in FIG.
It is the figure which overlapped and described the input-output characteristic of the input signal and output signal of the differential amplifier 1041a in 04a.
15, in the input / output characteristics, the horizontal axis represents the input voltage of the signal input with respect to the input voltage level of the reference input, and the vertical axis represents the values of the non-inverted output and the inverted output with respect to the input. The two input / output characteristics are characteristics 151 when the amplification factor of the differential amplifier 1041a is set to be relatively low.
And the characteristic 152 when the amplification factor is set high.

Further, FIG. 15 shows the input signal waveform with respect to the time axis. That is, the input waveform 15 when the reference input is accurately set at the center of the signal waveform
3 and the input waveform 154 when the signal waveform is applied after being shifted with respect to the reference input.

The inverted output waveform in the case of the input waveform 153 is
When the amplification factor is set low, it is indicated by a waveform 155, and when the amplification factor is set high, it is indicated by a waveform 156. Further, the inverted output waveform in the case of the input waveform 154 is shown as a waveform 157 when the amplification factor is set low, and is shown as a waveform 158 when the amplification factor is set high. As can be seen from this figure, when the amplification factor is high, there is a risk that an output signal cannot be obtained even if the signal input slightly deviates from the reference input. This also applies to the differential amplifier 1041b in the second amplification section 104b.

FIG. 16 shows the output signal waveform 162 of the preamplifier 101, the output 161 of the constant voltage output section 141, and the reference voltage generation section 103 when the background light of the DC level is present.
FIG. 6 is a diagram showing the output level 163 of FIG.

In FIG. 16, the difference 164 between the output level 161 of the constant voltage output section 141 and the base level of the output of the preamplifier 101 (the output level in the period when there is no optical signal) is:
This is due to the background light. In addition, reset signal 1
It is shown as 65.

The operation of the optical receiving circuit according to the third embodiment will be described below with reference to FIGS. As described above, in an optical communication system such as a passive double star configuration in which a plurality of terminals are connected to a switch via a star coupler, each terminal is temporally separated by the TDMA method to perform signal transmission. Even in such a case, the light emission levels at the time of extinction of the respective terminals at the timing of originally not transmitting may be added up to become a level that cannot be ignored with respect to the signal level. In addition, if a configuration is adopted in which different signals are exchanged at multiple wavelengths by using wavelength multiplexing technology, and if the wavelength-multiplexed light isolation is insufficient in the optical module, the optical signal of the unnecessary wavelength is It is conceivable that the light may go around the conversion element and adversely affect the background light.

The case where there is background light will be described below. The signal converted into a current by the photoelectric conversion element 51 is converted into a voltage signal by the preamplifier. In the signal waveform, as indicated by a waveform 162, a voltage difference 164 between the output level in the period when the optical signal is not received and the output level of the constant voltage output unit 141 is generated. The minimum value holding circuit 142 detects and holds the minimum value of the signal 162, and the resistors 143 and 144 set the reference voltage generation unit 103 to an intermediate value between the output of the minimum value holding circuit 142 and the output of the constant voltage output unit 141. Is generated as the output 163 of

The reset signal 165 is applied to the reference voltage generator 103 each time the burst signal ends. When the reset signal 165 is given, the minimum value holding circuit 14
The output of 2 converges on the output level 162 of the preamplifier 101. On the other hand, the output of the constant voltage output unit 141 is the waveform 16
Since the level is shown as 1, the reference voltage generation unit 10
The output of 3 is an intermediate level of the voltage difference 164.

When an optical signal is input, the output of the reference voltage generator 103 changes according to the input signal, but due to the influence of background light, it is not accurately set at the center of the signal waveform, and there is a shift. Will occur. In this case, particularly in the case of a small input signal, the reference input level relatively deviates from the signal level.

However, the differential amplifier 1041a of the first amplifying section 104a is set to have a low amplification factor, and its linear amplification region is set sufficiently wide. Therefore, for example, like the signal waveform 154, Even if the signal level is slightly deviated from the reference input level, the differential amplifier 1041
It is possible to extract the signal as the output of a. In this case, the operating characteristic of the differential amplifier 1041a is the waveform 151
It is assumed that the characteristics are shown as.

If the output can be taken out as the differential amplifier 1041a, the signal level and the reference level can be appropriately generated in the first amplifying section 104a by the same operation as described in the first embodiment. Is possible. As a result, the amplification factor can be set to be relatively high in the second amplification unit 104b, the signal is accurately amplified in the subsequent stages, and the pulse signal can be reproduced.

In the system of the third embodiment, the response of the minimum value holding circuit 142 is maintained even when the background light level in each burst period is different due to the different extinction ratios in the light emission levels of the respective terminals. If the speed is sufficiently high, the reference level corresponding to the signal level can be generated at high speed, so that the signal can be reproduced from the beginning of the burst signal even if the background light level fluctuates.

When there is a temperature fluctuation or a power supply voltage fluctuation, the constant voltage output section 141 has the same configuration as the preamplifier 101, so the fluctuation in the output from the constant voltage output section 141 is the same as that of the preamplifier 101. Although having the same tendency, it is generally difficult to make the variation characteristic of the minimum value holding circuit 142 equal to the variation characteristic of the preamplifier 101. for that reason,
The output of the reference voltage generation unit 103 changes with respect to the output signal level of the preamplifier 101.

However, even if the signal input level at the input of the first amplifying section 104a is slightly deviated from the reference input level, the linear amplification region of the differential amplifier 1041a is set to be sufficiently wide with respect to the deviation. As long as this is done, the differential amplifier 1041a can output a signal. Inside the first amplifier 104a, the first amplifier
With the same operation as that described in the above embodiment, the differential amplifier 1041a can be stably operated even when the temperature changes or the power supply voltage changes.
The output of the differential amplifier 1044a is set at the center of the non-inverted output signal of.

As described above, the first amplifying section 104a can accurately transmit the signal to the subsequent stage, and the comparator 105 can sufficiently amplify the signal transmitted by the second amplifying section 104b at the subsequent stage. It becomes possible to reproduce digital data.

Here, inside the comparator 105, the reference input is set to be offset by an offset voltage exceeding the noise component superimposed on the signal. By doing so, it is possible to reproduce the pulse signal only when the burst signal is input without amplifying noise by the comparator 105 even when there is no input.

First and second amplification sections 104a and 104a
With the configuration shown in FIG. 04b, as described in the first embodiment, the variation can be canceled with respect to the temperature variation and the power supply voltage variation. Therefore, it can be seen that the optical receiving circuit shown in the drawing can accurately reproduce the signal even in the presence of background light, temperature fluctuations, and power supply voltage fluctuations.

In the first to third embodiments described above,
Although two maximum value holding circuits are used as the peak value holding circuits, it is also possible to configure the amplifier or the optical receiving circuit of the present invention by using two minimum value holding circuits instead of this.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an amplifier according to a first embodiment of the present invention.

2 is a circuit diagram showing an example of a configuration of a differential amplifier 11 used in the amplifier of FIG.

3 is a circuit diagram showing an example of a configuration of a differential amplifier 14 used in the amplifier of FIG.

FIG. 4 is a waveform diagram showing signals of various parts in the amplifier of FIG.

FIG. 5 is a block diagram showing a configuration of an optical receiving circuit according to a second embodiment of the present invention.

6 is a preamplifier 52 used in the optical receiving circuit of FIG.
FIG. 3 is a circuit diagram showing an example of the configuration of FIG.

7 is a differential amplifier 57 used in the optical receiving circuit of FIG.
FIG. 3 is a circuit diagram showing an example of the configuration of FIG.

8 is a circuit diagram showing an example of a configuration of a maximum value holding circuit 55 (or 56) used in the optical receiving circuit of FIG.

FIG. 9 is a waveform chart showing signals of respective parts in the optical receiving circuit of FIG.

FIG. 10 is a block diagram showing a configuration of an optical receiving circuit according to a third embodiment of the present invention.

11 is a circuit diagram showing an example of a configuration of a differential amplifier 1041 used in the optical receiving circuit of FIG.

12 is a circuit diagram showing an example of a configuration of a differential amplifier 1044 used in the optical receiving circuit of FIG.

13 is a maximum value holding circuit 1042a (or 1042b, 1043a, 10) used in the optical receiving circuit of FIG.
It is a circuit diagram which shows an example of a structure of 43b).

14 is a circuit diagram showing an example of a configuration of a reference voltage generation unit 103 used in the optical receiving circuit of FIG.

15 is a diagram showing the relationship between the input and output of the differential amplifier 1041 used in the optical receiving circuit of FIG.

16 is a diagram showing an example of operation waveforms of the optical receiving circuit of FIG.

[Explanation of symbols]

 11, 14, 15, 54 and 57 ... Differential amplifiers 12 and 13 ... Maximum value holding circuit 51 ... Photoelectric conversion element 52 ... Preamplifier 55 and 56 ... Maximum value holding circuit 58 ... Reference voltage source 59 ... Comparator 101 ... Previous On-amplifier 102 ... Feedback resistor 103 ... Reference voltage generation unit 104 ... Main amplification unit 104a and 104b ... First and second amplification unit 105 ... Comparator

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number for FI Technical indication H01L 31/10 H03F 3/45 H04B 1/18 (72) Inventor Katsuyuki Fujito Kadoma, Osaka Prefecture 1006 Matsushita Electric Industrial Co., Ltd.

Claims (32)

[Claims] 1. An amplifier for amplifying an input burst signal, wherein the burst signal is amplified, and the amplification result is vertically symmetrical about an offset voltage which is an output voltage when there is no input. A first amplifier circuit that outputs a differential output including first and second outputs; and a first peak value holding unit that detects and holds a peak value of the first output of the first amplifier circuit. And a peak value of the second output of the first amplifier circuit (however,
A second peak value holding circuit for detecting and holding a peak value in the same direction as the peak value detected by the first peak value holding circuit; and a differential output between the first and second peak value holding circuits. A second amplifier circuit that generates a reference voltage that follows the DC level of the first output of the first amplifier circuit by amplifying. 2. The amplification factor of the second amplifier circuit is 0.5.
The offset voltage, which is set in the vicinity, is an output voltage when the differential input of the second amplifier circuit is not input, and is set to be substantially equal to the offset voltage of the first amplifier circuit. The amplifier according to claim 1. 3. The first and second amplifier circuits have their respective circuit configurations and circuit constants determined in association with each other so that the fluctuations in the output caused by the respective internal circuits become equal to each other. The amplifier according to claim 2, wherein: 4. The amplifier according to claim 3, wherein the first and second peak value holding circuits have the same circuit configuration as each other. 5. The first and second peak value holding circuits detect first and second maximum values of the first and second outputs of the first amplifier circuit, respectively, and hold the first and second maximum values, respectively. The amplifier of claim 4, including a value holding circuit. 6. The first amplifier circuit includes a first and a second transistor whose emitters are commonly connected to each other, and a first transistor which is connected to a common emitter of the first and second transistors. No. 1 current source, a first resistor interposed between the collector of the first transistor and a power supply line, and a second resistor interposed between the collector of the second transistor and a power supply line. The second amplification circuit includes at least third and fourth transistors, a third resistor having one end connected to the emitter of the third transistor, and a collector of the third transistor. A fourth resistor which is interposed between the power source line and has a resistance value equivalent to that of the first resistor and one end of which is connected to the emitter of the fourth transistor and which is equivalent to the third resistor. resistance A fifth resistor having a resistance, a sixth resistance interposed between the collector of the fourth transistor and a power supply line, and having a resistance value equivalent to that of the second resistance, and the third and fifth resistances. Connected to each of the other ends of the resistors, has the same configuration as the first current source, and the value of the current flowing therethrough is also the same as the value of the current flowing through the first current source. An amplifier according to claim 3 including a current source. 7. The first amplifier circuit receives the burst signal as a signal input, receives a fixed voltage provisionally set for the DC level of the burst signal as a reference input, and based on the fixed voltage, receives the fixed voltage. The amplifier of claim 1, including a differential amplifier that differentially amplifies the burst signal. 8. The first output of the first amplifier circuit is received as a signal input, the reference voltage output from the second amplifier circuit is received as a reference input, and the first output is received based on the reference voltage. The amplifier according to claim 1, further comprising a third amplifier circuit that differentially amplifies the output. 9. The first output of the first amplifier circuit is received as a signal input, the reference voltage output from the second amplifier circuit is received as a reference input, and the reference voltage is used as a threshold value. By distinguishing the output of the first
The amplifier according to claim 1, further comprising a comparator that shapes the output of the amplifier circuit of 1. into a digital waveform. 10. An optical receiver circuit for receiving and amplifying an optical burst signal, the photoelectric conversion element converting the received optical burst signal into a current signal, and the current signal from the photoelectric conversion element is a voltage signal. The first output that outputs the amplification result in the form of a differential output including first and second outputs that appear vertically symmetrical with respect to the offset voltage that is the output voltage when there is no input An amplifier circuit, a first peak value holding circuit that detects and holds a peak value of a first output of the first amplifier circuit, and a peak value of a second output of the first amplifier circuit (however,
A second peak value holding circuit for detecting and holding a peak value in the same direction as the peak value detected by the first peak value holding circuit; and a differential output between the first and second peak value holding circuits. And a second amplifier circuit that generates a reference voltage that follows the DC level of the first output of the first amplifier circuit by amplifying. 11. The amplification factor of the second amplifier circuit is 0.
The offset voltage, which is an output voltage when the differential input of the second amplifier circuit is not input, is set to be substantially equal to the offset voltage of the first amplifier circuit. The optical receiving circuit according to claim 10. 12. The circuit configurations and circuit constants of the first and second amplifier circuits are determined in association with each other so that variations in output due to the respective internal circuits become equal to each other. The optical receiver circuit according to claim 11, wherein: 13. The first and second peak value holding circuits have the same circuit configuration as each other.
The optical receiving circuit according to. 14. The first and second peak value holding circuits respectively include first and second peak value holding circuits of the first amplifier circuit.
14. The optical receiving circuit according to claim 13, further comprising first and second maximum value holding circuits that detect and hold the maximum value of the output of the. 15. The first amplifier circuit includes at least:
The first differential amplifier is composed of a first and a second emitter follower, and a first and a second feedback resistor, and the first differential amplifier has its emitters commonly connected. A first and a second transistor; a first current source connected to the commonly connected emitters of the first and second transistors; and a collector interposed between the first transistor and a power supply line. And a second resistor interposed between a collector of the second transistor and a power supply line, and the current signal output from the photoelectric conversion element is the first resistor.
An inverted output of the first differential amplifier provided to the base of the transistor of the first transistor and obtained from the collector of the first transistor is output via the first emitter follower, and from the collector of the second transistor. The obtained non-inverting output of the first differential amplifier is output via the second emitter follower, and the output of the first emitter follower is output via the first feedback resistor to the first feedback resistor. Is fed back to the base of a transistor, the output of the second emitter follower is fed back to the base of the second transistor via the second feedback resistor, and the second amplifier circuit has the base with the first A third transistor receiving the output of the first peak value holding circuit, and a fourth transistor receiving the output of the second peak value holding circuit at its base. A transistor, a third resistor interposed between the collector of the third transistor and the power supply line, having a resistance value equivalent to that of the first resistor, and a collector of the fourth transistor and the power supply line. A fourth resistor having a resistance value equivalent to that of the second resistor, a fifth resistor whose one end is connected to the emitter of the third transistor, and one end of which is the first resistor. A sixth resistor connected to the emitter of the fourth transistor; and a current which is connected to the other ends of the fifth and sixth resistors and has the same configuration as the first current source and which flows therethrough. Has a configuration equivalent to that of the second current source whose value is also equal to the value of the current flowing through the first current source, and the first and second emitter followers, and from the collector of the fourth transistor. Third emitter for receiving output signal And a Orowa, optical receiving circuit according to claim 12. 16. A reset signal is provided to the first and second maximum value holding circuits each time reception of an optical burst signal for each time ends, and the first and second maximum value holding circuits include: 11. The optical receiving circuit according to claim 10, wherein each output voltage is set to be substantially equal to an offset voltage of the first amplifier circuit in response to the reset signal. 17. The first output of the first amplifier circuit is received as a signal input, the reference voltage output from the second amplifier circuit is received as a reference input, and the first output is received based on the reference voltage. The optical receiver circuit according to claim 10, further comprising a third amplifier circuit that differentially amplifies an output. 18. The reference input level is used as a threshold value,
A comparator for shaping the output of the third amplifier circuit into a digital waveform by discriminating the output of the third amplifier circuit is further provided, and the level of the reference input of the comparator is when the optical burst signal is not input. 18. The optical receiving circuit according to claim 17, wherein the output level of the third amplifier circuit is set to a level obtained by adding an offset of noise amplitude. 19. The first output of the first amplifier circuit is received as a signal input, the reference voltage output from the second amplifier circuit is received as a reference input, and the reference voltage is used as a threshold value. The optical receiving circuit according to claim 10, further comprising a comparator that shapes the output of the first amplifier circuit into a digital waveform by discriminating the output of No. 1. 20. An optical receiving circuit for receiving and amplifying an optical burst signal, the photoelectric conversion element converting the received optical burst signal into a current signal, and the current signal from the photoelectric conversion element is a voltage signal. A preamplifier circuit for converting and amplifying the preamplifier, a reference voltage generating circuit for generating a reference voltage, and a main amplifier circuit for amplifying the output of the preamplifier circuit, wherein the main amplifier circuit is the preamplifier. The output of the circuit is received as a signal input, the output of the reference voltage generation circuit is received as a reference input, the signal input is differentially amplified based on the reference input, and the amplification result is the output voltage when there is no input. A first amplifier circuit that outputs in the form of a differential output that includes first and second outputs that appear vertically symmetrical with respect to an offset voltage, and a peak value of the first output of the first amplifier circuit is detected. And hold 1 of the peak value holding circuit, a second peak value of the output of said first amplifier circuit (however,
A second peak value holding circuit for detecting and holding a peak value in the same direction as the peak value detected by the first peak value holding circuit; and a differential output between the first and second peak value holding circuits. And a second amplifier circuit that generates a reference voltage that follows the DC level of the first output of the first amplifier circuit by amplifying. 21. The amplification factor of the second amplifier circuit is 0.
The offset voltage, which is an output voltage when the differential input of the second amplifier circuit is not input, is set to be substantially equal to the offset voltage of the first amplifier circuit. 21. The optical receiver circuit according to claim 20, wherein: 22. The circuit configurations and circuit constants of the first and second amplifier circuits are determined in association with each other so that the fluctuations in the outputs due to the respective internal circuits become equal to each other. 22. The optical receiving circuit according to claim 21, wherein 23. The first and second peak value holding circuits have the same circuit configuration as each other.
The optical receiving circuit according to. 24. The first and second peak value holding circuits are respectively the first and second peak value holding circuits of the first amplifier circuit.
24. The optical receiving circuit according to claim 23, further comprising first and second maximum value holding circuits that detect and hold the maximum value of the output of. 25. The optical receiving circuit according to claim 24, wherein the reference voltage generating circuit is composed of a fixed voltage source. 26. The reference voltage generation circuit according to claim 24, wherein the reference voltage generation circuit detects a maximum value and a minimum value of the output signal from the preamplifier circuit, and outputs an intermediate value. Optical receiver circuit. 27. The first amplifying circuit has a base which receives the output of the preamplifying circuit, and a base which receives the output of the reference voltage generating circuit.
And a first resistor interposed between the collector of the first transistor and the power supply line, and a second resistor interposed between the collector of the second transistor and the power supply line, A first current source, a third resistor interposed between the emitter of the first transistor and the first current source, an emitter of the second transistor and the first current source, A fourth resistor having a resistance value equivalent to that of the third resistor, and the second amplifier circuit receives at its base the output of the first peak value holding circuit. A third transistor, a fourth transistor whose base receives the output of the second peak value holding circuit, a third transistor which is interposed between a collector of the third transistor and a power supply line, and A fifth resistor having an equivalent resistance value A sixth resistor which is interposed between the collector of the fourth transistor and a power supply line and has a resistance value equivalent to that of the second resistor; and a configuration equivalent to that of the first current source, The value of the current flowing therethrough is also equal to the value of the current flowing through the first current source, and is interposed between the second current source and the emitter of the third transistor and the second current source. And a seventh resistor having a resistance value equivalent to that of the fifth resistor, and an emitter interposed between the emitter of the fourth transistor and the second current source, and equivalent to the sixth resistor. The optical receiving circuit according to claim 22, further comprising an eighth resistor having a resistance value. 28. A reset signal is applied to the first and second maximum value holding circuits each time reception of an optical burst signal is completed each time, and the first and second maximum value holding circuits include: 21. The optical receiving circuit according to claim 20, wherein each output voltage is set to be substantially equal to an offset voltage of the first amplifier circuit in response to the reset signal. 29. The main amplification circuit has a multi-stage configuration in which a plurality of sets of amplification units each including the first and second amplification circuits and the first and second peak value holding circuits as one set are cascade-connected. The first amplifying circuit in the second and subsequent amplifying units receives the first output of the first amplifying circuit in the preceding amplifying unit as a signal input, and the first amplifying circuit in the preceding amplifying unit receives the first output. 21. The optical receiver circuit according to claim 20, which receives the output of the second amplifier circuit as a reference input. 30. The optical amplifier according to claim 29, wherein the amplification rate of the first-stage amplification section in the main amplification circuit is set lower than the amplification rate of the second-stage and subsequent amplification sections. Receiver circuit. 31. The first output of the first amplification circuit in the final stage amplification section of the main amplification circuit is received as a signal input, and the reference voltage output from the second amplification circuit is received as a reference input. 31. The optical receiver circuit according to claim 30, further comprising a comparator that shapes the output of the first amplifier circuit into a digital waveform by discriminating the first output with the reference voltage as a threshold value. 32. The reference input level of the comparator is obtained by adding a noise amplitude offset to the output level of the second amplification circuit in the final stage amplification section when no optical burst signal is input. The optical receiving circuit according to claim 31, wherein the optical receiving circuit is set to a level.