JP5780281B2 - Limiter amplifier circuit - Google Patents

Description

  The present invention relates to a limiter amplifier circuit having excellent reception sensitivity and response characteristics for high-speed burst signals.

  As an optical transmission system that enables high-speed data transmission, an optical transmission system that time-multiplexes a plurality of data signal packets is known. In this system, an optical receiving circuit is used to receive a burst signal.

  FIG. 1 is a diagram showing a conventional optical receiving circuit. The photodiode 100 converts a minute optical signal into a current signal. A transimpedance amplifier (TIA: Trans Impedance Amplifier) 101 converts this current signal into a voltage signal and amplifies it. The limiter amplifier circuit 102 amplifies the output signal of the transimpedance amplifier 101 to a constant amplitude.

  In the optical receiver circuit having such a configuration, a DC offset is generated between the positive phase side IP and the negative phase side IN of the differential output of the transimpedance amplifier 101. The DC offset of the input signal is amplified by the gain of the transimpedance amplifier 101. Although the magnitude of the DC offset varies depending on the individual difference of the transimpedance amplifier 101, when the DC offset is large, there is a problem that the burst response of the limiter amplifier circuit is deteriorated and good response characteristics cannot be obtained.

  FIG. 2 is a diagram showing a conventional optical receiver circuit having an AC coupling configuration. Coupling capacitors C 1 and C 2 are provided between the transimpedance amplifier 101 and the limiter amplifier circuit 102. Thereby, the influence of the DC offset of the optical receiver circuit of FIG. 1 can be eliminated. FIG. 3 is a diagram showing the input of the limiter amplifier circuit of FIG. As shown in FIGS. 3A and 3B, there is a problem that the DC level changes depending on the time constant determined by the coupling capacitors C1 and C2 and the input impedance of the limiter amplifier circuit 102, and it takes time to stabilize. Here, FIGS. 3C and 3D show time response waveforms of the limiter amplifier inputs IP and IN in which the time width near 500 ns in FIGS. 3A and 3B is expanded. In a conventional limiter amplifier circuit that does not have an offset adjustment circuit, the DC output level of the positive-phase output signal and the negative-phase output signal are equal when no differential input signal is input, and noise is output when there is no signal. There is a problem that the characteristics of the receiving apparatus are affected.

  A limiter amplifier circuit for improving these problems has been proposed (see, for example, Patent Document 1). FIG. 4 is a diagram showing an improved conventional limiter amplifier circuit. The differential amplifier circuit 11 amplifies a differential input signal composed of a normal phase input signal IP and a negative phase input signal IN. The differential amplifier circuits 12 and 13 amplify the differential output signal of the differential amplifier circuit 11.

  The offset adjustment circuit 14 includes peak detection circuits 15 and 16 and a differential amplifier circuit 17. The peak detection circuit 15 detects and holds the DC component of the positive phase input signal IP. The peak detection circuit 16 detects and holds the direct current component of the negative phase input signal IN. The differential amplifier circuit 17 negatively feeds back the voltage difference between the DC component of the positive phase input signal IP detected by the peak detection circuits 15 and 16 and the DC component of the negative phase input signal IN to the differential amplifier circuit 11, and this potential difference. Accordingly, the DC offset voltage of the differential output signal of the differential amplifier circuit 11 is adjusted.

  The offset adjustment circuit 18 includes a peak detection circuit 19 and a differential amplifier circuit 20. The peak detection circuit 19 detects and holds the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated. The differential amplifier circuit 20 positively feeds back the voltage difference between the DC component of one of the differential output signals of the differential amplifier circuit 12 detected by the peak detection circuit 19 and the reference voltage REF to the differential amplifier circuit 12, The DC offset voltage of the differential output signal of the differential amplifier circuit 12 is adjusted according to this potential difference.

  The reference voltage REF is adjusted to a predetermined value. When a differential signal is input to the input of the limiter amplifier circuit, the offset adjustment circuit 18 does not add a DC offset to the DC offset voltage of the differential output signal of the differential amplifier circuit 13, and does not add to the input of the limiter amplifier circuit. When no dynamic signal is input, a DC offset is added to the DC offset voltage of the differential output signal of the differential amplifier circuit 13. For this reason, when a differential signal is not input to the input of the limiter amplifier circuit, it is possible to prevent the DC output levels of the positive phase output signal and the negative phase output signal from being equal, and to obtain good response characteristics. it can.

  FIG. 5 is a diagram showing a simulation result of input signal response characteristics of the limiter amplifier circuit of FIG. FIG. 5A shows an input signal of the limiter amplifier circuit. The input signal is a 10 (1 zero) alternating signal of 10 Gbps. As an input signal, 300 mVpp (one side) is input after 5 ns from the no-input state, and 20 mVpp (one side) is input after 70 ns (packet interval 25 ns) after the non-input state after 45 ns. FIG. 5B shows the output of the limiter amplifier at that time, but there is a problem that the packet signal after 70 ns is lost and is not output. FIGS. 5C and 5D show the input and output waveforms of the limiter amplifier whose time width near 20 ns is expanded, and FIG. 5E shows the input waveforms of the limiter amplifier whose time width near 70 ns is expanded.

  The cause and operation of this problem will be described below. FIG. 6 is a diagram illustrating an example of an optical packet signal. A difference in optical intensity occurs between the optical packet signals 1 and 2 depending on a transmission distance from the transmission side to the reception side. For this reason, the hold capacity of the peak detection circuits 15 and 16 maintains the signal level of the optical packet signal 1 as the non-input time becomes shorter. For this reason, the configuration of FIG. 4 has a problem that the preamble bits are lost as in the simulation result shown in FIG. 5, the responsiveness deteriorates, and the reception sensitivity also decreases. This operation will be described below.

  FIG. 7 is a diagram illustrating an example of a peak detection circuit. The diode 21 rectifies the signal input from the input terminal INPK and charges the hold capacitor 22 with electric charge. The hold capacitor 22 holds a voltage corresponding to the charged charge, and this voltage is output from the output terminal OUTPK. Here, in the initial state (when a packet signal is input from the time of no signal), the hold voltage in the hold capacitor 22 at the time of no signal is lower than the voltage corresponding to the packet signal. Is applied to charge the hold capacitor 22 by rectification. For the response time required for charging, the circuit constants of the diode 21 and the hold capacitor 22 are appropriately designed so that the packet signal can be normally received.

  On the other hand, as shown in FIG. 6, when the difference in light intensity transitions from large to small when transitioning from one packet signal to the next packet signal, the voltage on the cathode side of the diode 21 of the peak detection circuit in FIG. Since the voltage corresponding to the packet signal before the transition held by the capacitor 22 is obtained and the voltage on the anode side of the diode 21 is equivalent to the packet signal after the transition, a reverse voltage is applied to the diode 21. Applied. Accordingly, the voltage of the hold capacitor 22 is discharged to a voltage corresponding to the packet signal after the transition. The discharge response time is determined by the capacitance value, the input resistance of the differential amplifier circuit 17, and the reverse equivalent resistance of the diode 21, and is longer than the case of charging. For this reason, the packet signal is input before an appropriate offset voltage is applied to the limiter amplifier circuit, and the preamble bits are lost as described above, so that the responsiveness is deteriorated and the reception sensitivity is also lowered.

JP 2009-38556 A

  In the limiter amplifier circuit of FIG. 4, when a difference in optical intensity occurs between optical packet signals, the next optical packet signal is input before an appropriate offset voltage is applied after the first optical packet signal is input. End up. For this reason, there is a problem that the preamble bits are lost, the responsiveness deteriorates, and the reception sensitivity also decreases.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a limiter amplifier circuit having excellent reception sensitivity and response characteristics with respect to a high-speed burst signal.

  A limiter amplifier circuit according to the present invention includes a first differential amplifier circuit that amplifies a differential input signal composed of a positive phase input signal and a negative phase input signal, and a differential output signal of the first differential amplifier circuit. A differential output signal of the first differential amplifier circuit according to a voltage difference between a DC component of the positive phase input signal and a DC component of the negative phase input signal. A difference between the first offset adjustment circuit for adjusting the DC offset voltage and the second differential amplifier circuit according to the DC component of one of the differential output signals of the second differential amplifier circuit and the reference voltage. A second offset adjustment circuit that adjusts a DC offset voltage of the dynamic output signal; a reset pulse generation circuit that generates a reset pulse according to one of the differential output signals of the second differential amplifier circuit; 1 and a second initial value setting circuit, When the reference voltage is adjusted to a predetermined value and the differential input signal is input, the second offset adjustment circuit applies a DC offset to the DC offset voltage of the differential output signal of the second differential amplifier circuit. When the differential input signal is not input, a DC offset is added to the DC offset voltage of the differential output signal of the second differential amplifier circuit, and the first offset adjustment circuit is A first peak detection circuit for detecting a DC component of the positive phase input signal; a second peak detection circuit for detecting a DC component of the negative phase input signal; an output of the first peak detection circuit; And a third differential amplifier circuit for amplifying a voltage difference from the output of the second peak detection circuit, and when the reset pulse is generated, the first initial value setting circuit has a first initialization voltage. In the first peak detection The peak detected voltage of the road-initialized, the second initial value setting circuit initializes peak detection voltage of the second peak detection circuit in the second initialization voltage.

  According to the present invention, it is possible to obtain a limiter amplifier circuit having excellent reception sensitivity and response characteristics for high-speed burst signals.

It is a figure which shows the conventional optical receiver circuit. It is a figure which shows the conventional optical receiver circuit of AC coupling structure. It is a figure which shows the input of the limiter amplifier circuit of FIG. It is a figure which shows the conventional limiter amplifier circuit improved. FIG. 5 is a diagram showing a simulation result of input signal response characteristics of the limiter amplifier circuit of FIG. 4. It is a figure which shows the example of an optical packet signal. It is a figure which shows the example of a peak detection circuit. It is a figure which shows the limiter amplifier circuit which concerns on embodiment of this invention. It is a figure for demonstrating operation | movement of a reset pulse generation circuit and an initial value setting circuit. It is a figure which shows the simulation result of the input signal response characteristic of the limiter amplifier circuit which made the circuit of FIG. 8 a basic composition. FIG. 9 is an enlarged view around 70 ns in FIG. 8.

  FIG. 8 is a diagram showing a limiter amplifier circuit according to the embodiment of the present invention. The photodiode 100 converts an optical signal into an electrical signal. The electrical signal is amplified by the transimpedance amplifier 101. The limiter amplifier circuit 102 amplifies the differential output signal of the transimpedance amplifier 101.

  In the limiter amplifier circuit 102, the differential amplifier circuit 11 amplifies the differential input signal composed of the positive phase input signal IP and the negative phase input signal IN. The differential amplifier circuits 12 and 13 amplify the differential output signal of the differential amplifier circuit 11. The differential output signal of the differential amplifier circuit 13 becomes the positive phase output signal OP and the negative phase output signal ON of the limiter amplifier circuit 102.

  The offset adjustment circuit 14 adjusts the DC offset voltage of the differential output signal of the differential amplifier circuit 11 according to the voltage difference between the direct current component of the positive phase input signal IP and the direct current component of the negative phase input signal IN. Specifically, the offset adjustment circuit 14 includes a peak detection circuit 15 that detects and holds the DC component of the positive phase input signal IP, and a peak detection circuit 16 that detects and holds the DC component of the negative phase input signal IN. And a differential amplifier circuit 17 for amplifying a voltage difference between the output of the peak detection circuit 15 and the output of the peak detection circuit 16.

As shown in FIG. 7, the peak detection circuits 15 and 16 include a diode 21 and a capacitor 22 connected between the cathode of the diode 21 and the ground. The differential amplifier circuit 17 amplifies the voltage difference between the DC component of the positive phase input signal IP and the DC component of the negative phase input signal IN detected by the peak detection circuits 15 and 16 and feeds it to the differential amplifier circuit 11. A forward system is configured, and the DC offset voltage of the differential output signal of the differential amplifier circuit 11 is adjusted according to this voltage difference.

  The offset adjustment circuit 18 includes a peak detection circuit 19 and a differential amplifier circuit 20. The peak detection circuit 19 detects and holds the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated. The differential amplifier circuit 20 amplifies the voltage difference between the output of the peak detection circuit 19 and the reference voltage REF. The offset adjustment circuit 18 adjusts the DC offset voltage of the differential output signal of the differential amplifier circuit 12 according to the DC component of one of the differential output signals of the differential amplifier circuit 13 that is saturated and the reference voltage REF. adjust. The reference voltage REF is adjusted to a predetermined value. The offset adjustment circuit 18 constitutes a positive feedback loop and automatically adjusts the DC offset voltage of the differential amplifier circuit 12. Specifically, when a differential input signal is input to the limiter amplifier circuit 102, the offset adjustment circuit 18 does not add a DC offset to the DC offset voltage of the differential output signal of the differential amplifier circuit 12, and differential When no input signal is input, a DC offset is added to the DC offset voltage of the differential output signal of the differential amplifier circuit 12.

  The reset pulse generation circuit 103 includes a low-pass filter 23 that receives a positive-phase output signal OP of the differential output signal of the differential amplifier circuit 13, a differential comparator 24 that receives an output signal of the low-pass filter 23, and a differential comparator 24. A low-pass filter 25 for inputting the first output signal, and an AND circuit 26 for inputting the output signal of the low-pass filter 25 and the second output signal of the differential comparator 24. The reset pulse generation circuit 103 generates a reset pulse according to the positive phase output signal OP of the differential output signal of the differential amplifier circuit 13. When the reset generation pulse is generated using the reverse phase output signal ON of the differential output signal of the differential amplifier circuit 13, the first output signal of the differential comparator 24 is sent to the AND circuit 26, and the first output signal of the differential comparator 24 is turned on. Similarly, the reset pulse can be generated by inputting the output signal 2 to the low-pass filter 25.

  The initial value setting circuit 104a includes resistors Ra1 and Ra2 and a switch SWa. The resistors Ra1 and Ra2 are connected in series between the constant voltages VEE and GND. The initial value setting circuit 104b includes resistors Rb1 and Rb2 and a switch SWb. The resistors Rb1 and Rb2 are connected in series between the constant voltages VEE and GND. The switches SWa and SWb are SPST (Single pole Single Throw).

  The resistors Ra1 and Ra2 are first initial voltage value generating units that generate the initialization voltage VA1, and the resistors Rb1 and Rb2 are second initial voltage value generating units that generate the initialization voltage VA2. The initialization voltage VA1 is given by VA1 = Ra1 · VEE / (Ra1 + Ra2), and the initialization voltage VA2 is given by VA2 = Rb1 · VEE / (Rb1 + Rb2).

  When the reset pulse is generated by the reset pulse generation circuit 103, the switches SWa and SWb are turned on, the switch SWa selects and outputs the initialization voltage VA1, and the switch SWb selects and outputs the initialization voltage VA2. On the other hand, when the reset pulse is not generated, the switch SWa does not select the initialization voltage VA1 and opens the output, and the switch SWb does not select the initialization voltage VA2 and opens the output. Accordingly, the output voltages (voltages applied to PKp and PKn) of the initial value setting circuits 104a and 104b are VA1 and VA2 only when a reset pulse is generated, and the others are open.

  Thus, when the reset pulse is generated, the initial value setting circuit 104a applies the initialization voltage VA1 to the hold capacitor of the peak detection circuit 15 to initialize the peak detection voltage, and the initial value setting circuit 104b applies the initialization voltage VA2. The peak detection voltage is initialized by applying it to the hold capacity of the peak detection circuit 16. In other states, the hold capacitance potentials of the peak detection circuits 15 and 16 are maintained, and the offset adjustment function of the limiter amplifier circuit is maintained as it is.

  If the initialization voltages VA1 and VA2 are set to a value lower than the minimum value of the packet signal strength input in advance, the diode 21 of the peak detection circuits 15 and 16 even if the optical packet signal 2 in the latter stage of FIG. 6 is input. Becomes a forward state, and the capacitor is charged up to a voltage corresponding to the packet signal by the rectifying action of the diode 21, so that it is possible to obtain excellent reception sensitivity and response characteristics for a high-speed burst signal.

Since the differential amplifier circuit 11 is a feedforward circuit, the initialization voltage VA1 is set larger than the initialization voltage VA2. Thus, the head part of the AC coupled packet signal works to increase the DC level on the IN side so as to decrease the DC level on the IP side shown in FIGS. For this reason, the offset voltage of the offset adjustment circuit 14 can be adjusted earlier than when VA1 and VA2 are set to the same potential. When an appropriate VA1 is given, an appropriate DC offset voltage is given to the minimum input amplitude of the next packet signal as shown in FIG. 9 (g), so that a good response characteristic can be obtained.

  FIG. 9 is a diagram for explaining operations of the reset pulse generation circuit and the initial value setting circuit. Here, the initial value setting circuit 104a will be described as an example, but the same applies to the initial value setting circuit 104b. FIG. 9A shows the waveform of the positive phase output OP of the limiter amplifier circuit when a burst signal is input as an optical packet signal. FIG. 9B shows an output waveform after passing through the low-pass filter 23. Here, the broken line indicates the threshold level of the next-stage comparator. The positive-phase output of the comparator has a high-frequency component removed through the low-pass filter 25 to have a waveform as shown in FIG. 9C, and the reverse-phase output becomes as shown in FIG. 9D. Therefore, when the AND operation of the waveforms of FIGS. 9C and 9D is performed, the reset pulse shown in FIG. 9E is obtained at the output of the AND circuit 26.

  FIG. 10 is a diagram showing the simulation result of the input signal response characteristic of the limiter amplifier circuit based on the circuit of FIG. FIG. 10A shows the input signal of the limiter amplifier circuit under the same conditions as in FIG. FIG. 10B shows an example of a reset pulse input to PKp and PKn of the limiter amplifier circuit. The output of the limiter amplifier at this time is shown in FIG. In the conventional configuration, the packet signal after 70 ns is lost, but in order to initialize the offset adjustment circuit 14, the packet signal is output to the limiter amplifier output. FIG. 11 is an enlarged view around 70 ns in FIG. FIG. 11A shows the input of the limiter amplifier, and FIG. 11B shows the output of the limiter amplifier. Better output characteristics than the beginning of the packet can be obtained.

  As described above, in this embodiment, the hold capacity of the peak detection circuit can be initialized by the reset pulse generation circuit 103 and the initial value setting circuits 104a and 104b even if there is an intensity difference between the optical input packet signals. For this reason, it is possible to obtain excellent reception sensitivity and response characteristics for high-speed burst signals. In addition, since reset is generated from the limiter (saturation) output, the reset signal can be generated whenever the packet signal is terminated regardless of the optical input power. Furthermore, since there is no AGC (Auto Gain Control) function and the amplification is limited (limited) by matching the offset, the burst response (about 10 ns) is excellent.

11, 12, 13, 17, 20 Differential amplification circuit, 14, 18 Offset adjustment circuit, 15, 16, 19 Peak detection circuit, 21 Diode, 22 Capacitance, 23, 25 Low-pass filter, 24 Differential comparator, 26 AND circuit , 103 reset pulse generation circuit, 104a, 104b initial value setting circuit, Ra1, Ra2 resistance (first initial voltage value generation section), Rb1, Rb2 resistance (second initial voltage value generation section), SWa, SWb switch

Claims (6)

A first differential amplifier circuit for amplifying a differential input signal composed of a normal phase input signal and a negative phase input signal;
A second differential amplifier circuit for amplifying a differential output signal of the first differential amplifier circuit;
A first offset adjustment circuit that adjusts a DC offset voltage of a differential output signal of the first differential amplifier circuit according to a voltage difference between a DC component of the positive phase input signal and a DC component of the negative phase input signal. When,
A second offset for adjusting a DC offset voltage of the differential output signal of the second differential amplifier circuit according to a DC component of one signal of the differential output signal of the second differential amplifier circuit and a reference voltage An adjustment circuit;
A reset pulse generating circuit for generating a reset pulse in accordance with either one of the differential output signals of the second differential amplifier circuit;
First and second initial value setting circuits,
When the reference voltage is adjusted to a predetermined value and the differential input signal is input, the second offset adjustment circuit converts the DC offset voltage of the differential output signal of the second differential amplifier circuit to DC. If the differential input signal is not input without adding an offset, a DC offset is added to the DC offset voltage of the differential output signal of the second differential amplifier circuit,
The first offset adjustment circuit includes:
A first peak detection circuit for detecting a DC component of the positive phase input signal;
A second peak detection circuit for detecting a DC component of the negative phase input signal;
A third differential amplifier circuit for amplifying a voltage difference between the output of the first peak detection circuit and the output of the second peak detection circuit;
When the reset pulse is generated, the first initial value setting circuit initializes the peak detection voltage of the first peak detection circuit with a first initialization voltage, and the second initial value setting circuit includes: A limiter amplifier circuit characterized by initializing a peak detection voltage of the second peak detection circuit with a second initialization voltage.   2. The limiter amplifier circuit according to claim 1, wherein the first initialization voltage is larger than the second initialization voltage. The reset pulse generation circuit includes:
A first low-pass filter that inputs one of the differential output signals of the second differential amplifier circuit;
A differential comparator for inputting an output signal of the first low-pass filter;
A second low-pass filter for inputting a first output signal of the differential comparator;
The limiter amplifier circuit according to claim 1, further comprising an AND circuit that inputs an output signal of the second low-pass filter and a second output signal of the differential comparator. The first initial value setting circuit includes a first initial voltage value generation unit and a first switch,
The second initial value setting circuit includes a second initial voltage value generation unit and a second switch,
When the reset pulse is generated, the first switch selects and outputs the voltage value of the first initial voltage value generation unit, and the second switch outputs the second initial voltage value generation unit. Select and output the voltage value,
When the reset pulse is not generated, the first switch does not select the voltage value of the first initial voltage value generator, the output is opened, and the second switch is the second initial voltage value. 4. The limiter amplifier circuit according to claim 1, wherein the output value is opened without selecting the voltage value of the generator. 5.   5. The limiter according to claim 1, wherein each of the first and second peak detection circuits includes a diode and a capacitor connected between a cathode of the diode and a ground. Amplifier circuit.   The limiter amplifier circuit according to claim 1, wherein a differential output of the second differential amplifier circuit is saturated.

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