JP4409163B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention Manufacturing method of semiconductor device And more particularly with ferroelectric capacitors Manufacturing method of semiconductor device About.
[0002]
[Prior art]
Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories that can store information even when the power is turned off.
[0003]
Among them, the flash memory stores information by accumulating electric charges in the floating gate of an insulated gate field effect transistor (IGFET), and a tunnel current flows through the gate insulating film when writing information. And requires a relatively high voltage.
[0004]
On the other hand, FeRAM has a ferroelectric capacitor, uses a ferroelectric film as the capacitor dielectric film, and causes spontaneous polarization in the capacitor dielectric film by applying a write voltage between the upper electrode and the lower electrode. Let The spontaneous polarization remains even when the power is turned off due to the hysteresis characteristic of the ferroelectric material, and information is read out by detecting the magnitude and polarity. Such an FeRAM operates at a lower voltage than a flash memory, and can perform high-speed writing with low power consumption.
[0005]
The characteristics of the ferroelectric capacitor greatly depend on the crystallinity of the capacitor dielectric film, and the better the crystallinity, the better the characteristics. Therefore, as the uppermost layer of the lower electrode, a Pt film whose orientation is aligned in one direction and whose orientation is high is adopted, and the crystallinity of the capacitor dielectric film is increased by the action of the Pt film. Since the polarization direction of the capacitor dielectric film having a perovskite structure is the (001) direction, the orientation is preferably aligned with the (001) direction. However, in practice, it is difficult to form such a capacitor dielectric film. Therefore, a Pt film aligned in the (111) direction is formed, and the capacitor dielectric film thereon is also formed in the (111) direction. Make sure the alignment is aligned.
[0006]
However, since the Pt film is easily peeled off when formed on the insulating film, a Ti film is formed under the Pt film in order to prevent the peeling. This Ti film has a function of aligning the orientation of the Pt film in addition to preventing peeling.
[0007]
Therefore, the lower electrode has a two-layer structure of a Ti film and a Pt film. As a method for forming such a lower electrode and processes after the formation, there are the following.
[0008]
The first method is a method of continuously forming a Pt film after forming a Ti film. ₂ Adhesion with the film is improved and an increase in resistance of the lower electrode can be suppressed (see, for example, Patent Document 1).
[0009]
In the second method, a Ti film and a Pt film are continuously formed to form a lower electrode, and then a rapid heat treatment is performed on the lower electrode before forming a ferroelectric film (for example, , See Patent Document 2). According to this method, since the orientation of the lower electrode is aligned in the (111) direction, the orientation of the ferroelectric film thereon is also increased, and the spontaneous polarization of the capacitor is enhanced.
[0010]
The third method is a method in which a lower electrode made of a Ti film and a Pt film is formed, a PZT film is formed thereon as a ferroelectric film, and then the PZT film is subjected to heat treatment (for example, a patent). Reference 3). According to this method, a Pb—Pt—Ti—O reaction layer is formed at the interface between the PZT film and the Pt film, and a capacitor with little deterioration can be provided.
[0011]
[Patent Document 1]
Japanese Patent Laid-Open No. 9-223779 (paragraph number 0062)
[Patent Document 2]
JP 2000-91511 A (paragraph number 0032)
[Patent Document 3]
Japanese Unexamined Patent Publication No. 2000-40779 (paragraph number 0019)
[0012]
[Problems to be solved by the invention]
By the way, there are various indexes representing the characteristics of ferroelectric capacitors, but the most important one is the residual polarization quantity Q. _sw There is. Residual polarization Q _sw Is the amount of polarization remaining in the capacitor dielectric film when the power is turned off, and the larger the value, the easier the separation between “0” and “1”.
[0013]
However, the first to third methods described above have the residual polarization quantity Q. _sw The amount of residual polarization Q _sw And the residual polarization quantity Q _sw There is room for improvement in reducing variation in the distribution of wafers in the wafer plane.
[0014]
The present invention has been created in view of the problems of the related art, and can increase the amount of remanent polarization compared to the prior art and reduce the variation in distribution of the amount of remanent polarization in the wafer surface. Can Manufacturing method of semiconductor device The purpose is to provide.
[0015]
[Means for Solving the Problems]
The above issues A step of forming an insulating film above the semiconductor substrate; a step of forming a layer of Ti on the insulating film as a lower layer of the conductive film for the lower electrode; and a temperature of the semiconductor substrate of 0 ° C. to 100 ° C. And exposing the lower layer to the atmosphere, and after exposing the lower layer to the atmosphere, forming a layer made of Pt on the lower layer as the upper layer of the conductive film for the lower electrode, Forming a layer and the upper layer into a conductive film for a lower electrode; forming a ferroelectric film on the upper layer; forming a conductive film for an upper electrode on the ferroelectric film; Patterning the conductive film for the lower electrode, the ferroelectric film, and the conductive film for the upper electrode, a lower electrode made of the conductive film for the lower electrode, a capacitor dielectric film made of the ferroelectric film, A capacitor comprising an upper electrode made of the upper electrode conductive film; The method of manufacturing a semiconductor device, characterized in that it comprises the steps of forming, the Solved by.
[0017]
Next, the operation of the present invention will be described.
[0018]
According to the present invention, after the lower layer of the lower electrode conductive film is exposed to the atmosphere, the upper layer of the lower electrode conductive film is formed on the lower layer. By adopting such a method, while maintaining the ferroelectric film orientation strength required for FeRAM, the remanent polarization Q _sw And the residual polarization quantity Q in the wafer plane becomes larger. _sw Variation is smaller than conventional. Furthermore, the retention characteristic, imprint characteristic, and fatigue loss of the capacitor are improved as compared with the conventional one without deteriorating the leakage current characteristic. Moreover, such an advantage does not depend on the upper layer deposition temperature.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0020]
1 to 23 are sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 24 is a plan view corresponding to FIG.
[0021]
First, steps required until a sectional structure shown in FIG.
[0022]
As shown in FIG. 1, an element isolation insulating film 2 is formed on the surface of an n-type or p-type silicon (semiconductor) substrate 1 by a LOCOS (Local Oxidation of Silicon) method. As the element isolation insulating film 2, an STI (Shallow Trench Isolation) method may be adopted in addition to the LOCOS method.
[0023]
After such an element isolation insulating film 2 is formed, p-type impurities and n-type impurities are selectively introduced into predetermined active regions (transistor formation regions) in the memory cell region A and the peripheral circuit region B of the silicon substrate 1. Then, the p-well 3a and the n-well 3b are formed. Although not shown in FIG. 1, a p-well (not shown) is also formed in the peripheral circuit region B to form a CMOS.
[0024]
Thereafter, the surface of the active region of the silicon substrate 1 is thermally oxidized to form a silicon oxide film as the gate insulating film 4.
[0025]
Next, an amorphous or polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1, and n-type impurities are ion-implanted into the silicon film on the p-well 3a and p-type impurities are implanted into the silicon film on the n-type well 3b. Reduce the resistance of the silicon film. Thereafter, the silicon film is patterned into a predetermined shape by photolithography to form gate electrodes 5a to 5c.
[0026]
Two gate electrodes 5a and 5b are arranged substantially in parallel on one p-well 3a in the memory cell region A, and these gate electrodes 5a and 5b constitute a part of the word line WL.
[0027]
Next, in the memory cell region A, an n-type impurity is ion-implanted into the p-well 3a on both sides of the gate electrodes 5a and 5b to form an n-type impurity diffusion region 6a that becomes the source / drain of the n-channel MOS transistor. . At the same time, an n-type impurity diffusion region is formed in a p-well (not shown) in the peripheral circuit region B. Subsequently, in the peripheral circuit region B, p-type impurities are ion-implanted into the n-well 3b on both sides of the gate electrode 5c to form a p-type impurity diffusion region 6b that becomes the source / drain of the p-channel MOS transistor.
[0028]
Subsequently, after an insulating film is formed on the entire surface of the silicon substrate 1, the insulating film is etched back to leave the side wall insulating film 7 only on both sides of the gate electrodes 5a to 5c. As the insulating film, for example, silicon oxide (SiO 2) is formed by CVD. ₂ ).
[0029]
Further, by using the gate electrodes 5a to 5c and the sidewall insulating film 7 as a mask, n-type impurity ions are again implanted into the p-well 3a to make the n-type non-diffused region 6a have an LDD structure, and the n-well 3b By again implanting p-type impurity ions therein, the p-type impurity diffusion region 6b also has an LDD structure.
[0030]
The n-type impurity and the p-type impurity are divided using a resist pattern.
[0031]
As described above, in the memory cell region A, an n-type MOSFET is configured by the p-well 3a, the gate electrodes 5a and 5b, the n-type impurity diffusion regions 6a on both sides thereof, and the n-well 3b in the peripheral circuit region B. The gate electrode 5c and the p-type impurity diffusion regions 6b on both sides thereof constitute a p-type MOSFET.
[0032]
Next, after forming a refractory metal film, for example, a film of Ti or Co, on the entire surface, the refractory metal film is heated to form a high melting point on the surfaces of the n-type impurity diffusion region 6a and the p-type impurity diffusion region 6b, respectively. Metal silicide layers 8a and 8b are formed. Thereafter, the unreacted refractory metal film is removed by wet etching.
[0033]
Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover film 9 on the entire surface of the silicon substrate 1 by plasma CVD. Further, silicon dioxide (SiO 2) is used as the first interlayer insulating film 10 by plasma CVD using TEOS gas. ₂ ) Is grown on the cover film 9 to a thickness of about 1.0 μm.
[0034]
Subsequently, the first interlayer insulating film 10 is polished by a chemical mechanical polishing (CMP) method to planarize the surface.
[0035]
Next, steps required until a structure shown in FIG.
[0036]
First, a film formation temperature and a film formation time are set to 20 ° C. and 14 seconds, respectively, and a Ti layer is formed on the first interlayer insulating film 10 as the lower layer 11a of the lower electrode conductive film by DC sputtering. The thickness is formed. The film formation temperature of the lower layer 11a is not limited to 20 ° C., and may be a temperature of 0 ° C. to 300 ° C. Furthermore, as the lower layer 11a, in addition to the Ti layer, a layer made of any of Ti, Pt—Ti alloy, Ir—Ti alloy, and Ru—Ti alloy may be formed.
[0037]
Thereafter, the silicon substrate 1 is taken out of the chamber used to form the lower layer 11a, and the lower layer 11a is exposed to the atmosphere at room temperature (about 24 ° C.) for about 2 hours to naturally oxidize or absorb moisture on the surface. As a result, a Ti thin natural oxide film is formed on the surface of the lower layer 11a. The time for exposure to the atmosphere is not limited to the above, and may be 5 minutes to 7 days. Further, the temperature of the silicon substrate 1 at that time is not limited to the above, and may be 0 ° C. to 100 ° C. The effects obtained by exposure to the atmosphere will be described in detail later.
[0038]
Next, steps required until a structure shown in FIG.
[0039]
First, the film formation temperature and the film formation time are set to 100 ° C. and 112 seconds, respectively, and a Pt layer is formed on the lower layer 11a as the upper layer 11b of the lower electrode conductive film by DC sputtering to a thickness of about 175 nm. To form. As a result, the lower electrode conductive film 11 composed of the lower layer 11a and the upper layer 11b is formed. Thus, by forming the Pt layer (upper layer 11b) on the Ti layer (lower layer 11a), the orientation of the Pt layer is aligned in the (111) direction by the action of the Ti layer, and is formed later. The orientation of the PZT film can be aligned in the (111) direction. Further, the lower layer 11 a also plays a role of increasing the adhesion strength between the lower electrode conductive film 11 and the first interlayer insulating film 10.
[0040]
In addition to the Pt layer, the upper layer 11b may have a single-layer or multi-layer structure including any of Pt, Ir, Ru, Pd, PtOx, IrOx, RuOx, and PdOx.
[0041]
Next, steps required until a structure shown in FIG.
[0042]
First, PLZT (lead lanthanum zirconate titanate; (Pb, La) (Zr, Ti) O _Three ) Is formed on the lower electrode conductive film 11 to a thickness of 100 to 300 nm, for example, 240 nm, and this is used as the ferroelectric film 12. In some cases, PLZT may be doped with a small amount of calcium (Ca) or strontium (Sr). Also, instead of PLZT, PZT (Pb (Zr, Ti) O _Three ) 、 (Sr, Ti) O _Three , (Ba, Sr) TiO _Three Materials such as Bi _Four Ti ₂ O ₁₂ The ferroelectric film 12 may be composed of a Bi layer structure compound such as. Further, as a method of forming the ferroelectric film 12, there are a spin-on method, a sol-gel method, a MOD (Metal Organic Deposition) method, and an MOCVD method in addition to the above-described sputtering method.
[0043]
Subsequently, the silicon substrate 1 is placed in a mixed gas atmosphere of argon and oxygen, and the ferroelectric film 12 is formed at a temperature of 600 ° C. or higher, for example, 725 ° C. for 20 seconds and a temperature rising rate of 125 ° C./sec. The PLZT film to be crystallized is subjected to RTA (Rapid Thermal Annealing) treatment to crystallize the PLZT film. According to such a crystallization treatment, Pt constituting the upper layer 11b is densified, and interdiffusion between Pt and O in the vicinity of the boundary surface between the lower electrode conductive film 11 and the ferroelectric film 12 is suppressed. You can also.
[0044]
After such a ferroelectric film 12 is formed, iridium oxide (IrO) is formed thereon as the upper electrode conductive film 13. ₂ ) A film is formed by sputtering to a thickness of 100 to 300 nm, for example, 200 nm. As the upper electrode conductive film 13, a platinum film or a ruthenium strontium oxide (SRO) film may be formed by sputtering.
[0045]
Next, steps required until a structure shown in FIG.
[0046]
First, after an upper electrode-shaped resist pattern (not shown) is formed on the upper electrode conductive film 13, the upper electrode conductive film 13 is etched using the resist pattern as a mask. The conductive film 13 is used as the upper electrode 13a of the capacitor.
[0047]
Then, after removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes. This annealing is performed to recover the damage that has entered the ferroelectric film 12 during sputtering and etching.
[0048]
Subsequently, in the memory cell region A, the ferroelectric film 12 is etched in a state in which a resist pattern (not shown) is formed around the capacitor upper electrode 13a and the periphery thereof, and the remaining ferroelectric film 12 is removed from the dielectric film of the capacitor. Used as body membrane 12a. Then, after removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes. This annealing is performed to degas moisture and the like absorbed by the underlying film.
[0049]
Next, as shown in FIG. 6, a PLZT film is formed as an encap layer 14 on the upper electrode 13a, the dielectric film 12a, and the lower electrode conductive film 11 to a thickness of 50 nm by sputtering at room temperature. . The encap layer 14 is formed to protect the dielectric film 12a that is easily reduced from hydrogen and block hydrogen from entering the dielectric film 12a. Note that a PZT film, an alumina film, or a titanium oxide film may be formed as the encap layer 14.
[0050]
Thereafter, the ferroelectric film 12 under the encap layer 14 is rapidly heat-treated in an oxygen atmosphere under conditions of 700 ° C. for 60 seconds and a temperature rising rate of 125 ° C./sec to improve the film quality.
[0051]
Next, a resist is applied on the encap layer 14, and this is exposed and developed to leave on and around the upper electrode 13a and the dielectric film 12a. Then, using the resist as a mask, the encap layer 14 and the lower electrode conductive film 11 are etched, and the remaining lower electrode conductive film 11 is used as a capacitor lower electrode 11c (see FIG. 7). Etching of the encap layer 14 and the lower electrode conductive film 11 is performed by dry etching using chlorine.
[0052]
After removing the resist pattern, the ferroelectric film 12 is annealed in an oxygen atmosphere at a temperature of 650 ° C. for 60 minutes to recover from damage.
[0053]
As a result, as shown in FIG. 7, a capacitor Q including the lower electrode 11c, the dielectric film 12a, and the upper electrode 13a is formed on the first interlayer insulating film 10.
[0054]
A planar configuration excluding the insulating film in the memory cell region A is as shown in FIG. 24, and a plurality of upper electrodes 13a are formed on one rectangular dielectric film 12a, and the dielectric film 12a. The lower electrode 11c below is sized to extend to the side of the dielectric film 12a. In FIG. 24, contact holes, bit lines and the like which will be described later are also drawn.
[0055]
Next, as shown in FIG. 8, a SiO2 film having a thickness of 1200 nm is formed as a second interlayer insulating film 15 on the capacitor Q and the first interlayer insulating film 10. ₂ After the film is formed by the CVD method, the surface of the second interlayer insulating film 15 is planarized by the CMP method. The growth of the second interlayer insulating film 15 is performed by using silane (SiH as a reactive gas). _Four ) May be used, or TEOS may be used. The surface of the second interlayer insulating film 15 is planarized until the thickness reaches 200 nm from the upper surface of the upper electrode 13a.
[0056]
Next, as shown in FIG. 9, a resist 16 is applied on the second interlayer insulating film 15, and this is exposed and developed, so that the impurity diffusion layer 6a in the memory cell region A and the capacitor lower electrode 11c are covered. Hole forming windows 16a to 16e are formed on the upper and impurity diffusion layers 6b in the peripheral circuit region B, respectively.
[0057]
Subsequently, the first and second interlayer insulating films 10 and 15 and the cover film 9 are dry-etched to form contact holes 15a to 15e on the impurity diffusion layer 6a and the capacitor lower electrode 11c in the memory cell region A. At the same time, contact holes 15d and 15e are formed also on the impurity diffusion layer 6b in the peripheral circuit region B. The first and second interlayer insulating films 10 and 15 and the cover film 9 are made of CF gas such as CHF. _Three CF _Four Etching is performed using a mixed gas containing Ar.
[0058]
In this etching, the etching rate of the PLZT encap layer 14 covering the lower electrode 11c of the capacitor Q is smaller than that of other insulating films, so that the shallow contact hole 15c formed on the lower electrode 11a and the other Differences in the etching depths of the contact holes 15a, 15b, 15d, and 15e are absorbed by the encap layer 14.
[0059]
The contact holes 15a to 15e have a tapered shape with a wide upper portion and a narrow lower portion. 5 μm.
[0060]
Next, after removing the resist 16, as shown in FIG. 10, RF pretreatment etching is performed on the second interlayer insulating film 15 and the inner surfaces of the contact holes 15 a to 15 e, and then sputtering is performed on them. Thus, a titanium (Ti) film is formed to a thickness of 20 nm and a titanium nitride (TiN) film is formed to a thickness of 50 nm. In addition, tungsten fluoride gas (WF ₆ ), A tungsten film 18 is formed on the glue film 17 by a CVD method using a mixed gas of argon and hydrogen. Incidentally, at the initial growth stage of the tungsten film 18, silane (SiH _Four ) Gas is also used. The tungsten film 18 has a thickness that completely fills the contact holes 15 a to 15 e, for example, about 500 nm on the second interlayer insulating film 15.
[0061]
Since the contact holes 15a to 15e each have a tapered shape, it is difficult to form a cavity (also referred to as a void) in the tungsten film 18 embedded therein.
[0062]
Next, as shown in FIG. 11, the tungsten film 18 and the glue film 17 on the second interlayer insulating film 15 are removed by the CMP method, and are left only in the contact holes 15a to 15e. Thereby, the tungsten film 18 and the glue film 17 in the contact holes 15a to 15e are used as the plugs 18a to 18e. Here, if etch back is used instead of the CMP method, different etching gases are required for the etching of the tungsten film 18 and the etching of the glue film 17, so that the etching management is troublesome.
[0063]
In one p-well 3a of the memory cell region A, a first plug 18a on the n-type impurity diffusion region 6a sandwiched between the two gate electrodes 5a and 5b is connected to a bit line to be described later, and the remaining The two second plugs 18b are connected to the upper electrode 13a of the capacitor Q via a wiring to be described later. Furthermore, as shown in FIG. 24, the contact hole 15c on the lower electrode 11c and the plug 18c in the contact hole 15c are formed in a portion protruding from the dielectric film 12a. In order to facilitate understanding, it is drawn for the sake of convenience so as to be on the extension of the plurality of plugs 18a, 18b on the impurity diffusion layer 6a of the memory cell region A.
[0064]
Thereafter, in order to remove moisture adhering to the surface of the second interlayer insulating film 15 and penetrating into the second interlayer insulating film 15 in steps such as a cleaning process after the contact holes 15a to 15e are formed and a cleaning process after the CMP, a vacuum chamber is again formed. The second interlayer insulating film 15 is heated at a temperature of 390 ° C. to release water to the outside. After such dehydration treatment, N 2 while heating the second interlayer insulating film 15 ₂ Annealing for improving the film quality by exposure to plasma is performed, for example, for 2 minutes.
[0065]
Subsequently, as shown in FIG. 12, an SiON film is formed to a thickness of, for example, 100 nm on the second interlayer insulating film 15 and the plugs 18a to 18e by plasma CVD. This SiON film is made of silane (SiH _Four ) And N ₂ It is formed using a mixed gas of O, and is used as an antioxidant film 19 for preventing the plugs 18a to 18e from being oxidized.
[0066]
Next, as shown in FIG. 13, the encap layer 14 and the second interlayer insulating film 15 are patterned by photolithography to form a contact hole 15 f on the upper electrode 13 a of the capacitor Q.
[0067]
Thereafter, the dielectric film 12a of the capacitor Q is annealed in an oxygen atmosphere at 550 ° C. for 60 minutes to improve the film quality of the dielectric film 12a. In this case, the plugs 18 a to 18 e are prevented from being oxidized by the antioxidant film 19.
[0068]
Thereafter, as shown in FIG. 14, the SiON antioxidant film 19 is dry-etched using a CF-based gas. Then, the surfaces of the plugs 18a to 18e and the upper electrode 13a are etched by about 10 nm by the RF etching method to expose the clean surfaces.
[0069]
Next, as shown in FIG. 15, a conductive film having a four-layer structure containing aluminum is formed on the second interlayer insulating film 15, the plugs 18a to 18e, and the contact hole 15f of the capacitor Q by a sputtering method. The conductive film is, in order from the bottom, a titanium nitride film with a thickness of 50 nm, a copper-containing (0.5%) aluminum film with a thickness of 500 nm, a titanium film with a thickness of 5 nm, and a titanium nitride film with a thickness of 100 nm.
[0070]
Then, the conductive film is patterned by photolithography to form contact pads 20a and 20c and first-layer wirings 20b and 20d to 20f as shown in FIG.
[0071]
Here, in the memory cell region A, a contact pad 20a is formed on the plug 18a between the two gate electrodes 5a and 5b on the p well 3a. Further, the plug 18b between the element isolation insulating film 2 and the gate electrodes 5a and 5b and the upper electrode 13a of the capacitor Q are connected by the wiring 20b through the contact hole 15f. Further, another contact pad 20c is formed on the plug 18c on the lower electrode 11a of the capacitor Q in the arrangement shown in FIG.
[0072]
Note that the resist pattern used in the photolithography method is removed after the contact pad 20a, the wiring 20b, and the like are formed.
[0073]
Next, as shown in FIG. 16, SiO CVD is performed by plasma CVD using TEOS as a source. ₂ A film is formed as a third interlayer insulating film 21 to a thickness of 2300 nm, and the interlayer insulating film 21 covers the second interlayer insulating film 15, the contact pads 20a and 20c, the wiring 20b, and the like. Subsequently, the surface of the third interlayer insulating film 21 is planarized by the CMP method.
[0074]
Thereafter, the third interlayer insulating film 21 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such dehydration treatment, N 3 while heating the third interlayer insulating film 21 ₂ Dehydration and film quality improvement by exposure to O plasma.
Then, as shown in FIG. 17, SiO2 is formed by plasma CVD using TEOS. ₂ A protective insulating film 22 is formed on the third interlayer insulating film 21 to a thickness of 100 nm or more. When soot (void) is generated in the third interlayer insulating film 21, the void is blocked by the protective insulating film 22. Thereafter, the protective insulating film 22 is dehydrated at a temperature of 390 ° C. in a vacuum chamber and heated while N ₂ Dehydration and film quality improvement by exposure to O plasma.
[0075]
Next, steps required until a structure as shown in FIG.
[0076]
First, the third interlayer insulating film 21 and the protective insulating film 22 are patterned by photolithography, and then the contact pad 20a in the middle of the p-well 3a in the memory cell region A and the lower electrode 11a of the capacitor Q are formed. Holes 22a to 22c are formed on the wiring 20c and the wiring 20f in the peripheral circuit region B.
[0077]
Next, after performing RF pretreatment etching on the upper surface of the protective insulating film 22 and the inner surfaces of the holes 22a to 22c, a glue film 23 made of titanium nitride (TiN) having a thickness of 90 nm to 150 nm is formed by sputtering. Thereafter, a blanket tungsten film 24 is formed to a thickness of, for example, 800 nm by a CVD method so as to fill the holes 22a to 22c. For the growth of the blanket tungsten film 24, WF ₆ , H ₂ Source gas containing is used. By the way, the reason why the film thickness of the glue film 23 is 90 nm or more is that H used for forming the relatively thick tungsten film 24. ₂ This is to mitigate the penetration of the protective insulating film 22 to damage the capacitor Q. Note that, as described above, the tungsten film 18 shown in FIG. 10 is thinly formed to fill the contact holes 15a to 15f having a small diameter, so that the TiN glue film 17 thereon is as thin as 50 nm. May be.
[0078]
Next, as shown in FIG. 19, the tungsten film 24 is etched back and left only in the holes 22a to 22c, and the tungsten film 24 in the holes 22a to 22c is used as the plugs 25a to 25c of the second layer. As a result, the TiN glue film 23 remains on the protective insulating film 22.
[0079]
Next, as shown in FIG. 20, a conductive film 26 having a three-layer structure is formed on the TiN glue film 23 and the plugs 25a to 25c by a sputtering method. The conductive film 26 is a copper-containing (0.5%) aluminum film having a thickness of 500 nm, a titanium film having a thickness of 5 nm, and a titanium nitride film having a thickness of 100 nm in order from the bottom.
[0080]
Then, the conductive film 26 is patterned by photolithography as shown in FIG. 21 to form a second-layer contact pad and a second-layer aluminum wiring. For example, in memory cell region A, bit line 26a connected via plugs 18a and 25a and contact pad 20a is formed above impurity diffusion layer 6a at the center of p well 3a, and the lower electrode of capacitor Q 11c, plugs 18c and 25b and a second-layer wiring 26b connected via the contact pad 20c are formed. Further, on the first-layer aluminum wiring 20f in the peripheral circuit region B, the plug 25c is interposed. A second-layer aluminum wiring 26c connected to each other is formed. A plan view of this state is shown in FIG.
[0081]
Next, the steps as shown in FIGS. 17 to 21 are repeated to form the structure as shown in FIG. The process is as follows.
[0082]
First, SiO2 is formed by plasma CVD using TEOS as a source. ₂ A film is formed to a thickness of 2300 nm as the fourth interlayer insulating film 27, and the lower protective insulating film 22 and the wirings 26 a to 26 c are covered with this interlayer insulating film 27. Subsequently, the surface of the fourth interlayer insulating film 27 is planarized by the CMP method. Thereafter, the fourth interlayer insulating film 27 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such dehydration treatment, the fourth interlayer insulating film 27 is made N. ₂ Improve film quality by exposure to O plasma.
[0083]
Subsequently, SiO2 is formed by plasma CVD using TEOS. ₂ An upper protective insulating film 28 is formed on the fourth interlayer insulating film 27 to a thickness of 100 nm or more. Thereafter, the protective insulating film 28 is dehydrated in a vacuum chamber at a temperature of 390 ° C. and heated while N ₂ Improve film quality by exposure to O plasma. Further, the fourth interlayer insulating film 27 and the protective insulating film 28 are patterned by photolithography to form a hole 27a on the second-layer aluminum wiring 26b electrically connected to the lower electrode 11c of the capacitor Q. To do. Although a resist mask is used for the photolithography method, it is removed after the hole 27a is formed.
[0084]
Next, a glue film 29 made of titanium nitride (TiN) having a film thickness of 90 nm to 150 nm is formed on the upper surface of the protective insulating film 28 and the inner surface of the hole 27a by sputtering, and then blanket so as to bury the hole 27a. A tungsten film is formed to a thickness of 800 nm by a CVD method. Further, the bracket tungsten film is etched back and left only in the hole 27a, and the bracket tungsten film in the hole 27a is used as the plug 30 of the third layer.
[0085]
As a result, the TiN glue film 29 remains on the protective insulating film 28.
[0086]
Thereafter, a conductive film having a two-layer structure is formed on the glue film 29 and the plug 30 by sputtering. The conductive film is a copper-containing (0.5%) aluminum film having a thickness of 500 nm and a titanium nitride film having a thickness of 100 nm in order from the bottom. Then, the conductive film is patterned by a photolithography method to form third-layer aluminum wirings 31a to 31c.
[0087]
Next, as shown in FIG. 23, SiO CVD is performed by plasma CVD using TEOS as a source. ₂ A protective insulating film 32 made of 100 nm is formed. Thereafter, the protective insulating film 32 is heated at a temperature of 390 ° C. in a vacuum chamber to release water to the outside. After such dehydration treatment, the protective insulating film 32 is formed with N. ₂ Exposure to O plasma improves film quality with dehydration.
[0088]
Subsequently, a silicon nitride film 33 is formed on the protective insulating film 32 to a thickness of 350 nm by a CVD method to prevent water from entering the protective insulating film 32.
[0089]
Thereafter, a polyimide film is applied to a thickness of 3 μm on the silicon nitride film 33 and baked at 230 ° C. for 30 minutes to form a cover film 34.
[0090]
The process so far completes the FeRAM.
[0091]
As described above, in this embodiment, after the Ti lower layer 11a of the lower electrode conductive film 11 is formed, it is once exposed to the atmosphere, and then the Pt upper layer 11b is formed. The effect obtained by such a method will be described next.
[0092]
FIG. 25 shows the Pt upper layer 11b and the PLZT ferroelectric film 12 for the conventional example in which the Pt upper layer 11b is continuously formed without forming the Ti lower layer 11a after exposure to the atmosphere and the present invention. It is a graph which shows the result obtained by investigating the strength of each orientation. An X-ray diffractometer (XRD) was used for the investigation. The orientation strength in the (222) direction was examined for the Pt upper layer 11b, and the orientation strength in the (111) direction was examined for the PLZT ferroelectric film 12. Among the series of graphs, those indicated by “discontinuous W / N1 to W / N3” indicate the present invention, and “W / N1 to W / N3” indicates the wafer number. On the other hand, what is indicated by “continuous W / N1 to W / N3” is a conventional example in which a Ti lower layer 11a and a Pt upper layer 11b are continuously formed. This conventional example corresponds to the technique described in Japanese Patent Application Laid-Open No. 9-223779, in which the film forming conditions of the layers 11a and 11b are the same as those of the present embodiment.
[0093]
As shown in FIG. 25, in this embodiment, the strength of the orientation of the ferroelectric film 12 is slightly smaller than that of the conventional example, but 500,000 cps necessary for FeRAM can be secured.
[0094]
FIG. 26 shows the residual polarization quantity Q when a voltage of 3 V is applied to the capacitor Q. _sw Is a cumulative graph showing the results of examining the 71 points in the wafer surface. The vertical axis of the graph shows the cumulative probability. In this figure, there are three series for the present invention and the conventional example, but each series corresponds to the three wafers in FIG. In this investigation, a comparative example different from the present invention and the conventional example was investigated. In this comparative example, after the Ti lower layer 11a is formed, it is oxidized by RTA in a mixed atmosphere of oxygen and argon, and the Pt upper layer 11b is formed again in vacuum. In the comparative example, the film forming conditions of the layers 11a and 11b are the same as those in the present embodiment.
[0095]
As is understood from FIG. 26, the residual polarization quantity Q of the present invention. _sw Becomes larger than that of the conventional example. Further, when the Ti lower layer 11b is thermally oxidized as in the comparative example, the residual polarization quantity Q is compared with the case of spontaneous oxidation as in the present invention. _sw It is understood that will become smaller.
[0096]
FIG. 27 shows the amount of remanent polarization Q based on the investigation result of FIG. _sw 6 is a graph obtained by calculating the average value and standard deviation in the wafer surface.
[0097]
As shown in FIG. 27, in the present invention, the residual polarization quantity Q _sw The average value is the largest, and the standard deviation is the smallest of the three. _sw It can be seen that the distribution in the wafer surface becomes good. This is because when the surface of the Ti lower layer 11b is naturally oxidized, Ti is difficult to diffuse into the ferroelectric film 12 when the PLZT ferroelectric film 12 is subjected to crystallization annealing. This is considered to be because the characteristics of the interface between Pt and the Pt upper layer 11b are improved.
[0098]
Note that FIG. 34 shows the residual polarization quantity Q based on the investigation result of FIG. _sw This is a graph of the distribution in the wafer plane. As shown therein, the standard deviation in the present invention falls within the range of 0.372 to 0.425, and is smaller than the conventional example (0.539 to 1.006).
[0099]
28A and 28B are cumulative graphs of the leakage current density of the capacitor Q in the present invention, the conventional example, and the comparative example used in the investigation of FIG. In FIGS. 28A and 28B, a voltage of 6V is applied to the capacitor Q, but the polarity of the voltage is opposite to that in FIGS. 28A and 28B. The leakage current density was measured at 71 points in the wafer surface.
[0100]
As understood from FIGS. 28A and 28B, in the comparative example in which the Ti lower layer 11a is thermally oxidized, the leakage current density is increased by about 1 to 1.5 digits as compared with the conventional example. On the other hand, when the Ti lower layer 11a is naturally oxidized as in the present invention, the characteristics of the leakage current are almost the same as in the conventional example and do not increase as in the comparative example.
[0101]
FIG. 29 is a graph of Q2 (88) for each of the present invention, the conventional example, and the comparative example. Q2 (88) means that two capacitors Q are paired and a voltage of 3 V is applied, then one is set in a positive direction polarization, the other is set in a negative direction polarization, and the power is turned off and left at 150 ° C. for 88 hours. Refers to the amount of polarization remaining. This Q2 (88) is an index indicating the characteristics of the capacitor, and it is said that the larger the value, the better the retention characteristics of the capacitor.
[0102]
As shown in FIG. 29, Q2 (88) of the present invention is about 2-3 μC / cm than that of the conventional example. ² It can be understood that the retention characteristic is improved. On the other hand, when the Ti lower layer 11a is thermally oxidized as in the comparative example, the retention characteristics are deteriorated as compared with the conventional example.
[0103]
FIG. 30 is a graph of Q3 (88) for each of the present invention, the conventional example, and the comparative example. Q3 (88) is a pair of two capacitors Q, a voltage of 3 V is applied, one is positively polarized, the other is negatively polarized, and the power is turned off and left at 150 ° C. for 88 hours. It refers to the amount of polarization when the polarity is reversed by applying a voltage of 3 V again. This Q3 (88) indicates the imprint characteristic of the capacitor, and the smaller the value, the more the capacitor is affected by one polarity. Therefore, the larger Q3 (88), the better the imprint characteristics of the capacitor.
[0104]
As shown in FIG. 30, in the present invention, Q3 (88) is about 4 μC / cm higher than that of the conventional example. ² It is understood that the imprint characteristics are improved. It is also understood that the present invention has better imprint characteristics than the comparative example.
[0105]
FIG. 31 is a graph showing fatigue loss of the ferroelectric film 12a of the PLZT capacitor in each of the present invention, the conventional example, and the comparative example. Fatigue Loss is 2.88 × 10 at an acceleration voltage of 7V ⁷ After writing to the capacitor Q, the residual polarization amount Q when data is written at 3V and then the power is turned off. _sw Point to. Specifically, Fatigue Loss (%) is 100 × {(Q before acceleration _sw )-(Q after acceleration _sw )} / (Q before acceleration _sw The smaller the value, the harder the capacitor will deteriorate.
[0106]
As shown in FIG. 31, the fatigue loss of the present invention is almost the same as the conventional example. On the other hand, it is understood that the fatigue loss is larger in the comparative example in which the Ti lower layer 11a is thermally oxidized than in the conventional example.
[0107]
FIG. 32 shows the residual polarization quantity Q at 71 points in the wafer surface when the film forming temperature of the Pt upper layer 11b is varied. _sw It is the graph obtained by investigating the maximum value, minimum value, average value, and standard deviation. In addition to the present invention, this investigation was performed on the above-described conventional example.
[0108]
As shown in FIG. 32, in the present invention, the residual polarization quantity Q is higher than that of the conventional example regardless of the deposition temperature of the Pt upper layer 11b. _sw In addition, the average value is high and the standard deviation is also small, so that the in-plane distribution is improved.
[0109]
From the above experimental results, in the present invention, the remanent polarization amount Q is higher than that of the prior art while ensuring the orientation strength (about 500,000 cps) of the ferroelectric film 12 necessary for FeRAM. _sw The amount of residual polarization Q in the wafer surface can be increased. _sw Variation can be made smaller than before. Furthermore, the retention characteristic, imprint characteristic, and fatigue loss of the capacitor can be improved as compared with the conventional one without deteriorating the leakage current characteristic. Moreover, such an advantage can be obtained regardless of the deposition temperature of the Pt upper layer 11b.
[0110]
Next, consider a semiconductor manufacturing apparatus used for manufacturing FeRAM.
[0111]
FIG. 33A is a configuration diagram of a semiconductor manufacturing apparatus according to a conventional example. In the conventional example, since the Ti lower layer 11a and the Pt upper layer 11b are continuously formed, the Ti chamber 102 and the Pt chamber 103 need to be paired. It is provided around the transfer chamber 101.
[0112]
However, since the deposition time of the Pt upper layer 11b is several times longer than that of the Ti lower layer 11a, when the Pt upper layer 11b is deposited in the Pt chamber 103, the deposition in the Ti chamber 102 is performed. There is an inconvenience that the Ti chamber is in a standby state and the operation rate of the Ti chamber is lowered.
[0113]
In contrast, in the present invention, since the Ti lower layer 11a is formed and then exposed to the atmosphere, the number of Ti chambers 102 and Pt chambers 103 need not be equal.
[0114]
Therefore, for example, as shown in FIG. 33B, the number of Pt chambers 103 is reduced to one and the number of Ti chambers 102 is increased to three, so that film formation is always performed in the three Ti chambers 102. In this way, when the Ti lower layer 11a is formed, the silicon substrate 1 is retracted to a load lock or the like, so that the operation rate of the Ti chamber 102 can be increased to 1.5 times (= 3/2) the conventional one. it can.
[0115]
The features of the present invention are added below.
[0116]
(Appendix 1) a semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A lower electrode in which a lower layer and an upper layer are sequentially stacked, a capacitor dielectric film, and a capacitor formed by sequentially forming an upper electrode on the insulating film;
With
A semiconductor device, wherein a natural oxide film of the lower layer is formed on a surface of the lower layer of the lower electrode.
[0117]
(Additional remark 2) The said lower layer is a layer which consists of either Ti, a Pt-Ti alloy, an Ir-Ti alloy, and a Ru-Ti alloy, The semiconductor device of Additional remark 1 characterized by the above-mentioned.
[0118]
(Additional remark 3) The process of forming an insulating film above a semiconductor substrate,
Forming a lower layer of the lower electrode conductive film on the insulating film;
Exposing the lower layer to the atmosphere;
After exposing the lower layer to the atmosphere, forming an upper layer of the lower electrode conductive film on the lower layer, and making the upper layer and the upper layer a lower electrode conductive film;
Forming a ferroelectric film on the upper layer;
Forming an upper electrode conductive film on the ferroelectric film;
Patterning the conductive film for the lower electrode, the ferroelectric film, and the conductive film for the upper electrode to form a lower electrode made of the conductive film for the lower electrode, a capacitor dielectric film made of the ferroelectric film, Forming a capacitor comprising an upper electrode made of the upper electrode conductive film;
A method for manufacturing a semiconductor device, comprising:
[0119]
(Additional remark 4) The temperature of the said semiconductor substrate in the process to expose to the said atmosphere is 0 degreeC-100 degreeC, The manufacturing method of the semiconductor device of Additional remark 3 characterized by the above-mentioned.
[0120]
(Additional remark 5) The manufacturing method of the semiconductor device of Additional remark 3 or Additional remark 4 characterized by performing the process to the said atmosphere for 5 minutes-7 days.
[0121]
(Additional remark 6) The said lower layer is formed at the temperature of 0 degreeC-300 degreeC, The manufacturing method of the semiconductor device in any one of Additional remark 3 thru | or Additional remark 5 characterized by the above-mentioned.
[0122]
(Additional remark 7) The said lower side layer is a layer which consists of either Ti, a Pt-Ti alloy, an Ir-Ti alloy, and a Ru-Ti alloy, It is any one of Additional remark 3 thru | or Additional remark 6 characterized by the above-mentioned. Semiconductor device manufacturing method.
[0123]
(Supplementary note 8) Any of Supplementary notes 3 to 7, wherein the upper layer has a single-layer structure or a multi-layer structure including any of Pt, Ir, Ru, Pd, PtOx, IrOx, RuOx, and PdOx. A method for manufacturing the semiconductor device according to claim 1.
[0124]
(Supplementary Note 9) The ferroelectric film is (Sr, Ti) O. _Three , (Ba, Sr) TiO _Three , Pb (Zr, Ti) O _Three , (Pb, La) (Zr, Ti) O _Three The method for manufacturing a semiconductor device according to any one of appendix 3 to appendix 8, wherein the semiconductor device is a film made of any one of Bi and Bi-layered structural compounds.
[0125]
【The invention's effect】
As described above, according to the present invention, the lower layer of the lower electrode conductive film is exposed to the atmosphere and naturally oxidized, and then the upper layer of the lower electrode conductive film is formed on the lower layer. did.
[0126]
As a result, the amount of remanent polarization Q can be increased more than before, while ensuring the orientation strength of the ferroelectric film necessary for FeRAM. _sw And the residual polarization quantity Q in the wafer plane can be increased. _sw Variation can be made smaller than before. Furthermore, the retention characteristic, imprint characteristic, and fatigue loss of the capacitor can be improved as compared with the conventional one without deteriorating the leakage current characteristic. Moreover, such an advantage can be obtained regardless of the film formation temperature of the upper layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view (No. 1) illustrating a method for manufacturing a semiconductor manufacturing apparatus according to an embodiment of the present invention.
FIG. 2 is a sectional view (No. 2) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 4 is a sectional view (No. 4) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 5 is a sectional view (No. 5) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 6 is a sectional view (No. 6) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 7 is a sectional view (No. 7) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 8 is a sectional view (No. 8) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 9 is a sectional view (No. 9) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 10 is a sectional view (No. 10) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 11 is a sectional view (No. 11) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 12 is a cross-sectional view (No. 12) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 13 is a sectional view (No. 13) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 14 is a cross-sectional view (No. 14) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 15 is a cross-sectional view (No. 15) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 16 is a cross-sectional view (No. 16) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 17 is a cross-sectional view (No. 17) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 18 is a cross-sectional view (No. 18) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 19 is a cross-sectional view (No. 19) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 20 is a sectional view (No. 20) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 21 is a sectional view (No. 21) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 22 is a cross-sectional view (No. 22) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 23 is a cross-sectional view (No. 23) showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 24 is a plan view showing the method for manufacturing the semiconductor manufacturing apparatus according to the embodiment of the present invention.
FIG. 25 is a graph obtained by investigating the present invention and the conventional example with respect to the orientation strength of the Pt upper layer and the PLZT ferroelectric film.
FIG. 26 is a diagram illustrating a residual polarization quantity Q of a capacitor in each of the present invention, the conventional example, and the comparative example. _sw It is a cumulative graph which shows.
FIG. 27 is a diagram showing a residual polarization quantity Q of a capacitor in each of the present invention, the conventional example, and the comparative example. _sw It is a graph which shows the average value in a wafer, and a standard deviation.
FIG. 28 (a) is a cumulative graph of capacitor leakage current density in each of the present invention, the conventional example, and the comparative example, and FIG. 28 (b) is an applied voltage to FIG. 28 (a). It is a cumulative graph of the leakage current density when the above is reversed.
FIG. 29 is a graph of Q2 (88) of each of the present invention, the conventional example, and the comparative example.
FIG. 30 is a graph of Q3 (88) for each of the present invention, the conventional example, and the comparative example.
FIG. 31 is a graph showing fatigue loss of a ferroelectric film of a PLZT capacitor in each of the present invention, a conventional example, and a comparative example.
FIG. 32 shows the amount of residual polarization Q in the wafer surface when the film formation temperature of the Pt upper layer is varied. _sw It is the graph obtained by investigating the maximum value, the minimum value, the average value, and the standard deviation in the present invention and the conventional example.
FIG. 33 (a) is a configuration diagram of a semiconductor manufacturing apparatus according to a conventional example, and FIG. 33 (b) is a configuration diagram of a semiconductor manufacturing apparatus according to an embodiment of the present invention.
FIG. 34 shows the amount of remanent polarization Q based on the investigation result of FIG. _sw This is a graph of the distribution in the wafer plane.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Element isolation insulating film, 3a, 3b ... Well, 4 ... Gate insulating film, 5a-5c ... Gate electrode, 6a, 6b ... Impurity diffusion layer, 7 ... Side wall insulating film, 8a , 8b ... refractory metal silicide film, 9 ... cover film, 10 ... interlayer insulating film, 11 ... lower electrode conductive film, 11a ... lower layer, 11b ... upper layer, 11c ... lower electrode, 12 ... ferroelectric film , 12a ... dielectric film, 13 ... upper electrode conductive film, 13a ... upper electrode, 14 ... encap layer, 15 ... interlayer insulating film, 15a-15f ... contact hole, 16 ... resist, 17 ... glue film, 18 ... Tungsten layer, 18a to 18e ... plug, 19 ... antioxidant film, 20a, 20c ... contact pad, 20b, 20c-20f ... wiring, 21 ... interlayer insulating film, 22 ... protective insulating film, 23 ... glue film, 24 Tungsten film, 25a to 25c ... plug, 26 ... conductive layer, 27 ... interlayer insulating film, 28 ... protective insulating film, 29 ... adhesion layer, 30 ... plug, 31a-31f ... wiring, 32 ... protective insulating film, 33 ... silicon Nitride film 34 ... Cover film 101 ... Transfer chamber 102 ... Ti chamber 103 ... Pt chamber A ... Memory cell region B ... Peripheral circuit region Q ... Capacitor

Claims (3)

Forming an insulating film above the semiconductor substrate;
Forming a layer of Ti on the insulating film as a lower layer of the lower electrode conductive film;
Exposing the lower layer to the atmosphere while setting the temperature of the semiconductor substrate to 0 ° C. to 100 ° C . ;
After the lower layer is exposed to the atmosphere, a layer made of Pt is formed on the lower layer as an upper layer of the lower electrode conductive film, and the upper layer and the upper layer are formed on the lower electrode conductive film. And the process of
Forming a ferroelectric film on the upper layer;
Forming an upper electrode conductive film on the ferroelectric film;
Patterning the conductive film for the lower electrode, the ferroelectric film, and the conductive film for the upper electrode to form a lower electrode made of the conductive film for the lower electrode, a capacitor dielectric film made of the ferroelectric film, Forming a capacitor comprising an upper electrode made of the upper electrode conductive film;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the step of exposing to the atmosphere is performed for 5 minutes to 7 days. The method for manufacturing a semiconductor device according to claim 1 , wherein the lower layer is formed at a temperature of 0 ° C. to 300 ° C. 3.

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