JP4360826B2 - Semiconductor film and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor film used for a thin film transistor (hereinafter sometimes abbreviated as “TFT”) and a manufacturing method thereof, and further to a semiconductor device configured using the semiconductor film. In particular, the present invention can be used for active matrix liquid crystal display devices, organic EL display devices, contact image sensors, three-dimensional ICs, and the like.
[0002]
[Prior art]
In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a drive circuit are provided on the same substrate has begun to enter into a general household as well as a monitor for a personal computer (PC). For example, instead of CRT (Cathode-ray Tube), a liquid crystal display is introduced as a television, and a front projector for watching movies and playing games as entertainment is introduced into ordinary households. The market for equipment is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.
[0003]
The amount of information written to pixels for high-resolution image display is increasing. If the information is not written in a short time, it is impossible to display an image having a huge amount of information for high-definition display as a moving image. Accordingly, high-speed operation is required for TFTs used in driving circuits. In order to enable high-speed operation, it is required to realize a TFT using a crystalline semiconductor film having good crystallinity that can obtain high field effect mobility.
[0004]
As a method for obtaining a good crystalline semiconductor film on a glass substrate, the present inventors have conventionally added a metal element having an action of promoting crystallization to an amorphous semiconductor film, followed by heat treatment. We are developing a technology to obtain a good semiconductor film with uniform crystal orientation by heat treatment at lower temperature and shorter time.
[0005]
However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. Catalytic element segregates irregularly in the semiconductor film, especially at the grain boundaries, and this segregation of the catalytic element becomes a current escape path (leakage path), which causes sudden off-current. It is thought that it is causing the increase. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process. Hereinafter, the process of removing the catalyst element is referred to as a gettering process.
[0006]
Various processes and methods have been proposed for the gettering process and gettering method. The outline is that the concentration of the catalytic element in the active region (semiconductor layer) of the semiconductor device is mainly reduced by forming a gettering region having a gettering function and moving the catalytic element there. The relationship between the semiconductor layer and the gettering region can be divided into the following three methods.
[0007]
(1) In the crystalline semiconductor film, a gettering region is formed in a region other than a region to be a semiconductor layer, and a catalytic element is moved there.
[0008]
{Circle around (2)} A gettering region is formed in the semiconductor layer, and the catalyst element is moved to the gettering region to getter only a portion (channel region or the like) where the remaining catalyst element is particularly problematic in the semiconductor layer.
[0009]
(3) In the state of the crystalline semiconductor film, a gettering layer is formed on the upper surface thereof, and the catalytic element is moved in a direction perpendicular to the film surface.
[0010]
Among these methods, in the method (1), in order to cause a region other than the semiconductor layer to function as a gettering region in the crystalline semiconductor film, an element having a gettering effect (gettering element) is selectively used. Need to be introduced. Therefore, a photolithographic process for forming a mask at that time, a doping process for introducing a gettering element, and the like increase, resulting in an increase in manufacturing cost and a decrease in manufacturing yield. Further, since the catalytic element is moved to a region other than the semiconductor layer, a distance (gettering distance) necessary for moving the catalytic element is extended, and a long time is required for the heat treatment for the gettering movement. In this case, not only the tact time of the apparatus is extended and the manufacturing cost is increased, but also a large glass substrate or the like cannot cope with thermal deformation of the substrate, and it is difficult to manufacture.
[0011]
In the method (2), for example, by using the source / drain region as a gettering region, there is no need to add a step for gettering, and the manufacturing process can be simplified. Is big. However, the doping process at this time needs to satisfy both the conditions as the source / drain regions and the gettering, and the process margin becomes very small. Further, since the heat treatment for gettering is performed after the semiconductor layer is formed, there is a large problem of shrinkage in the glass substrate, and it is difficult to perform heat treatment sufficient for gettering. Therefore, in this method, the degree of freedom of the process after forming the semiconductor layer is greatly limited due to gettering, and the condition margin of each process is small.
[0012]
In contrast to these methods, in the method (3), gettering is performed in the vertical direction in a state where the crystalline semiconductor film is formed on the entire surface of the substrate (the stage before the first photolithography process). Although some additional steps for gettering are necessary, the heat treatment conditions for gettering can be set regardless of the shrinkage of the glass substrate, and sufficient heat treatment is possible. Further, the necessary gettering distance is sufficient only in the film thickness direction of the crystalline semiconductor film. Furthermore, since gettering can be completed in the state of the crystalline semiconductor film, a process with a high degree of freedom can be constructed in the subsequent process without considering the gettering process. From such a viewpoint, the advantage of the method (3) is great.
[0013]
A gettering method using the method (3) is described in Patent Document 1, Patent Document 2, and Patent Document 3.
[0014]
Patent Document 1 discloses a method of moving a catalytic element into an oxide film by thermally oxidizing the surface of a single crystal silicon film crystallized with the catalytic element using an SOI substrate. . Thereafter, the oxide film formed by thermal oxidation is removed to complete gettering of the single crystal silicon film. In Patent Document 1, the oxidizing atmosphere at this time is an atmosphere containing a halogen element, and the catalytic element is vaporized and removed by its action, and it is moved and gettered into the thermal oxide film.
[0015]
In Patent Document 2 and Patent Document 3, a barrier layer is formed over a semiconductor film crystallized with a catalytic element, and a second semiconductor film and a third semiconductor film (getter) containing a gettering element are formed thereon. A method is disclosed in which a catalytic element is transferred from a lower semiconductor film through a barrier layer to a second semiconductor film and a third semiconductor film by performing a heat treatment after forming the ring layer). Then, the catalyst element is gettered by removing the third semiconductor film / second semiconductor film / barrier layer. At this time, in Patent Document 2, a rare gas element is used as the gettering element, and the third semiconductor film contains the rare gas element. In Patent Document 3, one conductivity type impurity (phosphorus or the like) is used as a gettering element, and the third semiconductor film contains one conductivity type impurity. In these patent documents, the second semiconductor film is provided. This is because the gettering element contained in the third semiconductor layer is diffused into the first semiconductor film crystallized by the catalytic element. It is provided for the purpose of preventing, and may be omitted in some cases.
[0016]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-64817
[Patent Document 2]
JP 2002-246394 A
[Patent Document 3]
JP 2002-246395 A
[0017]
[Problems to be solved by the invention]
However, the gettering techniques disclosed in Patent Documents 1 to 3 are still not sufficient and have some problems.
[0018]
First, Patent Document 1 has a fundamental problem that the gettering effect is not sufficient and the residual amount of the catalyst element cannot be sufficiently reduced. As a result of actual confirmation by the present inventors, in the method described in Patent Document 1, the catalytic element in the crystalline semiconductor film after gettering can be reduced only to about 1/3 of the initial value. . This is because the diffusion coefficient of the catalytic element (typically nickel) in the oxide film is 3 or more orders of magnitude smaller than the diffusion coefficient in the semiconductor film, so that it diffuses and moves into the oxide film. The main gettering action is due to the action of the halogen element in the oxidizing atmosphere. ₂ And NiF ₂ It is thought that it has vaporized as a form. In such a reaction system, there is a certain effect on the film surface, but it is difficult to reduce the catalyst element concentration over the entire semiconductor film. Furthermore, in order to sufficiently advance such a reaction, a high temperature of 1000 ° C. or higher is necessary, and this is not a process in which a glass substrate can be used.
[0019]
As another problem, in the method of Patent Document 1, thermal oxidation is directly performed on a semiconductor film crystallized by a catalytic element. However, in the semiconductor film crystallized by a catalytic element, The catalyst element is a silicide compound (for example, NiSi ₂ ) As a local. Since the silicide compound has a higher oxidation rate with respect to the semiconductor film, there is a problem that oxidation proceeds locally in that region, and pits (small holes) are generated in the semiconductor film at the stage of removing the thermal oxide film. The size of the pit is as large as several μm or more, and there is a case where the semiconductor layer of the TFT is disconnected due to this. Therefore, the method of Patent Document 1 has many problems as described above, and in particular, it cannot be implemented by a TFT process that uses an inexpensive and large glass substrate.
[0020]
On the other hand, when Patent Document 2 or Patent Document 3 is used, it can be confirmed that the concentration of the catalytic element in the semiconductor film can be reduced to 1/1000 or less in the temperature range in which the glass substrate can be used. The gettering ability is very good. However, it has been found that there are many problems in terms of manufacturing method and yield.
[0021]
First, problems relating to the film quality, film thickness, and formation method of the barrier layer will be described. Although the barrier layer is provided for the purpose of an etching stopper for the upper gettering film, the catalytic element moves through the barrier layer to the upper gettering film. As the barrier layer, an extremely thin oxide film is used. However, since the diffusion of the catalytic element in the oxide film is extremely slow, if the oxide film is dense and thick, the catalytic element cannot move to the upper layer. Conversely, when a porous and thin film is used, it does not function as an etching stopper, and the lower semiconductor film is etched when the upper gettering layer is etched. Since this condition is extremely difficult and requires an unstable state, it cannot be controlled with a sufficient process margin, which is a big problem in yield. Even if the conditions can be set optimally, the heat treatment conditions for the gettering movement are determined by the barrier layer (oxide film) having the slowest diffusion movement speed, and the gettering distance may be the thickness of the semiconductor film. Regardless, a long heat treatment is required.
[0022]
The second problem is that the gettering layer peels very easily. Since the underlying barrier layer is halfway as a film, it is difficult to improve the adhesion with the upper gettering layer. If there are minute holes due to peeling in the gettering layer, the etching solution etches the underlying semiconductor film, and small holes are formed in the semiconductor film, which causes a reduction in manufacturing yield. Since dust in the gettering layer also has the same effect, there is a problem in using a sputtering film with high adhesion but a lot of dust.
[0023]
A third problem is an etching residue problem in the etching of the gettering layer. Since a very high selection ratio is required between the gettering layer and the barrier layer, a strong alkaline solution that is not normally used is used as the etching solution. It has been found that the etching of the silicon film with this strong alkali is unstable, and the etching action stops when the oxidizing component increases even during the etching, or the etching rate varies greatly depending on the oscillation of the liquid. As a result, etching residues are very likely to occur in the gettering layer mainly composed of a silicon film. As a countermeasure, if the etching time is extended, the barrier layer is damaged and the underlying semiconductor layer is also etched, which cannot be solved simply by extending the etching time. If there is an etching residue of the gettering layer, the channel surface of the TFT semiconductor layer is formed by the gettering layer in that region, and normal electrical characteristics cannot be expected.
[0024]
Therefore, when the technique of Patent Document 2 or Patent Document 3 is used, even if a high-performance TFT element can be partially probabilistically manufactured, the manufacturing process margin is extremely small, resulting in a high defect rate. Therefore, it is difficult to apply these techniques to mass production of TFT elements.
[0025]
In view of the above problems, an object of the present invention is to provide a highly reliable crystalline semiconductor film in which the content of the catalytic element is sufficiently reduced, and a semiconductor device using the crystalline semiconductor film. Moreover, it aims at providing the method of manufacturing such a semiconductor film simply, without increasing a manufacturing process or manufacturing cost.
[0026]
[Means for Solving the Problems]
The semiconductor film of the present invention is a semiconductor film having a plurality of crystal domains, and the plurality of crystal domains is mainly composed of a region in which a <111> crystal zone plane of the crystal is oriented, and is formed on the surface of the semiconductor film. The height is different depending on each of the plurality of crystal domains, whereby the above object is achieved.
[0027]
In a preferred embodiment, 50% or more of the region in which the <111> crystal plane is oriented is a (110) or (211) oriented region.
[0028]
The domain diameter of the plurality of crystal domains is preferably 2 μm or more and 10 μm or less.
[0029]
In a preferred embodiment, at least a part of the semiconductor film contains a catalytic element that promotes crystallization of the amorphous semiconductor film.
[0030]
It is preferable that the catalyst element does not precipitate as a compound but exists in a state of solid solution in the semiconductor film.
[0031]
Preferably, the catalyst element is nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium ( Os), iridium (Ir), platinum (Pt), copper (Cu), and at least one element selected from the group consisting of gold (Au).
[0032]
The catalyst element is 1 × 10 ¹⁴ atoms / cm ^Three 1 × 10 or more ¹⁷ atoms / cm ^Three It is preferable to be contained in at least a part of the semiconductor film at the following concentration.
[0033]
The semiconductor film may be formed using silicon (Si) as a main component.
[0034]
In a preferred embodiment, the catalyst element promotes crystallization of the amorphous semiconductor film by forming a silicide compound.
[0035]
The thickness of the semiconductor film is preferably 25 nm or more and 80 nm or less.
[0036]
The method for producing a semiconductor film of the present invention includes (1) preparing a first semiconductor film containing a catalytic element that promotes crystallization of an amorphous semiconductor film and having a crystalline region, and (2) the first A step of providing a second semiconductor film in contact with the first semiconductor film; and (3) performing a first heat treatment on the first semiconductor film, thereby causing the catalytic element present in the first semiconductor film to be converted into the first semiconductor film. 2) moving to the semiconductor film; (4) oxidizing the second semiconductor film; and (5) removing the oxidized second semiconductor film. The above objective is achieved.
[0037]
In a preferred embodiment, the step (1) includes: (1a) preparing an amorphous semiconductor film containing the catalytic element; and (1b) performing a second heat treatment on the amorphous semiconductor film. And a step of forming the first semiconductor film.
[0038]
Preferably, the method further includes a step of removing a natural oxide film formed on the surface of the first semiconductor film between the step (1) and the step (2).
[0039]
The second semiconductor film is preferably in an amorphous state.
[0040]
The second semiconductor film preferably contains a gettering element that attracts the catalyst element.
[0041]
The gettering element may include at least one rare gas element selected from the group consisting of Ar, Kr, and Xe.
[0042]
The gettering element may include at least one element selected from the group consisting of P, As, and Sb.
[0043]
The gettering element may include at least one element selected from the group consisting of P, As and Sb, and at least one element selected from the group consisting of B and Al.
[0044]
The step (3) preferably includes a step of performing the first heat treatment while maintaining the amorphous state of the second semiconductor film.
[0045]
The step (4) may include a step of performing a third heat treatment on the second semiconductor film in an oxidizing gas atmosphere.
[0046]
The third heat treatment step may be performed in a high-pressure atmosphere exceeding 1 atm.
[0047]
The third heat treatment step may include rapid thermal annealing (RTA) in which a heated oxidizing gas is sprayed on the surface of the second semiconductor film.
[0048]
Water vapor may be used as the oxidizing gas in the third heat treatment step.
[0049]
In a preferred embodiment, the thickness of the second semiconductor film is in the range of 1/10 to 2 times the thickness of the first semiconductor film.
[0050]
In a preferred embodiment, the step (2) includes exposing the surface of the first semiconductor film to a plasma atmosphere containing hydrogen, and exposing the first semiconductor film exposed to the plasma atmosphere to the atmosphere. Forming the second semiconductor film on the first semiconductor film.
[0051]
In a preferred embodiment, in the step (4), in addition to the second semiconductor film, a part of the first semiconductor film thereunder is also oxidized, and in the step (5), the oxidized second In addition to the semiconductor film, the oxidized part of the first semiconductor film is also removed.
[0052]
In the step (4), it is preferable that the amount of dangling bonds of semiconductor atoms in the first semiconductor film is reduced.
[0053]
The first heat treatment step in the step (3) and the third heat treatment step in the step (4) may be performed continuously.
[0054]
The first heat treatment and the third heat treatment may be performed simultaneously.
[0055]
The step (5) may include a step of removing the second semiconductor film by wet etching using an acid having hydrogen fluoride.
[0056]
In a preferred embodiment, the step (1a) includes the step of forming an amorphous semiconductor film, and the step of containing the catalytic element by applying a solution containing the catalytic element to the surface of the amorphous semiconductor film. Forming a first semiconductor film.
[0057]
Preferably, the step (1a) includes a step of obtaining the amorphous semiconductor film containing the catalytic element by selectively adding the catalytic element to a part of the amorphous semiconductor film, 1b) includes a step of obtaining the first semiconductor film by laterally crystallizing the amorphous semiconductor film from a region where the catalytic element is selectively added to a peripheral portion thereof.
[0058]
As the catalytic element, nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), It is preferable to use at least one element selected from the group consisting of iridium (Ir), platinum (Pt), copper (Cu), and gold (Au).
[0059]
A step of irradiating the first semiconductor film with laser light may be performed between the step (1b) and the step (2).
[0060]
Another semiconductor film of the present invention is manufactured by the manufacturing method described above.
[0061]
The semiconductor device of the present invention is configured with the above-described semiconductor film as an active region.
[0062]
Another semiconductor device of the present invention includes a thin film transistor (TFT) having the above-described semiconductor film as an active region (semiconductor layer).
[0063]
The electronic device of the present invention includes the semiconductor device described above.
[0064]
Another electronic device of the present invention includes a display portion including a plurality of pixels, and a display signal is supplied to the plurality of pixels through the above-described semiconductor device.
[0065]
DETAILED DESCRIPTION OF THE INVENTION
In the present embodiment, a first step of preparing a first amorphous semiconductor film containing a catalytic element that promotes crystallization of the amorphous semiconductor film, and a second step in the first amorphous semiconductor film A second step of forming a crystalline semiconductor film, a third step of providing a second semiconductor film so as to be in contact with the crystalline semiconductor film, and a first heat treatment And a fourth step of moving the catalytic element present in the crystalline semiconductor film to the second semiconductor film, a fifth step of oxidizing the second semiconductor film, and an oxidized first And a sixth step of removing the second semiconductor film. Here, the crystalline semiconductor film has a reduced catalytic element concentration and can be used later for a semiconductor layer (active region) of a semiconductor device or the like. The second semiconductor film functions as the aforementioned gettering layer.
[0066]
It is preferable to include a step of removing a natural oxide film on the surface of the crystalline semiconductor film between the second step and the third step.
[0067]
That is, in this embodiment, the natural oxide film on the crystalline semiconductor film is removed without providing the barrier layer that has been a problem in the conventional method, and the second semiconductor layer is provided so as to be in contact therewith. Thereby, the problem in the barrier layer can be solved, the catalyst element can be smoothly transferred to the gettering layer (second semiconductor film), the gettering ability can be improved, and the heat treatment time for gettering can be shortened. . In addition, even when the upper second semiconductor film is formed, the adhesion with the lower layer is increased, and the condition margin where no peeling occurs is greatly expanded. Then, by oxidizing and removing the gettering layer (second semiconductor film), selective etching without unevenness can be performed, and there is a problem of etching residue that becomes a problem when etching with the above-mentioned strong alkali is used. Does not occur.
[0068]
In addition, since the catalytic element is moved to the gettering layer and the gettering layer is oxidized and removed, in the lower crystalline semiconductor film, the oxidation process after the concentration of the catalytic element in the film is sufficiently reduced Thus, the problems associated with oxidation as seen in Patent Document 1 (low gettering ability and small holes due to local oxidation of silicide) do not occur. Further, since the oxidation step is aimed not only at the reaction with the halogen element but also at the oxidation, it can be processed in a temperature range where the glass substrate can be used.
[0069]
In the present embodiment, it is desirable that the second semiconductor film acting as a gettering layer is in an amorphous state. In the fourth step, the first heat treatment is preferably performed while maintaining the amorphous state of the second semiconductor film.
[0070]
The second semiconductor film preferably contains a gettering element having an effect of attracting the catalyst element. The gettering element is, for example, one or more kinds of rare gas elements selected from Ar, Kr, and Xe. Alternatively, the gettering element may be one or more kinds of elements belonging to Group B of the periodic table selected from P, As, and Sb. Alternatively, as the gettering element, one or more kinds of periodic table group B selected from P, As, Sb and one or more kinds of periodic table group B selected from B, Al. An element belonging to can also be used together.
[0071]
The movement mechanism of the catalytic element by gettering increases the segregation coefficient of the catalytic element in the gettering layer, and moves the catalytic element from the underlying crystalline semiconductor film using the force. In the lower crystalline semiconductor film crystallized by the catalytic element, not all is present in a solid solution state in the semiconductor film, but most of the crystalline semiconductor film is precipitated as a semiconductor compound and is crystalline. The diffusion of nickel into the gettering layer is performed in the semiconductor film below the solid solubility of the catalytic element, and the semiconductor compound of the catalytic element deposited in the crystalline semiconductor film dissolves and disappears. Gettering is performed.
[0072]
As a mechanism for increasing the segregation coefficient of the catalyst element in the gettering layer at this time, an action of increasing the solid solubility in the catalyst element from the lower semiconductor film and moving the catalyst element there (first gettering action), There is an action (second gettering action) in which a defect or a local segregation site that traps the catalytic element is formed, and the catalytic element is moved and trapped there. As described above, the second gettering effect can be obtained by setting the second semiconductor film acting as a gettering layer to an amorphous state. Then, by performing the first heat treatment for the gettering movement while maintaining the amorphous state of the second semiconductor film, the gettering layer can maintain high gettering capability over the entire period of the heat treatment, As a result, the concentration of the catalytic element in the lower crystalline semiconductor layer can be further reduced. If the gettering layer is crystallized during the heat treatment, the subsequent gettering action is reduced, and the catalyst element once moved may flow backward.
[0073]
Further, the first or second gettering action can be further enhanced by adding a gettering element having a gettering effect to the second semiconductor film which is a gettering layer. At this time, it is known that the action varies depending on the type and combination of gettering elements.
[0074]
When one or more kinds of rare gas elements selected from Ar, Kr, and Xe are used as gettering elements, large interstitial distortion occurs in the place where these rare gas elements are present in the gettering layer, and defects are generated. -The second gettering action by the segregation site works very strongly. At this time, the concentration of the rare gas element contained in the gettering layer is 1 × 10 ¹⁹ atoms / cm ^Three 3 × 10 or more ^{twenty one} atoms / cm ^Three If it is within the following range, sufficient gettering efficiency can be obtained.
[0075]
Further, when one or more kinds of elements belonging to Group B of the periodic table selected from P, As, and Sb are used as the gettering element, the solid solubility of the gettering layer with respect to the catalyst element increases. That is, the gettering movement is performed using the first gettering action. Among these elements, phosphorus is particularly effective. The concentration of these impurity elements contained in the gettering layer at this time is 1 × 10 ¹⁹ atoms / cm ^Three 1 × 10 or more ^{twenty one} atoms / cm ^Three If the concentration is within the following range, sufficient gettering efficiency can be obtained.
[0076]
Further, in addition to one or more types of periodic table group 5 B selected from P, As, and Sb as gettering elements, one or more types of periodic table selected from B and Al When used together with an element belonging to Group B, it has been found that only Group 5 B element has gettering ability, but in addition to this, when Group 3 B element is also introduced, a larger gettering effect can be obtained. . If the gettering layer contains, for example, boron as well as phosphorus, the gettering mechanism changes, and in the case of only phosphorus, diffusion transfer using the difference in solid solubility of the catalytic element with the underlying crystalline semiconductor film Type gettering (the above-mentioned first gettering action), but by adding boron, the catalytic element easily precipitates in the gettering layer, and gettering to defects or segregation sites (described above) The second gettering action) becomes dominant and the effect is synergistically enhanced. The concentration of the impurity element contained in the gettering layer at this time is 1 × 10 for elements belonging to Group B of the periodic table. ¹⁹ atoms / cm ^Three 1 × 10 or more ^{twenty one} atoms / cm ^Three The following concentrations and elements belonging to Group B of the periodic table are 1.5 × 10 5 ¹⁹ atoms / cm ^Three 3 × 10 or more ^{twenty one} atoms / cm ^Three The following concentration range is desirable, and within this range, high gettering efficiency can be obtained.
[0077]
In the present embodiment, in the third step of providing the second semiconductor film serving as a gettering layer, the surface of the semiconductor film having a lower crystalline layer is exposed to a plasma atmosphere containing hydrogen, and then released into the atmosphere. It is preferable that the second semiconductor film be formed over the crystalline semiconductor film. On the surface of the lower crystalline semiconductor film, a slight natural oxide film is formed even after treatment with hydrofluoric acid due to the influence of the residence time and the like. If the gettering layer is formed in such a state, it causes peeling of the gettering layer, and the gettering efficiency is lowered. Therefore, in order to completely remove the natural oxide film, it is effective to expose it to a plasma atmosphere containing hydrogen before forming the gettering layer, whereby the natural oxide film is removed by etching. Moreover, since it is a plasma process, a gettering layer can be continuously formed without taking it out into air | atmosphere after that.
[0078]
Next, the fifth step in the present embodiment can be performed by performing a third heat treatment on the second semiconductor film in an oxidizing gas atmosphere. At this time, the third heat treatment in an oxidizing gas atmosphere is preferably performed in a high-pressure atmosphere exceeding 1 atm. Alternatively, the third heat treatment in an oxidizing gas atmosphere may be performed by rapid thermal annealing (RTA) in which a heated oxidizing gas is blown onto the surface of the second semiconductor film. Further, it is preferable to use water vapor as the oxidizing gas in the third heat treatment.
[0079]
In the present embodiment, the purpose is to oxidize and remove the second semiconductor film that is the gettering layer, so that at least the entire second semiconductor film needs to be oxidized. The thickness of the second semiconductor film in this embodiment is preferably in the range of 1/10 to 2 times the thickness of the first amorphous semiconductor film (crystalline semiconductor film). The thickness of the first amorphous semiconductor film in the present embodiment is preferably in the range of 25 nm to 80 nm from the viewpoint of crystal growth. On the other hand, if the thickness is 1/10 or more, gettering is performed. In the layer, the gettering capability required in this embodiment can be ensured. If it is twice or less, the etching damage and non-uniform film loss of the underlying crystalline semiconductor film during removal by oxidation can be suppressed to a level that causes no problem. However, more optimally, the thickness of the second semiconductor film is not less than 1/5 and not more than 1 times the thickness of the first amorphous semiconductor film, and is substantially not less than 10 nm and not more than 50 nm.
[0080]
That is, in the present embodiment, since the second semiconductor film having a certain film thickness in such a range needs to be oxidized, a so-called thermal oxidation process in which a heat treatment is performed in an oxidizing gas atmosphere is performed. desirable. However, considering the heat resistance of the glass substrate at this time, it is not possible to use a thermal oxidation method in which processing is performed at a high temperature as in the conventional method.
[0081]
In this embodiment, by performing thermal oxidation treatment in a high-pressure oxidizing gas atmosphere exceeding 1 atm, the reactivity of the oxidizing gas can be increased and thermal oxidation can be performed at a lower temperature in a shorter time. Since the speed of the oxidation reaction at this time increases in proportion to the pressure, it is desirable to set it higher. However, there is a safety problem in terms of the manufacturing apparatus, and it is in the range of 5 to 15 atmospheres. It is desirable. Further, as heat treatment conditions in this case, it is desirable that the temperature is 550 ° C. or more and 600 ° C. or less and the treatment time is about 10 minutes or more and 2 hours or less.
[0082]
As another thermal oxidation method in this embodiment, it is also effective to use rapid thermal annealing (RTA) in which a heated oxidizing gas is blown onto the surface of the second semiconductor film. In this method, the entire substrate is instantly heated to a high temperature region where oxidation reactivity is high, and the oxidizing gas heated to a high temperature is blown directly onto the surface of the gettering layer to perform necessary oxidation treatment in a short time. Yes. Thereafter, the temperature can be rapidly lowered to allow processing without causing large thermal deformation of the glass substrate. As heat treatment conditions at this time, it is desirable that the temperature is 650 ° C. or higher and 800 ° C. or lower and the treatment time is about 5 minutes or longer and 20 minutes or shorter. Further, it is desirable that both the temperature increase rate and the temperature decrease rate at this time be 100 ° C./min or more.
[0083]
In the two thermal oxidation methods of the present embodiment described above, the oxidizing gas used is required to have high oxidation reactivity, and for this reason, water vapor is most desirable. In addition, ozone gas or the like can be used.
[0084]
In the present embodiment, in the fifth step of oxidizing the second semiconductor film, in addition to the second semiconductor film, a part of the semiconductor film having a crystalline layer thereunder may be oxidized. In this case, in the sixth step of removing the oxidized second semiconductor film, in addition to the oxidized second semiconductor film, a part of the oxidized crystalline semiconductor film may be removed. it can. That is, the oxidation may partially progress not only in the second semiconductor film that is the gettering layer but also in the underlying crystalline semiconductor film. In this case, by removing the oxidized portion, not only the gettering layer but also the layer in the vicinity of the surface of the lower crystalline semiconductor film is removed, and the film thickness becomes thinner than the original.
[0085]
The gettering layer and the underlying crystalline semiconductor layer are both the same semiconductor component, and there is almost no difference in oxidation rate. As described above, by maintaining the second semiconductor film, which is a gettering layer, in an amorphous state, the difference in structure between crystalline and amorphous (the oxidation rate is higher in the amorphous state). Since it is possible to make a difference in oxidation rate to some extent by using this, such a state is useful. However, since the gettering layer is insufficiently oxidized and is not completely removed and remains on the crystalline semiconductor film, the oxidation process becomes a problem in addition to the entire second semiconductor film. From the viewpoint of the manufacturing process margin, it is desirable to advance the crystal semiconductor film to a part above the crystalline semiconductor film.
[0086]
In the present embodiment, in the fifth step of oxidizing the second semiconductor film, it is possible to reduce the amount of dangling bonds of the semiconductor atoms in the semiconductor film having the underlying crystal. That is, the oxidation process of the second semiconductor film causes an excess of semiconductor atoms in the second semiconductor film, which diffuses into the underlying crystalline semiconductor film and bonds with dangling bonds (dangling bonds). And that's why it is terminated. Thus, in this embodiment, the effect | action which improves the crystallinity of a crystalline semiconductor film can be performed combining with gettering.
[0087]
In the present embodiment, it is preferable that the first heat treatment and the third heat treatment for oxidizing the second semiconductor film are continuously performed. By doing in this way, the second and third heat treatments are substantially one-time heat treatments, not only in the merit of shortening the manufacturing process and improving the tact time of the manufacturing apparatus, but also when the steps are performed separately. In comparison, dust adhering between the processes can be eliminated, and the manufacturing yield can be improved. Furthermore, the first heat treatment and the third heat treatment for oxidizing the second semiconductor film can be performed simultaneously as one heat treatment, so that the total heat treatment time can be further reduced. Simplify the process and improve the tact time of the manufacturing equipment.
[0088]
In this embodiment, the sixth step of removing the oxidized second semiconductor film can be performed by wet etching using an acid having hydrogen fluoride. By using such a method, a high etching selection ratio can be obtained between the oxidized semiconductor film and the underlying crystalline semiconductor film, and the film loss due to overetching of the crystalline semiconductor film and the film thickness variation caused thereby can be reduced. Can be reduced. In addition, the surface of the lower crystalline semiconductor film is an important surface for forming a channel surface in the semiconductor device. However, if the wet method is used, a good state can be maintained without causing etching damage by plasma or the like.
[0089]
In the present embodiment, the first step of preparing the first amorphous semiconductor film containing the catalytic element is to form the amorphous semiconductor film and apply a solution containing the catalytic element thereon. It is preferable to carry out by. In this embodiment, the concentration of the catalytic element added to the first amorphous semiconductor surface is 1 × 10. ¹¹ atoms / cm ² 1 × 10 or more ¹⁴ atoms / cm ² Since this is a concentration that is 1/100 or less of the monoatomic layer of catalyst atoms, a very small amount of control is required. In contrast, when a first amorphous semiconductor film is prepared by applying a solution containing a catalytic element to the amorphous semiconductor film, the surface of the amorphous semiconductor film is adjusted by adjusting the concentration of the catalytic element in the solution. The concentration of the catalyst element added can be controlled with a very small amount with good control.
[0090]
In this embodiment, typically, in the first step of preparing the first amorphous semiconductor film containing the catalytic element, the catalytic element is selectively added to a part of the amorphous semiconductor film. In the second step in which the second heat treatment is performed on the amorphous semiconductor film, the crystal is grown in the lateral direction from the region where the catalytic element is selectively added to the periphery thereof. A semiconductor film having quality is obtained. In this way, in the region where the crystal is grown in the lateral direction, a good crystalline semiconductor film in which the crystal growth direction is almost uniform can be obtained, and the current drive capability of the TFT can be further enhanced. is there. Also, in this laterally grown region, the concentration of the catalytic element in the film after crystal growth can be reduced by 1 to 2 orders of magnitude compared to the region where the catalytic element is directly added, so the load on the subsequent gettering process is reduced. can do.
[0091]
Further, in the present embodiment, after the second step, a step of irradiating the crystalline semiconductor film with laser light may be performed. When the crystalline semiconductor film obtained in this embodiment is irradiated with laser light, a crystal grain boundary part or a minute residual amorphous region (uncrystallized region) due to a difference in melting point between the crystalline part and the amorphous part. Are processed intensively. A crystalline semiconductor film crystallized by introducing a catalytic element is formed of columnar crystals, and the inside thereof is in a single crystal state. A high-quality crystalline semiconductor film close to the crystalline state is obtained, and the crystallinity is greatly improved. As a result, the on-characteristics of the TFT are greatly improved, and a semiconductor device superior in current drive capability can be realized.
[0092]
Here, in this embodiment, nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium as suitable catalyst elements. One or more elements selected from (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) are used. One or more kinds of elements selected from these have an effect of promoting crystallization in a very small amount. Among them, the most remarkable effect can be obtained particularly when Ni is used. The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. The crystal structure at that time acts as a kind of template during crystallization of the amorphous silicon film, and promotes crystallization of the amorphous silicon film. Ni is two Si and NiSi ₂ Form. NiSi ₂ Shows a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ Has a lattice constant of 0.5406 nm (5.406 angstroms), which is very close to the lattice constant of 0.5430 nm (5.430 angstroms) in the diamond structure of crystalline silicon. Therefore, NiSi ₂ Is optimal as a template for crystallizing an amorphous silicon film, and it is most desirable to use Ni as the catalyst element in this embodiment.
[0093]
Next, the characteristics of the semiconductor film in this embodiment will be described. As a result of manufacturing the semiconductor film of this embodiment using such a manufacturing method, the semiconductor film of this embodiment has a semiconductor film having a region composed of a plurality of crystal domains (substantially the same crystal plane orientation region). In this case, the plane orientation of the crystal domains is mainly constituted by <111> crystal zone planes, and height differences (unevenness) occur between the crystal domains on the film surface. That is, the height of the surface of the semiconductor film differs depending on each crystal domain.
[0094]
Further, the plane orientation of the plurality of crystal domains accounts for 50% or more of the total of (110) plane orientation and (211) plane orientation among the <111> crystal zone planes. In addition, the domain diameter of the crystal domain is typically 2 μm or more and 10 μm or less.
[0095]
In the semiconductor film of this embodiment, the semiconductor film contains a catalytic element that promotes crystallization of the amorphous semiconductor film. Here, the catalyst element contained in the semiconductor film typically does not precipitate as a compound but exists in a solid solution state.
[0096]
At this time, the catalyst element contained in the semiconductor film of this embodiment is preferably nickel (Ni), iron (Fe), cobalt (Co), tin (Sn), lead (Pb), ruthenium ( One or more elements selected from the group consisting of Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu) and gold (Au) It is. Here, in the semiconductor film of this embodiment, the catalyst element is 1 × 10 6. ¹⁴ atoms / cm ^Three 1 × 10 or more ¹⁷ atoms / cm ^Three It is preferably present at the following concentrations.
[0097]
In addition, the semiconductor film of this embodiment can be formed from a material containing silicon (Si) as a main component. Further, the catalyst element compound may be silicide.
[0098]
In addition, the thickness of the semiconductor film of the present embodiment is preferably in the range of 25 nm or more and 80 nm or less.
[0099]
In general, in crystallization without using a catalytic element, the plane orientation of the crystalline semiconductor film is (100) due to the influence of the insulator underlying the semiconductor film (particularly in the case of amorphous silicon dioxide) or the influence of the semiconductor film surface. Or it is easy to turn to (111). On the other hand, FIG. 7A shows a schematic diagram at the time of crystallization when a catalyst element is added to the amorphous semiconductor film to be crystallized. In FIG. 7A, 61 is a base insulator, 62 is an amorphous semiconductor film in an uncrystallized region, 63 is a crystalline semiconductor film, and 64 is a semiconductor compound of a catalytic element serving as a driving force for crystal growth. is there. As shown in FIG. 7A, the catalyst element compound 64 is present at the forefront of crystal growth, and the adjacent amorphous regions 62 are crystallized one after another toward the right side of the drawing. The catalytic element compound 64 has a property of growing strongly in the <111> direction. As a result, as the plane orientation of the obtained crystalline semiconductor film, a <111> crystal zone plane appears as shown in FIG.
[0100]
Further, the crystal structure at this time is composed of a plurality of columnar crystals with the catalytic element compound positioned at the tip, and the cross-sectional shape of each columnar crystal is 80 nm square in a stress-free state. That is, when the film thickness of the semiconductor film is 80 nm or less, it is composed of a single-layer columnar crystal in the film thickness direction, but when it is more than that, the crystal has a two-layer structure and the crystallinity is deteriorated. Therefore, the thickness of the semiconductor film is desirably 80 nm or less. Conversely, it has been found that when the thickness of the semiconductor film is extremely thin (25 nm or less), crystal growth hardly occurs.
[0101]
FIG. 7B shows the <111> crystal zone plane. In FIG. 7B, the horizontal axis represents the inclination angle from the (-100) plane, and the vertical axis represents the surface energy. The group 65 is a crystal plane that becomes a <111> crystal zone plane. The (100) plane and the (111) plane are not <111> crystal zone planes, but are shown for comparison. FIG. 7C shows a standard triangle of crystal orientation. Here, the distribution of the <111> crystal zone plane is as shown by a broken line. The numbers are typical pole indices. Among these <111> crystal zone planes, in the crystalline semiconductor film obtained in this embodiment, the (110) plane or (211) plane is predominantly oriented, and these planes occupy 50% or more of the entire plane. An advantage can be obtained. These two crystal planes have a very high hole mobility compared to the other planes, can improve the performance of P-channel TFTs that are inferior to N-channel TFTs, and are easily balanced in semiconductor circuits. There are benefits.
[0102]
FIG. 8 shows the plane orientation distribution of the crystalline semiconductor film obtained by this embodiment. FIG. 8 shows the result of EBSP (Electron Back Scattered Diffraction Pattern) measurement, in which the crystal orientation is specified for each minute region, and these are connected and mapped. FIG. 8A shows a plane orientation distribution in the crystalline semiconductor film of the present embodiment. FIG. 8B shows the relationship between adjacent mapping points based on the data in FIG. Those with a plane orientation tilt angle of a certain value or less (here, 5 ° or less) are painted with the same color to highlight the distribution of individual crystal domains. FIG. 8C shows a standard triangle having the crystal orientation described above with reference to FIG. As can be seen from FIG. 8 (C), the crystalline semiconductor film according to the present embodiment generally exhibits a plane orientation on the <111> crystal zone plane, and is particularly strongly oriented in (110) and (211). I can see that In this embodiment, the nucleation density is increased by the action of the rare gas element contained in the semiconductor film, and the size of each crystal domain (substantially the same plane orientation region) shown in FIG. 8B is 2 μm or more. It is distributed in the range of 10 μm or less.
[0103]
Here, in the semiconductor film of the present embodiment, a gettering layer is present in the upper layer, and gettering is performed by oxidizing and removing it. At this time, as described above, it is difficult to selectively oxidize and remove only the upper gettering layer, and the surface layer side of the lower crystalline semiconductor film is also partially oxidized and removed together. It is preferable from the viewpoint of margin. Therefore, also in the semiconductor film of this embodiment, it is desirable that the film surface is oxidized and removed to some extent. At this time, in the crystalline semiconductor film, since the oxidation rate varies depending on the plane orientation, a difference in oxidation rate occurs between crystal domains in the same plane region. As a result, in the semiconductor film of this embodiment, the amount of oxidation differs between crystal domains on the film surface. Then, after it is removed, a difference in level (unevenness) occurs between each crystal domain, which is one of the characteristics of the semiconductor film of this embodiment. The height difference between the domains at this time varies depending on how much the surface layer of the crystalline semiconductor film is oxidized (how much manufacturing margin is taken), but is preferably in the range of 1 nm to 20 nm.
[0104]
In addition, since the semiconductor film of this embodiment is obtained by introducing and crystallizing a catalytic element into an amorphous semiconductor film, the concentration of the catalytic element in the semiconductor film is completely obtained even if gettering is performed. However, there is a slight remaining catalyst element. However, it is the catalytic element semiconductor compound that has a negative effect on the electrical characteristics of the semiconductor device and that has become a nucleus during crystal growth and has driven crystal growth. Although these semiconductor compounds are segregated locally, the semiconductor film obtained in this embodiment is contained in the film by being dissolved and moved in the crystalline semiconductor film by gettering. The catalytic element does not precipitate as a compound but exists in a solid solution state. The concentration of the catalytic element in the semiconductor film at this time is 1 × 10 ¹⁴ atoms / cm ^Three 1 × 10 or more ¹⁷ atoms / cm ^Three 1 × 10 ¹⁷ atoms / cm ^Three The following does not cause the deposition of the semiconductor compound of the catalytic element that adversely affects the electrical characteristics of the semiconductor device. 1 × 10 ¹⁴ atoms / cm ^Three However, this is the lower limit at which the catalyst element concentration can be reduced by the gettering process.
[0105]
Hereinafter, embodiments of a semiconductor film and a manufacturing method thereof according to the present invention will be described with reference to FIG.
[0106]
(First embodiment)
Here, a method for manufacturing a semiconductor film according to the present invention over a glass substrate will be described. The semiconductor thin film of this embodiment can be used for an active region of a TFT, a PN junction diode, or the like. FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor thin film described here, and the manufacturing process sequentially proceeds in the order of (A) → (G).
[0107]
In FIG. 1A, a low alkali glass substrate or a quartz substrate can be used for the substrate 101. In this embodiment, a low alkali glass substrate is used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 ° C. to 20 ° C. than the glass strain point. A base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 on which the semiconductor film is formed in order to prevent impurity diffusion from the substrate 101. In the present embodiment, for example, a silicon oxynitride film produced from a material gas of SiH 4, NH 3, and N 2 O by plasma CVD is formed as a lower first base film 102, and similarly, plasma CVD is used thereon. A second base film 103 was stacked using SiH4 and N2O as material gases. At this time, the thickness of the silicon oxynitride film of the first base film 102 is 25 nm to 200 nm (for example, 100 nm), and the thickness of the silicon oxynitride film of the second base film 103 is 25 nm to 300 nm (for example, 100 nm). ). In this embodiment, a two-layer base film is used, but a single-layer structure including only a silicon oxide film can also be used.
[0108]
Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 104 having a thickness of 25 nm to 80 nm (for example, 50 nm) is formed by plasma CVD. In this embodiment, a multi-chamber parallel plate type plasma CVD apparatus is used, and the first base film 102, the second base film 103, and the a-Si film 104 are continuously formed without being exposed to the atmosphere. Filmed. By doing in this way, contamination and dust adhesion at the film interface can be suppressed as much as possible. Of course, the formation of the base films 102 and 103 and the a-Si film 104 is not limited to the above-described plasma CVD method, and other known methods such as a thermal CVD method and a sputtering method can also be used. In addition, as a semiconductor film, it is desirable to use a film containing silicon as a main component from the viewpoint of easy handling and characteristics as a semiconductor device, but a germanium film or the like can also be used. The thickness of the a-Si film 104 is preferably in the range of 25 nm to 80 nm from the viewpoint of crystal growth.
[0109]
Subsequently, a catalytic element is added to the a-Si film 104 and heat treatment is performed. An aqueous solution (nickel acetate aqueous solution) containing, for example, 10 ppm catalyst element (in this embodiment, nickel) in terms of weight is applied to the a-Si film by a spin coating method to form the catalyst element-containing layer 105. The catalyst element usable here is selected from the group consisting of nickel (Ni), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), iron (Fe), and copper (Cu). One or more elements are preferred. In addition, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and the like can be used. Prior to this step, the surface of the a-Si 104 may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 104 during spin coating.
[0110]
In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (in this embodiment, a nickel film) is deposited on the a-Si film 104 by vapor deposition or sputtering. You may take the means to form. This state corresponds to the state shown in FIG. When the nickel concentration on the surface of the a-Si 104 added in the state shown in FIG. 1A is measured by the total reflection X-ray fluorescence analysis (TRXRF) method, 5 × 10 5 is obtained. ¹² atoms / cm ² It was about. At this time, the concentration of nickel added to the surface of the a-Si film is 1 × 10 10 whatever the addition method is used. ¹¹ atoms / cm ² 1 × 10 or more ¹⁴ atoms / cm ² The following is desirable. Since this concentration is 1/100 or less of the nickel monoatomic layer, the added nickel is discretely present on the a-Si film and is not actually in a film state.
[0111]
Then, the second heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment, it is preferable to perform the annealing treatment under conditions where the temperature is 530 ° C. or higher and 620 ° C. or lower and the heating time is 30 minutes or longer and 8 hours or shorter. In this embodiment, as an example, heat treatment was performed at 580 ° C. for 1 hour. In this heat treatment, the nickel 105 added to the surface of the a-Si film is first diffused into the a-Si film 104, and then agglomerates to cause silicidation, which is used as a nucleus for the a-Si film 104. The crystallization proceeds. As a result, the a-Si film 104 is crystallized to become a crystalline silicon film 104a. Here, the heat treatment is performed using a general furnace, but an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source, an RTA apparatus by inserting a substrate into the furnace in a single wafer, The heat treatment may be performed using an RTA apparatus or the like that blows a heated inert gas onto the substrate surface. When such an RTA method is used, it is preferable to perform heat treatment at a temperature of 650 ° C. to 750 ° C. for 30 seconds to 10 minutes. When the crystal plane orientation of the crystalline silicon film 104a thus obtained is examined by EBSP measurement, it is mainly composed of <111> crystal zone planes, and among these, (110) plane orientation and (211) plane orientation are particularly important. In this, more than 50% of the total area is occupied. Moreover, the domain diameter of the crystal domain (substantially the same plane orientation region) is 2 μm or more and 10 μm or less. This state corresponds to FIG.
[0112]
Subsequently, as shown in FIG. 1C, the crystalline silicon film 104a obtained by the heat treatment is irradiated with a laser beam 106, whereby the crystalline silicon film 104a is further recrystallized to improve crystallinity. The formed crystalline silicon film 104b is formed. As the laser light at this time, an XeCl excimer laser (wavelength 308 nm) or a KrF excimer laser (wavelength 248 nm) can be applied. The beam size of the laser light at this time is shaped to be a long shape on the surface of the substrate 101, and the entire surface of the substrate is recrystallized by sequentially scanning in the direction perpendicular to the long direction. . At this time, scanning is performed so that parts of the beams overlap each other, so that laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 104a, thereby improving uniformity. If the energy of the laser beam at this time is too low, the crystallinity improving effect is small, and if it is too high, the crystalline state of the crystalline silicon film 104a obtained in the previous step is lost, so it is necessary to set it within an appropriate range. There is. As a laser that can be used at this time, a pulse oscillation type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser, or YVO 4 laser can be used. The practitioner may select the crystallization conditions as appropriate.
[0113]
In this embodiment, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used. The laser light irradiation conditions are a nitrogen atmosphere and an energy density of 300 mJ / cm. ² 500 mJ / cm ² The following (for example, 420 mJ / cm ² ). Further, the beam size was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 101, and scanning was sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. That is, a total of 20 times of laser irradiation are performed at an arbitrary point of the crystalline silicon film 104a.
[0114]
In this way, the crystalline silicon film 104a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 104b. Even after this laser irradiation step, the crystal plane orientation and crystal domain state before laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement.
[0115]
Next, after washing the crystalline silicon film 104b with an acid containing hydrogen fluoride and removing the natural oxide film on the surface, the crystalline silicon film 104b is directly in contact with the crystalline silicon film 104b as shown in FIG. A gettering layer 107 is formed. At this time, since the natural oxide film may be re-formed on the surface of the crystalline silicon film 104b after the cleaning with hydrofluoric acid, the gettering layer 107 can be formed promptly after the cleaning with hydrofluoric acid. desirable. If a natural oxide film of a certain degree or more exists on the crystalline silicon film 104b, it causes peeling of the gettering layer 107 and the gettering efficiency is lowered.
[0116]
Here, the gettering layer 107 is preferably in an amorphous state and preferably contains an element having a gettering effect. In this embodiment, several typical methods for forming the gettering layer 107 will be described. First, when an a-Si film containing a rare gas element (Ar in this embodiment) is used as the gettering layer 107, a sputtering method or a plasma CVD method can be used. In the case of the sputtering method, an amount of Ar necessary for gettering can be contained by using a silicon target and setting the sputtering gas to Ar. In plasma CVD, SiH _Four Using gas and Ar gas as materials, the Ar concentration in the a-Si film to be formed increases in the direction of decreasing both the film formation temperature and the film formation pressure. In order to further increase the Ar concentration, Ar elements can be easily included in the a-Si film by using a dual bias or dual frequency plasma CVD apparatus in which another bias is also applied to the substrate side. In this embodiment, as an example, a general plasma CVD apparatus is used, a film formation temperature is set to 250 ° C., a film formation pressure is set to about 20 Pa, and an a-Si film containing Ar with a thickness of 20 nm is formed. The Ar concentration in the a-Si film at this time is 5 × 10 ¹⁹ atoms / cm ^Three It was about. In addition to Ar, Kr and Xe can be used similarly. The concentration of these rare gas elements contained in the gettering layer is 1 × 10 ¹⁹ atoms / cm ^Three 3 × 10 or more ^{twenty one} atoms / cm ^Three It is preferable to be within the following range.
[0117]
Second, when an a-Si film containing an element belonging to Group B of the periodic table (P in this embodiment) is used as the gettering layer 107, a plasma CVD method is used, and silane (SiH _Four ) And phosphine (PH _Three ) As a material gas, an a-Si film containing P can be easily obtained. At this time, the content of P in the a-Si film is PH. _Three Gas and SiH _Four It can be controlled by the flow rate ratio with gas. In addition to P, As and Sb can be used, and the concentration of these elements contained in the gettering layer is 1 × 10 ¹⁹ / Cm ^Three 1 × 10 or more ^{twenty one} / Cm ^Three It may be within the following range.
[0118]
Third, the gettering layer 107 contains both elements belonging to Group B of the periodic table (P in the present embodiment) and elements belonging to Group B of the periodic table (B in the present embodiment). By using the a-Si film to be obtained, the gettering capability is further enhanced. In this case, plasma CVD is used, and diborane (B ₂ H ₆ ). And PH _Three Gas and SiH _Four Gas and B ₂ H ₆ Similarly, the contents of P and B in the a-Si film can be controlled by the flow ratio with the gas. At this time, in addition to B, Al can be used, and the concentration of these elements contained in the gettering layer is 1.5 × 10 5. ¹⁹ / Cm ^Three 3 × 10 or more ^{twenty one} / Cm ^Three It may be within the following range.
[0119]
Before the gettering layer 107 is formed, it is desirable that the surface of the crystalline silicon film 104b be subjected to plasma treatment in an atmosphere containing hydrogen and then continuously formed. When a gettering layer is formed by a plasma CVD apparatus as in this embodiment, hydrogen plasma treatment can be easily performed by simply switching the material gas, and then the gettering layer is continuously exposed without being exposed to the atmosphere. A film can be formed.
[0120]
Further, the film thickness of the gettering layer 107 is desirably in the range of 1/10 to 2 times the film thickness of the crystalline silicon film 104b, and optimally 1/5 to 1 times. In this embodiment, since the film thickness of the crystalline silicon film is 50 nm, the thickness of the gettering layer is preferably 5 nm or more and 100 nm or less, and particularly preferably 10 nm or more and 50 nm or less. In the present embodiment, the thickness of the gettering layer 107 is 20 nm.
[0121]
Then, this is subjected to a first heat treatment in an inert atmosphere. As a heat treatment method at this time, general furnace annealing and rapid thermal annealing (RTA) can be used. At this time, in the case of furnace annealing, the temperature is 500 ° C. or more and 600 ° C. or less and is 15 minutes or more and 4 hours or less. In the case of RTA, in this embodiment, the temperature is 600 ° C. or more and 750 ° C. or less and is about 30 seconds or more and 15 minutes or less. The heat treatment may be performed. In this embodiment, for example, the RTA process is performed in a nitrogen atmosphere. As RTA conditions at this time, the substrate is preheated to about 400 ° C., and then heated at a rate of temperature increase of 50 ° C./min to 300 ° C./min. Went. In the present embodiment, the RTA treatment of the above temperature profile is realized by providing a temperature gradient in the furnace using a resistance heating furnace and controlling the speed at which the substrate is inserted into the furnace. At this time, the substrates are processed one by one, and during the process, nitrogen gas heated at a high temperature is uniformly sprayed on the surface of the substrate 101, so that a high temperature increase rate and temperature increase that cannot be obtained only by thermal radiation are performed. The thermal uniformity within the substrate surface is obtained.
[0122]
FIG. 9 shows the configuration of the RTA apparatus used in this embodiment. A heater 803 is installed for each zone above the quartz tube 802. Reference numeral 804 denotes a quartz shower plate, and 805 denotes a substrate stage. The substrate stage 805 supports the substrate 801 with pin support so that heat exchange from the substrate is eliminated and instantaneous heating can be performed only with the heat capacity of the substrate 801. The substrate stage 805 is supported by a column flange 806 and is heated by moving it up and down as indicated by an arrow 809. Reference numeral 807 denotes an O-ring for sealing the chamber. Nitrogen gas 808 is introduced from the upper part of the quartz tube, is diffused and heated in a reservoir on the shower plate 804, and is uniformly sprayed on the surface of the substrate 801 through the shower plate. The raising / lowering speed of the substrate 801 is controlled by the vertical speed of the substrate stage (indicated by an arrow 809).
[0123]
By this heat treatment, the nickel in the crystalline silicon film 104b under the gettering layer 107 is moved upward as indicated by an arrow 108 in FIG. In this gettering step, first, nickel dissolved in the crystalline silicon film 104b moves to the gettering layer 107, so that the nickel concentration in the silicon film is lowered and Ni silicide precipitated in the film. Is performed by dissolving in the silicon film. These also move to the gettering layer 107 in a solid solution state, Ni silicide in the crystalline silicon 104b disappears, the concentration of nickel in the solid solution state is reduced, and the crystalline silicon film 104c is obtained. As a result, the nickel concentration of the crystalline silicon film 204c was measured by secondary ion mass spectrometry (SIMS) and found to be 5 × 10. ¹⁵ atoms / cm ^Three It was reduced to the extent that it was almost the lower limit of measurement. Here, the nickel remaining in the crystalline silicon film 104c is not in a silicide state but exists in a solid solution state as interstitial nickel.
[0124]
Subsequently, as shown in FIG. 1F, the gettering layer 107 is oxidized by heat treatment in an oxidizing gas atmosphere to form a silicon oxide film 109. As the oxidation treatment at this time, heat treatment in a relatively high-pressure oxidizing gas atmosphere exceeding 1 atm, or RTA treatment in which heated oxidizing gas is sprayed on the surface of the gettering layer 107 can be used. As the oxidizing gas at this time, water vapor is optimal from the viewpoint of high oxidation reactivity and safety. In the former method, the inside of the furnace may be pressurized with water vapor in a range of 5 to 15 atmospheres, and heat treatment may be performed at 550 ° C. to 600 ° C. for about 10 minutes to 2 hours. In the latter method, water vapor gas heated to a high temperature may be directly sprayed on the surface of the gettering layer, and RTA treatment may be performed at 650 ° C. to 800 ° C. for about 5 minutes to 20 minutes. It is desirable that both the temperature increase rate and the temperature decrease rate at this time be 100 ° C./min or more.
[0125]
In this embodiment, the gettering layer 107 is oxidized using the RTA apparatus shown in FIG. From the state where the introduced gas 808 is water vapor and the substrate is preheated to about 400 ° C., the temperature is raised at a rate of 100 ° C./min to 300 ° C./min, for example, heat treatment is performed at a temperature of 720 ° C. for 10 minutes. It was. As a result, the gettering layer 107 having a thickness of 20 nm is oxidized and becomes a silicon oxide film 109. At this time, the surface layer of the lower crystalline silicon film 104c was oxidized by about 10 nm, so that a crystalline silicon film 104d having a thickness of 40 nm was obtained. Further, during this step, oxidation of part of the surface layer of the gettering layer 107 and the crystalline silicon film 104c generates excess silicon atoms, which diffuse into the crystalline silicon film 104c and cause dangling bonds (dangs). It is terminated by bonding with a ring bond. As a result, the obtained crystalline silicon film 104d has a reduced defect density and higher crystallinity. Further, the surface of the crystalline silicon film 104d has unevenness between crystal domains due to the difference in oxidation rate depending on the crystal orientation, and the difference in height is about 2 nm or more and 5 nm or less.
[0126]
In the present embodiment, the heat treatment for gettering in the nitrogen atmosphere and the oxidation treatment with water vapor can be performed continuously using the apparatus shown in FIG. 9, which is effective. At this time, continuous processing can be easily performed by continuously switching from nitrogen gas to water vapor gas during RTA processing. Also, for oxidation in a high-pressure atmosphere, continuous treatment with gettering heat treatment is possible by switching the atmosphere gas in the same manner. Furthermore, by optimizing the heating conditions, gettering and oxidation can be performed simultaneously / continuously by heat treatment in a steam atmosphere.
[0127]
Then, the silicon oxide film 109 is entirely removed by etching. As an etchant at this time, a sufficiently low-layer crystalline silicon film 104d and 1: 100 buffered hydrofluoric acid (BHF) having etching selectivity were used and wet etching was performed.
[0128]
Through the above steps, a semiconductor film (crystalline silicon film) 104d according to the present invention is obtained as shown in FIG.
[0129]
FIG. 2A is a schematic plan view of a semiconductor film obtained by the method described above. As shown in FIG. 2A, the semiconductor film has a plurality of domains 10. Each domain 10 is in contact with an adjacent domain at a domain boundary 11.
[0130]
FIG. 2B is a cross-sectional view taken along the line AA ′ of the semiconductor film in FIG. In FIG. 2B, a base film 15 and a semiconductor film 16 are sequentially stacked over the substrate 12. Here, the base film 15 includes a first base film 13 and a second base film 14 (both are silicon oxynitride films). As can be seen from FIG. 2B, each domain 10 has a different surface height, and thus the surface of the semiconductor film 16 has irregularities corresponding to the shape of the domain 10. The reason why the surface height differs for each domain is that the oxidation rate differs depending on the crystal orientation as described above.
[0131]
(Second Embodiment)
Next, a second embodiment of the present invention will be described. The present embodiment is an n-channel TFT using the semiconductor thin film (crystalline silicon film) produced in the first embodiment described above and a method for producing it on a glass substrate. The TFT of this embodiment can be used as an element constituting a thin film integrated circuit as well as a driver circuit and a pixel portion of an active matrix type liquid crystal display device or an organic EL display device. FIG. 3 is a cross-sectional view showing a manufacturing process of the n-channel TFT described here, and the manufacturing process sequentially proceeds in the order of (A) → (E).
[0132]
FIG. 3A shows a state in which the crystalline silicon film 204d is manufactured by a method similar to the method described in the first embodiment, and corresponds to FIG. 1G of the first embodiment. That is, a silicon oxynitride film is formed as the first base film 202 on the glass substrate 201, and a silicon oxide film is formed as the second base film 203 thereon. A crystalline silicon film 204d produced according to the first embodiment is formed.
[0133]
Then, unnecessary portions of the crystalline silicon film 204d are removed to perform element isolation. By this step, as shown in FIG. 3B, an island-shaped semiconductor layer 210 that will later become an active region (source / drain region, channel region) of the TFT is formed.
[0134]
Next, a silicon oxide film having a thickness of 20 to 150 nm (here, 100 nm) is formed as the gate insulating film 211 so as to cover the semiconductor layer 210. Here, the silicon oxide film is formed using TEOS (Tetra Ethoxy Ortho Silicate) as a raw material and using an RF plasma CVD method at a substrate temperature of 150 ° C. to 600 ° C., preferably 300 ° C. to 450 ° C. together with oxygen. . Alternatively, TEOS as a raw material may be formed at a substrate temperature of 350 ° C. or higher and 600 ° C. or lower, preferably 400 ° C. or higher and 550 ° C. or lower by low pressure CVD or atmospheric pressure CVD together with ozone gas. After film formation, annealing is performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics of the crystalline silicon film / gate insulating film. May be.
[0135]
Subsequently, a conductive film is deposited on the gate insulating film 211 using a sputtering method, a CVD method, or the like, and this is patterned to form a gate electrode 212. As the conductive film, various materials such as a metal film, a refractory metal film, a low-resistance semiconductor film, and the like can be used. In this embodiment, an aluminum film (containing 1% scandium) having a thickness of 400 to 800 nm, for example, 500 nm is formed by sputtering and patterned to form the gate electrode 212. High temperature resistance is improved by mixing trace amounts of elements such as scandium, titanium, and silicon into the aluminum film. Here, when the TFT in this embodiment is applied as a pixel TFT of a liquid crystal display device or the like, the gate electrode 212 forms a gate bus line at the same time in a plan view.
[0136]
Then, as shown in FIG. 3C, a low-concentration impurity (phosphorus) 213 is implanted into the semiconductor layer 210 by an ion doping method using the gate electrode 212 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² ~ 1x10 ¹⁴ cm ^-2 For example 8 × 10 ¹² cm ^-2 And Through this process, in the semiconductor layer 210, a low concentration phosphorus 213 is implanted into a region 214 that is not covered with the gate electrode 212, and a region that is masked by the gate electrode 212 and is not implanted with phosphorus 213 later becomes a channel region 215 of the TFT. Become.
[0137]
Subsequently, as shown in FIG. 3D, a doping mask 216 made of a photoresist is provided so as to largely cover the gate electrode 212. Thereafter, an impurity (phosphorus) 217 is implanted into the semiconductor layer 210 at a high concentration by ion doping using the resist mask 216 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 8x10 ¹⁵ cm ^-2 For example 2 × 10 ¹⁵ cm ^-2 And By this step, the region where the impurity (phosphorus) 217 is implanted at a high concentration later becomes the source / drain region 218 of the TFT. In the semiconductor layer 210, a region covered with the resist mask 216 and not doped with high-concentration phosphorus 217 remains as a region into which low-concentration phosphorus is implanted, thereby forming an LDD (Lightly Doped Drain) region 219. . In this manner, by forming the LDD region 219, electric field concentration at the junction between the channel region and the source / drain region can be alleviated, leakage current at the time of TFT off operation can be reduced, and deterioration due to hot carriers can be suppressed. And the reliability of the TFT can be improved.
[0138]
Note that even if the LDD region 219 is left in a non-doped (intrinsic) state without doping with low concentration of phosphorus in FIG. 3C, a so-called offset gate structure is formed, and the leakage current during the TFT off operation is the same as in the LDD structure. Can be reduced and hot carrier resistance can be improved. However, in this case, since the resistance of the offset portion 219 becomes larger, the on-current value of the TFT is lower than that of the LDD structure. As a method for forming such an LDD structure or offset gate structure, in addition to the method using a resist mask as described above, the surface of the aluminum electrode is anodized to form an oxide layer on the surface, and the oxidation is performed. The above structure can also be formed by utilizing the thickness (width) of the physical layer. In addition, an insulating film or the like is formed on the gate electrode and etched back, whereby a sidewall can be formed on the side wall of the gate electrode and used. In this embodiment, the LDD region 219 is formed outside the gate electrode 212. However, the LDD region 219 may be formed so as to partially overlap the gate electrode (GOLD structure; Gate Overlapped LDD). This is particularly effective for suppressing hot carrier deterioration.
[0139]
Then, after removing the photoresist 216 used as a mask for doping, annealing is performed by laser beam irradiation from above the substrate to activate the ion-implanted impurity, and at the same time, the crystallinity is improved in the impurity introduction step. Improve the crystallinity of the deteriorated part. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) is used as the laser to be used, and the energy density is 200 to 450 mJ / cm. ² , Preferably 250 to 350 mJ / cm ² Irradiation was performed. At this time, the channel region 215 is not irradiated with laser light because the upper gate electrode 212 serves as a mask to block the laser light. The sheet resistance of the N-type impurity (phosphorus) region 218 formed in this manner was 200 to 500 Ω / □, and the sheet resistance of the LDD region 219 into which phosphorus was implanted at a low concentration was 30 to 50 kΩ / □.
[0140]
Here, the activation of impurities is performed by laser irradiation, but an RTA apparatus using a lamp or the like as a heat source, an RTA apparatus by inserting a substrate into a furnace in a single wafer, an inert gas heated to a high temperature, An RTA apparatus that sprays on the substrate surface may be used. When such an RTA method is used, it is preferable to carry out the heating at a temperature of 600 ° C. to 650 ° C. for about 30 seconds to 2 minutes because of the heat resistance of aluminum.
[0141]
Subsequently, as shown in FIG. 3E, a silicon oxide film or a silicon nitride film having a thickness of about 400 nm to 1000 nm is formed as the interlayer insulating film 220. When a silicon oxide film is used, it is possible to form TEOS as a raw material by using a plasma CVD method with oxygen, a low pressure CVD method with ozone, or an atmospheric pressure CVD method, and a good interlayer insulation with excellent step coverage. A membrane is obtained. SiH _Four And NH _Three If a silicon nitride film formed by a plasma CVD method is used as a source gas, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and there is an effect of reducing dangling bonds that degrade TFT characteristics.
[0142]
Next, a contact hole is formed in the interlayer insulating film 220, and a TFT electrode / wiring 221 is formed of a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. When this TFT 222 is used as a pixel TFT, it is an element for switching the pixel electrode, and therefore, the other drain electrode is provided with a pixel electrode made of a transparent conductive film such as ITO. In this case, the other electrode constitutes a source bus line, a video signal is supplied via the source bus line, and a necessary charge is written to the pixel electrode based on the gate signal of the gate bus line 212. Further, the TFT can be easily applied to a thin film integrated circuit or the like. In that case, a contact hole may be formed on the gate electrode 212 and necessary wiring may be provided.
[0143]
Finally, annealing is performed at 350 ° C. for 1 hour in a nitrogen atmosphere or a hydrogen atmosphere to complete the TFT 222 shown in FIG. Furthermore, if necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT for the purpose of protecting the TFT 222.
[0144]
The TFT manufactured according to the above embodiment has a field effect mobility of 300 cm. ² / Vs and the threshold voltage of about 1.5 V, despite the extremely high performance, the abnormal increase in leakage current during TFT OFF operation, which was a problem in the conventional example, is suppressed, and the threshold voltage is about 0.1 V per unit W. A very low value of several pA or less was stably shown. This value is completely different from that of a conventional TFT prepared without using a catalyst element, and the production yield can be greatly improved. In addition, even when repeated measurements and durability tests with bias and temperature stress were performed, the characteristics were hardly deteriorated and the reliability was very high compared to the conventional one.
[0145]
Further, when the TFT manufactured according to the present embodiment is applied to the pixel TFT of the active matrix substrate for liquid crystal display as a dual gate structure, the display unevenness is obviously smaller than that manufactured by the conventional method, and due to TFT leakage. A liquid crystal panel with high display quality and a high contrast ratio with very few pixel defects was obtained.
[0146]
(Third embodiment)
A third embodiment according to the present invention will be described. This embodiment is a circuit having a CMOS structure using the semiconductor thin film (crystalline silicon film) produced in the first embodiment and a process for producing the circuit on a glass substrate. The circuit of the CMOS structure of the present embodiment is configured by complementing a peripheral driving circuit of an active matrix type liquid crystal display device and an n-channel TFT and a p-channel TFT forming a general thin film integrated circuit. .
[0147]
FIG. 4 is a cross-sectional view showing a manufacturing process of a TFT described in this embodiment, and the process proceeds in order from FIG. 4A to FIG. 4F.
[0148]
FIG. 4A shows a state in which the crystalline silicon film 304d is manufactured according to the method described in the first embodiment, and corresponds to FIG. 1G of the first embodiment. That is, a silicon oxynitride film is formed as the first base film 302 on the glass substrate 301, and a silicon oxide film is formed as the second base film 303 thereon. A crystalline silicon film 304d produced according to the first embodiment is formed.
[0149]
Next, an unnecessary portion of the crystalline silicon film 304d is removed, and element isolation is performed. By this step, as shown in FIG. 4B, an island-like crystalline silicon film (semiconductor layer) 310n that will later become an active region (source / drain region, channel region) of an n-channel TFT and a p-channel TFT. And 310p are formed.
[0150]
Here, boron as an impurity element imparting p-type at a concentration of about 1 × 10 16 to 5 × 10 17 / cm 3 for the purpose of controlling the threshold voltage over the entire surface of the semiconductor layer of the n-channel TFT and the p-channel TFT. (B) may be added. Boron (B) may be added by an ion doping method, or may be added at the same time when an amorphous silicon film is formed.
[0151]
Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as a gate insulating film 311 so as to cover the semiconductor layers 310n and 310p. In the formation of the silicon oxide film, here, TEOS was used as a raw material, and it was decomposed and deposited by RF plasma CVD with oxygen at a substrate temperature of 300 to 450 ° C. As the gate insulating film 311, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0152]
Subsequently, a conductive film is deposited and patterned to form gate electrodes 312n and 312p. In the present embodiment, a refractory metal film is formed by a sputtering method as the conductive film. The refractory metal at this time is an element selected from tantalum (Ta) or tungsten (W), molybdenum (Mo) titanium (Ti), an alloy containing the above elements as a main component, or an alloy combining the above elements. A film (typically, a Mo—W alloy film or a Mo—Ta alloy film) may be used. Further, tungsten silicide, titanium silicide, or molybdenum silicide may be applied as another alternative material. In this embodiment, tungsten (W) is used and the thickness is set to 300 to 600 nm, for example, 450 nm. At this time, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance, and by setting the oxygen concentration to 30 ppm or less, a specific resistance value of 20 μΩcm or less could be realized.
[0153]
Next, as shown in FIG. 4C, a low concentration impurity (phosphorus) 313 is implanted into the semiconductor layer by the ion doping method using the gate electrodes 312n and 312p as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² ~ 1x10 ¹⁴ cm ^-2 For example 2 × 10 ¹³ cm ^-2 And By this step, in the semiconductor layers 310n and 310p, regions not covered with the gate electrodes 312n and 312p become regions 314n and 314p into which low-concentration phosphorus 313 has been implanted, and are masked by the gate electrodes 312n and 312p, and impurities 313 are not implanted. The regions will later become channel regions 315n and 315p of n-channel TFTs and p-channel TFTs.
[0154]
Next, as shown in FIG. 4D, in the later n-channel TFT, a doping mask 316n made of photoresist is provided so as to cover the gate electrode 312n so as to be slightly larger, and in the later p-channel TFT, the semiconductor A photoresist doping mask 316p is provided so as to cover the entire layer 310p. Thereafter, an impurity (phosphorus) 317 is implanted at a high concentration into the semiconductor layer by ion doping using the resist masks 316n and 316p as a mask. At this time, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 5 × 10 ¹⁵ cm ^-2 And By this process, in the n-channel TFT semiconductor layer 310n, the region into which the impurity (phosphorus) 317 is implanted at a high concentration later becomes the source / drain region 318 of the n-channel TFT and is covered with the resist mask 316n. The region where the high concentration phosphorus 317 is not doped remains as a region where phosphorus is implanted at a low concentration, thereby forming an LDD (Lightly Doped Drain) region 319. In the p-channel TFT later, since the entire semiconductor layer is covered with the mask 316p, the high concentration impurity (phosphorus) 317 is not implanted in this step. At this time, the concentration of the n-type impurity element (phosphorus) 317 in the film in the region 318 is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three It has become. The n-type impurity element (phosphorus) 313 concentration in the LDD region 319 of the n-channel TFT is 1 × 10 ¹⁷ ~ 1x10 ²⁰ / Cm ^Three In such a range, it functions as an LDD region.
[0155]
Next, after removing the resist masks 316n and 316p, as shown in FIG. 4E, a photoresist doping mask 320 is newly provided so as to cover the entire semiconductor layer 310n of the n-channel TFT. At this time, no mask is provided above the p-channel TFT, and the entire TFT is exposed. In this state, an impurity (boron) 321 imparting p-type conductivity is implanted into the semiconductor layer by ion doping using the resist mask 320 and the gate electrode 312p of the subsequent p-channel TFT as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 7 × 10 ¹⁵ cm ^-2 And Through this process, boron 321 is implanted at a high concentration into the region 314p exposed from the gate electrode 312p in the semiconductor layer of the p-channel TFT, and the low-concentration phosphorus implanted in the previous process is canceled (so-called The polarity is reversed from N-type to P-type by counter-doping. As a result, the source / drain region 322 of the p-channel TFT, and the region masked by the gate electrode 312p and not doped with impurities becomes the channel region 315p of the later p-channel TFT. In this process, since the semiconductor layer 310n of the later n-channel TFT is covered with the mask 320, the boron 321 is not doped at all.
[0156]
When doping the n-type impurity and the p-type impurity, the regions that do not need to be doped are covered with a photoresist so that each element is selectively doped, and the n-type high-concentration impurity region 318 and the p-type impurity are doped. The impurity region 322 can be formed separately. In this embodiment, an n-type impurity element is added to the semiconductor layer. However, the order of steps is not limited to this embodiment, and the practitioner may determine as appropriate.
[0157]
Next, after removing the resist mask 320, the resist mask 320 is subjected to heat treatment in an inert atmosphere. This heat treatment activates the ion-implanted impurity in the source / drain region and the LDD region, and at the same time improves the crystallinity of the portion where the crystallinity has deteriorated in the impurity introduction step. At this time, in this embodiment, since the refractory metal (W) is used as the gate electrode material, heat treatment at a relatively high temperature is possible, and the condition margin is expanded. Actually, in this embodiment, a general diffusion furnace was used, and the heat treatment was performed in a temperature range of 500 ° C. to 600 ° C. for about 30 minutes to 8 hours in a nitrogen atmosphere. In addition, an RTA apparatus that uses a lamp or the like as a heat source, an RTA apparatus that inserts a substrate into a furnace in a single wafer, an RTA apparatus that blows an inert gas heated to a high temperature onto the substrate surface, etc. are used. May be. When such an RTA method is used, it is preferably performed at a temperature of 600 ° C. or higher and 700 ° C. or lower under heating conditions of about 30 seconds or longer and within 10 minutes. As a result, the sheet resistance value of the source / drain region 318 of the n-channel TFT was about 500 to 800 Ω / □, and the sheet resistance value of the LDD region 319 was 30 to 60 kΩ / □. Further, the sheet resistance value of the source / drain region 322 of the p-channel TFT was about 1 to 1.5 kΩ / □.
[0158]
Next, as illustrated in FIG. 4F, an interlayer insulating film is formed. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 400 to 1500 nm (typically 600 to 1000 nm). In this embodiment, a silicon nitride film 323 having a thickness of 200 nm and a silicon oxide film 324 having a thickness of 700 nm are stacked to form a two-layer structure. As a film formation method at this time, a plasma CVD method is used, and a silicon nitride film is formed of SiH. _Four And NH _Three As a source gas, the silicon oxide film is TEOS and O ₂ Was continuously formed as a raw material. Of course, the inorganic interlayer insulating film is not limited to this, and another insulating film containing silicon may have a single layer or a laminated structure.
[0159]
Further, a process of hydrogenating the semiconductor layer is performed by performing heat treatment at 300 to 500 ° C. for 1 to several hours. In this step, hydrogen atoms are supplied to the semiconductor layer / gate insulating film interface to terminate and deactivate dangling bonds (dangling bonds) that degrade the TFT characteristics. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film (particularly the silicon nitride film 323) is sufficient, the effect can be obtained even if the heat treatment is performed in a nitrogen atmosphere. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0160]
Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode / wiring 325 is formed from a metal film, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour to complete the n-channel TFT 326 and the p-channel TFT 327 shown in FIG. Further, if necessary, contact holes are provided also on the gate electrodes 312n and 312p, and necessary electrodes are connected by the wiring 325. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0161]
The field effect mobility of each TFT manufactured according to the above embodiment is 250 to 300 cm for an n-channel TFT. ² / Vs, 120-150cm for p-channel TFT ² / Vs is high, and the threshold voltage is about 1 V for an n-channel TFT and about −1.5 V for a p-channel TFT, and exhibits very good characteristics. In addition, the abnormal increase in leakage current during TFT off operation, which was a problem in the conventional example, was suppressed, and even when repeated measurements and durability tests with bias and temperature stress were performed, there was almost no deterioration in characteristics. In addition, when a circuit such as an inverter chain or a ring oscillator is formed by a CMOS structure circuit in which the n-channel TFT and the p-channel TFT manufactured in this embodiment are complementarily formed, it is much more difficult than the conventional one. High reliability and stable circuit characteristics.
[0162]
(Fourth embodiment)
With reference to FIG. 5, a semiconductor film and a method for manufacturing the semiconductor film according to the fourth embodiment of the present invention will be described. In this embodiment, the amorphous semiconductor film is crystallized by a method different from the method described in the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing process in the present embodiment, and the manufacturing process sequentially proceeds according to (A) to (I).
[0163]
First, as in the first embodiment, a base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a substrate (a glass substrate in this embodiment) 401 in order to prevent impurity diffusion from the substrate. To do. In this embodiment, a silicon nitride film is formed as a lower first base film 402, and a silicon oxide film is stacked on the second base film 403. At this time, the thickness of the silicon oxynitride film of the first base film 402 is, for example, 100 nm, and the thickness of the silicon oxynitride film of the second base film 403 is, for example, 100 nm. Next, an a-Si film 404 is formed with a thickness of 25 nm to 80 nm. In this embodiment, an amorphous silicon film having a thickness of 50 nm is formed using a plasma CVD method. In this step, the base insulating film and the amorphous semiconductor film may be formed continuously without being released to the atmosphere.
[0164]
Next, a mask insulating film 405 made of a silicon oxide film is formed to a thickness of 200 nm. As shown in FIG. 5A, the mask insulating film has an opening 400 for adding a catalytic element to the semiconductor film.
[0165]
Next, as shown in FIG. 5B, an aqueous solution (nickel acetate aqueous solution) containing 100 ppm of the catalytic element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form the catalytic element layer 406. To do. At this time, the catalytic element 406 selectively contacts the a-Si film 404 in the opening 400 of the mask insulating film 405 to form a catalytic element addition region.
[0166]
In this embodiment, nickel is added by spin coating, but a thin film made of a catalytic element (in this embodiment, nickel film) is formed on the a-Si film by vapor deposition or sputtering. You may take the means to do.
[0167]
Next, heat treatment is performed at a temperature of 500 ° C. to 650 ° C. (preferably 550 ° C. to 600 ° C.) for 6 to 20 hours (preferably 8 to 15 hours). In this embodiment, a heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 5C, crystal nuclei are generated in the catalytic element addition region 400, and the a-Si film in the region 400 is first crystallized to become a crystalline silicon film 404a. Furthermore, crystallization proceeds in a direction parallel to the substrate (direction indicated by an arrow 407) starting from the crystallization region 404a, and a crystalline silicon film 404b having a uniform macroscopic crystal growth direction is formed. At this time, the nickel 406 existing on the mask 405 is blocked by the mask film 405 and does not reach the underlying a-Si film, and the a-Si film 404 is crystallized only by the nickel introduced in the region 400. Done. A region where the lateral crystal growth does not reach remains as an amorphous region 404c. However, depending on the layout, a boundary may be generated by colliding with a crystal growth region in the lateral direction from an adjacent opening, and in this case, it is not an amorphous region.
[0168]
After removing the silicon oxide film 405 used as a mask, the obtained crystalline silicon film is irradiated with laser light as shown in FIG. Improvements may be made. As a result, the crystalline silicon film in the region 404b in which the crystal is grown in the lateral direction is further improved in quality and becomes a crystalline silicon film 404d.
[0169]
Next, after removing the natural oxide film on the surface of the crystalline silicon film 404d, a gettering layer 409 is formed as shown in FIG. For the formation of the gettering layer, the same method as that in the first embodiment may be used.
[0170]
Then, this is subjected to a first heat treatment in an inert atmosphere. As a heat treatment method at this time, general furnace annealing or rapid thermal annealing (RTA) can be used. In this embodiment, RTA is used. When RTA is used, heat treatment is performed at a temperature of 600 ° C. to 750 ° C. for about 30 seconds to 15 minutes. When furnace annealing is used, heat treatment is preferably performed at a temperature of 500 ° C. to 600 ° C. for about 15 minutes to 4 hours.
[0171]
By this heat treatment, nickel in the crystalline silicon film 404d under the gettering layer 409 is moved upward as indicated by an arrow 410 in FIG. As a result, Ni silicide in the crystalline silicon film 404d disappears, the concentration of nickel in a solid solution state is reduced, and gettering is performed. Thus, a crystalline silicon film 404e having a reduced nickel concentration is obtained.
[0172]
Subsequently, as shown in FIG. 5G, the gettering layer 409 is oxidized by heat treatment in an oxidizing gas atmosphere to form a silicon oxide film 411. As the oxidation treatment at this time, as in the first embodiment, water vapor is used as the oxidizing gas, and the surface of the gettering layer 409 is heated by heat treatment in a high-pressure oxidizing gas atmosphere exceeding 1 atm. RTA treatment in which an oxidizing gas is blown may be used. By this step, the crystalline silicon film 404e becomes a crystalline silicon film 404f with higher defectivity and reduced defect density. Further, the surface of the crystalline silicon film 404f has irregularities between crystal domains due to the difference in oxidation rate depending on the crystal orientation.
[0173]
Then, as shown in FIG. 5H, the silicon oxide film 411 is entirely removed by etching to obtain a target high-quality crystalline silicon film 404f. Then, as shown in FIG. 5I, the crystalline silicon film in the laterally grown region 404f is etched into a predetermined shape to form a semiconductor layer 412 of the later TFT.
[0174]
By applying the crystallization method shown in this embodiment to the crystallization process in the first to third embodiments, a high-performance TFT with higher current driving capability can be realized.
[0175]
(Fifth embodiment)
The semiconductor device of this embodiment is an active matrix substrate. 6A and 6B are block diagrams of the active matrix substrate of this embodiment.
[0176]
FIG. 6A shows a circuit configuration for performing analog driving. This embodiment shows a semiconductor device having a source side driver circuit 50, a pixel portion 51, and a gate side driver circuit 52. Note that in this specification, a drive circuit refers to a generic name including a source side processing circuit and a gate side drive circuit.
[0177]
The source side driving circuit 50 includes a shift register 50a, a buffer 50b, and a sampling circuit (transfer gate) 50c. Further, the gate side driving circuit 52 is provided with a shift register 52a, a level shifter 52b, and a buffer 52c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.
[0178]
In the present embodiment, the pixel unit 51 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.
[0179]
Although not shown, a gate side driver circuit may be further provided on the opposite side of the gate side driver circuit 52 with the pixel portion 51 interposed therebetween.
[0180]
FIG. 6B shows a circuit configuration for performing digital driving. This embodiment shows a semiconductor device having a source side driver circuit 53, a pixel portion 54, and a gate side driver circuit 55. In the case of digital driving, as shown in FIG. 6B, a latch (A) 53b and a latch (B) 53c may be provided instead of the sampling circuit. The source side driving circuit 53 includes a shift register 53a, a latch (A) 53b, a latch (B) 53c, a D / A converter 53d, and a buffer 53e. The gate side driving circuit 55 includes a shift register 55a, a level shifter 55b, and a buffer 55c. If necessary, a level shifter circuit may be provided between the latch (B) 53c and the D / A converter 53d.
[0181]
In addition, the said structure is realizable according to the manufacturing process shown to above-mentioned Embodiment 1-4. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.
[0182]
(Sixth embodiment)
The semiconductor device of this embodiment is an active matrix type liquid crystal display device using the CMOS circuit or the pixel portion formed in the above-described embodiment and all electric appliances having such a liquid crystal display device as a display portion.
[0183]
Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned.
[0184]
In this embodiment, a crystalline semiconductor film having good crystallinity using a catalytic element can be formed, and further, the catalytic element can be sufficiently gettered. Thus, it is possible to realize a good CMOS driving circuit with high reliability and stable circuit characteristics. In addition, even in a switching TFT in a pixel in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch portion, etc., the generation of a leakage current considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, a good display without display unevenness is possible. In addition, since it is a good display with no display unevenness, it is not necessary to use a light source more than necessary, and wasteful power consumption can be reduced, and electric appliances that can reduce power consumption (cell phones, portable books, displays) ) Can be realized.
[0185]
As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. In addition, the electric appliance of the present embodiment can be realized using a display device manufactured by combining the above embodiments.
[0186]
As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible.
[0187]
For example, in addition to the pure silicon film shown in the above-described embodiment, a mixed film of germanium and silicon (silicon / germanium film) or a pure germanium film can be used as the semiconductor film targeted by the present invention.
[0188]
In addition, as a method of introducing nickel, a method of applying the surface of the amorphous silicon film with a solution in which a nickel salt is dissolved was adopted, but nickel was introduced to the surface of the base film before forming the amorphous silicon film, Alternatively, nickel may be diffused from the lower layer of the amorphous silicon film to cause crystal growth. In addition, various other methods can be used for introducing nickel. For example, SOG (spin on glass) material is used as a solvent for dissolving nickel salt, and SiO 2 ₂ There is also a method of diffusing from the film. Further, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing by an ion doping method, or the like can also be used.
[0189]
In the above-described embodiment, the entire amorphous silicon film formed on the entire surface of the substrate is crystallized to produce the crystalline semiconductor film. However, the present invention is not limited to this, and a part of the substrate is formed. Alternatively, a crystalline semiconductor film may be formed in each of the plurality of regions by the method described above.
[0190]
As described above, the present invention uses a stable gettering method that has a large manufacturing process margin, a high manufacturing yield, and an excellent gettering effect. Therefore, in a crystalline semiconductor film having good crystallinity manufactured using a catalytic element, the concentration of the catalytic element contained in the semiconductor film can be stably increased without damaging the crystalline semiconductor film itself such as etching. It can be greatly reduced. When such a semiconductor film is used, the generation of leakage current can be suppressed and the reliability can be improved, and further, the high performance semiconductor device (TFT, active matrix substrate, liquid crystal display) having stable characteristics with little characteristic variation. Including a wide range of devices and appliances). In addition, the yield rate can be greatly improved and the manufacturing cost can be reduced in the manufacturing process of such a semiconductor device.
[0191]
【The invention's effect】
According to the present invention, a highly reliable crystalline semiconductor film in which the content of a catalytic element is sufficiently reduced can be provided. Further, it is possible to provide a method for easily manufacturing such a semiconductor film without increasing manufacturing steps and manufacturing costs. Furthermore, by using the semiconductor film as an active layer, a high-performance semiconductor device (including TFT) can be realized, and a high-performance semiconductor device with a high degree of integration can be easily manufactured.
[0192]
In particular, when the present invention is applied to a liquid crystal display device (a driver monolithic active matrix substrate having an active matrix portion and a peripheral drive circuit portion on the same substrate), the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved. It is advantageous because it simultaneously satisfies the high performance and high integration required for TFTs constituting the peripheral drive circuit section, and can realize a compact, high performance and low cost module.
[Brief description of the drawings]
FIGS. 1A to 1G are schematic process cross-sectional views for explaining a semiconductor film manufacturing method according to a first embodiment of the present invention. FIGS.
2A and 2B are a schematic plan view and a cross-sectional view, respectively, of a semiconductor film according to a first embodiment of the present invention.
FIGS. 3A to 3E are schematic process cross-sectional views for explaining a thin film transistor manufacturing method according to a second embodiment of the present invention. FIGS.
4A to 4F are process cross-sectional views for explaining a method of manufacturing a circuit having a CMOS structure according to a third embodiment of the present invention.
FIGS. 5A to 5I are schematic cross-sectional views for explaining a semiconductor film formation method according to a fourth embodiment of the present invention. FIGS.
FIGS. 6A and 6B are block diagrams of an active matrix substrate according to a fifth embodiment of the present invention.
7A is a view showing crystal growth and FIG. 7B is a view showing a <111> crystal zone plane when a catalyst element is added to an amorphous semiconductor film for crystallization. FIG. (C) is a diagram showing a standard triangle of crystal orientation.
FIGS. 8A and 8B are diagrams showing a plane orientation distribution of a crystalline semiconductor film obtained by using a catalytic element, and FIG. 8C is a diagram showing a standard triangle of crystal orientation. .
FIG. 9 is a diagram schematically showing a configuration of an RTA apparatus used in an embodiment of the present invention.
[Explanation of symbols]
10 domains
11 Domain boundaries
12 Substrate
13, 14 Silicon oxynitride film
15 Underlayer
16 Semiconductor film
101 substrate
102, 103 Underlayer
104 Amorphous silicon film
104a, 104b crystalline silicon film
107 Gettering layer (amorphous silicon film)
108 Movement direction of catalytic element
109 Oxidized gettering layer (silicon oxide film)

Claims (21)

(1 a ) preparing an amorphous silicon film containing a catalytic element that promotes crystallization of the amorphous semiconductor film ;
(1b) subjecting the amorphous silicon film to a second heat treatment to crystallize the amorphous silicon film to obtain a first semiconductor film having a crystalline region;
(2) providing a second semiconductor film in contact with the first semiconductor film;
(3) transferring the catalyst element present in the first semiconductor film to the second semiconductor film by performing a first heat treatment on the first semiconductor film;
(4) oxidizing the second semiconductor film;
(5) removing the oxidized second semiconductor film ,
The method for producing a semiconductor film, wherein the second semiconductor film is an amorphous silicon film and the catalytic element is nickel . Between the step (1 b) and the step (2), further comprising the step of removing the natural oxide film formed on the surface of the first semiconductor film, a method of manufacturing a semiconductor film according to claim 1 . Said second semiconductor layer contains a gettering element of attracting the catalyst element, the gettering element, Ar, comprises at least one rare gas selected from a group consisting of Kr and Xe, claim 1 or 2. A method for producing a semiconductor film according to 2 . Said second semiconductor layer contains a gettering element of attracting the catalyst element, the gettering element, P, comprising at least one element selected from the group consisting of As and Sb, to claim 1 or 2 The manufacturing method of the semiconductor film of description. The second semiconductor film contains a gettering element that attracts the catalyst element, and the gettering element includes at least one element selected from the group consisting of P, As, and Sb, and a group consisting of B and Al. and at least one element selected method of manufacturing a semiconductor film according to claim 1 or 2. The step (3), the said maintaining the amorphous state of the second semiconductor film includes a first heat treatment is performed to process, the method of manufacturing a semiconductor film according to any one of claims 1 to 5. Said step (4), said the second semiconductor film includes a step of performing a third heat treatment under an oxidizing gas atmosphere, a method of manufacturing a semiconductor film according to any one of claims 1 to 6 . The method for manufacturing a semiconductor film according to claim 7 , wherein the third heat treatment step is performed in a high-pressure atmosphere exceeding 1 atm. The method of manufacturing a semiconductor film according to claim 7 , wherein the third heat treatment step includes rapid thermal annealing in which a heated oxidizing gas is sprayed on a surface of the second semiconductor film. Wherein as said oxidizing gas third heat treatment step, using steam, a method of manufacturing a semiconductor film according to any one of claims 7 through 9. The thickness of the second semiconductor layer, the first is in the thickness range of 1/10 or more than twice of the semiconductor film, the method of manufacturing a semiconductor film according to any one of claims 1 to 10. The step (2)
Exposing the surface of the first semiconductor film to a plasma atmosphere containing hydrogen;
Without exposing the first semiconductor layer exposed to the plasma atmosphere to the atmosphere, and forming the second semiconductor film over the first semiconductor film, according to any of claims 1 to 11 A method for manufacturing a semiconductor film. In the step (4), in addition to the second semiconductor film, a part of the lower first semiconductor film is oxidized,
In the step (5), in addition to the second semiconductor layer, wherein the oxidized, said portion of said first semiconductor film which is oxidized is also removed, the semiconductor film according to any one of claims 1 to 12 Manufacturing method. In the step (4), wherein the amount of dangling bonds of the semiconductor atoms in the first semiconductor film is reduced, the manufacturing method of a semiconductor film according to any one of claims 1 to 13. Performed continuously and the third heat treatment step of the first heat treatment step as the step of the step (3) (4) The method of manufacturing a semiconductor film according to any of claims 7 14, . Wherein the first heat treatment is performed third heat treatment at the same time, a method of manufacturing a semiconductor film according to claim 7 or al 14. Wherein step (5), the second semiconductor film includes a step of removing by etching a wet method using an acid having a hydrogen fluoride, a method of manufacturing a semiconductor film according to any of claims 1 to 16 . The step (1a)
Forming an amorphous semiconductor film;
By applying a solution containing the catalyst element on the surface of the amorphous semiconductor film, and forming a first semiconductor film containing the catalyst element, according to claim 1 or al 17 Manufacturing method of the semiconductor film. The step (1a) includes a step of obtaining the amorphous semiconductor film containing the catalytic element by selectively adding the catalytic element to a part of the amorphous semiconductor film, and the step (1b) includes the by catalytic element wherein the crystal growth of the amorphous semiconductor film in the transverse direction from selectively added area to the periphery thereof, comprising the step of obtaining the first semiconductor film, claims 1 18 The manufacturing method of the semiconductor film in any one of. Between the step (1b) and the step (2), a step of irradiating a laser beam to the first semiconductor film, a method of manufacturing a semiconductor film according to any one of claims 1 to 19. Semiconductor film manufactured by the manufacturing method according to any of claims 1 20.

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