JP4360798B2 - Semiconductor film and manufacturing method thereof, and semiconductor device, manufacturing method and semiconductor manufacturing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a thin film transistor (TFT), a manufacturing method thereof, and a semiconductor manufacturing device, and more specifically, a crystalline semiconductor layer obtained by crystallizing an amorphous semiconductor layer as an active region. The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention can be used for active matrix liquid crystal display devices, organic EL display devices, contact image sensors, three-dimensional ICs, and the like.
[0002]
[Prior art]
In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a drive circuit are provided on the same substrate has begun to enter into a general household as well as a monitor for a personal computer (PC). For example, instead of CRT (Cathode-ray Tube), a liquid crystal display is introduced as a television, and a front projector for watching movies and playing games as entertainment is introduced into ordinary households. The market for equipment is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.
[0003]
The amount of information written to the pixels increases to display a high-resolution image, and if that information is not written in a short time, an image with a huge amount of information for high-definition display can be displayed as a moving image. Is impossible. Accordingly, high-speed operation is required for TFTs used in driving circuits. In order to enable high-speed operation, it is required to realize a TFT by using a crystalline semiconductor layer having good crystallinity that can obtain high field effect mobility.
[0004]
As a method for obtaining a good crystalline semiconductor layer on a glass substrate, the present inventor has conventionally added a metal element having an action of promoting crystallization to an amorphous semiconductor layer, and then heat-treated, so that We are developing a technology to obtain a good semiconductor film with uniform crystal orientation by low-temperature and short-time heat treatment.
[0005]
However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. Catalytic element segregates irregularly in the semiconductor film, especially at the grain boundaries, and this segregation of the catalytic element becomes a current escape path (leakage path), which causes sudden off-current. It is thought that it is causing the increase. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process. Hereinafter, the process of removing the catalyst element is referred to as a “gettering process”.
[0006]
Various processes and methods have been proposed for the gettering process and gettering method.
[0007]
For example, in Patent Literature 1, lattice defects in an amorphous region are formed by forming an amorphous region in part of silicon crystallized with a catalytic element and performing heat treatment. A technique for moving (gettering) a catalyst element there is disclosed. As the amorphous region (gettering region) at this time, a method of forming outside the semiconductor element region and a method of using the source / drain region of the TFT are disclosed. When the source / drain region is used as the gettering region, the manufacturing process can be simplified. However, since the amorphous region does not function as the source / drain region, there is an additional step of activation using laser light or the like. Necessary.
[0008]
In Patent Document 2, attention is paid to the gettering action of phosphorus, and the active region (semiconductor layer) of a TFT formed of silicon crystallized by a catalytic element is compared with the source / drain of an N-channel TFT. Phosphorus is doped in the region, and in the P-channel TFT, the source / drain is doped with phosphorus and boron at a higher concentration, and the heat treatment is performed to getter the catalytic element into the source / drain region.
[0009]
In Patent Document 3, group 5 B elements such as phosphorus are selectively introduced into a portion of silicon crystallized by a catalytic element, and heat treatment is performed in a temperature range that does not exceed the strain point of the substrate. A technique for moving (gettering) a catalytic element to a region (gettering region) into which a Group 5 B element has been introduced is disclosed. As a result of the gettering of the catalytic element in the region into which the group 5 B element has been introduced, the region where the concentration of the catalytic element is reduced (also referred to as “low concentration region”) is used to form the semiconductor element (TFT). An active region is formed.
[0010]
[Patent Document 1]
JP-A-8-213317
[Patent Document 2]
JP-A-8-330602
[Patent Document 3]
Japanese Patent Laid-Open No. 10-270363
[0011]
[Problems to be solved by the invention]
Problems in the conventional gettering process, including the techniques disclosed in the above three patent documents, include increased process cost due to the addition of a process for gettering and increased cost due to increased load on the manufacturing apparatus. However, the biggest problem is that these conventional methods do not have a sufficient gettering effect and the residual amount of the catalytic element in the channel region of the TFT has not been sufficiently reduced.
[0012]
As described in Patent Documents 1 to 3, a gettering element such as an amorphous state or phosphorus (an element having an action of attracting a catalyst element is referred to as a “gettering element”) is introduced. When a method of forming a gettering region and moving the catalyst element in the silicon film to the gettering region is used, the amount of the catalyst element can be reduced by one digit or more. However, when TFTs are manufactured using the methods of these patent documents, there are slight differences in the effects due to the difference in the method of forming the gettering region. A defective TFT having a very large leakage current when the TFT is turned off appears with a probability of several percent to several percent. In the TFT manufactured as a reference and not subjected to gettering at all, the probability of occurrence of a TFT with defective leakage current is about 10% to 20%. Therefore, the methods of these patent documents ensure the gettering effect from the viewpoint of device characteristics. As can be seen, there is still a few percent of TFTs with poor leakage current. That is, in an active matrix substrate having 1 million TFTs, tens of thousands of TFTs become defective TFTs.
[0013]
Therefore, with the known gettering technique, the obtained champion data is still 0. I have to prepare for TFT defects of a few percent. When an active matrix substrate for liquid crystal or organic EL display is manufactured in such a state, a bright spot (point defect) is generated due to a leakage current during off-operation in some pixel TFTs, and a driver (driving circuit) In the portion), a line defect occurs due to a leakage current in the sampling TFT portion. As a result, the yield of the panel is greatly reduced.
[0014]
Analyzing a defective TFT with a large leakage current during the off operation, it is confirmed that silicide due to the catalytic element exists at the junction between the channel region and the drain region, and the primary cause is segregation of the catalytic element, The secondary cause is that gettering is still insufficient. Therefore, the technology of the above-mentioned patent document does not sufficiently getter the catalytic element, and even if a high-performance TFT can be partially probabilistically manufactured, the defect rate is high and the reliability is low, so that it can be applied to mass production. It's not a technology that can be done.
[0015]
The present invention has been made in view of the above-mentioned various points, and an object of the present invention is to manufacture a high-quality crystalline semiconductor layer and to provide a semiconductor device having a TFT (semiconductor element) having good characteristics using the crystalline semiconductor layer. To provide an apparatus. It is another object of the present invention to provide a manufacturing method and a semiconductor manufacturing apparatus that can realize such a semiconductor device in a low-cost manufacturing process without increasing the manufacturing process.
[0016]
[Means for Solving the Problems]
The semiconductor film of the present invention is a semiconductor film formed on an insulating surface, has a crystalline structure, includes at least one region containing a catalytic element that promotes crystallization of the semiconductor film, and is substantially It is characterized by containing a rare gas element throughout.
[0017]
It is preferable that the semiconductor film in the at least one region does not substantially contain the semiconductor compound of the catalytic element, and the catalytic element is dissolved in the crystalline semiconductor layer.
[0018]
In one embodiment, the semiconductor film is substantially composed of silicon, and the semiconductor compound of the catalytic element is silicide.
[0019]
The concentration of the catalytic element in the semiconductor film in the at least one region is 1 × 10 ¹⁷ atoms / cm ^Three The following is preferable.
[0020]
The concentration of the rare gas element is 5 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three It is preferable to be within the range.
[0021]
In one embodiment, the at least one region is formed substantially entirely.
[0022]
Another semiconductor film of the present invention is a semiconductor film formed on an insulating surface, which is composed of a crystalline semiconductor layer and includes an active element containing a catalytic element that promotes crystallization of the semiconductor film and a rare gas element. The active region includes a first region and a pair of second regions formed adjacent to both sides of the first region, wherein the first region substantially includes the semiconductor compound of the catalytic element. The catalytic element is solidly dissolved in the crystalline semiconductor layer.
[0023]
In one embodiment, the semiconductor film is substantially composed of silicon, and the semiconductor compound of the catalytic element is silicide.
[0024]
The concentration of the catalytic element in the crystalline semiconductor layer in the first region is 1 × 10 ¹⁷ atoms / cm ^Three The following is preferable.
[0025]
The pair of second regions preferably has a higher concentration of the catalytic element than the first region.
[0026]
The concentration of the catalytic element in the pair of second regions is 1 × 10 ¹⁸ atoms / cm ^Three 1 × 10 or more ²⁰ atoms / cm ^Three It is preferable to be within the following range.
[0027]
It is preferable that the crystalline semiconductor layers in the pair of second regions substantially do not contain the semiconductor compound of the catalytic element, and the catalytic element is dissolved in the crystalline semiconductor layer.
[0028]
In one embodiment, the semiconductor film is substantially composed of silicon, and the semiconductor compound of the catalytic element is silicide.
[0029]
In one embodiment, the pair of second regions includes an impurity element belonging to Group B of the periodic table that imparts n-type conductivity.
[0030]
In one embodiment, the active region includes the first region, the pair of second regions, and a gettering region having an action of attracting the catalytic element.
[0031]
In one embodiment, the gettering region has a higher concentration of the catalytic element than the first region.
[0032]
In one embodiment, the concentration of the catalytic element in the gettering region is 1 × 10 ¹⁸ atoms / cm ^Three 1 × 10 or more ²⁰ atoms / cm ^Three Within the following range.
[0033]
In one embodiment, the concentration of the catalytic element is higher in the gettering region than in the first region and the pair of second regions.
[0034]
In one embodiment, the gettering region includes more amorphous components than the first region and the pair of second regions.
[0035]
In one embodiment, the gettering region includes an impurity element belonging to Group B of the periodic table that imparts n-type conductivity and an impurity element belonging to Group B of the periodic table that imparts p-type conductivity. .
[0036]
In one embodiment, the gettering region contains at least one kind of rare gas element selected from the group consisting of Ar, Kr, and Xe at a higher concentration than other regions.
[0037]
In one embodiment, the gettering region contains a rare gas element having an atomic number larger than that of the rare gas element contained in the active region.
[0038]
In one embodiment, at least the crystalline semiconductor layer of the first region is mainly composed of a <111> crystal zone plane.
[0039]
In one embodiment, the (110) plane and the (211) plane occupy 50% or more of the <111> crystal zone plane mainly constituting the plane orientation.
[0040]
In one embodiment, the crystal grain size of the crystalline semiconductor layer in the at least first region is in the range of 2 μm to 10 μm.
[0041]
In one embodiment, an average surface roughness Ra of the crystalline semiconductor layer in at least the first region is in a range of 4 nm to 9 nm.
[0042]
The catalyst element is preferably at least one metal element selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu.
[0043]
The method for producing a semiconductor film of the present invention comprises (a) a step of forming an amorphous semiconductor layer containing a rare gas element on an insulating surface, and (b) a catalyst for promoting crystallization in the amorphous semiconductor layer. A step of crystallizing the amorphous semiconductor layer by applying a first heat treatment after applying the element to obtain a crystalline semiconductor layer; and (c) the catalytic element remaining in the crystalline semiconductor layer. Forming a low catalyst concentration region in which the concentration of the catalytic element is lower than other regions in the crystalline semiconductor layer by moving at least a part of the crystalline semiconductor layer.
[0044]
In one embodiment, the step (b) includes a process of crystal growth using the semiconductor compound of the catalytic element as a crystal nucleus, and the step (c) includes the semiconductor compound of the catalytic element in the low catalyst concentration region. In the crystalline semiconductor layer.
[0045]
In one embodiment, the step (c) includes a step of substantially eliminating the semiconductor compound of the catalytic element in the low catalyst concentration region.
[0046]
In one embodiment, the crystalline semiconductor layer is substantially composed of Si, and the semiconductor compound of the catalytic element is silicide.
[0047]
In one embodiment, in the step (a), the amorphous semiconductor layer introduces the rare gas element into the amorphous semiconductor layer while depositing the amorphous semiconductor layer using a plasma CVD method. Formed by.
[0048]
In one embodiment, in the step (a), the amorphous semiconductor layer is formed by forming an amorphous semiconductor layer and then ion-doping the rare gas element into the amorphous semiconductor layer. .
[0049]
In one embodiment, the plasma CVD process in the step (a) includes supplying a first power to the CVD electrode and supplying a second power different from the first power to the substrate having the insulating surface. To do.
[0050]
In one embodiment, the first power and the second power are RF powers having different frequencies.
[0051]
In one embodiment, the frequency of the second power is lower than the frequency of the first power.
[0052]
In one embodiment, the step (c) includes a step of forming a gettering region or a gettering layer having an action of attracting the catalyst element, and a second heat treatment is performed later on the step, whereby the crystalline material is obtained. And a step of moving the catalytic element remaining in the semiconductor film to the gettering region or the gettering layer.
[0053]
In one embodiment, the method further includes a step of patterning the crystalline semiconductor layer into a desired shape before the step (c). The desired shape is, for example, a shape corresponding to an active region (semiconductor layer) of a TFT to be formed later.
[0054]
In one embodiment, the gettering region or the gettering layer contains more amorphous components than other regions of the crystalline semiconductor film.
[0055]
In one embodiment, the gettering region or the gettering layer includes an impurity element belonging to Group B of the periodic table that imparts n-type conductivity.
[0056]
In one embodiment, the impurity element includes at least one element selected from the group consisting of P, As, and Sb.
[0057]
In one embodiment, the gettering region or the gettering layer includes an impurity element belonging to Group B of the periodic table that imparts p-type conductivity.
[0058]
In one embodiment, the impurity element includes at least one of B and Al.
[0059]
In one embodiment, the gettering region or the gettering layer has a concentration of the rare gas element in which the amorphous semiconductor layer contains at least one rare gas element selected from the group consisting of Ar, Kr, and Xe. Higher concentration.
[0060]
In one embodiment, the gettering region or the gettering layer includes at least one rare gas element having an atomic number larger than that of the rare gas element included in the amorphous semiconductor layer.
[0061]
In one embodiment, the impurity element and / or the at least one rare gas element included in the gettering region or the gettering layer is introduced by an ion doping method.
[0062]
In one embodiment, the method further includes the step of removing the gettering region or the gettering layer after the step (c).
[0063]
In one embodiment, in the step (b), after the catalytic element is selectively applied to a partial region of the amorphous semiconductor film, the first heat treatment is performed, whereby the catalytic element is Including a step of crystal growth in the lateral direction from the selectively applied partial region to the periphery thereof.
[0064]
In one embodiment, the step (b) includes a step of irradiating the crystalline semiconductor film with laser light after the first heat treatment.
[0065]
The catalyst element is preferably at least one metal element selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu.
[0066]
A method for manufacturing a semiconductor device of the present invention includes a step of preparing a semiconductor film manufactured by any one of the above-described methods for manufacturing a semiconductor film, and a step of manufacturing a thin film transistor having the semiconductor film in an active region. It is characterized by that.
[0067]
In one embodiment, the active region includes a channel region, a source region, and a drain region, and the step of manufacturing the thin film transistor includes a step of forming at least the channel region in the low catalyst concentration region.
[0068]
In one embodiment, the step of manufacturing the thin film transistor includes a step of forming the channel region, the source region, and the drain region in the low catalyst concentration region.
[0069]
In one embodiment, the active region includes a channel region, a source region, a drain region, and an LDD region (low concentration impurity region), and the step of manufacturing the thin film transistor includes at least the low catalyst concentration region in the low catalyst concentration region. Forming a channel region and the LDD region.
[0070]
In one embodiment, the step of manufacturing the thin film transistor includes a step of forming the channel region, the source region, the drain region, and the LDD region in the low catalyst concentration region.
[0071]
A semiconductor device of the present invention includes a thin film transistor having any one of the above semiconductor films in an active region.
[0072]
In one embodiment, the active region includes a channel region, a source region, and a drain region, and at least the channel region is formed in the first region.
[0073]
In one embodiment, the channel region, the junction region between the channel region and the source region, and the junction region between the channel region and the drain region are formed in the first region.
[0074]
In one embodiment, the junction region between the channel region and the source region and the junction region between the channel region and the drain region are within a range of 2 μm or less from each junction boundary.
[0075]
In one embodiment, the active region includes a channel region, a source region, a drain region, and an LDD region (low concentration impurity region), and at least the channel region and the LDD region are formed in the first region. ing.
[0076]
In one embodiment, the active region includes a channel region, a source region, and a drain region, the channel region is formed in the first region, and the source region and the drain region are the pair of pairs. It is formed in the second region.
[0077]
In one embodiment, the active region includes a channel region, a source region, a drain region, and an LDD region (low concentration impurity region), and the channel region and the LDD region are formed in the first region. The sole region and the drain region are formed in the pair of second regions.
[0078]
In one embodiment, the semiconductor device further comprises a gate insulating film formed on the channel region of the semiconductor film, and a gate electrode formed to face the channel region with the gate insulating film interposed therebetween, The electrode is formed of a metal film containing at least one element selected from the group consisting of W, Ta, Ti, and Mo.
[0079]
An electronic apparatus according to the present invention includes any one of the semiconductor devices described above.
[0080]
In one embodiment, an electronic apparatus includes a display unit including a plurality of pixels, and a display signal is supplied to the plurality of pixels via the semiconductor device.
[0081]
The semiconductor manufacturing apparatus of the present invention includes a chamber, a gas introduction port for supplying a semiconductor material gas and a rare gas into the chamber, a CVD electrode for generating plasma provided in the chamber, and the chamber A substrate holder for receiving a substrate; a first power source for supplying power to the CVD electrode; and a second power source for supplying power to the substrate holder, wherein the chamber is grounded, The CVD electrode and the substrate holder are electrically independent of the chamber, and power is supplied to the CVD electrode and the substrate holder independently of each other.
[0082]
In one embodiment, the first power source and the second power source respectively supply different RF powers to the CVD electrode and the substrate holder.
[0083]
In one embodiment, the power capacity of the first power source is greater than or equal to the power capacity of the second power source.
[0084]
In one embodiment, the RF frequency of the first power source is higher than the RF frequency of the second power source.
[0085]
In one embodiment, the semiconductor manufacturing apparatus includes a further chamber connected to the chamber directly or via a vacuum chamber.
[0086]
In one embodiment, the additional chamber is used to deposit an insulating film.
[0087]
DETAILED DESCRIPTION OF THE INVENTION
The present inventor has a fundamental question as to why the gettering techniques disclosed in Patent Documents 1 to 3 and the like are insufficient for gettering, and the catalyst element cannot be completely removed. The mechanism and cause were examined in detail. As a result, the cause was finally found and the present invention was conceived. The cause elucidation process, results, and embodiments of the present invention will be described below.
[0088]
Consider a method as described in Patent Documents 1 to 3 above, in which nickel is used as the catalyst element and the catalyst element in the silicon film is moved to the gettering region. The movement of nickel can be considered by the diffusion movement of nickel, but simply considering the diffusion coefficient of nickel in the silicon film, the movement time is only a short heat treatment. However, in practice, a long annealing process is required at a high temperature, which does not match the value calculated from the diffusion coefficient. On the other hand, since nickel is not present in the form of a solid solution in the silicon film, most of the nickel is precipitated, so this is incorporated into the model, and the silicon film A model is considered in which nickel diffusion and migration occurs only below the solid solubility of nickel. This model will be described with reference to FIG.
[0089]
As shown in FIG. 17, the localized Ni silicide is first dissolved from the silicide form and moves in the silicon film as interstitial Ni. In FIG. 17, line 171 is a line indicating the concentration of Ni in the silicon film, and line 172 is a line indicating the solid solubility of Ni. The region 176 is a region that has not been gettered yet, and Ni 173 having a concentration of a solid solubility of 172 or higher is deposited as Ni silicide. The region 177 is a region where gettering has been performed, and the Ni concentration 171 has a solid solubility of 172 or less. A region 178 is a gettering site (gettering region), and its gettering capability is assumed to be infinite, and the Ni concentration at the gettering site is assumed to be zero. That is, as shown in FIG. 17, a Ni concentration gradient 174 is generated at a concentration equal to or lower than the solid solubility 172 at the heat treatment temperature for gettering, and Ni is diffused and moved in the direction of 175 toward the gettering site 178. Ni silicide disappears. As a result, the gettering distance from the gettering site (the width of the region 177) increases sequentially, and this phenomenon is in good agreement with the actual experimental results.
[0090]
Based on this theory, the gettering distance (the width of the region 177) is expressed by the following equation, and the gettering distance L increases with time t. Where C ₀ Is the solid solubility of Ni in the silicon film, D is the diffusion coefficient of Ni in the silicon film, and is a function of temperature T, respectively. C ₁ Is the original Ni concentration in the silicon film.
L = √ (2C ₀ ・ Dt / C ₁ )
[0091]
The calculation result obtained by solving this equation is shown in FIG. In FIG. 18, the calculation is performed with the heat treatment for gettering being 550 ° C. A curve 181 shows the result of calculation based on the calculation formula, and the gettering distance increases with the heat treatment time of gettering. In contrast, the point 182 plots the gettering distance obtained from the experiment at the same time. In the experiment, the remaining Ni silicide was etched with hydrofluoric acid, and the gettering distance was confirmed based on whether or not the etching hole was present. In the gettering region, boron is doped in addition to phosphorus to enhance the gettering ability. The heat treatment for gettering is of course performed at 550 ° C. As can be seen from FIG. 18, the experimental value 182 and the theoretical value 181 agree very well, and it is considered that the above theoretical consideration is almost correct with respect to the gettering movement of Ni.
[0092]
However, when the gettering distance is actually examined under various conditions, it often does not match the theoretical value. One is a case where the ability of the gettering region is insufficient, and a deviation from the theoretical value assuming that the gettering ability is infinite occurs. However, the problem is that even if a gettering region having sufficient gettering capability is formed, the gettering distance may be significantly shorter than the theoretical value. This is the root cause that the conventional technology, which is the above-mentioned problem, cannot sufficiently getter the catalyst element, and the leakage current abnormality when the TFT is turned off cannot be partially suppressed.
[0093]
The present inventor investigated the cause of this, and found that a large difference was observed particularly in the difference in temperature at the time of crystal growth by adding a catalyst element. The experimental results are shown in FIG. The gettering heat treatment was performed at 550 ° C. and 4 H, and the gettering distance at that time was examined by the above method. The horizontal axis represents the heat treatment temperature when crystallization is performed using a catalyst element (first heat treatment). The heat treatment time at this time is fixed at 4 hours. The gettering distance 191 calculated by the above theory is about 20 μm and is a constant value regardless of the crystallization temperature, but the actual experimental value 192 greatly depends on the heat treatment temperature of the crystallization, and the heating during the crystallization. When the processing temperature rises, it decreases significantly.
[0094]
This is presumably because the segregation state of Ni silicide after crystal growth differs depending on the heat treatment temperature during crystallization. FIG. 20 shows an optical micrograph of Ni silicide etched with hydrofluoric acid after the heat treatment for crystallization. The black dots seen in the photograph are etch pits (fine holes) that are made obvious by etching the Ni silicide and causing great damage to the underlying layer. Although the annealing temperatures during crystallization are 550 ° C., 575 ° C., and 600 ° C., the higher the temperature, the larger the etch pits of individual Ni silicides. . That is, it is considered that the size of each individual Ni silicide increases as the heat treatment temperature during crystallization increases.
[0095]
Actually, Ni silicides (catalytic element semiconductor compounds) localized after crystal growth are distributed in various sizes in the film. Some are particularly large, others are relatively small. The temperature during the crystal growth described above affects the overall size (average value). In the conventional technique, even if crystallization is performed at a temperature of 550 ° C. or less, the A TFT defect of about several percent occurs and a sufficient production yield cannot be obtained. Although the present invention does not refer to the temperature at the time of crystallization, the above-described experiment on the crystallization temperature has provided a great hint for solving the above-mentioned conventional problems.
[0096]
That is, even under conditions where the gettering is apparently performed almost completely, the cause of the TFT defect caused by Ni is due to the size of the Ni silicide that exists in the film. This mechanism will be described with reference to FIG. A circle 251 in FIG. 21 schematically shows a large lump of Ni silicide, and a circle 252 schematically shows a small lump of Ni silicide. The mechanism of the gettering movement has been described with reference to FIG. 17, which is a model in which localized Ni silicide first dissolves from the silicide form and moves in the silicon film as interstitial Ni. That is, for gettering, Ni silicide must first be dissolved between silicon film lattices. In the above formula based on this model, the time required to dissolve the Ni silicide at this time is considered only by the initial nickel concentration, but in reality it is two-dimensional as shown by the arrow 253 in FIG. A solid solution occurs. Therefore, the solid solution time varies depending on the size of the silicide (radius 254), and the longer the radius 254, the longer the heat treatment is required for solid solution. Therefore, a term relating to the solid solution time depending on the radius 254 of the silicide needs to be added to the time required for actual gettering.
[0097]
The root cause of the prior art is that when a large Ni silicide lump exists, it takes a long time to dissolve the lump, and the size gradually decreases within the heat treatment time of gettering. It was found that even after the predetermined heat treatment time, Ni silicide still remains and is not apparently gettered. The size of Ni silicide (catalyst element compound) after crystal growth varies in the film, and particularly silicide having a large radius is not sufficiently gettered by the conventional method and remains at 0. This is still the cause of TFT defects with a probability of several percent.
[0098]
Based on the experimental results, the present inventor has thought that a sufficient gettering effect can be obtained by improving not the gettering process itself but the previous crystallization process. That is, the inventors focused attention on how much precipitates of the semiconductor compound of the catalytic element (silicide in the above example) and their lump can be dispersed small before the gettering step. This is because, from the above model, how small the catalyst compound semiconductor compound precipitates deposited on the semiconductor film can greatly affect the gettering effect in the subsequent gettering step. We thought that the gettering effect should be enhanced by dispersing the precipitation of the catalytic compound semiconductor compound in the crystal growth process as small as possible and keeping the size of the individual catalytic element semiconductor compounds as small as possible. .
[0099]
However, it is very difficult to actually create a state in which the deposits of the semiconductor compound of the catalytic element are small and dispersed. As shown in FIG. 19, the heat treatment temperature at the time of crystallization is lowered and the heating time is extended, so that the gettering effect can be enhanced. However, since the throughput is lowered, it is difficult to apply to mass production. Therefore, the present inventor has tried various experiments and found a method in which the precipitates of the semiconductor compound of the catalytic element described above can be dispersed small by using process parameters other than the crystallization temperature, thereby reducing the size of each lump. As a result, the catalyst element was gettered more efficiently than in the past, and a crystalline semiconductor layer having a lower catalyst concentration than in the past was successfully produced. When an active matrix substrate including a TFT having a crystalline semiconductor layer manufactured using this method in an active region (at least a channel region) is manufactured and applied to a liquid crystal display panel, a defect caused by a catalytic element is one more than conventional. It has fallen by more than an order of magnitude and has achieved an unprecedented high yield.
[0100]
The method for producing a semiconductor film of the present invention includes (a) a step of forming an amorphous semiconductor layer containing a rare gas element on an insulating surface, and (b) a catalytic element that promotes crystallization in the amorphous semiconductor layer. And a first heat treatment to crystallize the amorphous semiconductor layer to obtain a crystalline semiconductor layer, and (c) a catalyst in which the catalyst element existing in the crystalline semiconductor layer remains. And a step of forming a low catalyst region in which the concentration of the catalytic element is lower in the crystalline semiconductor layer than other regions by moving at least a part of the element (sometimes referred to as a “gettering step”). . In the step (b), the catalytic element forms a semiconductor compound, and the semiconductor compound serves as a crystal nucleus to grow a semiconductor crystal. A method of manufacturing a semiconductor device according to the present invention is characterized in that at least a channel region of a TFT is formed using the crystalline semiconductor film in which the concentration of the catalytic element is reduced.
[0101]
In the semiconductor film manufacturing method of the present invention, since the amorphous semiconductor layer contains a rare gas element, the lump of the semiconductor compound of the catalyst element formed by applying the catalyst element contains the rare gas element. It is smaller than the lump of the catalyst element semiconductor compound formed in the amorphous semiconductor layer, and can be easily dissolved in the semiconductor film and efficiently transferred to the gettering region or gettering layer. As a result, it is possible to manufacture a crystalline semiconductor layer in which the concentration of the remaining catalytic element is lower than that in the past. The region where the concentration of the catalytic element in the crystalline semiconductor layer is reduced does not substantially contain the semiconductor compound of the catalytic element, and almost all of the catalytic element can be in a solid solution state in the semiconductor layer.
[0102]
In the step (c), a gettering region having an action of attracting a catalytic element is provided in a partial region of the semiconductor film, and the catalytic element contained in the semiconductor film is moved to the gettering region, thereby adjacent to the gettering region. A method of reducing the concentration of the catalytic element in the region may be adopted. Alternatively, in the step (c), a gettering layer is provided on the semiconductor film, and the catalytic element contained in the semiconductor film is moved to the gettering layer, thereby reducing the concentration of the catalytic element in a region in contact with the gettering layer. A method may be adopted. The gettering region and the gettering layer may be removed as necessary. For example, if a gettering layer is provided over almost the entire semiconductor film, the catalyst element is moved to the gettering layer, and then the gettering layer is removed, the crystal in which the catalyst concentration is reduced over the entire region is lower than in the past. A quality semiconductor layer can be obtained. That is, a part of the crystalline semiconductor layer can be a low catalyst concentration region, or almost the entire surface of the crystalline semiconductor layer can be a low catalyst concentration region.
[0103]
The semiconductor film of the present invention manufactured by the above-described method is a semiconductor film formed on an insulating surface, and contains a rare gas element almost entirely, and at least a part thereof has crystallinity. And at least one region containing a catalytic element that promotes crystallization of the semiconductor. The catalyst concentration in the at least one region is lower than that of the prior art and has characteristics superior to those of the conventional crystalline semiconductor layer. By using this as an active region (semiconductor layer: at least a channel region), a TFT is produced. A TFT with better characteristics than before can be obtained.
[0104]
In the present invention, an amorphous semiconductor layer containing a rare gas element is formed, and a catalyst element is added to this to crystallize. The present inventor has found that by containing a rare gas element, the precipitates of the semiconductor compound of the catalytic element after crystallization can be further dispersed and individual chunks can be made smaller. By performing the gettering step on the crystalline semiconductor layer thus obtained, these small dispersed semiconductor compounds of the catalytic element are easily dissolved in the semiconductor film and the lump disappears. That is, a local catalytic element semiconductor compound (eg, NiSi) found in a conventional crystalline semiconductor layer. ₂ NiSi, Ni ₂ There is virtually no residual Si). As a result, when the crystalline semiconductor layer (low catalyst concentration region) according to the present invention is used at least in the channel region, the leakage current failure during the off operation of the TFT can be greatly improved. The crystalline semiconductor layer (low catalyst concentration region) of the present invention is preferably used in a channel region and a region including the vicinity of the junction between the channel region and the source region / drain region. Further, the entire active region (including the channel region, the source region, and the drain region) of the TFT may be formed using the crystalline semiconductor layer (low catalyst concentration region) of the present invention.
[0105]
Next, the results of experiments conducted by the inventor will be described with reference to FIG.
[0106]
FIG. 22 is a graph showing the relationship between the Ni concentration and the crystal nucleus generation density when Ni is used as the catalyst element. Here, a silicon film is used as the semiconductor film. The horizontal axis represents the Ni addition amount on the surface density of Ni on the silicon film surface measured by total reflection X-ray fluorescence analysis (TRXRF) after Ni addition. The vertical axis represents the nucleation density when heating and crystallizing the amorphous silicon film to which Ni has been added. ² This represents the number of crystal nuclei generated per hit. The crystal nucleus generation density is determined by stopping the heat treatment in the middle of crystallization (here, 550 ° C., 10 minutes) and observing the crystal nuclei generated at that time with an optical microscope. Was calculated. In FIG. 22, a line 261 shows a result when a conventional amorphous silicon film containing no rare gas element is used, and a line 262 shows a result when an amorphous silicon film containing a rare gas element is used. Is shown. Argon is used as the rare gas element, and the concentration in the silicon film is 2.3 × 10. ¹⁷ atoms / cm ^Three It is.
[0107]
As can be seen from FIG. 22, when the amount of Ni added is increased, the generation density of crystal nuclei increases. This is because Ni reacts with the silicon film to form Ni silicide and grows the crystal using it as a nucleus. Therefore, the larger the amount of Ni, the more the crystal nucleus increases. What should be noted here is that when compared with the same Ni addition amount, the generation density of crystal nuclei is significantly higher in the amorphous silicon film containing Ar than in the amorphous silicon film containing no rare gas element. The value is high, and the value is about 3 times.
[0108]
The smaller the amount of Ni added, the better. However, there is a limit, and when the generation density of crystal nuclei falls below the value indicated by the line 263, defective crystal growth begins to occur. This crystal growth defect is because the generation density of crystal nuclei is too low, and crystal grains grown from the crystal nuclei collide with each other, making it impossible to make the entire film a crystalline region. It shows that an amorphous region remains between the two. In such a state, there is a large variation in the degree of crystallinity in the semiconductor film, and it cannot be used for a semiconductor device.
[0109]
The value indicated by line 263 (1 × 10 ^-2 Piece / μm ² ) For the amorphous silicon film not containing a rare gas element, the limit minimum value of Ni addition necessary for generating crystal nuclei at the above density is about 5.5 at the point where the lines 261 and 263 intersect. × 10 ¹² atoms / cm ² On the other hand, in the case of an amorphous silicon film containing a rare gas element, 1.8 × 10 6 at the intersection of the lines 262 and 262. ¹² atoms / cm ² It will be about. That is, in the amorphous silicon film containing a rare gas element, the amount of the catalytic element can be reduced to 1/3 as compared with the case where the conventional rare gas element is not contained.
[0110]
In this way, by introducing the rare gas element, the amount of the catalytic element required to generate crystal nuclei with a predetermined density can be greatly reduced. There is an advantage that the amount of the remaining catalyst can be reduced.
[0111]
By introducing a rare gas element into the amorphous semiconductor film, in addition to the above advantages, the following advantages can be obtained. That is, the state of the semiconductor compound of the catalytic element aggregated and precipitated in the crystalline semiconductor layer obtained by crystallizing the amorphous semiconductor layer is easily moved (easily gettered) in the subsequent gettering step. That is.
[0112]
By introducing the rare gas element, the nucleation density is tripled with the same amount of addition of the catalytic element as compared to the case where the rare gas element is not introduced. This means that the amount of Ni forming each crystal nucleus is small. It means that the amount is 1/3. The individual crystal nuclei are generated by the conventional 1/3 amount of the catalytic element. As a result, the amount of the catalytic element that finally agglomerates and precipitates at the crystal grain boundary is also reduced to 1/3. The size of the compound is also 1/3. Therefore, the catalyst remaining in the crystalline semiconductor layer is easily gettered in a later gettering step.
[0113]
The arrangement distribution and the size of the semiconductor compound of the catalytic element that is agglomerated and precipitated in the semiconductor film after the crystallization step can be easily confirmed by exposing the semiconductor film to hydrofluoric acid. Since the semiconductor compound of the catalytic element is selectively removed by hydrofluoric acid, by exposing the crystallized semiconductor film to hydrofluoric acid, minute holes (etch pits) in which the semiconductor compound of the catalytic element is etched And the distribution and size of the semiconductor compound of the catalytic element can be confirmed by the etch pit. However, if the treatment time with hydrogen fluoride at this time is long, the etching damage to the insulator of the layer under the semiconductor film becomes serious and the etch pit becomes large.
[0114]
FIG. 23 shows a scanning electron microscope (SEM) image photograph of the surface of the crystalline semiconductor layer after revealing with hydrofluoric acid. FIG. 23A shows a crystalline silicon film obtained by adding Ni to an amorphous silicon film that does not contain a rare gas element and crystallizing, and relatively large etch pits, that is, Ni silicide aggregation occurs. I understand. On the other hand, FIG. 23B shows a crystalline silicon film obtained by adding Ni to an amorphous silicon film containing Ar as a rare gas element and crystallizing it. Compared with FIG. No pit (aggregation of Ni silicide) is observed, and it can be seen that the individual Ni silicides are finely dispersed in smaller lumps. This SEM photograph is an example, but the present inventor observed over a wider area and obtained the same result.
[0115]
Although it is not well understood at the present time how the rare gas element acts and creates such a state when adding a catalytic element to the amorphous semiconductor layer containing the rare gas element and crystallizing it, The inventor considers the following model.
[0116]
The catalytic element added to the amorphous silicon film diffuses in the amorphous semiconductor layer in the initial stage (including the temperature rising process) in the heat treatment during crystallization (typically laser beam irradiation). A certain amount of clusters (clusters) are formed to become a semiconductor compound, and crystal nuclei are generated. If the catalytic element can sufficiently diffuse in the silicon film at the initial stage of the heat treatment, large clusters are formed, and each becomes large crystal nuclei. As a result, the nucleation density decreases. On the other hand, if the catalyst element cannot be sufficiently diffused, only small clusters can be formed. Instead, many small crystal nuclei are formed and the nucleation density is increased. That is, the rare gas element contained in the amorphous semiconductor layer may act to inhibit the diffusion of the catalytic element in the semiconductor film at the initial stage of the heat treatment for crystallization. Conceivable.
[0117]
In the embodiment of the present invention, the crystalline semiconductor layer constituting the active region (at least the channel region) of the TFT is preferably a semiconductor film mainly composed of silicon. In the manufacturing method of the embodiment of the present invention, it is preferable that an amorphous silicon film is used as the amorphous semiconductor layer containing a rare gas element formed on the insulating surface, and the semiconductor compound of the catalytic element is a silicide compound. . Of course, in addition to the silicon film, a germanium film, a silicon-germanium film, or the like can be used. However, the indirect transition type silicon film has better TFT off characteristics than the direct transition type germanium, and the material. It is easy to handle.
[0118]
Further, in the gettering step, by taking a method in which the deposited semiconductor compound of the catalytic element is once dissolved in the crystalline semiconductor layer and moved, a small lump that is finely dispersed and precipitated in the semiconductor film is obtained. The semiconductor compound of the catalytic element can be efficiently eliminated. Further, by introducing a rare gas element into the semiconductor film, the concentration of the catalytic element existing in a solid solution state in the crystalline semiconductor layer can be reduced in addition to the semiconductor compound of the catalytic element. The catalytic element present in a solid state in the semiconductor film has a smaller effect on the TFT characteristics than the catalytic element in the compound state, but it may become a compound state and reprecipitate when the TFT is driven. It is preferable to reduce the concentration of the catalyst element in the state, and it is preferable to reduce it by an order of magnitude or more than the solid solubility (solubility limit concentration) in the semiconductor film.
[0119]
A method of manufacturing a semiconductor device according to a preferred embodiment of the present invention includes a first step of forming an amorphous semiconductor layer containing a rare gas element on an insulating surface, and promoting crystallization of the amorphous semiconductor layer. A second step of adding a catalytic element; a third step of crystallizing the amorphous semiconductor layer by performing a first heat treatment to form a crystalline semiconductor layer; and a catalytic element in part of the crystalline semiconductor layer And a fourth step of adding a gettering element having an effect of attracting the element and a second heat treatment to move the catalyst element present in the crystalline semiconductor layer to the gettering region to which the gettering element is added. And a sixth step of forming a TFT active region (semiconductor layer) or a channel region in the active region using a crystalline semiconductor layer in a region other than the region to which the gettering element is added.
[0120]
Alternatively, a first step of forming an amorphous semiconductor layer containing a rare gas element on the insulating surface, a second step of adding a catalyst element that promotes crystallization to the amorphous semiconductor layer, A third step of crystallizing the amorphous semiconductor layer to form a crystalline semiconductor layer by performing the heat treatment of 1, and a fourth step of forming a gettering layer having an effect of attracting the catalytic element on the crystalline semiconductor layer A fifth step of performing a second heat treatment to move the catalytic element present in the crystalline semiconductor layer to the gettering layer, and using the crystalline semiconductor layer to form an active layer (at least a channel region) of the TFT. And a sixth step of forming.
[0121]
A semiconductor device obtained by these methods is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region (at least a channel region), and the TFT has an insulating surface. An active region (semiconductor layer) including a channel region, a source region, and a drain region, a gate insulating film on the active region, and a gate electrode on the gate insulating film are included. The active region (at least the channel region) is a crystalline semiconductor layer containing a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. It is preferable that at least the crystalline semiconductor layer constituting the channel region is present in a state in which substantially all of the catalytic element is dissolved in the semiconductor film.
[0122]
Here, in the second step of adding the catalyst element to the amorphous semiconductor layer, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu are used as the catalyst element. Is desirable. One or more kinds of elements selected from these have an effect of promoting crystallization in a very small amount. Among them, the most remarkable effect can be obtained particularly when Ni is used. The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. The crystal structure at that time acts as a kind of template when the amorphous silicon film is crystallized, and promotes crystallization of the amorphous silicon film. Ni is two Si and NiSi ₂ Form. NiSi ₂ Shows a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ Has a lattice constant of 5.406 Å (0.5406 nm), which is very close to the lattice constant of 5.430 Å (0.5430 nm) in the diamond structure of crystalline silicon. Therefore, NiSi ₂ Is optimal as a template for crystallizing an amorphous silicon film, and it is most desirable to use Ni as the catalyst element in the present invention.
[0123]
As a result of manufacturing the semiconductor device of the present invention using such a catalytic element, in the semiconductor device of the present invention, Ni, Co, Sn are used as catalytic elements for promoting crystallization of the amorphous semiconductor layer in the active region. One or more elements selected from Pb, Pd, Fe, and Cu are present. In addition, the concentration of the catalytic element in the active region at that time is 1 × 10 ¹⁴ ~ 1x10 ¹⁷ atoms / cm ^Three As a result, the catalyst element concentration in the gettering region or the gettering layer is increased by 2 to 4 orders of magnitude.
[0124]
Another manufacturing method in the present invention includes a first step of forming an amorphous semiconductor layer containing a rare gas element on an insulating surface, and a catalyst element for promoting crystallization of the amorphous semiconductor layer. A second step of adding, a third step of crystallizing the amorphous semiconductor layer by performing a first heat treatment to form a crystalline semiconductor layer, and a crystalline semiconductor layer (for example, using an etching method) A fourth step of forming an active region (semiconductor layer) of the TFT after patterning; a fifth step of adding a gettering element having an effect of attracting the catalytic element to the source region and the drain region of the active region; And a sixth step of performing a second heat treatment to move the catalyst element in the active region from the channel region to the source region and the drain region to which the gettering element is added. In the case of this method, since gettering is performed using the source / drain regions of the active region as compared with the above manufacturing method, there is no need to provide a dedicated extra load step for the gettering step. Can be simplified and shortened. This is because, in this method, gettering and activation of the source / drain regions can be simultaneously performed using the second heat treatment.
[0125]
A semiconductor device obtained by this method is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT has a channel region and a source region on the insulating surface. And an active region (semiconductor layer) including a drain region, a gate insulating film on the active region and a gate electrode on the gate insulating film, and the active region promotes crystallization of a rare gas element and an amorphous semiconductor layer It is preferable that substantially all of the catalytic element is dissolved in the semiconductor film at least in the channel region of the active region. At this time, it is more preferable that the concentration of the catalytic element is lower by one digit or more than the solid solubility of the crystalline semiconductor layer.
[0126]
A semiconductor device according to another embodiment is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region and a source on the insulating surface. An active region (semiconductor layer) including a region and a drain region; a gate insulating film on the active region; and a gate electrode on the gate insulating film. The active region promotes crystallization of a rare gas element and an amorphous semiconductor layer. In the active region, at least in the vicinity of the junction between the channel region and the source and drain regions, substantially all of the catalytic element exists in a solid solution state in the semiconductor film.
[0127]
A semiconductor device according to another embodiment is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region and a source region on the insulating surface. And an active region (semiconductor layer) including a drain region, a gate insulating film on the active region, and a gate electrode on the gate insulating film, and the active region is a catalyst that promotes crystallization of a rare gas element and an amorphous semiconductor layer In the source region and the drain region of the active region, the catalytic element is present at a higher concentration than the channel region.
[0128]
Still another embodiment of the semiconductor device is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT has a channel region on the insulating surface. , Including an active region (semiconductor layer) including a source region and a drain region, a gate insulating film on the active region and a gate electrode on the gate insulating film, and the active region promotes crystallization of a rare gas element and an amorphous semiconductor layer In the active region, the source region and the drain region are present in a higher concentration than the vicinity of the junction between the channel region, the source region, and the drain region.
[0129]
That is, a semiconductor device obtained by using a method in which a gettering element is added to the source / drain region and the catalyst element in the active region is moved from the subsequent channel region to the source / drain region by the second heat treatment. Then, in the source region and the drain region of the active region, the catalyst element is 1 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three Is present at a concentration of On the other hand, the catalyst element concentration in the channel region at this time or in the vicinity of the junction between the channel region and the source region and the drain region is 1 × 10 ¹⁴ ~ 1x10 ¹⁷ atoms / cm ^Three It is reduced to the extent of the degree. Here, the vicinity of the junction between the channel region of the active region and the source and drain regions is preferably a region within a range of 2 μm from the junction boundary between the channel region and the source and drain regions. This is because the effect of electric field concentration at the junction occurs within a range of 2 μm from the junction.
[0130]
In still another embodiment of the semiconductor device, the source region and drain region of the active region contain an impurity element belonging to Group B of the periodic table that imparts n-type conductivity. Alternatively, one or more kinds of rare gas elements selected from argon (Ar), krypton (Kr), and xenon (Xe) are contained in the source region and the drain region of the active region more than other regions in the active region. Contained in high concentration. Alternatively, the source region and the drain region of the active region contain one or more kinds of rare gas elements having an atomic number larger than that of the rare gas element contained in the active region. This is because impurity elements belonging to Group B of the periodic table and rare gas elements such as Ar, Kr, and Xe function as gettering elements. When a rare gas element is used as the gettering element, the semiconductor layer according to the present invention also contains a rare gas element in the channel region in the active region. Therefore, in order to move the catalyst element from the channel region to the source / drain region, It is preferable that the concentration of the rare gas element in the source / drain region be higher than the concentration of the rare gas element contained in the channel region. In addition, since the gettering efficiency when using a rare gas element as a gettering element is higher as the atomic number (atomic weight) is larger, the rare gas element having a larger atomic number than the rare gas element originally contained in the active region. It is also effective to introduce as a gettering element into the source / drain region. Details of the gettering element will be described later.
[0131]
In another embodiment of the manufacturing method according to the present invention, a first step of forming an amorphous semiconductor layer containing a rare gas element on an insulating surface and crystallization of the amorphous semiconductor layer are promoted. A second step of adding a catalytic element, a third step of crystallizing the amorphous semiconductor layer by performing a first heat treatment to form a crystalline semiconductor layer, and patterning (for example, etching) the crystalline semiconductor layer ) To form a TFT active region (semiconductor layer) later, and a gettering element having an effect of attracting the catalytic element to the region other than the channel region, source region and drain region in the active region. A sixth step of adding and forming a gettering region and a second heat treatment to move the catalytic element in the active region from the channel region, the source region, and the drain region to the gettering region Having at least the door.
[0132]
Further, the formation of the gettering region in the fifth step is performed in a region other than the region where the gettering region is adjacent to the source region and / or the drain region and electrons or holes move in the active region. And a step of forming a wiring for electrically connecting the TFTs in the source region and the drain region. The wiring formation step is performed so that the wiring includes at least a part of the source region and the drain region. Even in this method, the second heat treatment can be used to simultaneously perform gettering and activation of the source / drain regions, and there is no need to provide a dedicated extra load step for the gettering step. The process can be simplified and shortened. Furthermore, since a dedicated gettering region is provided separately from the source / drain region in the active region, the gettering region can be optimized as compared with the above-described method in which the source / drain region is also used as the gettering region. it can. This is because in the above-described method in which the source / drain regions are also used as gettering regions, it is necessary to maintain the function (particularly low resistance) as the source / drain regions, and there are significant restrictions due to this. However, the gettering region is preferably arranged so as not to hinder the movement of carriers (electrons or holes) in at least the active region as described above.
[0133]
A semiconductor device obtained by this manufacturing method is a semiconductor device including a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region and a source on the insulating surface. An active region (semiconductor layer) including a region and a drain region, a gettering region, a gate insulating film on the active region and a gate electrode on the gate insulating film, and the active region includes a crystal of a rare gas element and an amorphous semiconductor layer It is preferable that substantially all of the catalytic elements are present in a solid solution in the semiconductor film at least in the channel region of the active region.
[0134]
Alternatively, the semiconductor device includes a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region, a source region and a drain region, and a gettering region on the insulating surface. Including an active region (semiconductor layer), a gate insulating film on the active region, and a gate electrode on the gate insulating film. The active region includes a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. In addition, at least in the vicinity of the junction between the channel region and the source region and drain region of the active region, substantially all of the catalytic element may exist in a solid solution state in the semiconductor film.
[0135]
Alternatively, the semiconductor device includes a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region, a source region and a drain region, and a gettering region on the insulating surface. Including an active region (semiconductor layer), a gate insulating film on the active region, and a gate electrode on the gate insulating film. The active region includes a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. In addition, it is preferable that at least the channel region, the source region, and the drain region of the active region are present in a state where substantially all the catalytic elements are in solid solution in the semiconductor film.
[0136]
From another viewpoint, focusing on the positional relationship with the gettering region, the semiconductor device according to an embodiment of the present invention is a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region. The TFT includes a channel region, a source region and a drain region, an active region (semiconductor layer) including a gettering region on an insulating surface, and a gate insulating film and a gate insulating film on the active region. The active region includes a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. The active region gettering region has a higher concentration of the catalytic element than the channel region. Existing.
[0137]
Alternatively, the semiconductor device includes a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region, a source region and a drain region, and a gettering region on the insulating surface. Including an active region (semiconductor layer), a gate insulating film on the active region, and a gate electrode on the gate insulating film. The active region includes a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. In addition, in the gettering region of the active region, the catalytic element is present at a higher concentration than the vicinity of the junction between the channel region and the source and drain regions.
[0138]
Alternatively, the semiconductor device includes a TFT having a crystalline semiconductor layer formed on an insulating surface as an active region, and the TFT includes a channel region, a source region and a drain region, and a gettering region on the insulating surface. Including an active region (semiconductor layer), a gate insulating film on the active region, and a gate electrode on the gate insulating film. The active region includes a rare gas element and a catalytic element that promotes crystallization of the amorphous semiconductor layer. The gettering region of the active region includes a higher concentration of the catalytic element than the channel region, the source region, and the drain region.
[0139]
Further, in these semiconductor devices, the gettering region in the active region is adjacent to the source region and / or the drain region, and is formed in a region other than the region where electrons or holes move in the active region. A wiring for electrically connecting the TFTs in the region is connected so as to include at least a part of the source region and the drain region.
[0140]
That is, a dedicated gettering region is provided in the active region separately from the source / drain regions, and this region is maintained even after the TFT is completed. This is not only the structure obtained as a result of the manufacturing method, but it is advantageous to always provide a gettering region in the device. In other words, when there is no gettering region in the element, a considerable amount of heat is generated by driving the TFT, and in rare cases, a new semiconductor compound is precipitated from the remaining catalyst element at a concentration lower than the solid solubility. Because there are cases. In this respect, a structure having a strong gettering region in the active region even after the completion of the semiconductor device has a gettering capability even when driving the TFT, and such precipitation is unlikely to occur. Furthermore, since the gettering region can be optimized as a dedicated area, a strong gettering capability can be provided. As a result, the reliability of the TFT can be further increased. However, since the gettering region is optimized for gettering ignoring characteristics such as resistance, the arrangement of the gettering region prevents the movement of carriers (electrons or holes) at least in the active region as described above. It is desirable to arrange so that there is no.
[0141]
As described above, when the method of adding a gettering element to the gettering region and moving the catalytic element in the active region to the gettering region by the second heat treatment, the obtained semiconductor device has the active region. In the gettering region, the catalyst element is 1 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three Is present at a concentration of On the other hand, the catalyst element concentration in the channel region at this time, in the vicinity of the junction between the channel region and the source / drain region, or in the entire channel region and the source / drain region is 1 × 10 ¹⁴ ~ 1x10 ¹⁷ atoms / cm ^Three It is reduced to the extent of the degree.
[0142]
In addition, it is desirable that the gettering region of the active region contains more amorphous components than other regions in the active region. The content of the amorphous component can be determined by performing microscopic laser Raman spectroscopy measurement on each region, and the gettering region is amorphous in the Raman spectrum compared to other regions in the active region. The ratio Pa / Pc between the TO phonon peak Pa of the crystalline Si and the TO phonon peak Pc of the crystalline Si is preferably large.
[0143]
As the mechanism of the gettering region, the solid solubility of the catalyst element in that region is increased from the other regions, the catalyst element is moved there (first gettering effect), and the catalyst element is trapped. There is an action (second gettering action) in which a defect or a local segregation site is formed and the catalytic element is moved and trapped there. That is, the gettering region of the active region is configured to contain more amorphous components than the other regions in the active region, whereby the effect of the second gettering action can be brought out. . It is important to maintain this state even after the TFT is completed. If the gettering region in an amorphous state is crystallized in the middle of the process, the subsequent gettering action is reduced, and it is temporarily moved by heat treatment. In some cases, the catalyst element thus caused flows backward in the subsequent process. Even if such a backflow of the catalytic element is prevented in the manufacturing process, a considerable amount of heat is generated by driving the TFT, and the catalytic element once moved to the gettering region moves to the channel region when driving the TFT. In some cases, problems occur in reliability. Therefore, when a gettering region is provided in the active region of the TFT, the region is maintained in an amorphous state even when the TFT is completed, and always has the same level of gettering capability as in the gettering step. It is desirable.
[0144]
Further, in such a semiconductor device configuration and manufacturing method thereof, the TFT active region has a gettering region in addition to the source region and the drain region, and the gettering region moves TFT carriers (electrons or holes). The source / drain regions are not affected by gettering, and the amount of addition of n-type impurities and p-type impurities is optimally set as a separate process. be able to. That is, even if the gettering region is configured to contain an amorphous component, the TFT is not affected at all by the high resistance. As a result, the process margin is widened, the throughput of the doping apparatus can be greatly improved, the resistance of the source / drain can be reduced, and the on-characteristics of the TFT can be improved.
[0145]
The gettering region in the active region includes an impurity element belonging to Group B of the periodic table that imparts n-type and an impurity element belonging to Group B of the periodic table that imparts p-type. Preferably it is. Alternatively, the gettering region of the active region preferably contains one or more kinds of rare gas elements selected from Ar, Kr, and Xe at a higher concentration than other regions in the active region. Alternatively, the gettering region of the active region preferably contains one or more kinds of rare gas elements having an atomic number larger than that of the rare gas element contained in the active region. This is because, as described above, an impurity element belonging to Group B of the periodic table or a rare gas element such as Ar, Kr, or Xe has a function as a gettering element. This is because the larger the (atomic weight), the higher the gettering effect.
[0146]
In addition, in the semiconductor device configuration described above, a gettering element is added to the source / drain region of the active region, and the catalytic element is thermally moved to the region, and a dedicated gettering region is provided in the active region. In the method of forming and thermally moving the catalyst element to the region, the second heat treatment for gettering is performed while also activating the source / drain regions. That is, since the second heat treatment is performed after the gate electrode is formed, the material of the gate electrode is an element selected from W, Ta, Ti, and Mo, which is a high-melting metal having high heat resistance, It is desirable to select from one or more elemental alloy materials.
[0147]
Now, in the manufacturing method of a semiconductor film of the present invention, that is, the rare gas element contained in the amorphous semiconductor layer in the active region of the semiconductor device of the present invention includes argon (Ar), krypton (Kr), It is desirable that the element is one or more elements selected from xenon (Xe). With these rare gas elements, the effects of the present invention as described above are particularly high, the generation density of crystal nuclei during crystallization can be increased, the amount of addition of catalyst elements can be greatly reduced, and further agglomerated and precipitated after crystallization. It is possible to finely disperse the semiconductor compound of the catalytic element being used, to reduce the size of each lump, and to form a state that is easily gettered in a later gettering step.
[0148]
In the present invention, the concentration of the rare gas element in the active region (at least the channel region) of the semiconductor device is 5 × 10 5. ¹⁶ atoms / cm ^Three 5 × 10 or more ¹⁸ atoms / cm ^Three It is desirable to be within the following range. A preferable concentration range of the rare gas element will be described with reference to experimental data performed by the present inventor on the concentration of the rare gas element shown in FIG. Here, a silicon film is used as the semiconductor film, nickel is used as the catalyst element, and argon is used as the rare gas element.
[0149]
FIG. 24A shows the relationship between the Ar concentration in the silicon film and the crystal nucleus generation density during crystallization. The crystal nucleus generation density on the vertical axis was measured by the same method as in FIG. FIG. 24B shows the relationship between the Ar concentration in the silicon film and the size of the catalytic element compound (Ni silicide) deposited after crystallization. With respect to the size of Ni silicide, hydrofluoric acid treatment for revealing was performed, SEM observation as shown in FIG. 23 was performed, and individual sizes were measured as etch pits. In FIG. 24A and FIG. 24B, the data point at the left end plots the result of the silicon film containing no rare gas element, and the Ar concentration was below the lower limit of measurement.
[0150]
From FIG. 24A, even when Ar is added to the silicon film, the concentration is 5 × 10 5. ¹⁶ atoms / cm ^Three When it is lower than (line 271), it can be seen that no effect of increasing the nucleation density is observed. Ar concentration is 5 × 10 ¹⁶ atoms / cm ^Three Above (line 271), a significant increase in nucleation density is observed. That is, the concentration of the rare gas element introduced into the amorphous silicon film is 5 × 10. ¹⁶ atoms / cm ^Three It turns out that it is preferable above.
[0151]
As can be seen from FIG. 24B, the size of Ni silicide varies greatly from small to large even under the same conditions (error bar in the figure), but when the concentration of the line 271 is exceeded, Ni silicide As a result, there is a tendency that the overall size of Ni is reduced, and particularly large lumps of Ni silicide cannot be seen. When the Ar concentration is further increased, the nucleus generation density is increased in FIG. 24A, and the size of Ni silicide is reduced in FIG. 24B, but it is almost saturated. There is no merit to raise. On the contrary, the concentration 5 × 10 shown in FIG. 24 (A) and FIG. 24 (B). ¹⁸ atoms / cm ^Three When exceeding (line 272), Ar contained in the amorphous silicon film has an adverse effect on the crystalline state, and the merit of high quality crystallinity obtained by adding the catalytic element is impaired. However, since the mobility of the semiconductor layer may decrease, the concentration of the rare gas element contained in the active region is 5 × 10 5. ¹⁶ atoms / cm ^Three 5 × 10 or more ¹⁸ atoms / cm ^Three It is preferable to be within the following range.
[0152]
He stated that if the concentration of the rare gas element contained in the amorphous semiconductor layer before the introduction of the catalytic element increases, it adversely affects the crystal growth and a high-quality crystalline semiconductor layer based on the catalytic element cannot be realized. Next, the crystal state and crystallinity of the crystalline semiconductor layer constituting the active region in the present invention will be described.
[0153]
The crystalline semiconductor film (used for forming the active region or at least the channel region of the active region) according to the present invention has a crystal plane orientation mainly composed of <111> crystal zone planes. More specifically, the ratio of the plane orientation of the crystalline semiconductor film occupies a region of 50% or more of the (110) plane orientation and (211) plane orientation in the <111> crystal zone plane. ing. In general, in crystallization without using a catalytic element, the plane orientation of the crystalline semiconductor film tends to be (111) due to the influence of the insulator underlying the semiconductor film (particularly in the case of amorphous silicon dioxide). On the other hand, a schematic diagram showing how the plane orientation of a crystalline semiconductor film obtained when a catalytic element is added to an amorphous semiconductor film and crystallized is mainly composed of <111> crystal zone planes. 25 (A). In FIG. 25A, 281 is a base insulator, 282 is an amorphous semiconductor layer in an uncrystallized region, 283 is a crystalline semiconductor layer, and 284 is a semiconductor compound of a catalytic element serving as a driving force for crystal growth. is there.
[0154]
As shown in FIG. 25A, the catalytic element compound 284 is present at the forefront of crystal growth, and the adjacent amorphous regions 282 are crystallized one after another toward the right side of the drawing. The catalytic element compound 284 has a property of growing strongly in the <111> direction. As a result, as the plane orientation of the obtained crystalline semiconductor film, a <111> crystal zone plane appears as shown in FIG.
[0155]
FIG. 25B shows a <111> crystal zone plane. In FIG. 25B, the horizontal axis represents the inclination angle from the (-100) plane, and the vertical axis represents the surface energy. The group 285 is a crystal plane that becomes a <111> crystal zone plane. The (100) plane and the (111) plane are not <111> crystal zone planes, but are shown for comparison.
[0156]
FIG. 25C shows a standard triangle of crystal orientation. Here, the distribution of the <111> crystal zone plane is as shown by a broken line. The numbers are typical pole indices. Among these <111> crystal zone planes, in the crystalline semiconductor film obtained by the present invention, the (110) plane or (211) plane is predominantly oriented, and these planes occupy 50% or more of the entire plane. Superiority is obtained. These two crystal planes have a very high hole mobility compared to the other planes, can improve the performance of P-channel TFTs that are inferior to N-channel TFTs, and are easily balanced in semiconductor circuits. There are benefits.
[0157]
As described above, when the concentration of the rare gas element contained in the amorphous semiconductor film is too high, that is, when the upper limit line 272 in FIG. 24 is exceeded, such plane orientation collapses, and the plane orientation is shown in FIG. ) Begins to deviate in the direction of 111 points from the distribution on the <111> crystal zone plane indicated by a broken line in the standard triangle. That is, there is a tendency to approach a crystalline state of random orientation when no catalyst element is used.
[0158]
An example of the plane orientation distribution of the crystalline semiconductor film obtained by the present invention is shown in FIG. FIG. 26 shows the measurement result of the backscattered electron diffraction image (EBSP). The crystal orientation is divided into individual minute regions, which are connected and mapped. FIG. 26A shows a plane orientation distribution in the crystalline semiconductor layer of the present invention. FIG. 26B shows a plane between adjacent mapping points based on the data in FIG. Those having an azimuth inclination of a certain value or less (here, 5 ° or less) are painted with the same color, and the distribution of individual crystal grains (crystal grains: regions having substantially the same plane orientation) is highlighted. FIG. 26C shows the standard triangle of the crystal orientation described with reference to FIG.
[0159]
As can be seen from FIG. 26 (C), the crystalline semiconductor layer according to the present invention generally exhibits a plane orientation on the <111> crystal zone, and is particularly strongly oriented in (110) and (211). I understand. In the present invention, the nucleation density is increased by the action of the rare gas element contained in the semiconductor film, and the size of each crystal grain shown in FIG. 26B is distributed in the range of 2 μm to 10 μm. . Therefore, the semiconductor device of the present invention has a crystalline semiconductor layer having a crystal grain size in the range of 2 μm to 10 μm as its active region or at least a channel region. The crystalline state of the crystalline semiconductor layer according to the present invention (that is, the plane orientation and the ratio of plane orientation, the grain size of crystal grains) is characterized by EBSP measurement.
[0160]
Next, a process of forming an amorphous semiconductor layer containing a rare gas element in the method for manufacturing a semiconductor film of the present invention will be described.
[0161]
In the manufacturing method of the present invention, the step of forming the amorphous semiconductor layer containing a rare gas element is most preferably performed by introducing a rare gas element during film formation using a plasma CVD method. Instead of the above method, an amorphous semiconductor layer may be formed first, and then the amorphous semiconductor film may be ion-doped with a rare gas element. The latter method is excellent in terms of controllability of the rare gas element concentration, but requires an expensive doping apparatus in addition to the film forming apparatus, and the film formation and doping are performed in separate processes. There is a demerit of cost. In addition to the above two methods, there is a method in which a rare gas is used as a sputtering gas and an amorphous semiconductor layer is formed by sputtering using a semiconductor target. In this method, discharge by RF or pulse DC is performed. This is indispensable. In particular, when the substrate size is large, it is difficult to obtain a stable discharge, and there are problems that the number of particles specific to sputtering is very large.
[0162]
On the other hand, in the plasma CVD method, mass production apparatuses for large sized glass substrates are generally on the market, and chamber cleaning with a cleaning gas can be performed, so that particle countermeasures are good. However, since the film is formed by a chemical reaction, a rare gas element that is inert to the chemical reaction is simply introduced as a film forming gas, but only acts as a carrier gas in the semiconductor film. It is hard to be included.
[0163]
Therefore, in a preferred embodiment, the step of forming the amorphous semiconductor layer containing a rare gas element on the insulating surface of the substrate uses a plasma CVD method, and the rare gas element is placed in a chamber (CVD reaction chamber) during film formation. In addition to the CVD electrode that is introduced into the substrate and generates plasma, a separate bias is also applied to the substrate side (substrate holder that receives the substrate) having an insulating surface on which an amorphous semiconductor layer is formed. Perform with dual bias. Furthermore, in another preferred embodiment, the step of forming the amorphous semiconductor layer containing a rare gas element uses a plasma CVD method, introduces a rare gas element during film formation, applies an RF bias to the CVD electrode, A two-frequency method is also applied in which an RF bias having a frequency different from that of the CVD electrode is applied to the substrate side.
[0164]
In this way, the present inventor uses a semiconductor material gas and a rare gas element as at least a source gas in a plasma CVD process, and forms a film with a dual bias that separately applies a separate bias to the substrate side in addition to the CVD electrode. It was found that an amorphous semiconductor layer containing a large amount of a rare gas element can be formed by performing the above.
[0165]
As the bias at this time, the method of applying the RF bias to the CVD electrode and applying the RF bias alone to the substrate side is the most effective, and the obtained non-biased value is higher than the case of applying the DC bias to the substrate side. The content of rare gas elements in the crystalline semiconductor film (for example, amorphous silicon film) was higher. However, even when a DC voltage was applied to the substrate side, the effect was of course seen as compared with the case where no bias was applied. Further, the frequency of the RF bias applied to the CVD electrode and the frequency of the RF bias applied to the substrate (insulator) side are different from each other, and the RF bias applied to the substrate side is higher than the frequency of the RF bias applied to the CVD electrode. It is desirable that the bias frequency is smaller. With such a configuration, a stable discharge with good plasma matching can be obtained.
[0166]
Next, the configuration of a semiconductor manufacturing apparatus suitably used for executing the manufacturing method according to the present invention will be described.
[0167]
A semiconductor manufacturing apparatus according to the present invention is a plasma CVD apparatus for forming an amorphous semiconductor layer containing a rare gas element, and the plasma CVD apparatus includes a CVD electrode and an amorphous film in a CVD reaction chamber (chamber). It has a substrate holder in contact with the substrate on which the semiconductor layer is formed, and further has a power supply power source. The potential of the CVD chamber is grounded, and the potential on the CVD electrode side and the amorphous semiconductor layer are formed. The potential on the side of the substrate holder in contact with the substrate to be filmed is independent from the CVD chamber, and is connected to the power supply power source connected to the CVD electrode and the substrate holder in contact with the substrate on which the amorphous semiconductor layer is formed. It is different from the power supply power source, and the CVD chamber is provided with at least gas introduction ports for semiconductor film forming material gas and rare gas. Furthermore, the power supply power source connected to the CVD electrode and the power supply power source connected to the substrate holder in contact with the substrate on which the amorphous semiconductor layer is formed are each an RF power supply power source (RF oscillation source). Is preferred.
[0168]
Here, the power supply power source or the RF power supply power source connected to the CVD electrode is compared with the power supply power source or the RF power supply power source connected to the substrate holder in contact with the substrate on which the amorphous semiconductor layer is formed. The power capacity is preferably equal or higher. Furthermore, the RF frequency of the RF power supply power source connected to the CVD electrode is preferably larger than the RF frequency of the RF power supply power source connected to the substrate holder in contact with the substrate on which the amorphous semiconductor layer is formed. .
[0169]
A structure of a plasma CVD apparatus suitably used for manufacturing a semiconductor film according to the present invention will be described with reference to FIGS. FIG. 15A is a diagram schematically showing the configuration of a known plasma CVD apparatus, and FIG. 15B schematically shows an example of the configuration of the plasma CVD apparatus used in the embodiment of the present invention. .
[0170]
In the normal plasma CVD shown in FIG. 15A, the substrate 151 is grounded and has the same potential as the chamber 153. Then, RF power 154 is supplied to the CVD electrode 152 to form a film. On the other hand, in the CVD apparatus shown in FIG. 15B, the potential of the substrate 151 is independent from the CVD chamber 153, and the RF power 154 supplied to the CVD electrode 152 is different from the RF power supplied from the RF power 154. Power 155 is supplied. The CVD chamber 153 is grounded. When a rare gas is used as a deposition gas in such a configuration, an amorphous semiconductor film in which a rare gas element is contained in the film as described above can be easily obtained. Here, as the power supply power source, the effect can be obtained even with DC especially on the substrate 151 side, but RF is more effective for increasing the content of the rare gas element. Further, the RF power 154 supplied to the CVD electrode 152 is larger than the RF power 155 supplied to the substrate 151 side, and the RF frequency supplied to the CVD electrode 152 is the RF frequency supplied to the substrate 151 side. A higher value is preferable because the stability of the plasma increases.
[0171]
Another semiconductor manufacturing apparatus suitably used in the semiconductor film manufacturing method of the present invention has a configuration in which a plurality of CVD chambers are connected to each other directly or indirectly via a vacuum chamber (so-called multi-chamber configuration). )have. At least one of the plurality of CVD chambers is configured by a dual-bias or dual-frequency plasma CVD chamber having the configuration described above with reference to FIG. 15B, and at least one of the other CVD chambers. One CVD chamber is configured as a chamber for forming an insulating film (protective film).
[0172]
FIG. 16 schematically shows the chamber configuration of the multi-chamber plasma CVD apparatus having such a configuration according to the present invention. The semiconductor manufacturing apparatus according to the embodiment of the present invention shown in FIG. 16 includes a cassette station 161, load lock chambers 162 and 163, four plasma CVD chambers 164 to 167, and a cluster chamber 168.
[0173]
First, a cassette containing substrates is set in the cassette station 161. The substrate is sent to the load lock chambers 162 and 163 by the robot, where it is evacuated to a reduced pressure state. Although the load lock chamber may be one, the work efficiency is improved by adopting the two-room configuration as shown in FIG. The four plasma CVD chambers 164 to 167 are connected to the rod lock chambers 162 and 163 by a cluster chamber 168, and all these chambers are kept in a reduced pressure state. After the atmosphere in the load lock chambers 162 and 163 is replaced under reduced pressure, the substrate is sent to each plasma CVD chamber 164 to 167 by the robot in the cluster chamber 168. In FIG. 16, four plasma CVD chambers are provided, but one may be a preheat chamber for preheating the substrate. By adopting such a configuration, when different film types are successively formed on the substrate, the substrate can be transferred to another CVD chamber without being exposed to the atmosphere, and in a vacuum (or reduced pressure atmosphere). Continuous film formation is possible. By using such an apparatus, in the present invention, an amorphous semiconductor containing a rare gas element and a lower insulating film can be continuously formed. These interfaces serve as back channels in the TFT and greatly affect the TFT characteristics and reliability. Therefore, it is desirable to keep them clean, and the semiconductor manufacturing apparatus of the present invention can easily realize this.
[0174]
In the entire semiconductor film manufacturing method of the present invention as described above, a catalytic element is added to an amorphous semiconductor layer containing a rare gas element, and the first heat treatment is performed to crystallize the amorphous semiconductor layer. In the crystallization step, the catalytic element is selectively added to a part of the amorphous semiconductor layer, and the first heat treatment is performed, so that the region where the catalytic element is selectively added is laterally transferred to the periphery thereof. It is preferable to carry out crystal growth in the direction. By doing this, in the region where the crystal is grown in the lateral direction, the crystal growth direction is almost uniform (typically, the <111> crystal zone plane is aligned in the growth direction). Thus, the current driving capability of the TFT can be further increased. Also, in this laterally grown region, the concentration of the catalytic element in the film after crystal growth can be reduced by 1 to 2 orders of magnitude compared to the region where the catalytic element is directly added, so the load on the subsequent gettering process is reduced. can do.
[0175]
Furthermore, in a preferable embodiment of the present invention, after the (first) heat treatment for crystallization, a step of irradiating the crystalline semiconductor layer with laser light is included. When laser light is irradiated to the crystalline semiconductor layer, the crystal grain boundary part and minute residual amorphous region (uncrystallized region) are processed intensively due to the difference in melting point between the crystalline part and the amorphous part. The The crystalline silicon film crystallized by introducing the catalytic element is formed of columnar crystals and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary is treated by laser light irradiation, the entire surface of the substrate is covered. Thus, a high-quality crystalline silicon film close to a single crystal state is obtained, and crystallinity is greatly improved. As a result, the on-characteristics of the TFT are greatly improved, and a semiconductor device superior in current drive capability can be realized.
[0176]
The crystalline semiconductor film (low concentration region) of the embodiment according to the present invention preferably has an average surface roughness Ra within a range of 4 nm to 9 nm. As can be seen from the SEM photograph of FIG. 23, the surface of the crystalline semiconductor film is uneven. This occurs at the boundary due to the difference in volume expansion coefficient when the semiconductor film is melted, solidified and recrystallized by irradiating laser light, and is generally called a ridge. If the average surface roughness at this time is less than 4 nm, the laser power may be insufficient, and the crystallinity may not be sufficiently improved. On the other hand, if the average surface roughness Ra is more than 9 nm, the laser power is excessive, so that the crystallinity is locally deteriorated and the variation becomes large, and the influence on the reliability (gate insulating film breakdown voltage) is concerned.
[0177]
In the method of manufacturing a semiconductor film according to an embodiment of the present invention, the fourth step of adding a gettering element having an effect of attracting a catalytic element to a part of a crystalline semiconductor layer is performed by an ion doping method. The region to which the element is added (gettering region) is more amorphous than the other regions. That is, by making the gettering region amorphous, crystal defects or local segregation sites that trap the catalytic element can be actively formed, and the second gettering action described above can be used. . In this manufacturing method, for example, if the gettering region is formed outside the active region, the gettering region does not remain in the active region after the second gettering step, and even if the gettering region is made amorphous, there is a problem. Don't be.
[0178]
Further, when a method of adding a gettering element to the source / drain region of the active region and moving the catalyst element thereto is adopted, the fifth step of adding the gettering element to the source region and the drain region of the active region includes: The source and drain regions, which are formed by an ion doping method and to which a gettering element is added, are more amorphous than the channel region. Also in this case, the second gettering action can be brought out by making the source / drain regions amorphous. However, since the source / drain regions function as TFTs, the resistance must finally be reduced. Therefore, it is preferable to recover the crystallinity to some extent during the second heat treatment time for gettering after the amorphization is once advanced.
[0179]
In addition, when a manufacturing method in which a dedicated gettering region is formed in the active region separately from the source / drain regions, a gettering element is added to the channel region in the active region and the regions other than the source region and the drain region. The fifth step of forming the ring region is performed by an ion doping method, and the gettering region to which the gettering element is added is more amorphous than the channel region, the source region, and the drain region. Also in this case, the second gettering action can be brought out by making the gettering region amorphous. In this case, the gettering region may remain in an amorphous state after the TFT is completed, and the degree of freedom of the process is high. As described above, it is preferable that the semiconductor device has a gettering region in the active region, and the gettering region contains many amorphous components.
[0180]
As the gettering element used in the method for producing a semiconductor film of the present invention, first, it is preferable to use one or more kinds of elements belonging to Group B of the periodic table selected from P, As, and Sb. When these elements belonging to Group 5B of the periodic table are introduced into the silicon film, the solid solubility of the catalytic element in that region increases, that is, the gettering effect is obtained by utilizing the first gettering action described above. A move is made. Among these elements, phosphorus is particularly effective. In addition, these elements can be used as they are as source / drain regions in an N-channel TFT.
[0181]
Furthermore, in addition to one or more types of periodic table group 5 B selected from P, As, and Sb as gettering elements, one or more types of periodic table selected from B and Al. It is more desirable to use together with an element belonging to Group 3 B. Only the Group 5 B element has a gettering ability, but it has been found that a larger gettering effect can be obtained when a Group 3 B element is also introduced. When the silicon film in the gettering region is doped with boron as well as phosphorus, the gettering mechanism changes. In the case of only phosphorus, diffusion transfer type gettering (the first gettering action described above) using the difference in solid solubility of the catalytic element from the non-doped non-gettering region, but also contains boron. On the contrary, the catalytic element is likely to precipitate in the gettering region, gettering to the defect or segregation site (the above-mentioned second gettering action) becomes dominant, and the effect is synergistically enhanced. However, since an element for imparting P-type is superimposed on an element for imparting N-type, gettering regions into which these elements are introduced are likely to have high resistance, and exclusive getters other than the source / drain regions are provided. It is more effective in the method of providing the ring region. The concentration of the impurity element contained in the gettering region at this time is 1 × 10 for elements belonging to Group B of the periodic table. ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three The element belonging to Group 3 B of the periodic table is preferably 1.5 × 10 5. ¹⁹ ~ 3x10 ^{twenty one} / Cm ^Three It is preferable that it exists in the density range. In any case, if the concentration is within this range, sufficient gettering efficiency can be obtained.
[0182]
As another gettering element used in the method for producing a semiconductor film of the present invention, one or more kinds of rare gas elements selected from Ar, Kr, and Xe can be used. When these rare gas elements are present in the gettering region, large interstitial distortion occurs there, and the second gettering action due to defects / segregation sites is very powerful. At this time, the concentration of the rare gas element contained in the gettering region is 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three If it is within the range, sufficient gettering efficiency can be obtained.
[0183]
Furthermore, in the method for manufacturing a semiconductor film of the present invention, when such a rare gas element is used as a gettering element, one or more having a larger atomic number than the rare gas element species contained in the amorphous semiconductor layer It is desirable to use a kind of rare gas element. The gettering efficiency when a rare gas element is used as a gettering element is higher as the atomic number (atomic weight) is larger. In the present invention, almost all of the crystalline semiconductor film (low concentration region) contains a rare gas element. Therefore, in order to move the catalytic element to the gettering region, the rare gas element species originally contained in the active region is used. It is more effective to use a rare gas element species having a larger atomic number as a gettering element.
[0184]
According to a preferred embodiment of the present invention, a method of manufacturing a semiconductor film includes forming a gettering layer having an effect of attracting a catalytic element on a crystalline semiconductor layer, performing a second heat treatment, and remaining on the crystalline semiconductor layer. A step of moving the catalytic element to be moved to the gettering layer. In this method, the second heat treatment is performed, and after the fifth step (gettering step) of moving the catalytic element remaining in the crystalline semiconductor layer to the gettering layer, the step of removing the gettering layer is performed. Further, it may be included. In this way, unlike other methods, a crystalline semiconductor layer having a low catalyst concentration over almost the entire surface without a region (gettering region) where the catalytic elements are collected on the entire surface of the substrate is obtained. The degree of freedom of process and design layout can be increased.
[0185]
Here, as the gettering layer, it is desirable to use an amorphous semiconductor layer containing one or more kinds of elements belonging to Group B of the periodic table selected from P, As, and Sb. Alternatively, as the gettering layer, one or more kinds of periodic table group 5 B elements selected from P, As, and Sb, and one or more kinds of periodic table group 3 B selected from B and Al are used. It is desirable to use an amorphous semiconductor layer containing both elements belonging to the above. The reason for using the amorphous semiconductor film is that, as described above, the second gettering action utilizing the crystal defects / segregation sites can be brought out. The reason for including the element species is that the element species functions as a gettering element as described above.
[0186]
In addition to the above gettering layers that can be used, one or more kinds of rare gas elements selected from Ar, Kr, and Xe are used at a higher concentration than the rare gas concentration contained in the crystalline semiconductor layer. It is desirable to use an amorphous semiconductor layer contained therein. Alternatively, it is desirable to use an amorphous semiconductor layer containing a rare gas element species having an atomic number larger than that of the rare gas element species contained in the crystalline semiconductor layer as the gettering layer. When an amorphous semiconductor layer containing a rare gas element is used as a gettering layer, balance with the rare gas element contained in the lower crystalline semiconductor layer is important. Therefore, the condition of the gettering layer is that the rare gas element concentration needs to be higher than the rare gas element concentration contained in the lower crystalline semiconductor layer, and the gettering efficiency is high. It is preferable to use it for the ring layer.
[0187]
(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. Here, a method for manufacturing over an n-channel TFT glass substrate will be described. The TFT of this embodiment can be used as an element constituting a thin film integrated circuit as well as a driver circuit and a pixel portion of an active matrix type liquid crystal display device or an organic EL display device. FIG. 1 is a cross-sectional view showing a manufacturing process of an n-channel TFT described here, and the manufacturing process sequentially proceeds in the order of (A) → (H).
[0188]
First, as shown in FIG. 1A, a base film 103 made of silicon oxide having a thickness of about 300 to 500 nm is formed on a glass substrate 101 by, for example, a plasma CVD method. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate. Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 104 having a thickness of about 20 to 80 nm, for example, 40 nm is formed.
[0189]
The a-Si film 104 is formed by a plasma CVD method using a silane-based gas and a rare gas as material gases. At this time, a rare gas element can be easily included in the a-Si film 104 by using a dual-bias or dual-frequency plasma CVD apparatus as shown in FIG. Further, even in a normal plasma CVD apparatus as shown in FIG. 15A, the substrate heating temperature is lowered, the gas pressure at the time of film formation is reduced, and the gas flow ratio of silane gas / rare gas is reduced. In the direction, the concentration of the rare gas element contained in the a-Si film 104 to be formed can be increased to some extent. In this way, the rare gas element concentration in the film is 5 × 10 5. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three An a-Si film 104 is obtained.
[0190]
Examples of rare gas element species that can be used here include argon (Ar), krypton (Kr), and xenon (Xe). In this embodiment, SiH _Four The a-Si film 104 was formed using a dual-frequency parallel plate plasma CVD apparatus shown in FIG. The substrate heating temperature at this time is 350 ° C., and the gas flow rate is SiH. _Four The gas was 100 sccm and the Ar gas was 1000 sccm. The gas pressure was 0.7 Torr, the RF frequency supplied to the CVD electrode was 27.1 MHz, the RF power was 100 W, the RF frequency supplied to the substrate side was 1.6 MHz, and the RF power was 50 W. The Ar concentration in the a-Si film 104 thus obtained is about 5 × 10 ¹⁷ atoms / cm ^Three It was about. Note that the method for forming the a-Si film 104 containing a rare gas element and the film formation conditions may be appropriately selected and set by the practitioner regardless of the above methods and conditions.
[0191]
Next, a small amount of nickel 106 is added on the surface of the a-Si film 104. The catalyst element that can be used here is a kind selected from nickel (Ni), cobalt (Co), tin (Sn), lead (Pb), palladium (Pd), iron (Fe), copper (Cu), or Multiple elements are preferred. In addition, ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), and the like can be used. The addition of a small amount of nickel 106 was performed by holding a solution in which nickel was dissolved on the a-Si film 104, and uniformly extending the solution onto the substrate 101 with a spinner and drying it. In this embodiment, nickel acetate is used as the solute, water is used as the solvent, and the nickel concentration in the solution is 10 ppm. This state corresponds to the state shown in FIG. At this time, the amount of the catalyst element to be added is extremely small, and the concentration of the catalyst element on the surface of the a-Si film 104 is managed by the total reflection X-ray fluorescence analysis (TRXRF) method. In this embodiment, 4 × 10 ¹² atoms / cm ² It was about. Prior to this step, the surface of the a-Si film 104 may be slightly oxidized with ozone water or the like in order to improve the wettability of the surface of the a-Si film 104 during spin coating.
[0192]
Then, the first heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. As annealing conditions at this time, annealing treatment is performed at 530 to 600 ° C. for 30 minutes to 8 hours. In this embodiment, as an example, heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, nickel 105 added to the surface of the a-Si film 104 is diffused into the a-Si film 104 and silicidation occurs, and crystallization of the a-Si film 104 proceeds using this as a nucleus. As a result, the a-Si film 104 is crystallized to become a crystalline silicon film 104a. Note that although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.
[0193]
When the crystal plane orientation of the crystalline silicon film 104a thus obtained is examined by EBSP measurement, it is mainly composed of <111> crystal zone planes, and among these, (110) plane orientation and (211) plane orientation are particularly important. In this, more than 50% of the total area is occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0194]
Subsequently, as shown in FIG. 1B, the crystalline silicon film 104a obtained by the heat treatment is irradiated with a laser beam 107, whereby the crystalline silicon film 104a is further recrystallized to improve crystallinity. The formed crystalline silicon film 104b is formed. As the laser light at this time, an XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) or a KrF excimer laser (wavelength 248 nm) can be applied. The beam size of the laser light at this time is shaped to be a long shape on the surface of the substrate 101, and the entire surface of the substrate is recrystallized by sequentially scanning in the direction perpendicular to the long direction. . At this time, scanning is performed so that parts of the beams overlap each other, so that laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 104a, thereby improving uniformity. If the energy of the laser beam at this time is too low, the crystallinity improvement effect is small, and if it is too high, the crystalline state of the crystalline silicon film 104a obtained in the previous step is reset, so it is necessary to set it within an appropriate range. There is. In this way, the crystalline silicon film 104a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 104b. Even after this laser irradiation step, the crystal plane orientation and crystal grain state before laser irradiation are maintained as they are, and no significant change is observed in the EBSP measurement. However, ridges are generated on the surface of the crystalline silicon film 104b, and the average surface roughness Ra is 4 to 9 nm.
[0195]
Next, as shown in FIG. 1C, a photoresist mask 108 is formed over the crystalline silicon film 104b. As for the arrangement of the mask 108 at this time, a part of the crystalline silicon film 104b is masked in an island shape by the mask 108, and the crystalline silicon film in the region covered by this mask is formed later. An active region (semiconductor layer) of the TFT is configured.
[0196]
Next, in this state, as shown in FIG. 1C, phosphorus 109 is ion-doped from above the substrate 101 over the entire surface. As a doping condition of phosphorus 109 at this time, phosphine (PH _Three ), The acceleration voltage is 5 to 15 kV, for example, and the dose is 5 × 10 5 ¹⁵ ~ 2x10 ¹⁶ cm ^-2 It was. By this step, phosphorus 109 is implanted into the exposed crystalline silicon film 104b, and a phosphorus-doped region 110 is formed. This region 110 is a region where the crystal is somewhat broken by the ion doping process and becomes amorphous. The crystalline silicon film 104b in the region covered with the mask 108 is not doped with phosphorus 109 and, of course, the crystalline state is not destroyed.
[0197]
Then, after the mask 108 made of photoresist is removed by ashing (oxygen plasma treatment) and a stripping solution, second heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this embodiment, heat treatment is performed in a nitrogen atmosphere at 500 ° C. to 600 ° C. for 30 minutes to 8 hours, for example, at 550 ° C. for 4 hours. At this time, the phosphorus-doped amorphous region 110 serves as a gettering region, and a gettering process is performed. In the region 110, defects trapping nickel, segregation sites, and the like are formed, and the solid solubility of the silicon film with respect to nickel is greatly increased by phosphorus doping. Utilizing these forces, as shown in FIG. 1D, the nickel 106 remaining in the crystalline silicon film in the region covered by the mask 108 is gettered in the direction indicated by the arrow 113. Move to ring area 110. By this gettering step, first, nickel present in a solid solution in the crystalline silicon film moves to the gettering region 110. As a result, the nickel concentration in the silicon film is lowered, and the deposited Ni silicide is dissolved into the silicon film. Then, they also enter a solid solution state and move to the gettering region 110. Finally, Ni silicide disappears, and the concentration of nickel in the solid solution state is also reduced. As a result, the nickel concentration in the crystalline silicon film 104b in the region covered with the mask 108 was measured by secondary ion mass spectrometry (SIMS). ¹⁵ atoms / cm ^Three It was reduced to the extent that it was almost the lower limit of measurement. Further, the nickel remaining in this region is not in a silicide state but exists in a solid solution state as interstitial nickel.
[0198]
Thereafter, unnecessary portions of the crystalline silicon film 104b are removed, and element isolation is performed. By this step, as shown in FIG. 1E, an island-like crystalline silicon film 114 that will later become an active region (source / drain region, channel region) of the TFT is formed. Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 115 so as to cover the crystalline silicon film 114 serving as the active region. In the formation of the silicon oxide film, TEOS (Tetra Ethoxy Ortho Silicate) was used as a raw material here, and it was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. together with oxygen. Alternatively, the substrate temperature may be 350 to 600 ° C., preferably 400 to 550 ° C. by TEOS as a raw material together with ozone gas by a low pressure CVD method or a normal pressure CVD method. After film formation, annealing is performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics of the crystalline silicon film / gate insulating film. May be.
[0199]
Subsequently, an aluminum film having a thickness of 400 to 800 nm, for example, 600 nm is formed by sputtering. Then, the aluminum film is patterned to form the gate electrode 116. Further, the surface of the aluminum electrode is anodized to form an oxide layer 117 on the surface. This state corresponds to FIG. Here, when the present embodiment is applied as a pixel TFT of a liquid crystal display device or the like, the gate electrode 116 simultaneously constitutes a gate bus line in a plan view. The anodic oxidation is performed in an ethylene glycol solution containing 1 to 5% tartaric acid, and the voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 117 is 300 nm. Note that since the oxide layer 117 has a thickness for forming an offset gate region in a subsequent ion doping step, the length of the offset gate region can be determined in the anodic oxidation step.
[0200]
Next, as shown in FIG. 1G, an N-type impurity (phosphorus) 122 is implanted into the active region by ion doping using the gate electrode 116 and the surrounding oxide layer 117 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 8x10 ¹⁵ cm ^-2 For example 2 × 10 ¹⁵ cm ^-2 And Through this step, the region into which the impurity is implanted later becomes the source / drain region 130 of the TFT, and the region not masked by the gate electrode 116 and its surrounding oxide layer 117 becomes the channel region 119 of the TFT later. Thereafter, annealing is performed by laser beam irradiation from above the substrate to activate the ion-implanted N-type impurity, and at the same time, the crystallinity of the portion where the crystallinity has deteriorated in the impurity introduction step is improved. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) is used as the laser to be used, and the energy density is 150 to 400 mJ / cm. ² , Preferably 200 to 250 mJ / cm ² Irradiation was performed. At this time, the channel region 119 is not irradiated with laser light because the upper gate electrode 116 serves as a mask to block the laser light. The sheet resistance of the N-type impurity (phosphorus) region 130 thus formed was 200 to 500 Ω / □.
[0201]
Subsequently, as shown in FIG. 1H, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as an interlayer insulating film 134. When a silicon oxide film is used, it is possible to form TEOS as a raw material by using a plasma CVD method with oxygen, a low pressure CVD method with ozone, or an atmospheric pressure CVD method, and a good interlayer insulation with excellent step coverage. A membrane is obtained. SiH _Four And NH _Three If a silicon nitride film formed by a plasma CVD method is used as a source gas, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and there is an effect of reducing dangling bonds that degrade TFT characteristics.
[0202]
Next, a contact hole is formed in the interlayer insulating film 134, and a TFT electrode / wiring 135 is formed from a metal film, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. When this TFT 136 is used as a pixel TFT, it is an element for switching the pixel electrode, and therefore, the other drain electrode is provided with a pixel electrode made of a transparent conductive film such as ITO. In this case, the other electrode constitutes a source bus line, a video signal is supplied through the source bus line, and a necessary charge is written to the pixel electrode based on the gate signal of the gate bus line 116. Further, the TFT can be easily applied to a thin film integrated circuit or the like. In that case, a contact hole may be formed on the gate electrode 116 and necessary wiring may be provided.
[0203]
Finally, annealing is performed at 350 ° C. for 1 hour in a nitrogen atmosphere or a hydrogen atmosphere to complete the TFT 136 shown in FIG. Further, if necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT 136 for the purpose of protecting the TFT 136.
[0204]
The TFT manufactured according to the above embodiment has a field effect mobility of 300 cm. ² / Vs and a threshold voltage of about 1.5 V, despite the extremely high performance, there is no abnormal increase in leakage current frequently observed in the TFT off operation, which is frequently observed in the conventional example, and 0 per unit W. . A very low value of several pA or less was stably shown. This value is completely different from that of a conventional TFT manufactured without using a catalytic element, and the defect occurrence rate of TFT is 1 / 10,000 or less, which can greatly improve the manufacturing yield. It was. In addition, even when repeated measurements and durability tests with bias and temperature stress were performed, the characteristics were hardly deteriorated and the reliability was very high compared to the conventional one.
[0205]
(Second Embodiment)
A second embodiment using the present invention will be described. In the present embodiment, as in the first embodiment, a case where the present invention is used in a process for manufacturing an N-channel TFT on a glass substrate will be described.
[0206]
2A to 2H are cross-sectional views showing a manufacturing process of the N-type TFT described in this embodiment, and the manufacturing processes are sequentially performed in the order of (A) → (H). proceed.
[0207]
In FIG. 2A, a low alkali glass substrate or a quartz substrate can be used for the substrate 201. In this embodiment, a low alkali glass substrate is used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 201 on which the TFT is formed in order to prevent impurity diffusion from the substrate 201. In this embodiment, for example, SiH is formed by plasma CVD. ₄ , NH ₃ , N ₂ A silicon oxynitride film produced from a material gas of O is formed as a lower first base film 202, and SiH is similarly formed thereon by plasma CVD. ₄ , N ₂ A second base film 203 was stacked using O as a material gas. At this time, the film thickness of the silicon oxynitride film of the first base film 202 is 25 to 200 nm, for example, 100 nm, and the film thickness of the silicon oxynitride film of the second base film 303 is 25 to 300 nm, for example, 100 nm. . Next, an intrinsic (I-type) amorphous silicon film (a-Si film) 204 containing a rare gas element having a thickness of 20 to 80 nm, for example, 50 nm is formed by plasma CVD.
[0208]
In the present embodiment, a multi-chamber parallel plate type plasma CVD apparatus as shown in FIG. 16 is used, and three layers of the first base film 202, the second base film 203, and the a-Si film 204 are exposed to the atmosphere. The film was continuously formed without any problems. At this time, the a-Si film 204 can be formed using the same method as in the first embodiment. In this embodiment, as an example, film formation was performed by a normal plasma CVD method as shown in FIG. 15A using Ar as a rare gas element and silane-based gas and Ar gas as material gases. The substrate heating temperature at this time is 250 ° C., and the gas flow rate is SiH. _Four The gas was 100 sccm and Ar gas was 5000 sccm. The gas pressure is 0.5 Torr, the RF frequency supplied to the CVD electrode is 27.1 MHz, the RF power is 100 W, and the substrate side is grounded. The Ar concentration in the a-Si film 204 thus obtained is about 1 × 10 6. ¹⁷ atoms / cm ^Three It was about.
[0209]
Subsequently, a catalytic element is added to the a-Si film 204 and heat treatment is performed. An aqueous solution (nickel acetate aqueous solution) containing, for example, 10 ppm catalyst element (in this embodiment, nickel) in terms of weight is applied to the a-Si film by a spin coating method to form the catalyst element-containing layer 206. In this embodiment, nickel is added by spin coating, but a thin film made of a catalytic element (in this embodiment, nickel film) is deposited on the amorphous silicon film 204 by vapor deposition or sputtering. It is also possible to take the means to form This state corresponds to the state shown in FIG. When the nickel concentration on the surface of the a-Si 204 added in the state shown in FIG. 2A is measured by the total reflection X-ray fluorescence analysis (TRXRF) method, 4 × 10 4 is obtained. ¹² atoms / cm ² It was about.
[0210]
Then, the first heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. This heat treatment is preferably performed at 550 to 600 ° C. for 30 minutes to 4 hours. In this embodiment, the heat processing for 1 hour were performed at 580 degreeC as an example. In this heat treatment, nickel 206 added to the surface of the a-Si film diffuses into the a-Si film 204 and silicidation occurs, and crystallization of the a-Si film 204 proceeds using this as a nucleus. As a result, the a-Si film 204 is crystallized to become a crystalline silicon film 204a. The crystal plane orientation of the crystalline silicon film 204a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0211]
Subsequently, as shown in FIG. 2B, the crystalline silicon film 204a obtained by the heat treatment is irradiated with a laser beam 207, whereby the crystalline silicon film 204a is further recrystallized to improve crystallinity. The formed crystalline silicon film 204b is formed. As the laser light at this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used. The laser light irradiation condition is that the substrate is heated to 200 to 450 ° C., for example, 400 ° C. during irradiation, and the energy density is 250 to 450 mJ / cm. ² For example, 350 mJ / cm ² Irradiated with. In this embodiment, the beam size is formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 201, and scanning is performed sequentially with a step width of 0.05 mm in the direction perpendicular to the long direction. It was. That is, a total of 20 laser irradiations are performed at an arbitrary point of the crystalline silicon film 204a. In this way, the crystalline silicon film 204a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 204b. The crystal plane orientation of the crystalline silicon film 204b obtained in this way maintains the state of the crystalline silicon film 204a before laser irradiation, but its average surface roughness Ra is 4 to 9 nm. .
[0212]
Next, the surface of the crystalline silicon film 204b is thin-film oxidized to form a silicon oxide thin film 211 serving as an etching stopper. The silicon oxide film 211 was formed by holding ozone water on the surface of the crystalline silicon film 204b. At this time, the ozone concentration in the ozone water is desirably 5 mg / L or more, and in the present embodiment, the ozone concentration is 8 mg / L. The retention time of ozone water on the surface of the crystalline silicon film 204b was 1 minute. In order to form a denser silicon oxide film 211, it is desirable to remove a natural oxide film on the surface of the crystalline silicon film 204b before the ozone water treatment. The thickness of the silicon oxide film 211 formed in this way was measured with a spectroscopic ellipso, and was about 30 mm (about 3 nm).
[0213]
Next, an a-Si film 212 containing phosphorus is formed by plasma CVD so as to cover the oxide film 211. The a-Si film containing phosphorus functions as a gettering layer. At this time, the formation of the a-Si film 212 containing phosphorus is performed using a plasma CVD method using silane (SiH _Four ) And phosphine (PH _Three ) As a material gas. At this time, the concentration of phosphorus in the a-Si film 212 can be arbitrarily changed by the flow rate ratio of the phosphine gas. In this embodiment, PH _Three / SiH _Four The flow rate ratio was 3/100. At this time, the phosphorus concentration in the a-Si film 212 was about 1%. In the present embodiment, phosphorus is used as the gettering element contained in the gettering layer, but the gettering ability can be further enhanced by adding boron in addition to phosphorus. At this time, diborane (B ₂ H ₆ ). In addition, a high gettering effect can be obtained by introducing a rare gas element such as Ar at the time of film formation in place of phosphorus and forming an a-Si film containing these rare gases. In this case, the concentration of the rare gas element contained in the gettering layer 212 needs to be equal to or higher than the concentration of the rare gas element contained in the crystalline silicon film 204b. This state corresponds to FIG.
[0214]
Then, the second heat treatment is performed in an inert atmosphere. In this embodiment, for example, rapid thermal annealing is performed in a nitrogen atmosphere. As conditions for the rapid thermal annealing at this time, the substrate is preheated to about 400 ° C. and then heated at a rate of temperature increase from 50 ° C./min to 300 ° C./min. The annealing temperature and processing time are 600 to 750. It is desirable that it is 30 seconds to 15 minutes at a temperature of ° C, more preferably 1 minute to 10 minutes at a temperature of 650 to 700 ° C. In the present embodiment, a high-speed thermal annealing process with the above temperature profile is realized by using a resistive heating furnace to provide a temperature gradient in the furnace and controlling the speed at which the substrate is inserted into the furnace. At this time, the substrates are processed one by one, and during the treatment, nitrogen gas heated at a high temperature is uniformly blown onto the surface of the substrate 201, so that a high temperature increase rate that cannot be obtained only by thermal radiation and a temperature increase in the middle The thermal uniformity within the substrate surface is obtained.
[0215]
By the rapid thermal annealing treatment, the nickel 206 in the crystalline silicon film 204b under the a-Si film 212 containing phosphorus is moved upward as indicated by an arrow 213 in FIG. At this time, nickel moves through the thin silicon oxide film 211, but the movement of the silicon oxide film having the thickness as in the present embodiment is not hindered. The solid solubility of nickel in the a-Si film 212 is greatly increased by phosphorus, and a gettering process is performed by causing defects and the like as segregation traps for nickel to bring out the gettering action. In this gettering step, first, nickel dissolved in the crystalline silicon film 204b moves to the gettering layer 212, so that the nickel concentration in the silicon film decreases, and Ni silicide precipitated in the film. Is performed by dissolving in the silicon film. These also move to the gettering layer 212 in a solid solution state, Ni silicide in the crystalline silicon 204b disappears, and the concentration of nickel in the solid solution state is also reduced. As a result, the nickel concentration of the crystalline silicon film 204b was measured by secondary ion mass spectrometry (SIMS) and found to be 5 × 10. ¹⁵ atoms / cm ^Three It was reduced to the extent that it was almost the lower limit of measurement. Here, the nickel remaining in the crystalline silicon film 204b is not in a silicide state but exists in a solid solution state as interstitial nickel.
[0216]
Next, the a-Si film 212 which is a gettering layer is removed by etching over the entire surface. As the etching at this time, an etchant having a sufficient etching selectivity with respect to the silicon oxide film is required so that the lower silicon oxide film 211 sufficiently functions as an etching stopper. In this embodiment, a strong alkali solution such as a developer is used. Then, after removing the gettering layer a-Si layer 212, the silicon oxide film 211 is removed by etching. As an etchant at this time, 1: 100 buffered hydrofluoric acid (BHF) having sufficient selectivity with respect to the underlying silicon film 204b was used and wet etching was performed.
[0217]
Thereafter, unnecessary portions of the crystalline silicon film 204b are removed, and element isolation is performed. By this step, as shown in FIG. 2E, an island-like crystalline silicon film 214 that later becomes an active region (source / drain region, channel region) of the TFT is formed. Subsequently, a gate insulating film 215 that covers these island-like crystalline silicon films 214 is formed. As the gate insulating film 215, a silicon oxide film having a thickness of 20 to 150 nm is preferable. Here, a 100 nm silicon oxide film is formed by a plasma CVD method using TEOS and oxygen gas as materials. After the film formation, in order to improve the bulk characteristics of the gate insulating film itself and the interface characteristics of the crystalline silicon film / gate insulating film, annealing was performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere.
[0218]
Subsequently, a conductive film is deposited on the gate insulating film 215 using a sputtering method, a CVD method, or the like, and this is patterned to form a gate electrode 216. In this embodiment, an aluminum film (containing 1% scandium) having a thickness of 400 to 800 nm, for example, 500 nm is formed by sputtering and patterned to form the gate electrode 216. High temperature resistance is improved by mixing trace amounts of elements such as scandium, titanium, and silicon into the aluminum film.
[0219]
Next, as shown in FIG. 2F, a low concentration impurity (phosphorus) 218 is implanted into the active region by ion doping using the gate electrode 216 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² ~ 1x10 ¹⁴ cm ^-2 For example 8 × 10 ¹² cm ^-2 And In this process, in the island-like silicon film 214, a low concentration phosphorus 218 is implanted into a region 220 not covered with the gate electrode 216, and a region where the gate electrode 216 is masked and phosphorous 218 is not implanted is a TFT channel. Region 219 is formed.
[0220]
Subsequently, as shown in FIG. 2G, a doping mask 221 made of a photoresist is provided so as to cover the gate electrode 216 one size. Thereafter, an impurity (phosphorus) 222 is implanted at a high concentration into the active region by ion doping using the resist mask 221 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 8x10 ¹⁵ cm ^-2 For example 2 × 10 ¹⁵ cm ^-2 And By this step, the region where the impurity (phosphorus) 222 is implanted at a high concentration later becomes the source / drain region 230 of the TFT. In the active region 214, the region covered with the resist mask 221 and not doped with the high concentration phosphorus 222 remains as a region where phosphorus is implanted at a low concentration, thereby forming an LDD (Lightly Doped Drain) region 223. . Thus, by forming the LDD region 223, electric field concentration at the junction between the channel region and the source / drain region can be alleviated, leakage current at the time of TFT off operation can be reduced, and deterioration due to hot carriers can be suppressed. And the reliability of the TFT can be improved.
[0221]
Then, after removing the photoresist 221 used as a mask for doping, annealing is performed by laser light irradiation from above the substrate to activate the ion-implanted impurities, and at the same time, the crystallinity is improved in the impurity introduction step. Improve the crystallinity of the deteriorated part. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) is used as the laser to be used, and the energy density is 150 to 400 mJ / cm. ² , Preferably 200 to 250 mJ / cm ² Irradiation was performed. The sheet resistance of the N-type impurity (phosphorus) region 230 thus formed was 200 to 500 Ω / □, and the sheet resistance of the LDD region 223 into which phosphorus was implanted at a low concentration was 30 to 50 kΩ / □.
[0222]
Subsequently, as shown in FIG. 2H, a silicon oxide film or a silicon nitride film having a thickness of about 400 to 1000 nm is formed as an interlayer insulating film 234, a contact hole is formed in this, and a metal material, for example, A TFT electrode / wiring 235 is formed of a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. When the TFT 236 is used as a pixel TFT, the other drain electrode is provided with a pixel electrode made of a transparent conductive film such as ITO. Finally, annealing is performed at 350 ° C. for 1 hour in a nitrogen atmosphere or a hydrogen atmosphere to complete the TFT 236 shown in FIG. Furthermore, if necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT for the purpose of protecting the TFT 236.
[0223]
The TFT fabricated according to the above embodiment showed very good electrical characteristics similar to the TFT fabricated in the first embodiment. When the TFT manufactured according to the present embodiment is applied to the pixel TFT of the active matrix substrate for liquid crystal display as a dual gate structure, the display unevenness is clearly smaller than that manufactured by the conventional method, and due to TFT leakage. A liquid crystal panel with high display quality and a high contrast ratio with very few pixel defects was obtained.
[0224]
(Third embodiment)
A third embodiment using the present invention will be described. In the present embodiment, a peripheral drive circuit of an active matrix liquid crystal display device and a circuit having a CMOS structure in which an n-channel TFT and a p-channel TFT forming a general thin film integrated circuit are complementary are formed on a glass substrate. The manufacturing process will be described.
[0225]
3 and 4 are cross-sectional views showing the manufacturing process of the TFT described in this embodiment, and the process proceeds in order from FIG. 3 (A) to (E) and FIG. 4 (A) to (C). To do.
[0226]
In FIG. 3A, a low alkali glass substrate is used as the substrate 301. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 301 on which the TFT is formed in order to prevent impurity diffusion from the substrate 301. In this embodiment, for example, SiH is formed by plasma CVD. ₄ , NH ₃ , N ₂ A silicon oxynitride film formed from a material gas of O is formed as a lower first base film 302, and SiH is similarly formed thereon by plasma CVD. ₄ , N ₂ A second base film 303 was stacked using O as a material gas. At this time, the film thickness of the silicon oxynitride film of the first base film 302 is 25 to 200 nm, for example, 50 nm, and the film thickness of the silicon oxynitride film of the second base film 303 is 25 to 300 nm, for example, 100 nm. . In this embodiment, a two-layer base film is used. However, for example, a single layer of a silicon oxide film is not a problem.
[0227]
Next, a silicon film (a-Si film) 304 containing a rare gas element and having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is used, and a silane-based gas and a rare gas are used as material gases. As a plasma CVD method. In this embodiment, the amorphous silicon film is formed to a thickness of 50 nm. Further, the base films 302 and 303 and the amorphous silicon film 304 may be formed continuously. By using a multi-chamber plasma CVD apparatus as shown in FIG. 16, it is possible to prevent contamination of the surface by forming the underlying film and then not exposing it to the air atmosphere. Variations and fluctuations in threshold voltage can be reduced. The a-Si film 304 was formed using Ar as a rare gas element and using a dual-frequency plasma CVD apparatus as shown in FIG. The substrate heating temperature at this time is 350 ° C., and the gas flow rate is SiH. _Four The gas was 100 sccm and Ar gas was 3000 sccm. The gas pressure was 0.7 Torr, the RF frequency supplied to the CVD electrode was 27.1 MHz, the RF power was 100 W, the RF frequency supplied to the substrate side was 1.6 MHz, and the RF power was 80 W. The rare gas element concentration in the a-Si film is 5 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three In this embodiment, the Ar concentration in the a-Si film 304 is about 1 × 10 10. ¹⁸ atoms / cm ^Three It was about. In this embodiment, argon (Ar) is used as a rare gas element, but krypton (Kr) and xenon (Xe) can also be used.
[0228]
Then, a small amount of catalytic element (nickel in this embodiment) 306 is added on the surface of the a-Si film 304. This small amount of nickel 306 was added by holding a solution in which nickel was dissolved on the a-Si film 304, and uniformly extending the solution onto the substrate 301 by a spinner and drying it. In this embodiment, nickel acetate is used as the solute, water is used as the solvent, and the nickel concentration in the solution is 8 ppm. This state corresponds to the state shown in FIG. When the nickel concentration on the surface of the a-Si film 304 in the state of FIG. 3A added in this way is measured by a total reflection X-ray fluorescence (TRXRF) method, 3 × 10 ¹² atoms / cm ² It was about. As a method for adding the catalytic element to the amorphous silicon film, a gas phase method such as a plasma doping method, a vapor deposition method, or a sputtering method can be used in addition to a method of applying a solution containing the catalytic element. In the method using a solution, the addition amount of the catalyst element can be easily controlled, and a very small amount can be easily added.
[0229]
Then, the first heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. As the heat treatment at this time, annealing treatment is performed at 520 to 600 ° C. for 1 to 8 hours. In this embodiment, the heat processing for 1 hour were performed at 580 degreeC as an example. In this heat treatment, nickel 306 added to the surface of the a-Si film diffuses into the a-Si film 304 and silicidation occurs, and crystallization of the a-Si film 304 proceeds using this as a nucleus. As a result, as shown in FIG. 3B, the a-Si film 304 is crystallized into a crystalline silicon film 304a. The crystal plane orientation of the crystalline silicon film 304a thus obtained is mainly constituted by <111> crystal zone planes, and among them, (110) plane orientation and (211) plane orientation are 50% of the total. These areas are occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0230]
Next, as shown in FIG. 3C, the crystalline silicon film 304a is further recrystallized by irradiating a laser beam 307 to improve its crystallinity. As the laser light at this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used. The irradiation condition of the laser beam is that the substrate is not heated and the energy density is 250 to 500 mJ / cm. ² For example, 400 mJ / cm ² Irradiated with. The beam shape was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 301, and scanning was sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. That is, a total of 20 laser irradiations are performed at an arbitrary point on the crystalline silicon film 304a. In this way, the crystalline silicon film 304a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 304b. The crystal plane orientation of the crystalline silicon film 304b thus obtained maintains the state of the crystalline silicon film 304a before laser irradiation, but the average surface roughness Ra is 4 to 9 nm. . As a laser that can be used at this time, a pulse oscillation type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser, or YVO 4 laser can be used. The practitioner may select the crystallization conditions as appropriate.
[0231]
Thereafter, unnecessary portions of the crystalline silicon film 304b are removed, and element isolation is performed. By this step, as shown in FIG. 3D, island-like crystalline silicon films 314n and 314p, which later become active regions (source / drain regions, channel regions) of the n-channel TFT and the p-channel TFT, are formed. It is formed.
[0232]
Here, boron as an impurity element imparting p-type at a concentration of about 1 × 10 16 to 5 × 10 17 / cm 3 for the purpose of controlling the threshold voltage over the entire active region of the n-channel TFT and the p-channel TFT. (B) may be added. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film.
[0233]
Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as a gate insulating film 315 so as to cover the crystalline silicon films 314n and 314p serving as the active regions. In the formation of the silicon oxide film, here, TEOS was used as a raw material, and it was decomposed and deposited by RF plasma CVD with oxygen at a substrate temperature of 300 to 450 ° C. As the gate insulating film 315, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0234]
Subsequently, a refractory metal is deposited by a sputtering method and patterned to form gate electrodes 316n and 316p. The refractory metal at this time is an element selected from tantalum (Ta), tungsten (W), molybdenum (Mo) titanium (Ti), an alloy containing the element as a main component, or an alloy combining the elements. A film (typically, a Mo—W alloy film or a Mo—Ta alloy film) may be used. Further, tungsten silicide, titanium silicide, or molybdenum silicide may be applied as another alternative material. In this embodiment, tungsten (W) is used and the thickness is set to 300 to 600 nm, for example, 450 nm. At this time, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance, and by setting the oxygen concentration to 30 ppm or less, a specific resistance value of 20 μΩcm or less could be realized.
[0235]
Next, as shown in FIG. 3E, an N-type impurity (phosphorus) 322 is implanted into the active region by ion doping using the gate electrodes 316n and 316p as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 6 × 10 ¹⁵ cm ^-2 And By this process, in the active region 314n of the subsequent N-channel TFT and the active region 314p of the subsequent P-channel TFT, phosphorus 322 is implanted at a high concentration in the regions not covered by the gate electrodes 316n and 316p. Region 324. In the active region 314n of the later N-channel TFT, the region 324 into which phosphorus is implanted at this high concentration becomes the later source / drain region 330, and the region where the gate electrode 316n is masked and phosphorous 322 is not implanted is later. A channel region 319n is formed. In this process, the reason why phosphorus is also implanted into the active region 314p of the P channel TFT later is that phosphorus implanted at a high concentration is used as a gettering element, and the second heat treatment process is performed later. This is because gettering is performed to the source and drain regions.
[0236]
Next, as shown in FIG. 4A, a doping mask 325 made of a photoresist is provided so as to cover the entire active region 314n of the subsequent n-channel TFT. In this state, an impurity (boron) 326 imparting p-type is implanted into the active region 314p of the p-channel TFT by ion doping using the resist mask 325 and the gate electrode 316p of the p-channel TFT as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 5 × 10 ¹⁵ ~ 2x10 ¹⁶ cm ^-2 For example, 1 × 10 ¹⁶ cm ^-2 And By this process, the region where boron 326 is implanted at a high concentration is inverted in polarity from N-type to P-type by so-called counter-doping, and later becomes a source / drain region 331 of a p-channel TFT, and a mask is formed on the gate electrode 317p. The region into which impurities are not implanted becomes a channel region 319p of a later p-channel TFT. In this process, since the active region 314n of the later n-channel TFT is entirely covered with the mask 325, the boron 326 is not doped at all, and the source / drain regions 330 of the later n-channel TFT are formed separately. Can do. When doping the n-type impurity and the p-type impurity, the regions that do not need to be doped are covered with a photoresist so that each element is selectively doped, and the n-type high-concentration impurity region 330 and the p-type impurity are doped. Impurity regions 331 are formed. In this embodiment, an n-type impurity element is added to the semiconductor layer. However, the order of steps is not limited to this embodiment, and the practitioner may determine as appropriate.
[0237]
Next, after removing the resist mask 325, a second heat treatment is performed on the resist mask 325 in an inert atmosphere, for example, in a nitrogen atmosphere. In the present embodiment, the heat treatment is performed in the range of 520 to 600 ° C. for about 30 minutes to 8 hours. In this heat treatment step, as shown in FIG. 4B, in the active region 314n of the later n-channel TFT and the active region 314p of the P-channel TFT, phosphorus doped in the source / drain regions By increasing the solid solubility with respect to nickel and moving the nickel existing in the channel region from the channel regions 319n and 319p to the source / drain regions 330 and 331 in the direction indicated by the arrow 313, gettering is performed. A process is performed.
[0238]
In this gettering step, first, nickel dissolved in the channel regions 319n and 319p moves to the source / drain regions 330 and 331, so that the nickel concentration in the channel region is lowered and deposited there. Ni silicide is performed by dissolving in the channel region. These also move to the source / drain regions 330 and 331 in a solid solution state. Finally, Ni silicide in the channel region disappears, and the concentration of nickel in the solid solution state is also reduced. As a result, the nickel concentration in the channel regions 319n and 319p was measured by secondary ion mass spectrometry (SIMS) and found to be 5 × 10. ¹⁵ atoms / cm ^Three It was reduced to the extent that it was almost the lower limit of measurement. Here, the nickel remaining in the channel region is not in a silicide state but exists in a solid solution state as interstitial nickel. Conversely, since nickel moves to the source / drain regions, the nickel concentration in the source / drain regions 330 and 331 is 1 × 10 5. ¹⁹ / Cm ^Three That's it.
[0239]
In this heat treatment step, n-type impurity (phosphorus) 322 doped in the source / drain region 330 of the n-channel TFT and p-type impurity (boron) doped in the source / drain region 331 of the p-channel TFT. ) Activation of 326 is also performed at the same time. As a result, the sheet resistance value of the source / drain region 330 of the n-channel TFT is about 400 to 700 Ω / □, and the sheet resistance value of the source / drain region 331 of the p-channel TFT is 1 to 1.5 kΩ / □. It was about.
[0240]
Next, as shown in FIG. 4C, an inorganic interlayer insulating film is formed. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 400 to 1500 nm (typically 600 to 1000 nm). In this embodiment, a silicon nitride film 333 having a thickness of 200 nm and a silicon oxide film 334 having a thickness of 700 nm are stacked to form a two-layer structure. As a film formation method at this time, a plasma CVD method is used, and a silicon nitride film is formed of SiH. _Four And NH _Three As a source gas, the silicon oxide film is TEOS and O ₂ Was continuously formed as a raw material. Of course, the inorganic interlayer insulating film is not limited to this, and another insulating film containing silicon may have a single layer or a laminated structure.
[0241]
Further, a process of hydrogenating the semiconductor layer is performed by performing heat treatment at 300 to 500 ° C. for 1 to several hours. In this step, hydrogen atoms are supplied to the active region / gate insulating film interface to terminate and inactivate dangling bonds that degrade TFT characteristics. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film (particularly the silicon nitride film 333) is sufficient, the effect can be obtained even if heat treatment is performed in a nitrogen atmosphere. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0242]
Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode / wiring 335 is formed of a two-layer film of a metal material, for example, titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour, and the n-channel TFT 336 and the p-channel TFT 337 shown in FIG. 4H are completed. Further, if necessary, a contact hole is also provided on the gate electrodes 316n and 316p, and necessary electrodes are connected by a wiring 335. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0243]
The field effect mobility of each TFT manufactured according to the above embodiment is 250 to 300 cm for an n-channel TFT. ² / Vs, 120-150cm for p-channel TFT ² / Vs is high, and the threshold voltage is about 1V for the N-type TFT and about -1.5V for the P-type TFT, and exhibits very good characteristics. In addition, there was no abnormal increase in leakage current frequently observed in the TFT off operation, which was frequently observed in the conventional example, and even when repeated measurements and durability tests due to bias and temperature stress were performed, there was almost no deterioration in characteristics. In addition, when a circuit such as an inverter chain or a ring oscillator is formed by a CMOS structure circuit in which the n-channel TFT and the p-channel TFT manufactured in this embodiment are complementarily formed, it is much more difficult than the conventional one. High reliability and stable circuit characteristics.
[0244]
(Fourth embodiment)
A fourth embodiment using the present invention will be described. Also in this embodiment, a process for manufacturing a circuit having a CMOS structure in which an n-channel TFT and a p-channel TFT are complementary to each other on a glass substrate will be described.
[0245]
FIG. 5 and FIG. 6 are cross-sectional views showing the manufacturing process of the TFT described in this embodiment, and the process proceeds in order from FIG. 5 (A) to (F) and FIG. 6 (A) to (D). To do.
[0246]
In FIG. 5A, a base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the low alkali glass substrate 401 on which the TFT is formed in order to prevent impurity diffusion from the substrate 401. In this embodiment, a silicon nitride film is formed as a lower first base film 402, and a silicon oxide film is stacked on the second base film 403. The film thickness of the silicon oxynitride film of the first base film 402 was set to 100 nm, for example, and the film thickness of the silicon oxynitride film of the second base film 403 was set to 100 nm, for example, and both were continuously formed by plasma CVD.
[0247]
Next, a silicon film (a-Si film) 404 having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed. Here, the a-Si film 404 is formed using a silane-based gas as a material gas by a general plasma CVD method as shown in FIG. At this stage, the a-Si film 404 does not yet contain a rare gas element. In the present embodiment, the thickness of the a-Si film at this time is 50 nm. Further, the base films 402 and 403 and the amorphous silicon film 404 may be formed continuously.
[0248]
Then, as shown in FIG. 5A, the a-Si film 404 is ion-doped with a rare gas element (Ar in this embodiment) 405 from above the substrate. The doping conditions for argon 405 at this time are as follows: 100% Ar is used as a doping gas, the acceleration voltage is 5 to 15 kV, and the dose is 1 × 10. ¹³ ~ 1x10 ¹⁵ cm ^-2 For example, 1 × 10 ¹⁴ cm ^-2 It was. As the rare gas element at this time, one or more kinds of rare gas elements selected from Ar, Kr, and Xe can be used. In this step, the concentration of the rare gas element in the a-Si film is 5 × 10 5. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three In this embodiment, the Ar concentration in the a-Si film 404 is about 1 × 10 6. ¹⁸ atoms / cm ^Three It was about.
[0249]
Subsequently, a small amount of a catalyst element (nickel in this embodiment) 406 is added on the surface of the a-Si film 404. This small amount of nickel 406 was added by holding a solution in which nickel was dissolved on the a-Si film 404, and uniformly extending the solution onto the substrate 401 by a spinner and drying. In this embodiment, nickel acetate is used as the solute, water is used as the solvent, and the nickel concentration in the solution is 8 ppm. This state corresponds to the state shown in FIG. When the nickel concentration on the surface of the a-Si film 404 added in this manner in the state of FIG. 5B is measured by a total reflection X-ray fluorescence analysis (TRXRF) method, 3 × 10 ¹² atoms / cm ² It was about.
[0250]
And this is heat-processed in inert atmosphere, for example, nitrogen atmosphere. As the heat treatment at this time, annealing treatment is performed at 520 to 600 ° C. for 1 to 8 hours. In this embodiment, as an example, the heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, nickel 406 added to the surface of the a-Si film is diffused into the a-Si film 404 and silicidation occurs, and crystallization of the a-Si film 404 proceeds using this as a nucleus. As a result, as shown in FIG. 5C, the a-Si film 404 is crystallized into a crystalline silicon film 404a. The crystal plane orientation of the crystalline silicon film 404a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0251]
Next, as shown in FIG. 5D, the crystalline silicon film 404a is further recrystallized by irradiation with a laser beam 407 to improve the crystallinity thereof. As the laser light at this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used. The laser light irradiation condition is, for example, an energy density of 400 mJ / cm. ² The beam was shaped so as to have a long shape of 150 mm × 1 mm, and scanning was sequentially performed at a step width of 0.05 mm in the direction perpendicular to the long direction. That is, a total of 20 laser irradiations are performed at an arbitrary point of the crystalline silicon film 404a. Thus, the crystalline silicon film 404a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 404b. The crystal plane orientation of the crystalline silicon film 404b thus obtained maintains the state of the crystalline silicon film 404a before laser irradiation, but the average surface roughness Ra is 4 to 9 nm. .
[0252]
Thereafter, unnecessary portions of the crystalline silicon film 404b are removed, and element isolation is performed. By this step, as shown in FIG. 5E, island-like crystalline silicon films 414n and 414p, which later become active regions (source / drain regions, channel regions) of the n-channel TFT and the p-channel TFT, are formed. It is formed.
[0253]
Here, for the purpose of controlling the threshold voltage over the entire active region of the n-channel TFT and the p-channel TFT, 1 × 10 ¹⁶ ~ 5x10 ¹⁷ / Cm ³ Boron (B) may be added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film.
[0254]
Next, a silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as a gate insulating film 414 so as to cover the crystalline silicon films 414n and 414p serving as the active regions. In the formation of the silicon oxide film, TEOS was used as a raw material here, and it was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 to 600 ° C., preferably 300 to 450 ° C. together with oxygen.
[0255]
Subsequently, as shown in FIG. 5F, a refractory metal is deposited by a sputtering method and patterned to form gate electrodes 416n and 416p. In this embodiment, tantalum (Ta) doped with a slight amount of nitrogen is used as the refractory metal at this time, and the thickness is set to 300 to 600 nm, for example, 450 nm.
[0256]
Next, a low concentration impurity (phosphorus) 418 is implanted into the active region by ion doping using the gate electrodes 416n and 416p as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² ~ 1x10 ¹⁴ cm ^-2 For example 2 × 10 ¹³ cm ^-2 And By this process, in the island-shaped silicon films 414n and 414p, the region not covered with the gate electrodes 416n and 416p becomes the region 420 into which low-concentration phosphorus 418 is implanted, and the impurity 418 is masked by the gate electrodes 416n and 416p. The regions that are not formed later become channel regions 419n and 419p of the n-channel TFT and the p-channel TFT. This state corresponds to FIG.
[0257]
Next, as shown in FIG. 6A, in the later n-channel TFT, a photoresist doping mask 421n is provided so as to cover the gate electrode 416n so as to be slightly larger, and in the later p-channel TFT, the active A doping mask 421p made of a photoresist is provided so as to cover the entire region 414p. Thereafter, an impurity (phosphorus) 422 is implanted into the active region at a high concentration by ion doping using the resist masks 421n and 421p as a mask. At this time, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 2 × 10. ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 5 × 10 ¹⁵ cm ^-2 And By this process, in the active region 414n of the later n-channel TFT, the region into which the impurity (phosphorus) 422 has been implanted at a high concentration later becomes the source / drain region 430 of the n-channel TFT and covers the resist mask 421n. In other words, the region that is not doped with the high concentration phosphorus 422 remains as a region where phosphorus is implanted at a low concentration, and forms an LDD (Lightly Doped Drain) region 423. Further, in the p-channel TFT later, since the entire active region is covered with the mask 421p, the high concentration impurity (phosphorus) 422 is not implanted in this step. The n-type impurity element (phosphorus) 422 concentration in the region 430 at this time is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three It has become. Further, the n-type impurity element (phosphorus) 418 concentration in the LDD region 423 of the n-channel TFT is 1 × 10 ¹⁷ ~ 1x10 ²⁰ / Cm ^Three In such a range, it functions as an LDD region.
[0258]
Next, after removing the resist masks 421n and 421p, as shown in FIG. 6B, a photoresist doping mask 425 is newly provided so as to cover the entire active region 414n of the later n-channel TFT. . At this time, no mask is provided above the subsequent p-channel TFT, and the entire TFT is exposed. In this state, an impurity (boron) 426 imparting p-type conductivity is implanted into the active region by ion doping using the resist mask 425 and the gate electrode 416p of the p-channel TFT later as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 7 × 10 ¹⁶ cm ^-2 And Further, a rare gas element (Ar in this embodiment) 429 is implanted into the active region 414p of the p-channel TFT by ion doping using the resist mask 425 and the gate electrode 416p of the subsequent p-channel TFT as a mask. To do. The doping conditions of argon 429 at this time are as follows: 100% Ar is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example, 1 × 10 ¹⁵ cm ^-2 It was. As the rare gas element at this time, one or more kinds of rare gas elements selected from Ar, Kr, and Xe can be used. In this embodiment, these two dopings were performed separately, but diborane (B ₂ H ₆ ) A gas mixture of a rare gas (Ar) and a rare gas (Ar) may be used as a doping gas, and these two elements (426 and 429) may be implanted simultaneously by a single doping step.
[0259]
Through this step, boron 426 and argon 429 are implanted at a high concentration later in the active region 414p of the p-channel TFT in addition to the channel region 419p below the gate electrode 416p. The implanted boron 426 becomes a p-type by inverting the n-type impurity phosphorus 418 implanted at a low concentration in the previous step, and a source / drain region 431 of the later p-channel TFT is formed. Since argon is an inert element, the carrier distribution of the semiconductor is not affected. Here, the reason for injecting the rare gas element into the source / drain region 431 of the p-channel TFT is that the rare gas element is used as a gettering element, and the gettering element is subsequently obtained in the second heat treatment step. This is to perform the ring. That is, in the n-channel TFT, phosphorus 422 itself implanted into the source / drain region 430 functions as a gettering element. However, in a p-channel TFT, boron 426 alone does not function as a gettering element. Even if the source / drain region is formed only by this, gettering is not performed. Therefore, in the present embodiment, in the p-channel TFT, argon is introduced into the source / drain region as a gettering element to cause a gettering action. At this time, the concentration in the film of the p-type impurity element (boron) 426 in the region 431 is 1.5 × 10 5. ¹⁹ ~ 3x10 ^{twenty one} / Cm ^Three The concentration of the rare gas element (Ar) is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} atoms / cm ^Three It has become.
[0260]
When doping the n-type impurity and the p-type impurity, the regions which do not need to be doped are covered with a photoresist so that each element is selectively doped, and the n-type high concentration impurity region 430 and the p-type impurity are doped. Thus, an n-channel TFT and a p-channel TFT can be formed. In this embodiment, an n-type impurity element is added to the semiconductor layer. However, the order of steps is not limited to this embodiment, and the practitioner may determine as appropriate.
[0261]
Next, after removing the resist mask 425, a second heat treatment is performed on the resist mask 425 in an inert atmosphere, for example, in a nitrogen atmosphere. In this embodiment, the heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment step, in the active region 414n of the later n-channel TFT, phosphorus doped at a high concentration in the source / drain region 430 increases the solid solubility with respect to nickel in the region and exists in the channel region. The nickel being moved is moved from the channel region 419n to the source / drain region 430 in the direction indicated by the arrow 413 in FIG. In the active region 414p of the later p-channel TFT, argon doped in the source / drain region 431 forms a segregation site with respect to nickel to cause a gettering action, and the nickel existing in the channel region is removed. Then, the channel region 419p is moved from the channel region 419p to the source / drain region 431 in the direction indicated by the arrow 413. In this way, the gettering process is performed for both the n-channel TFT and the p-channel TFT.
[0262]
In this gettering step, first, nickel dissolved in the channel regions 419n and 419p moves to the source / drain regions 430 and 431, so that the nickel concentration in the channel region is lowered and deposited there. Ni silicide is performed by dissolving in the channel region. These also move to the source / drain regions 430 and 431 in a solid solution state. Finally, Ni silicide in the channel region disappears, and the concentration of nickel in the solid solution state is also reduced. As a result, the nickel concentration in the channel regions 419n and 419p was measured by secondary ion mass spectrometry (SIMS) and found to be 5 × 10. ¹⁵ atoms / cm ^Three It was reduced to the extent that it was almost the lower limit of measurement. Here, the nickel remaining in the channel region is not in a silicide state but exists in a solid solution state as interstitial nickel. Conversely, since nickel moves to the source / drain regions, the nickel concentration in the source / drain regions 430 and 431 is 1 × 10 5. ¹⁹ / Cm ^Three That's it.
[0263]
In this heat treatment step, the n-type impurity (phosphorus) 422 doped in the source / drain region 430 and the LDD region 423 of the n-channel TFT and the p-type doped in the source / drain region 431 of the p-channel TFT. The activation of the type impurity (boron) 426 is also performed at the same time. As a result, the sheet resistance value of the source / drain region 430 of the n-channel TFT was about 400 to 700 Ω / □, and the sheet resistance value of the LDD region 423 was 30 to 60 kΩ / □. The sheet resistance value of the source / drain region 431 of the p-channel TFT was about 1 to 1.5 kΩ / □.
[0264]
Next, as illustrated in FIG. 6D, an interlayer insulating film is formed. A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 400 to 1500 nm (typically 600 to 1000 nm). In this embodiment, a 200-nm-thick silicon nitride film 433 and a 700-nm-thick silicon oxide film 434 are stacked to form a two-layer structure. Of course, the inorganic interlayer insulating film is not limited to this, and another insulating film containing silicon may have a single layer or a laminated structure.
[0265]
Further, heat treatment is performed at 300 to 500 ° C. for about 1 hour. As a result, hydrogen atoms are supplied from the interlayer insulating film (especially the silicon nitride film 433) to the interface between the active region and the gate insulating film, terminating dangling bonds (dangling bonds) that deteriorate TFT characteristics and inactive. Turn into. In this embodiment, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere.
[0266]
Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode / wiring 435 is formed of a two-layer film of a metal material, for example, titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour to complete the n-channel TFT 436 and the p-channel TFT 437 shown in FIG. 6D. Further, if necessary, contact holes are also provided on the gate electrodes 416n and 416p, and necessary electrodes are connected by the wiring 435. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0267]
The field effect mobility of each TFT manufactured according to the above embodiment shows good characteristics similar to those of the third embodiment.
[0268]
Furthermore, in this embodiment, a gettering region is simultaneously formed in the n-channel TFT and the p-channel TFT by using the respective source / drain region forming steps as compared with the first or second embodiment. Can do. Accordingly, there are no additional steps for gettering (deposition step, photolithography step, doping step, annealing step). As a result, the manufacturing process can be simplified, the manufacturing cost of the semiconductor device can be reduced, and the yield rate can be improved.
[0269]
(Fifth embodiment)
A fifth embodiment using the present invention will be described. Also in this embodiment, a process for manufacturing a circuit having a CMOS structure in which an n-channel TFT and a p-channel TFT are complementary to each other on a glass substrate will be described.
[0270]
7 and 8 are cross-sectional views showing the manufacturing process of the TFT described in this embodiment, and the process proceeds sequentially in the order of FIGS. 7A to 7E and FIGS. 8A to 8D. To do.
[0271]
In FIG. 7A, in order to prevent impurity diffusion from the substrate 501 on the surface of the glass substrate 501 on which the TFT is formed, a lower first base film 502 made of a silicon oxynitride film and a second base film made of a silicon oxide film. A base film 503 was laminated. At this time, the film thickness of the silicon oxynitride film of the first base film 502 is, for example, 50 nm, and the film thickness of the silicon oxide film of the second base film 503 is, for example, 100 nm.
[0272]
Next, an amorphous silicon film (a-Si film) 504 containing a rare gas element having a thickness of 30 to 80 nm is formed. In this embodiment, an a-Si film having a thickness of 50 nm is formed by a dual bias dual frequency plasma CVD method as shown in FIG. 15B using silane-based gas and rare gas as material gases. Ar is used as a rare gas element, the substrate heating temperature is 350 ° C., and the gas flow rate is SiH. _Four The gas was 100 sccm and the Ar gas was 1000 sccm. The gas pressure was 0.7 Torr, the RF frequency supplied to the CVD electrode was 27.1 MHz, the RF power was 100 W, the RF frequency supplied to the substrate side was 1.6 MHz, and the RF power was 50 W. The rare gas element concentration in the a-Si film 504 is 5 × 10. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three In this embodiment, about 5 × 10 ¹⁷ atoms / cm ^Three It was about. In addition, since both the base films 502 and 503 and the a-Si film 504 can be formed by a plasma CVD method, both may be continuously formed.
[0273]
Then, a small amount of catalyst element (nickel in this embodiment) 506 is added on the surface of the a-Si film 504. This small amount of nickel 506 was added by holding a solution in which nickel was dissolved on the a-Si film 504, and uniformly extending the solution onto the substrate 501 by a spinner and drying it. In this embodiment, nickel acetate is used as the solute, water is used as the solvent, and the nickel concentration in the solution is 8 ppm. This state corresponds to the state shown in FIG. When the nickel concentration on the surface of the a-Si film 504 thus added in the state of FIG. 7A is measured by a total reflection X-ray fluorescence analysis (TRXRF) method, 5 × 10 5 is obtained. ¹² atoms / cm ² It was about.
[0274]
And this is heat-processed in inert atmosphere, for example, nitrogen atmosphere. In this embodiment, the heat processing for 1 hour were performed at 580 degreeC as an example. In this heat treatment, nickel 506 added to the surface of the a-Si film diffuses into the a-Si film 504 and silicidation occurs, and crystallization of the a-Si film 504 proceeds using this as a nucleus. As a result, as shown in FIG. 5B, the a-Si film 504 is crystallized into a crystalline silicon film 504a. The crystal plane orientation of the crystalline silicon film 504a thus obtained is mainly composed of the <111> crystal zone plane, and among them, the (110) plane orientation and the (211) plane orientation are 50% of the whole. These areas are occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0275]
Next, as shown in FIG. 7C, the crystalline silicon film 504a is further recrystallized by irradiating a laser beam 507 to improve its crystallinity. In this way, the crystalline silicon film 504a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 504b. The crystal plane orientation of the crystalline silicon film 504b thus obtained maintains the state of the crystalline silicon film 504a before laser irradiation, but the average surface roughness Ra is 4 to 9 nm. .
[0276]
Thereafter, unnecessary portions of the crystalline silicon film 504b are removed, and element isolation is performed. By this step, as shown in FIG. 7D, island-like crystalline silicon films 514n and 514p, which later become active regions (source / drain regions, channel regions) of the n-channel TFT and the p-channel TFT, are formed. It is formed.
[0277]
Here, for the purpose of controlling the threshold voltage over the entire active region of the n-channel TFT and the p-channel TFT, 1 × 10 ¹⁶ ~ 5x10 ¹⁷ / Cm ³ Boron (B) may be added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film.
[0278]
Next, a silicon oxide film having a thickness of, for example, 100 nm is formed as a gate insulating film 515 so as to cover the crystalline silicon films 514n and 514p serving as the active regions. In the formation of the silicon oxide film, TEOS was used as a raw material here, and it was decomposed and deposited together with oxygen by an RF plasma CVD method.
[0279]
Subsequently, as shown in FIG. 7E, a refractory metal is deposited by sputtering and patterned to form gate electrodes 516n and 516p. In the present embodiment, tungsten (W) is used as the refractory metal at this time, and the thickness is, for example, 450 nm.
[0280]
Next, a low concentration impurity (phosphorus) 518 is implanted into the active region by ion doping using the gate electrodes 516n and 516p as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 80 kV, and the dose is 2 × 10 ¹³ cm ^-2 It was. In this process, in the island-shaped silicon films 514n and 514p, the region not covered with the gate electrodes 516n and 516p becomes a region 520 into which low-concentration phosphorus 518 is implanted, and is masked by the gate electrodes 516n and 516p and the impurity 518 is implanted The regions that are not formed later become channel regions 519n and 519p of the n-channel TFT and the p-channel TFT. This state corresponds to FIG.
[0281]
Next, as shown in FIG. 8A, in the later n-channel TFT, a photoresist doping mask 521n is provided so as to cover the gate electrode 516n so as to be slightly larger, and in the later p-channel TFT, the gate A doping mask 521p made of a photoresist is provided so as to cover the electrode 516p further and expose the outer edge of the active region 514p. Thereafter, an impurity (phosphorus) 522 is implanted at a high concentration into the active region by ion doping using the resist masks 521n and 521p as a mask. At this time, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 2 × 10. ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 5 × 10 ¹⁵ cm ^-2 And Through this process, in the later n-channel TFT, part of the region 524 into which the impurity (phosphorus) 522 is implanted at a high concentration later constitutes the source / drain region of the n-channel TFT. Then, in the active region 514n, a region covered with the resist mask 521n and not doped with high-concentration phosphorus 522 remains as a region into which low-concentration phosphorus is implanted, thereby forming an LDD (Lightly Doped Drain) region 523. . In addition, by this step, in a p-channel TFT later, a region 524 into which an impurity (phosphorus) 522 is implanted at a high concentration later forms a gettering region of the p-channel TFT. The n-type impurity element (phosphorus) 522 concentration in the region 524 at this time is 1 × 10 ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three It has become. The n-type impurity element (phosphorus) 518 concentration in the LDD region 523 of the n-channel TFT is 1 × 10 ¹⁷ ~ 1x10 ²⁰ / Cm ^Three In such a range, it functions as an LDD region.
[0282]
Next, after removing the resist masks 521n and 521p, as shown in FIG. 8B, the LDD region 523 formed earlier in the active region 514n of the later n-channel TFT is newly enlarged. A photoresist doping mask 525 is provided so as to cover the outer edge of the active region 514n. At this time, no mask is provided above the subsequent p-channel TFT, and the entire TFT is exposed. In this state, an impurity (boron) 526 imparting p-type conductivity is implanted into the active region by ion doping using the resist mask 525 and the gate electrode 516p of the subsequent p-channel TFT as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 7 × 10 ¹⁶ cm ^-2 And By this step, in the n-channel TFT later, a region where boron 526 is implanted at a high concentration later functions as a gettering region 532n of the n-channel TFT. In the active region 514p of the p-channel TFT later, boron 526 is implanted at a high concentration in addition to the channel region 519p below the gate electrode 516p, and phosphorus 518 of n-type impurity implanted at a low concentration in the previous step. Is inverted to become a p-type, and later becomes a source / drain region 531 of a p-channel TFT. Further, a higher concentration boron 526 is implanted into the region 524 where the high concentration phosphorus 522 is implanted, and a gettering region 532p of the p-channel TFT is formed. At this time, the concentration of the p-type impurity element (boron) 526 in the region 531 and the regions 532n and 532p is 1.5 × 10 ¹⁹ ~ 3x10 ^{twenty one} / Cm ^Three It has become. The concentration is 1 to 2 times that of the n-type impurity element (phosphorus). By this step, the gettering region 532n of the n-channel TFT and the gettering region 532p of the p-channel TFT are regions in which phosphorus 522 in the previous step and boron 526 in this step are doped together. .
[0283]
When doping the n-type impurity and the p-type impurity, the regions that do not need to be doped are covered with a photoresist so that each element is selectively doped, and the n-type high-concentration impurity region 530 and the p-type impurity are doped. The impurity region 531 and the gettering regions 532n and 532p are formed, and an n-channel TFT and a p-channel TFT can be formed. In this embodiment, an n-type impurity element is added to the semiconductor layer. However, the order of steps is not limited to this embodiment, and the practitioner may determine as appropriate.
[0284]
Next, after removing the resist mask 525, a second heat treatment is performed on the resist mask 525 in an inert atmosphere, for example, in a nitrogen atmosphere. In this embodiment, the heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment step, in the active region 514n of the n-channel TFT later, phosphorus and boron doped in a high concentration in the gettering region 532n formed outside the source / drain region are treated with nickel in the region. In addition, the segregation sites for nickel are formed, and the crystal defects generated during doping also function as the segregation sites for nickel. Then, the nickel existing in the channel region 519n, the LDD region 523, and the source / drain region 530 is transferred from the channel region to the LDD region, further to the source / drain region, and the gettering region 532n in FIG. It is moved in the direction indicated by 513. The source / drain region 530 doped only with phosphorus also has a gettering effect. However, since the ability of the gettering region 532n doped with phosphorus and boron is overwhelmingly high, nickel is collected in the gettering region 532n. Further, in the active region 514p of the later p-channel TFT, phosphorus and boron doped in high concentration in the gettering region 532p formed outside the source / drain regions perform the same function, and the channel region 519p. Similarly, nickel existing in the source / drain region 531 is moved from the channel region to the source / drain region and then to the gettering region 532p in the direction indicated by the arrow 513. The gettering step is performed by the above steps.
[0285]
In this gettering step, first, nickel dissolved in the channel regions 519n and 519p, the LDD region 523, and the source / drain regions 530 and 531 moves to the gettering regions 532n and 532p. The nickel concentration is lowered, and Ni silicide deposited there is dissolved in the silicon film. These also move to the gettering regions 532n and 532p in a solid solution state, Ni silicide disappears, and the concentration of nickel in the solid solution state is also reduced. By this heat treatment process, nickel moves to the gettering regions 532n and 532p, so that the nickel concentration in the gettering regions 532n and 532p is 1 × 10. ¹⁹ / Cm ^Three That's it. On the other hand, the nickel concentration is measured by secondary ion mass spectrometry (SIMS) in the channel region of the TFT active region, the junction between the channel region and the source / drain region, or the junction between the LDD region. 5 × 10 ¹⁵ atoms / cm ^Three It was about the lower limit of measurement. In addition, the nickel remaining in these regions is not in a silicide state, but is present in a solid solution state as interstitial nickel.
[0286]
In this heat treatment step, n-type impurities (phosphorus) doped in the source / drain regions 530 and LDD regions 523 of the n-channel TFT and p-type doped in the source / drain regions 531 of the p-channel TFT. Impurity (phosphorus) activation is also performed at the same time. As a result, the sheet resistance value of the source / drain region 530 of the n-channel TFT was about 400 to 700 Ω / □, and the sheet resistance value of the LDD region 523 was 30 to 60 kΩ / □. The sheet resistance value of the source / drain region 531 of the p-channel TFT was about 1 to 1.5 kΩ / □.
[0287]
Next, as illustrated in FIG. 8D, an interlayer insulating film is formed. A 200-nm-thick silicon nitride film 533 and a 700-nm-thick silicon oxide film 534 are stacked to form a two-layer structure. Of course, the inorganic interlayer insulating film is not limited to this, and another insulating film containing silicon may have a single layer or a laminated structure.
[0288]
Further, heat treatment is performed at 300 to 500 ° C. for about 1 hour. As a result, hydrogen atoms are supplied from the interlayer insulating film (especially the silicon nitride film 533) to the interface between the active region and the gate insulating film, terminating dangling bonds (dangling bonds) that deteriorate TFT characteristics and inactive. Turn into.
[0289]
Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode / wiring 535 is formed from a metal film, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour to complete the n-channel TFT 536 and the p-channel TFT 537 shown in FIG. Further, if necessary, contact holes are provided also on the gate electrodes 516n and 516p, and necessary electrodes are connected by the wiring 535. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0290]
The field effect mobility of each TFT manufactured according to the above embodiment shows good characteristics similar to those of the third embodiment and the fourth embodiment.
[0291]
Furthermore, also in this embodiment, gettering regions can be simultaneously formed in the n-channel TFT and the p-channel TFT using the respective source / drain region forming steps. Accordingly, there are no additional steps (gettering step, doping step, annealing step) for gettering. As a result, the manufacturing process can be simplified, the manufacturing cost of the semiconductor device can be reduced, and the yield rate can be improved.
[0292]
(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIGS. Also in this embodiment, a method for manufacturing an n-channel TFT and a p-channel TFT on the same substrate will be described.
[0293]
A first base insulating film 602 made of a silicon nitride film with a thickness of 50 nm is formed on the glass substrate 601, and then a second base insulating film 603 made of a silicon oxide film with a thickness of 100 nm is formed. Further, an a-Si film 604 having a thickness of 20 to 100 nm, for example, 50 nm is formed. At this time, the a-Si film 604 can be formed by the same method as in the first to fifth embodiments. In this embodiment, a normal plasma CVD method as shown in FIG. 15A is used, the substrate heating temperature is 250 ° C., and the gas flow rate is SiH. _Four An a-Si film 604 containing Ar was formed with a gas of 100 sccm, an Ar gas of 5000 sccm, a gas pressure of 0.5 Torr, an RF frequency supplied to the CVD electrode of 27.1 MHz, and an RF power of 100 W. . The Ar concentration in the a-Si film 604 thus obtained is about 1 × 10 6. ¹⁷ atoms / cm ^Three It was about.
[0294]
Subsequently, a catalytic element is added to the a-Si film 604 and heat treatment is performed. An aqueous solution (nickel acetate aqueous solution) containing a catalytic element (nickel in this embodiment) of 10 ppm in terms of weight is applied to the amorphous silicon film by a spin coating method to form the catalytic element-containing layer 606. This state corresponds to FIG.
[0295]
Then, the first heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. As the heat treatment at this time, annealing treatment is performed at 520 to 600 ° C. for 1 to 8 hours. In this embodiment, as an example, the heat treatment was performed at 550 ° C. for 4 hours. In this heat treatment, silicidation of nickel 606 added to the surface of the a-Si film occurs, and crystallization of the a-Si film 604 proceeds using this as a nucleus. As a result, as shown in FIG. 9B, the a-Si film 604 is crystallized into a crystalline silicon film 604a. The crystal plane orientation of the crystalline silicon film 604a thus obtained is mainly composed of the <111> crystal zone plane, and among them, (110) plane orientation and (211) plane orientation are 50% of the whole. These areas are occupied. The grain size of the crystal grains (substantially the same plane orientation region) is 2 to 10 μm.
[0296]
Subsequently, as shown in FIG. 9C, the crystalline silicon film 604a obtained by the heat treatment is irradiated with laser light to form a crystalline silicon film 604b with improved crystallinity. The crystallinity of the crystalline silicon film 604b is greatly improved by this laser light irradiation. Also in this embodiment, a pulse oscillation type XeCl excimer laser (wavelength: 308 nm) is applied as the laser light. The crystal plane orientation of the crystalline silicon film 604b thus obtained maintains the state of the crystalline silicon film 604a before laser irradiation, but the average surface roughness Ra is 4 to 9 nm. .
[0297]
Subsequently, as shown in FIG. 9D, the crystalline silicon film is etched into a predetermined shape to form an active region 614n of the later n-channel TFT and an active region 614p of the p-channel TFT.
[0298]
Next, a gate insulating film 615 covering these active regions 614n and 614p is formed. Subsequently, a conductive film is formed over the gate insulating film 615 by a sputtering method, a CVD method, or the like. As the conductive film, any one of refractory metals W, Ta, Ti, Mo, or an alloy material thereof may be used. Then, as shown in FIG. 9E, the conductive film is etched to form gate electrodes 616n and 616p.
[0299]
Next, a low concentration n-type impurity (phosphorus) 618 is implanted into the active region by ion doping using the gate electrodes 616n and 616p as a mask. In this embodiment, phosphine (PH _Three ), The acceleration voltage is 80 kV, and the dose is 2 × 10 ¹³ cm ^-2 It was. In this process, in the island-like silicon films 614n and 614p, the region not covered with the gate electrodes 616n and 616p becomes the region 620 into which low-concentration phosphorus 618 is implanted, and the gate electrodes 616n and 616p are masked and the impurity 618 is implanted. The regions that are not formed later become channel regions 619n and 619p of the n-channel TFT and the p-channel TFT. This state corresponds to FIG.
[0300]
Next, as shown in FIG. 9F, in the active region 614n of the n-channel TFT, a photoresist doping mask 621n is provided so as to largely cover the gate electrode 616n, and the active region of the p-channel TFT is provided. In 614p, a photoresist doping mask 621p is provided so as to cover the entire active region. Thereafter, an impurity (phosphorus) 622 is implanted at a high concentration into the active region by ion doping using the resist masks 621n and 621p as a mask. In this embodiment, phosphine (PH _Three ), Acceleration voltage is 80 kV, dose amount is 5 × 10 ¹⁵ cm ^-2 It was. By this step, in the later n-channel TFT, a high concentration (1 × 10 ¹⁹ ~ 1x10 ^{twenty one} / Cm ^Three A portion of the region 624 in which phosphorus 622 is implanted at a concentration of the n-channel TFT later becomes a source / drain region. In the active region 614n, a region that is covered with the resist mask 621n and is not doped with high-concentration phosphorus 622 remains as a region into which low-concentration phosphorus is implanted, thereby forming an LDD (Lightly Doped Drain) region 623. . In the later p-channel TFT, no phosphorus is implanted into the active region 614p.
[0301]
Next, after removing the resist masks 621n and 621p, as shown in FIG. 10A, a doping mask 625 made of photoresist is provided so as to cover the entire active region 614n of the subsequent n-channel TFT. At this time, no mask is provided on the active region 614p of the subsequent p-channel TFT, and the entire TFT is exposed. In this state, an impurity (boron) 626 imparting p-type conductivity is implanted into the active region by ion doping using the resist mask 625 and the gate electrode 616p of the subsequent p-channel TFT as a mask. As a doping gas, diborane (B ₂ H ₆ ), The acceleration voltage is 65 kV, and the dose is 7 × 10 ¹⁶ cm ^-2 It was. Through this step, boron 626 is implanted at a high concentration in the active region 614p of the p-channel TFT later than the channel region 619p below the gate electrode 616p, and the n-type impurity implanted at a low concentration in the previous step. The phosphorus 618 is inverted to become a p-type impurity region 627.
[0302]
Next, after removing the resist mask 625, as shown in FIG. 10B, a new n-channel TFT gate electrode 616n and a later p-channel TFT gate electrode 616p are newly covered. Masks 628n and 628p made of resist are formed. The masks 628n and 628p at this time expose part (outer edge portions) of the active regions 614n and 614p of the later n-channel TFT and p-channel TFT. In this state, a rare gas element (Kr in this embodiment) 629 is ion-doped from above the substrate. By this step, the rare gas element 629 is implanted into the exposed region of the TFT active region, and gettering regions 632n and 632p are formed at the outer edges of the active regions 614n and 614p of the n-channel TFT and the p-channel TFT. The The doping condition of krypton 629 at this time is 100% Kr as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 3 × 10 ¹⁵ cm ^-2 It was. A region covered with the masks 628n and 628p is not doped with a rare gas element. As the rare gas element at this time, one or a plurality of kinds of rare gas elements selected from Ar, Kr, and Xe can be used, but the rare gas element originally contained in the active region (Ar in this embodiment) is used. However, an element having a large atomic number is preferable. In this step, the concentration of the rare gas element in the gettering regions 632n and 632p is 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three To be. Further, by this step, the crystallinity of the gettering regions 632n and 632p is destroyed and made amorphous.
[0303]
Then, after removing the resist masks 628n and 628p, a second heat treatment is performed in an inert atmosphere, for example, a nitrogen atmosphere. In the present embodiment, RTA (Rapid Thermal Annealing) is used. An RTA apparatus of a type in which high-temperature nitrogen gas was blown onto the substrate surface in a nitrogen atmosphere to instantaneously raise and lower the temperature was used. Specific treatment conditions include a holding temperature in the range of 550 to 750 ° C., a holding time of about 30 seconds to 15 minutes, and more preferably a holding temperature in the range of 600 to 700 ° C. and a holding time of about 1 minute to 10 minutes. . In this embodiment, the RTA treatment was performed at 670 ° C. for 5 minutes. It is preferable that the temperature increase rate and the temperature decrease rate are both 100 ° C./min or more. In the embodiment, the rate is about 200 ° C./min. In the active region of each TFT, gettering regions 632n and 632p formed outside the source / drain regions are highly doped with krypton 629 and crystal defects caused by amorphization at the time of doping However, it forms a segregation site for nickel and causes a gettering action. As a result, in this heat treatment step, as shown in FIG. 10C, nickel existing in the channel region 619n, the LDD region 623, and the source / drain region 630 in the active region 614n of the later n-channel TFT. Are moved from the channel region to the LDD region, further to the source / drain region and the gettering region 632n in the direction indicated by the arrow 613. Similarly, in the active region 614p of the later p-channel TFT, nickel existing in the channel region 619p and the source / drain region 631 is similarly transferred from the channel region to the source / drain region and the gettering region 632p. Move in the direction indicated by arrow 613.
[0304]
In this gettering step, first, nickel dissolved in the channel regions 619n and 619p, the LDD region 623, and the source / drain regions 630 and 631 moves to the gettering regions 632n and 632p. The nickel concentration decreases, and Ni silicide deposited there begins to dissolve in the silicon film. These also move to the gettering regions 632n and 632p in a solid solution state. Finally, Ni silicide disappears and the concentration of nickel in the solid solution state is also reduced. Since nickel moves to the gettering region by this heat treatment step, the nickel concentration in the gettering regions 632n and 632p is 1 × 10. ¹⁹ / Cm ^Three That's it. In the channel region of the TFT active region, the junction between the channel region and the source / drain region, or the junction between the LDD region, the nickel concentration was measured by secondary ion mass spectrometry (SIMS) and found to be 5 × 10. ¹⁵ atoms / cm ^Three It was about the lower limit of measurement. In addition, the nickel remaining in these regions is not in a silicide state, but is present in a solid solution state as interstitial nickel.
[0305]
In this heat treatment step, n-type impurity (phosphorus) doped in the source / drain region 630 and LDD region 623 of the n-channel TFT and p-type doped in the source / drain region 631 of the p-channel TFT. Impurity (boron) activation is also performed at the same time. As a result, the sheet resistance value of the source / drain region 630 of the n-channel TFT was about 400 to 700 Ω / □, and the sheet resistance value of the LDD region 623 was 30 to 60 kΩ / □. The sheet resistance value of the source / drain region 631 of the p-channel TFT was about 1 to 1.5 kΩ / □. In this embodiment, in the active region of the n-channel TFT and the p-channel TFT, a gettering region is formed in a region different from the source region or the drain region. There is no problem even if the resistance increases in the source region or drain region of the TFT.
[0306]
After this step, the ratio Pa / Pc between the amorphous Si TO phonon peak Pa and the crystalline Si TO phonon peak Pc in the Raman spectrum of each TFT channel region and gettering region is measured by laser Raman spectroscopy. Then, the gettering region is larger than the channel region. This measurement can be performed from the back side of the substrate when a transparent glass substrate or the like is used as in this embodiment. Further, after this heat treatment step, no further high temperature step is performed, so this state is maintained even after the TFT is completed.
[0307]
Next, as illustrated in FIG. 10D, an interlayer insulating film is formed. In this embodiment, a silicon nitride film 633 having a thickness of 200 nm and a silicon oxide film 634 having a thickness of 700 nm are stacked to form a two-layer structure.
[0308]
Further, heat treatment is performed at 300 to 500 ° C. for about 1 hour. As a result, hydrogen atoms are supplied from the interlayer insulating film (particularly the silicon nitride film 633) to the interface between the active region and the gate insulating film, terminating dangling bonds (dangling bonds) that deteriorate TFT characteristics and inactive. Turn into.
[0309]
Next, a contact hole is formed in the interlayer insulating film, and a TFT electrode / wiring 635 is formed from a metal material, whereby an n-channel TFT 636 and a p-channel TFT 637 shown in FIG. 10D are completed. Further, if necessary, a contact hole is also provided on the gate electrodes 616n and 616p, and necessary electrodes are connected by a wiring 635.
[0310]
The field effect mobility of each TFT fabricated according to the above embodiment showed good characteristics similar to those of the third to fifth embodiments.
[0311]
(Seventh embodiment)
In the present embodiment, a crystallization method different from those in the first to sixth embodiments will be described. FIG. 11 is used for the description. FIG. 11 is a cross-sectional view showing a manufacturing process in the present embodiment, and the manufacturing process sequentially proceeds according to FIGS.
[0312]
First, as in the first to sixth embodiments, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like is formed on a substrate (in this embodiment, a glass substrate) 701 in order to prevent impurity diffusion from the substrate. A base film is formed. In the present embodiment, a silicon nitride film is formed as a lower first base film 702, and a silicon oxide film is stacked on the second base film 703. At this time, the film thickness of the silicon oxynitride film of the first base film 702 is, for example, 100 nm, and the film thickness of the silicon oxynitride film of the second base film 703 is, for example, 100 nm. Next, an a-Si film 704 having a thickness of 30 to 80 nm is formed by the same method as in the first to sixth embodiments. In this embodiment, the amorphous silicon film is formed to a thickness of 50 nm by plasma CVD. In this step, the base insulating film and the amorphous semiconductor layer may be formed continuously without being released to the atmosphere.
[0313]
Next, a mask insulating film 705 made of a silicon oxide film is formed to a thickness of 200 nm. As shown in FIG. 11A, the mask insulating film has an opening 700 for adding a catalytic element to the semiconductor film.
[0314]
Next, as shown in FIG. 11B, an aqueous solution (nickel acetate aqueous solution) containing 100 ppm of the catalytic element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form the catalytic element layer 706. To do. At this time, the catalytic element 706 selectively contacts the a-Si film 704 in the opening 700 of the mask insulating film 705 to form a catalytic element addition region. The catalyst elements that can be used here are iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum. One or more elements selected from (Pt), copper (Cu), and gold (Au).
[0315]
In this embodiment, nickel is added by spin coating, but a thin film made of a catalytic element (in this embodiment, nickel film) is formed on the a-Si film by vapor deposition or sputtering. You may take the means to do.
[0316]
Next, heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 20 hours (preferably 8 to 15 hours). In this embodiment, a heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 11C, crystal nuclei are generated in the catalytic element addition region 700, and the a-Si film in the region 700 is first crystallized to become a crystalline silicon film 704a. Furthermore, crystallization proceeds in a direction parallel to the substrate (direction indicated by an arrow 707) starting from the crystallization region, and a crystalline silicon film 704b having a uniform macroscopic crystal growth direction is formed. At this time, the nickel 706 existing on the mask 705 is blocked by the mask film 705 and does not reach the underlying a-Si film, and the a-Si film 704 is crystallized only by the nickel introduced in the region 700. Done. A region where the lateral crystal growth does not reach remains as an amorphous region 704c. However, depending on the layout, a boundary may be generated by colliding with a crystal growth region in the lateral direction from an adjacent opening, and in this case, it is not an amorphous region.
[0317]
After removing the silicon oxide film 705 used as a mask, the obtained crystalline silicon film is irradiated with a laser beam as shown in FIG. 11D, similarly to the first to fifth embodiments. The crystallinity may be improved. As a result, the crystalline silicon film in the region 704b in which the crystal is grown in the lateral direction is further improved in quality and becomes a crystalline silicon film 704d.
[0318]
Subsequently, the crystalline silicon film in the laterally grown region 704d is etched into a predetermined shape to form an active region 709 of the subsequent TFT.
[0319]
By applying the crystallization method shown in this embodiment to the crystallization process in the first to fifth embodiments, a high-performance TFT with higher current driving capability can be realized.
[0320]
(Eighth embodiment)
In this embodiment, the gettering region in the active region for moving the catalyst element used for crystallization of the semiconductor film shown in the fifth or sixth embodiment is shown in FIG. 12 and FIG. An example is shown.
[0321]
By applying this embodiment to the TFT manufacturing process of the fifth or sixth embodiment, various shapes of gettering regions can be formed in the active regions of the n-channel TFT and the p-channel TFT. Further, the areas of the gettering region in the active region of the n-channel TFT and the gettering region in the active region of the p-channel TFT are made approximately equal, and the distance from the gettering region to the channel region is made approximately equal. In addition, it is possible to improve the effect that the gettering efficiency for the catalytic elements of the n-channel TFT and the p-channel TFT is made uniform. Examples of the shape of the gettering region formed in the active region are shown below. Note that to make the area of the gettering region in the active region of the n-channel TFT and the gettering region in the active region of the p-channel TFT approximately equal to each other, the width of the active region (channel region) in each TFT is W, When the area S of the gettering region is defined, the ratio S / W of the width W of the active region (channel region) and the area S of the gettering region is approximately equal in the n-channel TFT and the p-channel TFT.
[0322]
FIG. 12A shows that the gettering regions 83a and 84a are long in the direction parallel to the gate electrode 85a at a position (outer edge portion of the active region) away from the channel region formed in the active region below the gate electrode 85a. In this example, the corners of the rectangle are arranged so as to hang over the corners of the active region.
[0323]
In FIG. 12B, the gettering regions 83b and 84b are perpendicular to the gate electrode 85b at a position away from the channel region formed in the active region below the gate electrode 85b (outer edge portion of the semi-active region). This is an example in which a rectangular shape having a long side is arranged such that the corner portion of the rectangle is hooked on the corner portion of the active region.
[0324]
FIG. 12C shows that the gettering regions 83c and 84c are separated from the channel region formed in the active region below the gate electrode 85c (outer edge portion of the active region) and extend in a direction parallel to the gate electrode 85c. This is an example of a complicated shape formed by combining a rectangle having a side and a rectangle having a long side in the vertical direction, and the corner portion of the shape is placed on the corner portion of the active region. In this case, compared with FIG. 12A or FIG. 12B, the area of the gettering region can be increased, and the gettering efficiency for the catalytic element can be further increased.
[0325]
In any of the above arrangement examples, the gettering region is a contact portion formed in each of the source region and the drain region (the portion where the wiring electrically connecting each TFT is connected to the active region is described in this specification. In this case, the current flowing between the contact portions is not disturbed. That is, the gettering regions 83a and 84a in FIG. 12A are arranged at positions that do not hinder the current flowing between the contact portion 86a formed in the source region 81a and the contact portion 87a formed in the drain region 82a. Has been.
[0326]
Further, the gettering regions 83b and 84b in FIG. 12B are arranged at positions that do not hinder the current flowing between the contact portion 86b connected to the source region 81b and the contact portion 87b formed in the drain region 82b. Has been.
[0327]
Further, the gettering regions 83c and 84c in FIG. 12C are arranged at positions that do not hinder the current flowing between the contact portion 86c formed in the source region 81c and the contact portion 87c formed in the drain region 82c. Has been.
[0328]
FIG. 12D is basically the same arrangement example as FIG. 12C. However, in order to increase the gettering efficiency of the gettering regions 83d and 84d, the area of the gettering regions 83d and 84d is further expanded. In this example, the gettering region 83d is applied to a part of the contact portion 86d. Basically, there is no problem even if the gettering regions 83d and 84d cover a part of the contact portions 86d and 87d, but care must be taken so that the overlapping area is at most half of the contact portions 86d and 87d. . Accordingly, the design distance between the contact portions 86d and 87d and the gettering regions 83d and 84d is set to a suitable design distance in consideration of the alignment accuracy of the exposure apparatus used in the photolithography process corresponding to each region formation. It is necessary to decide. Note that the position where the gettering region is provided is not limited to the configuration of the present embodiment, and may be any location as long as it does not affect (does not disturb) the current flowing between the source region and the drain region. It may be provided.
[0329]
In FIG. 13A, the active region is crossed by a plurality of gate electrodes 85e, and a plurality of channel regions are formed below the active region. A source region 81e (or drain region 82e), a gettering region 88e, and a contact portion 89e are formed between the plurality of gate electrodes. As in FIGS. 12A to 12D, gettering regions 83e and 84e are formed at the outer edge portion of the active region, and a source region 81e or drain region 82e and contact portions 86e and 87e are formed inside thereof. ing. Also in the case shown in FIG. 13A, the gettering region 83e may cover a part of the contact portion 86e, but basically, the overlapping area is at most less than half of the contact portions 86e and 87e. It is necessary to pay attention to this.
[0330]
FIG. 13B is also an example in which a plurality of gate electrodes 85f cross the active region and a plurality of channel regions are formed therebelow. In FIG. 13B, two TFTs are connected in series while sharing an active region, and there is no contact portion at the connection portion, that is, an arrangement in which there is no need to take out an electric signal from the connection portion. is there. The TFT having such a configuration is actually used in a circuit such as a clocked inverter or a latch circuit. A source region 81f (or drain region 82f) and a gettering region 88f are formed between the plurality of gate electrodes. In addition, gettering regions 83f and 84f are formed in the outer edge portion of the active region as in FIGS. 12A to 12D, and a source region 81f or drain region 82f and contact portions 86f and 87f are formed inside thereof. ing. In the region of the connecting portion, the gettering region 88f is arranged at a position that does not hinder at least the current flowing from the contact portion 86f to the contact portion 87f.
[0331]
Note that the shape of the active region of the TFT varies depending on the amount of current required for the TFT. As shown in FIGS. 12 and 13, the width of the channel region is narrower than that of the source / drain region, and the wedge shape is obtained when the source / drain region and the channel region have the same width. In either case, the present invention can be similarly applied.
[0332]
Further, no matter which shape of the gettering region is applied, the catalytic element moves to the gettering region by heat treatment for gettering, so that the catalytic element is 1 × 10 6. ¹⁹ / Cm ^Three It becomes the above density.
[0333]
This embodiment can be applied in combination with the fifth embodiment or the sixth embodiment.
[0334]
(Ninth embodiment)
A block diagram of a semiconductor device manufactured using the present invention is shown in FIG. FIG. 14A shows a circuit configuration for performing analog driving. This embodiment shows a semiconductor device having a source side driver circuit 90, a pixel portion 91, and a gate side driver circuit 92. Note that in this specification, a drive circuit refers to a generic name including a source side processing circuit and a gate side drive circuit.
[0335]
The source side driver circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate side driving circuit 92 includes a shift register 92a, a level shifter 92b, and a buffer 92c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.
[0336]
In the present embodiment, the pixel unit 91 includes a plurality of pixels, and each of the plurality of pixels includes a TFT.
[0337]
Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 92 with the pixel portion 91 interposed therebetween.
[0338]
FIG. 14B shows a circuit configuration for performing digital driving. This embodiment shows a semiconductor device having a source side driver circuit 93, a pixel portion 94, and a gate side driver circuit 95. In the case of digital driving, a latch (A) 93b and a latch (B) 93c may be provided instead of the sampling circuit as shown in FIG. The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, a D / A converter 93d, and a buffer 93e. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.
[0339]
In addition, the said structure is realizable according to the manufacturing process shown to above-mentioned Embodiment 1-8. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.
[0340]
(10th Embodiment)
A CMOS circuit and a pixel portion formed by implementing the present invention can be used for an active matrix liquid crystal display device. That is, the present invention can be implemented in all electric appliances in which these liquid crystal display devices are incorporated in a display portion.
[0341]
Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned.
[0342]
By applying the present invention, a crystalline silicon film having good crystallinity using a catalytic element can be formed, and the catalytic element can be sufficiently gettered. Therefore, an n-channel TFT and a p-channel TFT Thus, it is possible to realize a good CMOS driving circuit with high reliability and stable circuit characteristics. In addition, even in a switching TFT in a pixel in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch portion, etc., the generation of a leakage current considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, a good display without display unevenness is possible. In addition, since it is a good display with no display unevenness, it is not necessary to use a light source more than necessary, and wasteful power consumption can be reduced, and electric appliances that can reduce power consumption (cell phones, portable books, displays) ) Can be realized.
[0343]
As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. In addition, the electric appliance of the present embodiment can be realized using the display device manufactured by combining the embodiments and the embodiments.
[0344]
As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, Various deformation | transformation based on the technical idea of this invention is possible.
[0345]
For example, as a method for forming an amorphous silicon film containing a rare gas element, a rare gas was used as a sputtering gas in addition to the above-described plasma CVD method or the ion doping method using a rare gas element for an amorphous silicon film. A sputtering method or a method of plasma doping a rare gas element into an amorphous silicon film can also be applied. In addition to the pure silicon film shown in the above-described embodiment, a mixed film of germanium and silicon (silicon / germanium film) or a pure germanium film can also be used as the semiconductor film targeted by the present invention.
[0346]
Moreover, as a method of introducing nickel, a method of applying a solution in which a nickel salt was dissolved on the surface of the amorphous silicon film was adopted, but before the amorphous silicon film was formed, nickel was introduced to the surface of the base film, Alternatively, nickel may be diffused from the lower layer of the amorphous silicon film to cause crystal growth. In addition, various other methods can be used for introducing nickel. For example, SOG (spin on glass) material is used as a solvent for dissolving nickel salt, and SiO 2 ₂ There is also a method of diffusing from the film. Further, a method of forming a thin film by a sputtering method, a vapor deposition method, a plating method, a method of directly introducing by an ion doping method, or the like can also be used.
[0347]
In the above embodiment, phosphorus is used in the gettering step, but arsenic and antimony may also be used. Further, xenon has a great effect as a rare gas element for gettering in addition to argon and krypton.
[0348]
【The invention's effect】
By using the present invention, a catalytic element remaining in a device region of a crystalline semiconductor layer having a good crystallinity produced using a catalytic element, particularly a channel region or a junction between a channel region and a source region or a drain region. Can be sufficiently reduced. By using such a TFT using a semiconductor film, the generation of leakage current can be suppressed, the reliability can be improved, and a high-performance semiconductor element having stable characteristics with little characteristic variation can be realized. it can. Furthermore, an additional process for gettering can be reduced, and the manufacturing process can be simplified. As a result, the yield rate can be greatly improved in the manufacturing process, and the manufacturing cost of the semiconductor device can be reduced.
[0349]
Therefore, by using the present invention, a high-performance semiconductor element can be realized, and a high-performance semiconductor device with a high degree of integration can be obtained by a simple manufacturing process. Particularly in liquid crystal display devices, the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance and high integration required for the TFT constituting the peripheral drive circuit section are simultaneously satisfied. In addition, in a driver monolithic type active matrix substrate that constitutes an active matrix portion and a peripheral drive circuit portion, the module can be made compact, high performance, and low cost.
[Brief description of the drawings]
FIGS. 1A to 1H are schematic cross-sectional views illustrating manufacturing steps of a semiconductor device according to Embodiment 1 of the present invention. FIGS.
FIGS. 2A to 2H are schematic cross-sectional views illustrating manufacturing steps of a semiconductor device according to Embodiment 2 of the present invention. FIGS.
FIGS. 3A to 3E are schematic cross-sectional views showing manufacturing steps of a semiconductor device according to Embodiment 3 of the present invention. FIGS.
FIGS. 4A to 4C are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to Embodiment 3 of the present invention (continuation of FIG. 3).
FIGS. 5A to 5F are schematic cross-sectional views showing manufacturing steps of a semiconductor device according to Embodiment 4 of the present invention. FIGS.
6A to 6D are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to Embodiment 4 of the present invention (continuation of FIG. 5).
FIGS. 7A to 7E are schematic cross-sectional views illustrating manufacturing steps of a semiconductor device according to Embodiment 5 of the present invention. FIGS.
8A to 8D are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention (continuation of FIG. 7).
FIGS. 9A to 9F are schematic cross-sectional views showing manufacturing steps of a semiconductor device according to Embodiment 6 of the present invention. FIGS.
FIGS. 10A to 10D are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to Embodiment 6 of the present invention (continuation of FIG. 9).
FIGS. 11A to 11E are schematic cross-sectional views showing another crystallization method used for manufacturing a crystalline semiconductor film according to an embodiment of the present invention. FIGS.
FIGS. 12A to 12D are diagrams schematically showing an example of arrangement of gettering regions in an eighth embodiment of the present invention.
FIGS. 13A and 13B are diagrams schematically showing another arrangement example of gettering regions in the eighth embodiment of the present invention. FIGS.
FIGS. 14A and 14B are views schematically showing a configuration of a semiconductor device according to an eighth embodiment of the present invention.
FIGS. 15A and 15B are diagrams schematically showing a plasma CVD apparatus used for depositing an amorphous semiconductor film, in which FIG. 15A shows a known CVD apparatus, and FIG. 15B is suitably used in an embodiment of the present invention. FIG.
FIG. 16 is a schematic view showing another plasma CVD apparatus suitably used in the embodiment of the present invention.
FIG. 17 is a schematic view for explaining a gettering mechanism in the method of manufacturing a semiconductor film of the present invention.
FIG. 18 is a graph showing the relationship between gettering annealing time and getterable distance.
FIG. 19 is a graph showing the relationship between the heat treatment temperature during crystallization and the getterable distance.
FIG. 20 is an optical micrograph of a crystalline silicon film that is made visible by etching Ni silicide with hydrofluoric acid after heat treatment for crystallization.
FIG. 21 is a schematic diagram for explaining the mechanism of Ni silicide solid-solution.
FIG. 22 is a graph showing the relationship between Ni concentration and crystal nucleus generation density when an amorphous silicon film is crystallized using Ni as a catalyst element.
FIG. 23 is a scanning electron microscope (SEM) photograph showing a state after Ni silicide of a silicon film crystallized using Ni is etched, (A) is amorphous silicon containing no rare gas element; 1B shows a crystallized film, and FIG. 1B shows a crystallized amorphous silicon film containing Ar as a rare gas element.
FIG. 24A is a graph showing the relationship between the Ar concentration in a silicon film and the crystal nucleus generation density during crystallization, and FIG. 24B shows the Ar concentration in the silicon film and precipitated after crystallization. It is a graph which shows the relationship with the magnitude | size of the catalyst element compound (Ni silicide) which is.
FIGS. 25A to 25C are diagrams for explaining a state of crystal orientation in a crystalline semiconductor film obtained by the present invention. FIGS.
FIGS. 26A to 26C are diagrams showing the state of crystal orientation in the crystalline semiconductor film obtained by the present invention, and are images obtained by performing image processing on the measurement result of the backscattered electron diffraction image (EBSP). FIGS. is there.
[Explanation of symbols]
101 glass substrate
103 Underlayer
104 Amorphous semiconductor film containing rare earth elements (a-Si film)
104a Crystalline semiconductor film (crystalline silicon film)
104b High quality crystalline semiconductor film (crystalline silicon film)
106 Catalytic element (nickel)
107 Laser light
108 mask
109 Gettering element (phosphorus)
110 gettering region (region doped with phosphorus)
113 Arrow indicating catalyst element movement direction
114 crystalline silicon film
115 Gate insulating film
116 Gate electrode
117 oxide layer
119 Region where impurities are not implanted
122 N-type impurity (phosphorus)
130 Impurity implanted region
134 Interlayer insulation film
135 Electrode / Wiring
136 TFT (semiconductor element)

Claims (20)

(A) forming an amorphous silicon layer containing a rare gas element at a concentration of 5 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less on the insulating surface;
(B) A catalyst element for promoting crystallization is applied to the amorphous silicon layer at a concentration of 1.8 × 10 ¹² cm ⁻² or more and 9.0 × 10 ¹² cm ⁻² or less, and then a first heat treatment is performed. To crystallize the amorphous silicon layer to obtain a crystalline semiconductor layer,
(C) By moving at least a part of the catalyst element remaining in the crystalline semiconductor layer, a low catalyst concentration region in which the concentration of the catalyst element is lower than other regions is formed in the crystalline semiconductor layer. Process,
The noble gas element is argon, the catalyst element is nickel,
In the step (a), the amorphous silicon layer includes a plasma CVD step of introducing the rare gas element into the amorphous silicon layer while depositing the amorphous silicon layer using a plasma CVD method.
The plasma CVD step includes a step of supplying a first power to the CVD electrode and a second power different from the first power to the substrate having the insulating surface . The step (b) includes a process of crystal growth using a semiconductor compound of the catalytic element as a crystal nucleus, and the semiconductor compound is nickel silicide,
2. The method of manufacturing a semiconductor film according to claim 1 , wherein the step (c) includes a step of dissolving the semiconductor compound of the catalytic element in the crystalline semiconductor layer in the low catalyst concentration region. It said first power and said second power frequency is different RF power from each other, the method of manufacturing a semiconductor film according to claim 1 or 2. The method of manufacturing a semiconductor film according to claim 3 , wherein a frequency of the second power is lower than a frequency of the first power. In the step (c), a gettering region or a gettering layer having an action of attracting the catalyst element is formed, and a second heat treatment is performed after this step, so that it remains in the crystalline semiconductor film. comprising a step of moving the catalyst element to the gettering region or the gettering layer, a method of manufacturing a semiconductor film according to any one of claims 1 to 4. The method of manufacturing a semiconductor film according to claim 5 , further comprising a step of patterning the crystalline semiconductor layer into a desired shape before the step (c). The gettering region or the gettering layer, comprising said more than other regions of the amorphous component of the crystalline semiconductor film, a method of manufacturing a semiconductor film according to claim 5 or 6. The gettering region or the gettering layer contains an impurity element belonging to periodic table group V B which imparts n-type conductivity, a method of manufacturing a semiconductor film according to any of claims 5-7. The method of manufacturing a semiconductor film according to claim 8 , wherein the impurity element includes at least one element selected from the group consisting of P, As, and Sb. The gettering region or the gettering layer contains an impurity element belonging to periodic table group III B which imparts p-type conductivity, a method of manufacturing a semiconductor film according to any of claims 5 to 9. The method of manufacturing a semiconductor film according to claim 10 , wherein the impurity element includes at least one of B and Al. The gettering region or the impurity elemental that the gettering layer contains is introduced by an ion doping method, a method of manufacturing a semiconductor film according to any of claims 8 to 11. Wherein in after step (c), a method of manufacturing a semiconductor film according to any one of the gettering region or the further encompasses claims 5-12 removing the gettering layer. In the step (b), after the catalytic element is selectively applied to a partial region of the amorphous silicon film, the catalytic element is selectively applied by performing the first heat treatment. and comprising the step of crystal growth and its periphery in the lateral direction from the partial region, a method of manufacturing a semiconductor film according to any one of claims 1 to 13. The step (b), after the first heat treatment, comprising the step of irradiating the laser light to the crystalline semiconductor film, a method of manufacturing a semiconductor film according to any one of claims 1 to 14. Preparing a semiconductor film manufactured by the manufacturing method of a semiconductor film according to any of claims 1 to 15,
Producing a thin film transistor having the semiconductor film in an active region;
A method for manufacturing a semiconductor device including: The active region includes a channel region, a source region, and a drain region,
The method for manufacturing a semiconductor device according to claim 16 , wherein the step of manufacturing the thin film transistor includes a step of forming at least the channel region in the low catalyst concentration region. The method of manufacturing a semiconductor device according to claim 17 , wherein the step of manufacturing the thin film transistor includes a step of forming the channel region, the source region, and the drain region in the low catalyst concentration region. The active region includes a channel region, a source region, a drain region, and an LDD region,
The method of manufacturing a semiconductor device according to claim 16 , wherein the step of manufacturing the thin film transistor includes a step of forming at least the channel region and the LDD region in the low catalyst concentration region. The method for manufacturing a semiconductor device according to claim 19 , wherein the step of manufacturing the thin film transistor includes a step of forming the channel region, the source region, the drain region, and the LDD region in the low catalyst concentration region.

Images