JP4115153B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a thin film transistor (TFT) and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device including a thin film transistor having a crystalline region manufactured by crystallizing an amorphous semiconductor film as a channel formation region or the like, and a manufacturing method thereof. The present invention is particularly suitably used for active matrix liquid crystal display devices, organic EL display devices, contact image sensors, three-dimensional ICs, and the like.
[0002]
[Prior art]
In recent years, high-resolution liquid crystal display devices and organic EL display devices, high-speed, high-resolution contact image sensors, three-dimensional ICs, etc. have been developed on insulating substrates such as glass and insulating films. Attempts have been made to form high performance semiconductor devices. In particular, a liquid crystal display device in which a pixel portion and a drive circuit are provided on the same substrate has begun to enter into a general household as well as a monitor for a personal computer (PC). For example, instead of CRT (Cathode-ray Tube), liquid crystal displays as televisions and front projectors for watching movies and playing games as entertainment have been introduced into ordinary homes. The market for equipment is growing at a considerable rate. Furthermore, development of a system-on-panel in which a logic circuit such as a memory circuit or a clock generation circuit is built on a glass substrate is being promoted.
[0003]
The amount of information written to a pixel increases to display a high-resolution image, and if that information is not written in a short time, an image having an enormous amount of information for high-definition display is displayed as a moving image. Is impossible. Accordingly, high-speed operation is required for TFTs used in driving circuits. In order to enable high-speed operation, it is required to realize a TFT using a crystalline semiconductor film having good crystallinity that can obtain high field effect mobility.
[0004]
As a method for obtaining a good crystalline semiconductor film on a glass substrate, the present inventors have conventionally added a metal element having an action of promoting crystallization to an amorphous semiconductor film, followed by heat treatment. We are developing a technology to obtain a good semiconductor film with uniform crystal orientation by heat treatment at lower temperature and shorter time.
[0005]
However, a TFT manufactured using a crystalline silicon film obtained by using a catalytic element as a semiconductor layer as it is has a problem that off-current suddenly increases. Catalytic element segregates irregularly in the semiconductor film, especially at the grain boundaries, and this segregation of the catalytic element becomes a current escape path (leakage path), which causes sudden off-current. It is thought that it is causing the increase. Therefore, it is necessary to reduce the concentration of the catalytic element in the semiconductor film by moving the catalytic element from the semiconductor film after the crystalline silicon film manufacturing process. Hereinafter, the process of removing the catalyst element is referred to as a gettering process.
[0006]
Various methods have been proposed for this gettering process. In Japanese Patent Laid-Open No. 10-270363, a silicon crystallized by a catalytic element is selectively introduced with a group 5 B (phosphorus, etc.) element such as phosphorus, and a heat treatment is performed. A technique for moving (gettering) a catalytic element to a region into which a Group 5 B element has been introduced is disclosed. According to this technique, the active region of the semiconductor device is formed using a region other than the region where the Group 5 B element is introduced (that is, a region where the concentration of the catalytic element is reduced by gettering).
[0007]
Japanese Patent Laid-Open No. 11-40499 discloses that a catalytic element is more gettered by irradiating a region where a group 5 B element is selectively introduced with intense light such as laser light and then performing heat treatment. A technique for enhancing the effect of ringing is disclosed.
[0008]
Furthermore, Japanese Patent Application Laid-Open No. 11-54760 discloses a technique for enhancing the gettering effect on the catalytic element by introducing a Group 3 B element (boron or the like) in addition to the Group 5 B element.
[0009]
[Problems to be solved by the invention]
The first problem in the conventional gettering process is that the process becomes complicated due to the addition of a process for gettering, and the manufacturing cost increases. As a solution to this problem, a method of removing the catalytic element from the channel region by moving the catalytic element to the source or drain region of the TFT active region instead of removing all the catalytic element from the TFT active region is considered. It was.
[0010]
In this method, a region to be a source region or a drain region is used as a region for collecting a catalyst element (referred to as a “gettering region” in this specification). Therefore, an element belonging to Group B of the periodic table having a function of moving the catalyst element (typically phosphorus, arsenic, etc .: also an impurity element imparting n-type) is highly concentrated in the source / drain regions. Added and heat-treated. By this heat treatment, the catalyst element moves to the source / drain region, and the concentration of the catalyst element contained in the channel formation region is reduced. At this time, as taught in Japanese Patent Laid-Open No. 11-54760, an impurity element belonging to Group B of the periodic table (typically boron, aluminum, etc .: also an impurity element imparting p-type) is used as a source. -A higher gettering effect can be expected by adding a high concentration to the drain region.
[0011]
However, when the source region or the drain region is used as a gettering region, in an n-channel TFT, an element belonging to Group 5 B that imparts n-type (phosphorus or the like) acts alone as a gettering element. In a channel TFT, only an element belonging to Group 3 B that imparts p-type (boron or the like) does not act as a gettering element. For this reason, it is necessary to add an element (phosphorus or the like) belonging to Group 5 B that imparts n-type as a gettering element to the source region or drain region of the p-channel TFT. That is, in the p-channel TFT, it is necessary to invert the region to which the impurity element imparting n-type at a high concentration is added to p-type (referred to as counter-doping) for the gettering process with respect to the catalyst element. In order to invert the n-type to the p-type in the p-channel TFT semiconductor layer, the p-type impurity element must be added 1.5 to 3 times the n-type impurity element. Therefore, when the amount of addition of an element belonging to Group B that imparts n-type (such as phosphorus) is increased to increase the gettering effect, the amount of addition of an element belonging to Group B that imparts p-type (such as boron) is also increased. It was necessary to raise it to an insane level, and the processing capacity of the doping apparatus was greatly reduced, and it was not a process capable of mass production.
[0012]
Furthermore, as the gettering effect, the addition of an element belonging to Group 3 B that imparts p-type (boron or the like) in addition to an element belonging to Group 5 B that imparts n-type (such as phosphorus) increases. There is also a problem that the gettering capability is not uniform between the n-channel TFT and the p-channel TFT. If there is a difference in gettering capability, the efficiency of moving the catalytic element contained in the semiconductor film to the gettering region differs between the n-channel TFT and the p-channel TFT, resulting in variations in device characteristics. It was one of the causes.
[0013]
In addition, an n-channel TFT that performs gettering only with an element belonging to Group 5 B that imparts n-type (phosphorus or the like) does not have a sufficient gettering effect, and the residual amount of catalyst element in the TFT channel region is still insufficient. It has not been reduced. When the inventors actually conducted experiments using the methods described in Japanese Patent Application Laid-Open Nos. 10-270363 and 11-40499 and prototyped TFT elements, there were slight differences in the effects. As can be seen, a defective TFT with a very large leakage current when the TFT is turned off appears with a probability of several percent. Then, when the cause of the defective TFT was analyzed, it was confirmed that silicide due to the catalytic element was present at the junction between the channel region and the drain region. Therefore, in the technique of the above publication, the catalytic element cannot be sufficiently gettered, and even if a high-performance TFT element can be partially manufactured, the defect rate is high, the reliability is low, and mass production is possible. It was not a good technique.
[0014]
On the other hand, as in the technique described in Japanese Patent Application Laid-Open No. 11-54760, both an impurity element belonging to Group 5 B and an impurity element belonging to Group B are added to the n-channel TFT. The gettering effect can be further enhanced. However, in this case, in the n-channel TFT, the n-type impurity element must be added at a higher concentration than the p-type impurity element. On the other hand, in a p-channel TFT, the p-type impurity element must be added at a higher concentration than the n-type impurity element. Therefore, the manufacturing process becomes very complicated. In addition, since the concentration of the impurity added in the gettering regions in the semiconductor layers having different conductivity types is different, the problem that the gettering efficiency is different between the n-channel TFT and the p-channel TFT cannot be solved.
[0015]
Furthermore, it has been found that the phenomenon that the leakage current increases during the TFT off operation is mainly caused by segregation of the catalytic element present at the junction between the channel region and the drain region. Therefore, when the source region and the drain region are used as gettering regions, the junction between the channel region and the source / drain region is also a boundary between the gettering region and the non-gettering region. It is difficult to suppress an increase in leakage current.
[0016]
The present invention has been made in view of the above problems, and a main object of the present invention is to provide a semiconductor device having good characteristics by manufacturing a thin film transistor using a high-quality crystalline semiconductor region.
[0017]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a semiconductor layer including a crystalline region including a channel formation region, a source region, and a drain region, a gate electrode that controls conductivity of the channel formation region, the gate electrode, and the semiconductor layer The semiconductor layer includes a gettering region doped with a rare gas element.
[0018]
In a preferred embodiment, the concentration of the rare gas element in the gettering region is higher than the concentration of the rare gas element in the channel formation region, the source region, and the drain region.
[0019]
In a preferred embodiment, the gettering region is formed outside the crystalline region in the semiconductor layer.
[0020]
In a preferred embodiment, the gettering region is not adjacent to the channel forming region.
[0021]
In a preferred embodiment, the gettering region is located outside a portion where a wiring electrically connecting each thin film transistor is in contact with the semiconductor layer.
[0022]
In a preferred embodiment, the gettering region is formed at an outer edge portion of the semiconductor layer, and a portion where a wiring electrically connecting each thin film transistor is in contact with the semiconductor layer is a part of the gettering region. And a region including the crystalline region.
[0023]
In a preferred embodiment, the gettering region is formed at an outer edge portion of the semiconductor layer, and a portion where a wiring electrically connecting each thin film transistor is in contact with the semiconductor layer is in the crystalline region.
[0024]
In a preferred embodiment, a plurality of thin film transistors are allocated to one of the semiconductor layers, the source region or the drain region is shared by the plurality of thin film transistors, and the gettering region is shared by the plurality of thin film transistors. It is formed at a position adjacent to the source region or drain region.
[0025]
In a preferred embodiment, the gettering region is formed in an outer edge portion of the semiconductor layer and a region sandwiched between the source region or the drain region, and a wiring electrically connecting each thin film transistor is connected to the semiconductor layer. The contact portion is a region including a part of the gettering region and a region including the crystalline region.
[0026]
In a preferred embodiment, the gettering region is formed in an outer edge portion of the semiconductor layer and a region sandwiched between the source region or the drain region, and a wiring electrically connecting each thin film transistor is connected to the semiconductor layer. The contacting portion is in the crystalline region.
[0027]
In a preferred embodiment, a semiconductor layer including a crystalline region including a channel formation region, a source region, and a drain region, a gate electrode that controls conductivity of the channel formation region, and the gate electrode and the semiconductor layer An n-channel thin film transistor having a gate insulating film provided therebetween, a semiconductor layer including a crystalline region including a channel formation region, a source region, and a drain region, and conductivity of the channel formation region are controlled A semiconductor device comprising a p-channel thin film transistor having a gate electrode and a gate insulating film provided between the gate electrode and the semiconductor layer, wherein each semiconductor layer is doped with a rare gas element Includes gettering area.
[0028]
In a preferred embodiment, the concentration of the rare gas element in the gettering region is higher than the concentration of the rare gas element in the channel formation region, the source region, and the drain region.
[0029]
In a preferred embodiment, the gettering region is formed outside the crystalline region in each semiconductor layer.
[0030]
In a preferred embodiment, the ratio S / W of the area S of the gettering region to the width W of the active region in the n-channel TFT is such that the ratio of the gettering region to the width W of the active region in the p-channel TFT. It is approximately equal to the ratio S / W of the area S.
[0031]
In a preferred embodiment, the distance L from the junction between the source region or drain region and the channel portion in the n-channel TFT to the gettering region is such that the source region or drain region and the channel portion in the p-channel TFT. Is approximately equal to the distance L from the junction to the gettering region.
[0032]
In a preferred embodiment, the semiconductor layer is made of crystalline silicon.
[0033]
In a preferred embodiment, the gettering region is doped with at least one kind of rare gas element selected from the group consisting of Ar, Kr, and Xe.
[0034]
In a preferred embodiment, the gettering region includes 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three Is doped with a rare gas element at a concentration of.
[0035]
In a preferred embodiment, the rare gas element concentration in the channel formation region is 1 × 10 ¹⁹ atoms / cm ^Three It is as follows.
[0036]
In a preferred embodiment, the gettering region includes at least one selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu as a catalytic element for promoting crystallization of an amorphous silicon film. Species elements are present.
[0037]
In a preferred embodiment, the gettering region contains 1 × 10 catalyst elements that promote crystallization of the amorphous silicon film. ¹⁹ atoms / cm ^Three It exists in the above concentration.
[0038]
In a preferred embodiment, the gate electrode is made of at least one material selected from the group consisting of W, Ta, Ti, and Mo.
[0039]
The method for manufacturing a semiconductor device according to the present invention includes a step of preparing an amorphous semiconductor film to which a catalytic element for promoting crystallization is added at least partially, and a first heat treatment for the amorphous semiconductor film. Performing a step of crystallizing at least a part of the amorphous semiconductor film to obtain a semiconductor film including a crystalline region; and patterning the semiconductor film so that each of the plurality of crystalline regions includes a plurality of crystalline regions. A step of forming an island-shaped semiconductor layer; a step of selectively adding a rare gas element to a part of the island-shaped semiconductor layer to form a gettering region; and a second heat treatment, whereby the island-shaped semiconductor layer is formed. Moving at least part of the pre-catalyst element in the semiconductor layer to the gettering region.
[0040]
In a preferred embodiment, the method further includes a step of doping a selected portion of the island-shaped semiconductor layer with an n-type impurity and / or a p-type impurity before performing the second heat treatment.
[0041]
In a preferred embodiment, a step of forming a gate insulating film on the island-shaped semiconductor layer, a step of forming a gate electrode on the gate insulating film, and the island-shaped semiconductor layer not covered with the gate electrode Doping the region with n-type impurities and / or p-type impurities.
[0042]
In a preferred embodiment, the step of preparing the amorphous semiconductor film includes a step of forming a mask having an opening on the amorphous semiconductor film, and the catalyst element is passed through the opening. Adding to selected areas.
[0043]
In a preferred embodiment, the gettering region is formed at a position adjacent to the source region or drain region of the thin film transistor and not adjacent to the channel region.
[0044]
In a preferred embodiment, the gettering region is formed in a region other than a region where electrons or holes move.
[0045]
In a preferred embodiment, the gettering region is formed at a position closer to the outer edge of the island-shaped semiconductor layer than the center of the contact region for electrically connecting the island-shaped semiconductor layer and the wiring.
[0046]
In a preferred embodiment, the gettering region partially overlaps the contact region.
[0047]
In a preferred embodiment, the concentration of the rare gas element in the gettering region is 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three Adjust within the range.
[0048]
In a preferred embodiment, the rare gas element is at least one element selected from the group consisting of Ar, Kr, and Xe.
[0049]
In a preferred embodiment, the method further includes a step of irradiating the semiconductor film with laser light after the first heat treatment.
[0050]
In a preferred embodiment, the impurity doped in the island-like semiconductor layer is activated by the second heat treatment.
[0051]
In a preferred embodiment, the catalytic element is at least one element selected from the group consisting of Ni, Co, Sn, Pb, Pd, Fe, and Cu.
[0052]
An electronic apparatus according to the present invention includes any one of the above semiconductor devices.
[0053]
In a preferred embodiment, a display unit is provided that performs a display operation using the semiconductor device.
[0054]
DETAILED DESCRIPTION OF THE INVENTION
The present inventors have found a rare gas element as a new gettering element that replaces the Group 5 B element. The rare gas element has a higher gettering efficiency than the group 5 B element with respect to the catalyst element, and is inert even in the semiconductor film. However, it has been found that the resistance value is greatly deteriorated when added to an n-type or p-type low-resistance semiconductor film. That is, when the catalytic element in the channel region is gettered using the source region and drain region of the TFT active region as a gettering region, a problem of increased resistance occurs when a rare gas element is added to the source region and drain region. Further, when such a source region and drain region are used as a gettering region as they are, the junction between the channel region and the source / drain region is also a boundary between the gettering region and the non-gettering region, and the channel region and the drain region The segregation of the catalytic elements present in the joints cannot be removed.
[0055]
In the present invention, the semiconductor layer functioning as the active region of the TFT has a gettering region separately from the source region and the drain region, and the gettering region is a carrier (electron or hole) of the TFT. The carrier is formed in a region other than the region where the carrier moves so as not to hinder the movement.
[0056]
When the gettering region contains a rare gas element, high gettering efficiency can be realized. In order to ensure gettering efficiency, the concentration of the rare gas element in the gettering region needs to be higher than the concentration of the rare gas element in the channel region and the source / drain regions.
[0057]
By providing the source / drain region and the gettering region at different positions, the addition amount of the n-type impurity and the p-type impurity to be doped into the source / drain region can be set optimally. As a result, the process margin can be expanded and the throughput of the doping apparatus can be greatly improved. Further, the resistance of the source / drain regions can be lowered, and the on-characteristics of the TFT can be improved.
[0058]
By providing a gettering region outside the source / drain region, the concentration of the catalytic element in the source / drain region is sufficiently reduced, so that the catalytic element remaining at the junction between the channel region and the source / drain region creates a leak path. There is almost no possibility. As a result, along with high gettering efficiency due to rare gas elements, it is possible to almost completely suppress an increase in leakage current during off operation, which is a problem in TFT characteristics, and at the same time ensure high reliability. Can do.
[0059]
As described above, according to the present invention, it is possible to suppress the generation of leakage current due to segregation of the catalytic element, and it is possible to realize a TFT having good characteristics particularly when used as a switching element in a pixel portion.
[0060]
Since a semiconductor film crystallized using a catalytic element exhibits good crystallinity, the TFT of the semiconductor device according to the present invention is good even when used as an element of a drive circuit that requires high field effect mobility. The characteristic can be exhibited.
[0061]
In the TFT manufactured by the prior art, the abnormal increase phenomenon of the leakage current when the TFT is turned off, which was seen with a probability of about 3%, was not seen at all with the semiconductor device according to the present invention.
[0062]
In the liquid crystal display device manufactured using the semiconductor device of the present invention, there is no linear display irregularity (due to the sampling TFT in the driver section) that frequently occurs in the conventional method, or pixel defects due to leakage current at the time of OFF, and display quality is improved. Greatly improve. Moreover, the yield rate can be increased and realized with a simple manufacturing process.
[0063]
By forming the gettering region so as not to be adjacent to the channel formation region, gettering from the junction between the channel region and the source / drain regions can be sufficiently achieved as described above. For this reason, it is possible to almost completely suppress an increase in leakage current at the time of TFT off operation, which is likely to be caused by the segregation residue of the catalytic element at the junction.
[0064]
If a gettering region is formed at a position closer to the outer edge of the semiconductor layer than a region (contact region) to which wiring for electrically connecting each TFT is connected, the path of TFT carriers (electrons or holes) is not obstructed. An efficient arrangement can be realized, and a gettering region having a large area as much as possible can be realized.
[0065]
Even if a gettering region is formed in the outer edge portion of the semiconductor layer and the contact region and the gettering region are partially overlapped, a carrier path that is not obstructed by the gettering region can be secured. The relatively high resistance in the region does not greatly reduce the on-current of the TFT.
[0066]
If the contact region is arranged avoiding the gettering region, the carrier path of the TFT can be secured most stably, and a high on-current can be obtained.
[0067]
When a plurality of TFTs are arranged on the same substrate and various circuits such as a clocked inverter and a latch circuit are formed, a plurality of TFTs are used by using one semiconductor layer (active region) for efficient use of the layout area. It is preferable to form a TFT. In that case, a gettering region can be provided in a portion shared by adjacent TFTs. Even in this case, the gettering region is preferably formed in a region other than the region where the TFT carrier moves. For example, gettering regions can be arranged in the outer edge of the semiconductor layer and in a region sandwiched between source / rain regions.
[0068]
In such a case, the contact region is preferably arranged in a region other than the gettering region, but the contact region and the gettering region may partially overlap as long as the carrier path of the TFT can be secured.
[0069]
The present invention can also be applied to the case where an n-channel TFT and a p-channel TFT are formed on the same substrate. If the n-channel TFT and the p-channel TFT contain the rare gas element having the same concentration as the gettering element, the n-channel TFT and the p-channel TFT have substantially the same gettering capability. The gettering efficiency can be made uniform in the type TFT and the p-channel type TFT.
[0070]
As a result, the concentration of the catalytic element remaining in each of the n-channel TFT and the p-channel TFT becomes substantially equal, and variations in device characteristics due to the residual concentration of the catalytic element can be reduced. Furthermore, the concentration of the catalytic element can be sufficiently reduced at the channel forming region or at the junction between the channel forming region and the source / drain region.
[0071]
In a pair of n-channel TFT and p-channel TFT, the ratio S / W of the area S of the gettering region to the width W of the active region is set to be approximately equal between the n-channel TFT and the p-channel TFT. Is preferred. In addition, it is preferable that the distance L from the junction formed between the source / drain region and the channel portion to the gettering region is approximately the same between the n-channel TFT and the p-channel TFT.
[0072]
The gettering effect for the catalytic element existing in the channel region of the TFT is most dominant in the gettering efficiency of the gettering region. However, as other factors, the ratio of the area of the gettering region to the width of the TFT channel region and the distance L from the TFT channel region to the gettering region are parameters that have an important influence on the gettering effect.
[0073]
The gettering capability increases as the area S of the gettering region increases, and the gettering efficiency of the channel region is determined by S / W. The gettering distance (= “distance L”) necessary for the gettering movement of the catalytic element greatly affects the gettering efficiency for the channel region.
[0074]
In the present invention, the n-channel TFT and the p-channel TFT are designed so that the S / W and the L are substantially the same, and the gettering efficiency is more uniform in the n-channel TFT and the p-channel TFT. In addition, since the remaining catalyst element concentrations in both the n-channel TFT and the p-channel TFT are substantially equal, variation in device characteristics due to the remaining concentration of the catalyst element can be reduced.
[0075]
In the present invention, the active region (semiconductor layer) of the TFT is preferably formed from a crystalline silicon film having crystallinity. By using the crystalline silicon film as the active region, stable TFT characteristics can be obtained, and the balance between the on characteristics and the off characteristics in the TFT is excellent. The manufacturing process is also easy and the material is very easy to handle. In addition to the crystalline silicon film, materials applicable to the present invention include a microcrystalline silicon film and a crystalline germanium film.
[0076]
Next, the manufacturing method of the present invention will be described.
[0077]
In the present invention, an amorphous semiconductor film in which a catalyst element for promoting crystallization is added at least in part is prepared, and the amorphous semiconductor film is subjected to a first heat treatment, whereby an amorphous semiconductor film is obtained. Crystallizing at least a part of the crystalline semiconductor film to obtain a semiconductor film including a crystalline region, and forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film; Then, a rare gas element is selectively added to a part of the island-shaped semiconductor layer to form a gettering region, and a second heat treatment is performed, so that at least one of the previous catalyst elements in the island-shaped semiconductor layer is obtained. Moving the part to the gettering region.
[0078]
Before performing the second heat treatment, an impurity element imparting n-type (n-type impurity element) and / or p is used to form a source / drain region for a selected portion of the island-shaped semiconductor layer. A step of doping an impurity element imparting a mold (p-type impurity element) may be performed.
[0079]
When introducing the catalytic element into the amorphous semiconductor film, first, a mask having an opening is formed on the amorphous semiconductor film, and the catalytic element is applied to a selected region of the amorphous semiconductor film through the mask opening. It may be added. By the subsequent first heat treatment, crystal growth can be performed in the lateral direction from the region where the catalytic element is selectively added to the periphery thereof, so that a crystalline semiconductor film can be formed. As a result, it is possible to obtain a good crystalline semiconductor film in which the crystal growth direction is aligned substantially in one direction, and it is possible to further increase the current driving capability of the TFT.
[0080]
The gettering region is preferably formed adjacent to the source region or the drain region and not adjacent to the channel region in the active region of the TFT. The gettering region is preferably formed in a region other than the region where electrons or holes move.
[0081]
If the gettering region contains one or more kinds of rare gas elements selected from Ar, Kr, and Xe, a large interstitial distortion occurs there, and the gettering site serves as a gettering action of the catalytic element. Works powerfully. The group 5 B element (phosphorus, etc.) used in JP-A-10-270363 and JP-A-11-40499 is used as a gettering region by increasing the solid solubility of the catalytic element in the semiconductor film. Although it acts, the rare gas element in the present invention is a completely different action and has a stronger gettering action. If one or more kinds of rare gas elements selected from Ar, Kr, and Xe are used, a sufficient gettering effect can be obtained in the present invention. In particular, the most effective of these rare gas elements is Ar is the most effective when Ar is used.
[0082]
The concentration of the rare gas element added to the gettering region of the active region is 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three It is preferable that By setting the concentration of the rare gas element in the gettering region within such a range, the gettering effect of the present invention can be suitably obtained. On the other hand, the concentration of the rare gas element in the gettering region is 1 × 10. ¹⁹ atoms / cm ^Three If it is less, the gettering action on the catalytic element cannot be seen. This concentration is 3 × 10 ^{twenty one} atoms / cm ^Three If it is larger, the gettering effect becomes saturated and the film quality of the gettering region becomes porous, causing problems such as peeling of the semiconductor layer in that region.
[0083]
The rare gas element added to the gettering region stays in the region until the semiconductor device is manufactured and does not move to another region.
[0084]
The rare gas element concentration in the channel formation region is 1 × 10 ¹⁹ atoms / cm ^Three The following is preferable. Although it is not necessary to forcibly add a rare gas element to the channel region, there is a possibility that a trace amount of a rare gas element is contained in the original film formation of the semiconductor film. In order to obtain the effect of the present invention, it is preferable that the concentration of the rare gas element in the non-gettering region is lower than that in the gettering region. The concentration of the channel region is 1 × 10 ¹⁹ atoms / cm ^Three The following is preferable.
[0085]
As the catalyst element, one or more elements selected from Ni, Co, Sn, Pb, Pd, Fe, and Cu can be used. These elements have an effect of promoting crystallization in a small amount. In particular, the most prominent effect can be obtained when Ni is used. The following model can be considered for this reason. The catalytic element does not act alone, but acts on crystal growth by bonding to the silicon film and silicidation. The crystal structure at that time is a model that acts as one type of template during crystallization of the amorphous silicon film and promotes crystallization of the amorphous silicon film. Ni is two Si and NiSi ₂ The silicide is formed. NiSi ₂ Shows a meteorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, NiSi ₂ Has a lattice constant of 5.406 、, which is very close to the lattice constant of 5.430 で in the diamond structure of crystalline silicon. Therefore, NiSi ₂ Is the best template for crystallizing an amorphous silicon film, and it is most desirable to use Ni as the catalyst element in the present invention.
[0086]
When the semiconductor device of the present invention is manufactured using such a catalyst element, the above catalyst added as a catalyst element for promoting crystallization of the amorphous silicon film in the gettering region in the final semiconductor device. Elements will be present. The concentration of the catalytic element is 1 × 10 6 in the gettering region. ¹⁹ atoms / cm ^Three As described above, the concentration of the catalytic element in the channel region is 1 × 10 ¹⁵ ~ 1x10 ¹⁷ atoms / cm ^Three Reduced to the extent of the degree. Thus, the catalyst element concentration in the gettering region is increased by 2 to 4 orders of magnitude compared to the catalyst element concentration in the channel region.
[0087]
After crystallization using the above catalyst element, it is preferable to further irradiate the crystalline semiconductor film thus obtained with laser light. By laser light irradiation, crystal grain boundaries and minute residual amorphous regions (uncrystallized regions) are intensively processed due to the difference in melting point between the crystalline portion and the amorphous portion.
[0088]
The crystalline silicon film crystallized by introducing the catalytic element is formed of columnar crystals, and the inside thereof is in a single crystal state. Therefore, when the crystal grain boundary is processed by laser light irradiation, Thus, a high-quality crystalline silicon film close to a single crystal state is obtained, and the crystallinity is greatly improved. As a result, the on-characteristics of the TFT are greatly improved, and a semiconductor device with improved current driving capability can be realized.
[0089]
It is preferable that activation of the n-type impurity element or the p-type impurity element added to the active region is performed at the same time by using a heat treatment performed for gettering. If gettering and activation are performed simultaneously by this heat treatment, the number of steps is shortened. As a result, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0090]
When the heat treatment for gettering is performed after the formation of the gate electrode, the gate electrode of the TFT is preferably formed of a material selected from W, Ta, Ti, and Mo, or a combination of these materials. Since heat treatment requires a temperature of 500 ° C. or higher for gettering, a refractory metal is desirable from the viewpoint of heat resistance.
[0091]
The efficiency with which the catalytic element moves to the gettering region can be observed, for example, by the following method.
[0092]
When the catalytic element (nickel) moves to the gettering region due to the influence of the element added to the gettering region, the catalytic element combines with Si in the process of moving from the channel formation region to the gettering region, and thus NiSi. _x (Nickel silicide). This nickel silicide forms a silicon oxide film with ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) is removed by a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa Corporation), and the volume ratio is HF (concentration 50%): H ₂ O ₂ (Concentration 33%): H ₂ By immersing the substrate in a chemical solution (FPM solution) mixed at O = 45: 72: 4500 for 40 minutes, NiSi _x Can be selectively removed.
[0093]
NiSi _x After the removal, the holes become NiSi _x The hole after the removal is observed as a black spot in the transmission mode of the optical microscope. If the number of observed black spots is large, it can be evaluated that the catalyst element (nickel) can be moved to the gettering region in a large amount, that is, the gettering efficiency is good.
[0094]
(Embodiment)
An embodiment of the present invention will be described with reference to FIG.
[0095]
In this embodiment, an n-channel TFT is manufactured on a glass substrate. 1A to 1G are cross-sectional views illustrating a manufacturing process of an n-channel TFT, and the process proceeds in the order of (A) to (G). Although a single TFT is shown in FIG. 1, in practice, a large number of TFTs are formed simultaneously on the same substrate.
[0096]
First, reference is made to FIG.
[0097]
A base insulating film 12 made of a silicon oxide or silicon nitride film having a thickness of 50 to 300 nm is formed on the glass substrate 11. This base insulating film is provided to prevent diffusion of impurities from the glass substrate. Thereafter, an intrinsic (I-type) amorphous silicon film (a-Si film) 13 having a film thickness of 20 to 80 nm is deposited on the base insulating film 12.
[0098]
Next, a heat treatment is performed after adding a catalytic element to the a-Si film 13 for crystallization. Specifically, first, an aqueous solution (nickel acetate aqueous solution) containing, for example, 10 ppm of a catalytic element (nickel in this embodiment) in terms of weight is applied to the a-Si film 13 by a spin coating method to contain the catalytic element. Layer 14 is formed. The catalyst elements that can be used here are iron (Fe), nickel (Ni), cobalt (Co), tin (Sn), lead (Pb), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium. These are one or more elements selected from the group consisting of (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au). The amount of the catalytic element to be added is extremely small, and the concentration of the catalytic element on the surface of the a-Si film 13 is managed by the total reflection X-ray fluorescence analysis (TRXRF) method. In the present embodiment, the catalyst element concentration on the surface of the a-Si film 13 is 7 × 10. ¹² atoms / cm ² Adjusted to degree.
[0099]
In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film (a nickel film in this embodiment) formed from a catalytic element is formed by an evaporation method, a sputtering method, or the like. It may be deposited on top.
[0100]
Next, the substrate subjected to the above treatment is heated in an inert atmosphere (for example, a nitrogen atmosphere). This heat treatment is preferably performed at 550 to 600 ° C. for about 30 minutes to 4 hours (for example, at 580 ° C. for 1 hour). In this heat treatment, nickel 14 added to the surface of the a-Si film 13 diffuses into the a-Si film 13 and silicidation occurs, and the a-Si film 13 is crystallized using the generated silicide as a nucleus. Progresses. As a result, the a-Si film 13 is crystallized to become a crystalline silicon film 13a. Although crystallization is performed here by heat treatment using a furnace, crystallization may be performed by an RTA (Rapid Thermal Annealing) apparatus using a lamp or the like as a heat source.
[0101]
Next, as shown in FIG. 1B, the crystalline silicon film 13b is irradiated with a laser beam 15 to form a crystalline silicon film 14b with improved crystallinity of the crystalline silicon film 13a. As the laser light, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) or a KrF excimer laser (wavelength 248 nm) can be used. The beam size of the laser light is formed to be a long shape on the surface of the substrate 11, and the entire surface of the substrate can be recrystallized by sequentially scanning in the direction perpendicular to the long direction. preferable. At this time, scanning is performed so that parts of the beams overlap each other, so that laser irradiation is performed a plurality of times at any one point of the crystalline silicon film 13a, and uniformity can be improved. In this way, the crystalline silicon film 13a obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 13b.
[0102]
Thereafter, unnecessary portions of the crystalline silicon film 13b are removed, and element isolation is performed. By this step, as shown in FIG. 1C, an island-like crystalline silicon film 16 that will later become an active region (source / drain region, channel region) of the TFT is formed. In this specification, each “active region” refers to an individual island-shaped semiconductor layer including a source / drain region, a channel formation region, and a gettering region. In the present invention, one or more thin film transistors are formed using one active region.
[0103]
Next, a gate insulating film 17 covering these island-like crystalline silicon films 16 is formed. As the gate insulating film 17, a silicon oxide film having a thickness of 20 to 150 nm is preferable. In this embodiment, a silicon oxide film having a thickness of 100 nm is used.
[0104]
After depositing a conductive film on the gate insulating film 17 by sputtering or CVD, the conductive film is patterned to form the gate electrode 18. As the conductive film, refractory metals W, Ta, Ti, Mo, or any of these alloy materials may be used. The thickness of the conductive film is preferably 300 to 600 nm. In this embodiment, the gate electrode 18 is formed from Ta to which nitrogen having a thickness of 450 nm is added in a small amount.
[0105]
Next, as shown in FIG. 1D, a mask 19 made of a resist is formed over the gate insulating film 17 so as to cover the gate electrode 18. This mask 19 does not cover all of the island-shaped semiconductor, and a part (outer edge portion) of the active region 16 of the TFT is exposed. In this state, a rare gas element (Ar in this embodiment) 20 is ion-doped from above the substrate 11 to the entire surface of the substrate 11. Through this step, the rare gas element 20 is implanted into the exposed region 21 of the TFT active region 16 to form the gettering region 21. A region covered with the mask 19 is not doped with a rare gas element. As the rare gas element, one or more kinds of rare gas elements selected from Ar, Kr, and Xe can be used. The doping condition is that the rare gas element concentration in the gettering region 21 is 1 × 10. ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three It is adjusted to become.
[0106]
After removing the mask 19, an n-type impurity (phosphorus) 22 is implanted into the active region 16 at a high concentration by ion doping using the gate electrode 18 as a mask as shown in FIG. By this step, high concentration phosphorus 22 is implanted into the region 24 not covered with the gate electrode 18 in the TFT active region 16. Of the region where phosphorus 22 is implanted, the portion other than the gettering region 21 finally becomes the source / drain region of the TFT. Further, the region 23 masked by the gate electrode 18 and not implanted with phosphorus 22 finally becomes a channel region of the TFT. Next, heat treatment is performed in an inert atmosphere (for example, a nitrogen atmosphere) to perform gettering as illustrated in FIG. Specifically, in the gettering region 21 formed outside the source / drain region 24, argon 20 that is highly doped is used to replace nickel existing in the channel region 23 and the source / drain region 24, The channel region is moved to the source / drain region and the gettering region 21 in the direction indicated by the arrow 25. Therefore, the catalyst element remaining at the channel forming region of the TFT active region or the junction between the channel forming region and the source region or the drain region can be gettered, and generation of a leakage current due to segregation of the catalyst element can be suppressed. .
[0107]
As described above, in the embodiment of the present invention, the gettering region 21 exists in the active region 16, and the gettering region 21 is provided in a portion other than the source region and the drain region. Since the gettering region 21 is separated from the pn junction located between the channel region and the source / drain regions, the problem of causing leakage of impurities that promote crystallization remains in the pn junction. can do.
[0108]
In addition, since the gettering region does not exist on the current path between the source and the drain, even if the electrical resistance of the gettering region is increased by introducing a rare gas element, the electrical resistance of the source region or the drain region is increased. There is no problem.
[0109]
Note that the catalytic element moves to the gettering region by the above heat treatment step, and thus the catalytic element in the gettering region is 1 × 10 6. ¹⁹ / Cm ^Three It becomes the above density.
[0110]
This heat treatment is desirably performed in the range of 450 to 600 ° C. for 30 minutes to 8 hours. Similar processing is possible with RTA. In this heat treatment step, the n-type impurity (phosphorus) 22 doped in the source / drain region 24 is also activated, and the sheet resistance value of the source / drain region 24 is lowered to 2 kΩ / □ or less. Is done.
[0111]
Subsequently, as shown in FIG. 1G, after a silicon oxide film or a silicon nitride film is formed as the interlayer insulating film 26, contact holes are formed. Next, TFT electrodes / wirings 27 are formed on the interlayer insulating film 26 by deposition and patterning of a metal material.
[0112]
Finally, annealing is performed at 350 ° C. for 1 hour in a hydrogen atmosphere of 1 atm to complete the TFT 28 shown in FIG. Furthermore, if necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT 28 for the purpose of protecting the TFT 28. In this manner, a semiconductor device including a thin film transistor can be obtained.
[0113]
The semiconductor device of the present embodiment is a top gate type in which the gate electrode is formed on the semiconductor layer, but the present invention is not limited to this, and the bottom gate type in which the gate electrode is located below the semiconductor layer, or It is also possible to apply to other types of transistors.
[0114]
In this embodiment, silicon is used as a semiconductor, but the present invention is not limited to this. Other types of semiconductor materials may be used. The base of the semiconductor layer is not limited to the glass substrate, and may be a plastic substrate, an insulator that is not a flat plate, or a semiconductor substrate on which an interlayer insulating film is deposited.
[0115]
Note that the “semiconductor device” in this specification does not refer only to individual TFTs but includes a wide range of devices having a structure utilizing the properties of a semiconductor, such as an active matrix substrate and a three-dimensional LSI.
[0116]
(Example 1)
A first embodiment of the present invention will be described.
[0117]
In this embodiment, a peripheral drive circuit of an active matrix type liquid crystal display device and a circuit having a CMOS structure in which an n-channel TFT and a p-channel TFT forming a general thin film integrated circuit are complementary are formed on a glass substrate. The manufacturing process will be described.
[0118]
2 and 3 are cross-sectional views showing a manufacturing process of a TFT described in this embodiment. The processes are sequentially performed in the order of FIGS. 2 (A) to 2 (E) and FIGS. 3 (A) to 3 (D). To do.
[0119]
First, reference is made to FIG. As the substrate 101, a low alkali glass substrate or a quartz substrate can be used. In this embodiment, a low alkali glass substrate is used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. In order to prevent impurity diffusion from the substrate 101, a base film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 on which the TFT is formed. In this embodiment, for example, SiH is formed by plasma CVD. _Four , NH _Three , N ₂ A silicon oxynitride film produced from a material gas of O is formed as a lower first undercoat film 102, and SiHH is similarly formed thereon by plasma CVD. _Four , N ₂ A second base film 103 was stacked using O as a material gas. At this time, the film thickness of the silicon oxynitride film of the first base film 102 is set to 25 to 200 nm (for example, 100 nm), and the film thickness of the silicon oxynitride film of the second base film 103 is set to 25 to 300 nm (for example, 100 nm). . In this embodiment, a two-layer base film is used, but for example, a single layer of a silicon oxide film may be used.
[0120]
Next, a silicon film (a-Si film) 104 having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this example, an amorphous silicon film was formed to a thickness of 50 nm by plasma CVD. Further, since the base films 102 and 103 and the amorphous silicon film 104 can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent contamination of the surface by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics of TFTs to be manufactured and variations in threshold voltage.
[0121]
Next, a small amount of catalyst element (nickel in this embodiment) 105 is added onto the surface of the a-Si film 104. The nickel 105 was added in a small amount by holding the nickel solution on the a-Si film 104, uniformly spreading the solution on the substrate 101 with a spinner, and drying. In this example, nickel acetate was used as the solute, water was used as the solvent, and the nickel concentration in the solution was 10 ppm.
[0122]
When the nickel concentration on the surface of the a-Si film 104 in the state of FIG. 2A is measured by a total reflection X-ray fluorescence analysis (TRXRF) method, 7 × 10 7 is obtained. ¹² atoms / cm ² It was about. As a method of adding the catalytic element to the a-Si film 104, a gas phase method such as a plasma doping method, a vapor deposition method, or a sputtering method can be used in addition to a method of applying a solution containing the catalytic element. . In the method using a solution, the addition amount of the catalyst element can be easily controlled, and a very small amount can be easily added.
[0123]
Next, heat treatment is performed in an inert atmosphere (for example, a nitrogen atmosphere). As the heat treatment at this time, annealing treatment is performed at 520 to 600 ° C. for 1 to 8 hours. In this example, heat treatment was performed at 580 ° C. for 1 hour. In this heat treatment, nickel 105 added to the surface of the a-Si film 104 diffuses into the a-Si film 104 and silicidation occurs, and the crystallization of the a-Si film 104 proceeds using silicide as a nucleus. . As a result, the a-Si film 104 is crystallized into a crystalline silicon film 106 as shown in FIG.
[0124]
Next, as shown in FIG. 2C, the crystalline silicon film 106 is melted and recrystallized by irradiating the laser beam 107 to improve its crystallinity. As the laser light at this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec) was used. The laser light irradiation condition is an energy density of 250 to 500 mJ / cm. ² (For example, 400 mJ / cm ² ). The beam size was formed to be a long shape of 150 mm × 1 mm on the surface of the substrate 101, and scanning was sequentially performed with a step width of 0.05 mm in a direction perpendicular to the long direction. That is, a total of 20 laser irradiations are performed at any one point of the crystalline silicon film 106. In this manner, the crystalline silicon film 106 obtained by solid-phase crystallization is reduced in crystal defects by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 108. Lasers that can be used at this time include pulse oscillation type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser, or YVO. _Four A laser can be used. The practitioner may select the crystallization conditions as appropriate.
[0125]
Thereafter, unnecessary portions of the crystalline silicon film 108 are removed, and element isolation is performed. By this step, as shown in FIG. 2D, the island-shaped crystalline silicon film 109n serving as an active region where an n-channel TFT is formed and the island-shaped serving as an active region where a p-channel TFT is formed. A crystalline silicon film 109p is formed.
[0126]
Here, for the purpose of controlling the threshold voltage of the transistor, 1 × 10 5 is applied to the entire active region of the n-channel TFT and the p-channel TFT. ¹⁶ ~ 5x10 ¹⁷ / Cm ^Three You may add boron as a p-type impurity element so that it may become a density | concentration of a grade. Boron may be added by an ion doping method, or may be added at the same time when an amorphous silicon film is deposited.
[0127]
Next, a silicon oxide film having a thickness of 20 to 150 nm (in this embodiment, a thickness of 100 nm) is formed as the gate insulating film 110 so as to cover the crystalline silicon films 109n and 109p serving as the active regions. For the formation of the silicon oxide film, TEOS (Tetra Ethoxy Ortho Silicate) was used as a raw material, and was decomposed and deposited by RF plasma CVD with oxygen. The substrate temperature at the time of deposition was 150 to 600 ° C. (preferably 300 to 450 ° C.). After the film formation, the bulk characteristics of the gate insulating film 110 and the interface characteristics between the crystalline silicon film and the gate insulating film are shown. In order to improve, annealing may be performed at 500 to 600 ° C. for 1 to 4 hours in an inert gas atmosphere. As the gate insulating film 110, another insulating film containing silicon may be used as a single layer or a stacked structure.
[0128]
Next, as shown in FIG. 2D, after depositing a refractory metal by a sputtering method, this is patterned to form gate electrodes 111n and 111p. As the refractory metal, an element selected from tantalum (Ta), tungsten (W), molybdenum (Mo) titanium (Ti), an alloy containing the element as a main component, or an alloy film combining the elements (typical) For example, the conductive layer (A) 107 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, molybdenum nitride (MoN). MoN) is used. Further, tungsten silicide, titanium silicide, or molybdenum silicide may be applied as another alternative material. In this embodiment, tungsten (W) is used and the thickness is set to 300 to 600 nm, for example, 450 nm. At this time, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance, and by setting the oxygen concentration to 30 ppm or less, a specific resistance value of 20 μΩcm or less could be realized.
[0129]
Next, a low concentration impurity (phosphorus) 112 is implanted into the active region by ion doping using the gate electrodes 111n and 111p as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹² ~ 1x10 ¹⁴ cm ^-2 For example 2 × 10 ¹³ cm ^-2 And In this process, in the island-shaped silicon films 109n and 109p, the regions not covered with the gate electrodes 111n and 111p become regions 114n and 114p into which low-concentration phosphorus 112 has been implanted, and are masked by the gate electrodes 111n and 111p. The regions where no ions are implanted later become channel regions 113n and 113p of n-channel TFTs and p-channel TFTs. This state corresponds to FIG.
[0130]
Next, as shown in FIG. 2E, a doping mask 115 made of photoresist is provided so as to cover the gate electrode 111n of the subsequent n-channel TFT, and the active region 109p of the subsequent p-channel TFT is covered. Thus, a doping mask 116 made of a photoresist is provided. Thereafter, an impurity (phosphorus) 117 is implanted into the active region by ion doping using the resist masks 115 and 116 as a mask. As doping gas, phosphine (PH _Three ), The acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 5 × 10 ¹⁵ cm ^-2 And By this step, the region 119 into which the impurity (phosphorus) 117 is implanted at a high concentration later becomes the source / drain region of the n-channel TFT. In the active region 109n, the region covered with the resist mask 115 and not doped with the high concentration phosphorus 117 remains as a region 114n into which low concentration phosphorus is implanted, thereby forming an LDD (Lightly Doped Drain) region 118. To do. By forming the LDD region 118 in this way, electric field concentration at the junction between the channel region and the source / drain region can be alleviated, leakage current at the time of TFT off operation can be reduced, and deterioration due to hot carriers can be suppressed. And the reliability of the TFT can be improved. In the active region 109p of the later p-channel TFT, since the entire surface is covered with the mask 116, the high concentration phosphorus 117 is not doped.
[0131]
Next, after removing the resist masks 115 and 116, as shown in FIG. 3A, a resist mask 120 is provided so as to cover the active region 109n of the n-channel TFT. In this state, a p-type impurity (boron) 121 is implanted into the active region 109p of the p-channel TFT by ion doping using the resist mask 120 and the gate electrode 111p of the p-channel TFT as a doping mask. At this time, diborane (B ₂ H ₆ ), The acceleration voltage is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 5 × 10 ¹⁵ cm ^-2 And By this step, the region 122 into which boron 121 is implanted at a high concentration becomes the source / drain region of the p-channel TFT, and the region where impurities are not implanted by being masked by the gate electrode 111p is the channel region 113p of the p-channel TFT. Become. In this step, since the active region 109n of the n-channel TFT is entirely covered with the mask 120, the boron 121 is not doped.
[0132]
When doping an n-type impurity and a p-type impurity, each region is selectively doped by covering a region where doping is not necessary with a photoresist. As a result, an n-type high concentration impurity region 119 and a p-type impurity region 122 are formed, and an n-channel TFT and a p-channel TFT can be formed as shown in FIG. In this embodiment, the p-type impurity element is doped after the n-type impurity element is doped, but the order of doping is not limited to this.
[0133]
Next, after removing the resist mask 120, as shown in FIG. 3B, a resist mask 122 is formed so as to cover the gate electrode 111n of the n-channel TFT and the gate electrode 111p of the p-channel TFT. The resist mask 122 does not cover and expose a part (outer edge portion) of the active region 109n of the n-channel TFT and the active region 109p of the p-channel TFT.
[0134]
In this state, as shown in FIG. 3B, a rare gas element (Ar in this embodiment) 123 is ion-doped on the entire surface of the substrate from above. By this step, a rare gas element 123 is implanted into the exposed region of the TFT active region, and a gettering region 124 is formed at the outer edge portion of the active region 109n of the n-channel TFT and the active region 109p of the p-channel TFT. The
[0135]
As the rare gas element to be doped, any one or plural kinds of rare gas elements selected from the group consisting of Ar, Kr, and Xe can be used. A region covered with the resist mask 19 in the active region is not doped with a rare gas element.
[0136]
In this embodiment, 100% Ar is used as the doping gas, the acceleration voltage is set to 60 to 90 kV, for example, 80 kV, and the dose amount is 1 × 10. ¹⁵ ~ 1x10 ¹⁶ cm ^-2 For example 3 × 10 ¹⁵ cm ^-2 The conditions were adopted. According to this condition, the concentration of the rare gas element in the gettering region 124 is 1 × 10 ¹⁹ ~ 3x10 ^{twenty one} atoms / cm ^Three It becomes.
[0137]
In this embodiment, the layout is designed so that the ratio (W / S) of the area S of the gettering region 124 to the channel width W of the TFT is about 1. Usually, an n-channel TFT and a p-channel TFT have different current driving capabilities. In the case of this embodiment, the current driving capability of the n-channel TFT is twice or more larger than that of the p-channel TFT. Therefore, in order to pass the same current between the n-channel TFT and the p-channel TFT, it is necessary to set the channel width of the p-channel TFT to be large. For example, if the channel region width W in the active region 109n of the n-channel TFT is 20 μm, the channel width W in the active region 109p of the p-channel TFT is set to 40 μm. In this case, the area of the gettering region 124 in each active region is set so that the p-channel TFT is approximately twice as large as the n-channel TFT. By doing so, the gettering efficiency can be made equal in the active regions of the n-channel TFT and the p-channel TFT.
[0138]
Next, after removing the resist mask 122, heat treatment is performed in an inert atmosphere (for example, a nitrogen atmosphere). In this embodiment, a heat treatment step is performed in a nitrogen atmosphere at 500 to 600 ° C. for 30 minutes to 8 hours, more preferably at a temperature of 530 to 580 ° C. for 30 minutes to 2 hours. By this heat treatment step, gettering proceeds as shown in FIG. That is, in the active region 109n of the n-channel TFT, argon 123 that is doped at a high concentration in the gettering region 124 formed outside the source / drain region becomes the channel region 113n, the LDD region 118, and the source / drain region. Nickel present in the region 119 is moved in the direction indicated by the arrow 125 from the channel region to the LDD region, further to the source / drain region, and finally to the gettering region 124. Further, in the active region 109p of the p-channel TFT, argon 123 that is highly doped in the gettering region 124 formed outside the source / drain region is present in the channel region 113p and the source / drain region 122. Similarly, the nickel being moved is moved from the channel region to the source / drain region and the gettering region 124 in the direction indicated by the arrow 125.
[0139]
Since nickel moves to the gettering region 124 by the above heat treatment process, the nickel concentration in the gettering region 124 is 1 × 10 5. ¹⁹ / Cm ^Three It rises with the above.
[0140]
In this manner, in this embodiment, the remaining catalyst element can be gettered in the channel forming region of the TFT active region, the junction between the channel formation region and the source / drain region, or the junction with the LDD region. In addition, generation of leakage current due to segregation of catalyst elements can be suppressed.
[0141]
According to the above heat treatment process, the n-type impurity (phosphorus) 117 doped in the source / drain region 119 and the LDD region 118 of the n-channel TFT and the p-type doped in the source / drain region 122 of the p-channel TFT. The activation of the type impurity (phosphorus) 121 is also performed at the same time. As a result, the sheet resistance value of the source / drain region 119 of the n-channel TFT is about 400 to 700 Ω / □, and the sheet resistance value of the LDD region 118 is 30 to 60 kΩ / □. The sheet resistance value of the source / drain region 122 of the p-channel TFT is about 1 to 1.5 kΩ / □.
[0142]
In this embodiment, in the active region of the n-channel TFT and the p-channel TFT, a gettering region is formed in a region different from the source region or the drain region. Therefore, a part of the TFT active region is introduced by introducing a rare gas element. Even if the electrical resistance is gradually referred to, the transistor characteristics are not affected.
[0143]
The above heat treatment step may be performed using RTA (Rapid Thermal Annealing).
[0144]
Next, as shown in FIG. 3D, an inorganic interlayer insulating film that covers the n-channel TFT and the p-channel TFT is formed. As the interlayer insulating film, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is preferably formed with a thickness of 400 to 1500 nm (typically 600 to 1000 nm). In this example, a 200-nm-thick silicon nitride film 126 and a 700-nm-thick silicon oxide film 127 are stacked to form a two-layer structure. These films were formed using a plasma CVD method. The deposition of silicon nitride film is SiH _Four And NH _Three The silicon oxide film is deposited using TEOS and O. ₂ As a raw material. These two layers were formed continuously.
[0145]
The inorganic interlayer insulating film is not limited to the above example, and other insulating films containing silicon and other films may be deposited as a single layer or stacked layers.
[0146]
Next, heat treatment is performed at 300 to 500 ° C. for 1 to 12 hours to hydrogenate the semiconductor layer. This step is performed to supply hydrogen atoms to the active region / gate insulating film interface to terminate and inactivate dangling bonds that degrade the TFT characteristics. In this example, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. If the amount of hydrogen contained in the interlayer insulating film (particularly the silicon nitride film 126) is sufficient, the effect can be obtained even if heat treatment is performed in a nitrogen atmosphere. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0147]
After a contact hole is formed in the interlayer insulating film, a TFT electrode / wiring 128 is formed from a metal material (for example, a double layer film of titanium nitride and aluminum). The titanium nitride film is provided as a barrier film for the purpose of preventing aluminum from diffusing into the semiconductor layer. Finally, annealing is performed at 350 ° C. for 1 hour to complete the n-channel TFT 201 and the p-channel TFT 202 shown in FIG. Further, if necessary, contact holes are provided also on the gate electrodes 111n and 111p, and necessary electrodes are connected by the wiring 128. For the purpose of protecting the TFT, a protective film made of a silicon nitride film or the like may be provided on each TFT.
[0148]
The field effect mobility of each TFT manufactured according to the above example is 250 to 300 cm for an n-channel TFT. ² / Vs, 120-150cm for p-channel TFT ² / Vs is high, and the threshold voltage is about 1V for the N-type TFT and about -1.5V for the P-type TFT, and exhibits very good characteristics. In addition, there was no abnormal increase in leakage current frequently observed in the TFT off operation, which was frequently observed in the conventional example, and even when repeated measurements and durability tests due to bias and temperature stress were performed, there was almost no deterioration in characteristics. In addition, when a circuit such as an inverter chain or a ring oscillator is formed with a CMOS structure circuit in which the n-channel TFT and the p-channel TFT manufactured in this embodiment are complementarily configured, it is much more difficult than the conventional one. High reliability and stable circuit characteristics.
[0149]
(Example 2)
In this embodiment, a process of manufacturing an active matrix substrate with a built-in driver for liquid crystal display using the n-channel TFT 201 and the p-channel TFT 202 manufactured in Embodiment 1 will be described below.
[0150]
Please refer to FIG.
[0151]
First, an n-channel TFT 201 and a p-channel TFT 202 that form the driver circuit 205 are manufactured using the method described in Embodiment 1. At this time, the pixel TFT 203 and the storage capacitor 204 are simultaneously formed in the pixel portion 206 on the same substrate. In the present specification, a substrate having the configuration shown in FIG. 4 is referred to as an “active matrix substrate”.
[0152]
The n-channel TFT 201 of the drive circuit 205 has a channel formation region 113n, a source / drain region 119, an LDD region 118, and a gettering region 124 in the active region 109n. The n-channel TFT 201 further includes a gate insulating film 110 formed on the active region 109 n and a gate electrode 111 n formed on the gate insulating film 110, and is connected to the source / drain region 119. The wiring 128 is connected to another TFT.
[0153]
The p-channel TFT 202 of the driver circuit has a channel formation region 113p, a source / drain region 122, and a gettering region 124 in the active region 109p. The p-channel TFT 202 further includes a gate insulating film 110 formed on the active region 109 p and a gate electrode 111 p formed on the gate insulating film 110, and is connected to the source / drain region 122. The wiring 128 is connected to another TFT.
[0154]
In FIG. 4, only two TFTs are shown as TFTs constituting the drive circuit 205, but in reality, many other TFTs constituting the drive circuit 205 are formed on the same substrate.
[0155]
The pixel TFT 203 of the pixel portion 206 is manufactured in exactly the same process as the process of manufacturing the n-channel TFT 201 of the driver circuit 205. The pixel TFT 203 includes a channel formation region 113g, a source / drain region 119, an LDD region 118, and a gettering region 124 in an active region 109g. A double gate structure in which two gate electrodes 111g are arranged in series is formed on the gate insulating film 110. This double gate structure has a function of suppressing a leakage current during an off operation. In order to further suppress this leakage current, it is desirable that the length of the LDD region is also optimized and formed to be longer than the LDD region of the n-channel TFT 201 in the driver circuit portion. Since the position of the LDD region 118 is defined by the resist mask, the length of the LDD region can be designed to an arbitrary value for an arbitrary TFT by adjusting the layout of the resist mask.
[0156]
The pixel TFT 204 of this embodiment has a double gate structure as described above, but the pixel TFT 204 may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes. You may have.
[0157]
The storage capacitor portion 204 is formed of a semiconductor layer 109c having a region 119 in which an n-type impurity element is partially added, with an insulating film generated from the same material as the gate insulating film 110 serving as a capacitor. Is formed of an electrode 111c made of the same material as the gate electrode 111. These electrodes are all formed simultaneously with the manufacturing process of the n-channel TFT.
[0158]
A pixel electrode 129 is formed on the interlayer insulating film having a two-layer structure of the silicon nitride film 126 and the silicon oxide film 127 by forming a transparent conductive film with a thickness of 80 to 120 nm and patterning the transparent conductive film. For transparent conductive films, in addition to commonly used ITO, indium zinc oxide alloy (In ₂ O _Three -ZnO) and zinc oxide (ZnO) are also suitable materials, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added can also be applied to increase visible light transmittance and conductivity. .
[0159]
In the pixel portion 206, electrodes / wirings 130 and 131 that are electrically connected to the source / drain regions 119 are formed. The electrode 131 is connected to the pixel electrode 129, and the electrode 130 is connected to the source bus line. A video signal is supplied to the electrode 130 via the source bus line, and necessary charges are written to the pixel electrode 129 based on the gate signal of the gate bus line 111g.
[0160]
In the storage capacitor portion 204, the pixel electrode 129 is electrically connected to the n-type impurity addition region 119 of the semiconductor layer 109 c functioning as one electrode forming the storage capacitor by the wiring 132. Note that these electrodes are formed of the same material at the same time in the process of forming the wiring 128 of the n-channel TFT 201 and the p-channel TFT 202 in the driver circuit portion.
[0161]
Note that although a transparent conductive film is used as the pixel electrode 129 in this embodiment, a reflective display device can be manufactured by forming a pixel electrode using a reflective conductive material. it can. In that case, the pixel electrode can be formed at the same time in the step of manufacturing the electrode, and the material of the pixel electrode should be a highly reflective material such as a film containing Al or Ag as a main component or a laminated film thereof. Is desirable.
[0162]
FIG. 5 shows a top view of the active matrix substrate manufactured through the above steps. The AA ′ line in FIG. 5 corresponds to the AA ′ line in FIG. 4 and crosses the active region 109g, the gate electrode 111g, and the wiring 130 of the pixel TFT. Similarly, the BB ′ line in FIG. 5 corresponds to the BB ′ line in FIG. 4 and crosses the semiconductor layer 109c, the pixel electrode 129, and the wiring 131.
[0163]
As described above, in this embodiment, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. Further, by forming the gate electrode from a conductive material having heat resistance, the gettering efficiency of the catalytic element can be increased and the process can be simplified, and the activation of the LDD region, the source region, and the drain region can be easily performed. In addition, the wiring resistance can be sufficiently reduced by forming the wiring with a low resistance material. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 10 inch class or more.
[0164]
(Example 3)
In this embodiment, an active matrix liquid crystal display device (also referred to as a liquid crystal display panel) is manufactured from the active matrix substrate of Embodiment 2.
[0165]
Please refer to FIG.
[0166]
First, an active matrix substrate shown in FIG. 4 is prepared. By patterning an organic resin film such as an acrylic resin film on the active matrix substrate, columnar spacers 181 for maintaining a distance between the counter substrate and the active matrix substrate to be provided later are formed at predetermined positions. Instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate. Thereafter, an alignment film 180 is formed, and the alignment film 180 is rubbed.
[0167]
Next, a counter substrate 182 is prepared. Color layers 183 and 184 and a planarization film 185 are formed on the counter substrate 182. The red colored layer 183 and the blue colored layer 184 are partially overlapped to form the second light shielding portion. Although not shown in FIG. 6, the first light-shielding portion is formed by partially overlapping the red colored layer and the green colored layer. After the counter electrode 186 is formed in the pixel portion, an alignment film 187 is formed on the entire surface of the counter substrate, and a rubbing process is performed.
[0168]
Next, the active matrix substrate on which the pixel portion 206 and the driving circuit 205 are formed is bonded to a counter substrate with a sealant 188. A filler is mixed in the sealing material 188, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 189 is injected between both the substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 189.
[0169]
Thus, the active matrix type liquid crystal display device shown in FIG. 6 is completed. If necessary, the active matrix substrate or the counter substrate is divided into a predetermined shape. Further, after appropriately providing a polarizing plate or the like using a known technique, an FPC (Flexible Printed Circuit) is attached.
[0170]
Next, the configuration of the liquid crystal display panel manufactured by the above method will be described with reference to FIG. In FIG. 7, the same reference numerals are used for portions corresponding to those in FIG.
[0171]
FIG. 7A illustrates an upper surface of the liquid crystal display panel in a state where an active matrix substrate and a counter substrate 182 provided with a color filter or the like are bonded to each other with a sealant 188 interposed therebetween. FIG. 7A illustrates a pixel portion 206, driving circuits 205a and 205b, an external input terminal 210 to which an FPC is attached, a connection wiring 211 for connecting the external input terminal to the input portion of each circuit, and the like.
[0172]
FIG. 7B shows a cross section taken along line ee ′ of the external input terminal 210 shown in FIG. An FPC formed of a base film 213 and a wiring 214 is bonded to the external input terminal 210 by an anisotropic conductive resin 215, and mechanical strength is further enhanced by a reinforcing plate. The wiring 217 is formed by patterning a conductive film deposited to form the pixel electrode 140. Since the outer diameter of the conductive particles 216 is smaller than the pitch of the wirings 217, if the amount dispersed in the adhesive 215 is appropriate, the conductive particles 216 are electrically connected to the corresponding wiring on the FPC side without short-circuiting with the adjacent wirings. A connection can be formed.
[0173]
The liquid crystal display panel of this embodiment can be used as a display portion of various electronic devices. When the lighting evaluation of the liquid crystal display device of this example was actually performed, the display unevenness was clearly smaller than that of the conventional liquid crystal display device, the pixel defect due to TFT leakage was extremely small, and a high display quality liquid crystal panel with a high contrast ratio was obtained. Obtained.
[0174]
Example 4
The semiconductor device of this example will be described with reference to FIG. FIG. 8 shows an analog driving circuit configuration of a semiconductor device including a source side driving circuit 90, a pixel portion 91, and a gate side driving circuit 92. In this specification, the “drive circuit” is a general term for circuits including a source side processing circuit and a gate side drive circuit.
[0175]
The source side driving circuit 90 of this embodiment includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate side driving circuit 92 includes a shift register 92a, a level shifter 92b, and a buffer 92c. If necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.
[0176]
The pixel portion 91 is composed of a plurality of pixels arranged in a matrix composed of rows and columns, and each pixel includes the TFT element configured as described above. Although not shown, a gate side driver circuit may be further provided on the opposite side of the gate side driver circuit 92 with the pixel portion 91 interposed therebetween.
[0177]
When digital driving is performed instead of analog driving, a latch (A) 93b and a latch (B) 93c may be provided instead of the sampling circuit, as shown in FIG. The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, a D / A converter 93d, and a buffer 93e. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.
[0178]
Each of the above configurations can be manufactured according to the manufacturing method described for the first and second embodiments. 8 and 9 show only the arrangement of the pixel portion and the driver circuit, a memory or a microprocessor may be formed on the substrate of the display panel. The TFTs constituting the memory and the microprocessor can also be manufactured using a process for manufacturing a TFT of a driver circuit or a pixel portion.
[0179]
(Example 5)
The present embodiment will be described with reference to FIG.
[0180]
In this example, crystallization is performed by a method different from the crystallization method of Example 1. FIG. 10 is a cross-sectional view showing a manufacturing process in this example, and the manufacturing process proceeds sequentially according to (A) to (D).
[0181]
First, a base insulating film 51 formed of a silicon nitride oxide film having a thickness of 300 nm and an amorphous silicon film 52 having a thickness of 50 nm are deposited in this order on the glass substrate 50. In this deposition step, it is preferable that the base insulating film and the amorphous semiconductor film are continuously formed in the same thin film deposition apparatus without exposing them to the atmosphere.
[0182]
Next, a mask insulating film 53 formed of a silicon oxide film is formed to a thickness of 200 nm. As shown in FIG. 10A, the mask insulating film has an opening for adding a catalytic element to the semiconductor film.
[0183]
As shown in FIG. 10B, a catalytic element layer 54 is formed by applying an aqueous solution (nickel acetate aqueous solution) containing a catalytic element (nickel in this embodiment) of 10 ppm in terms of weight by a spin coating method. At this time, the catalytic element layer 54 selectively contacts the amorphous silicon film 52 at the opening of the mask insulating film 53 to form the catalytic element addition region 55. The catalyst elements that can be used here are iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum. One or more elements selected from (Pt), copper (Cu), and gold (Au).
[0184]
In this embodiment, nickel is added by spin coating, but a thin film (for example, nickel film) formed from a catalytic element may be formed on the amorphous silicon film 52 by vapor deposition or sputtering. .
[0185]
Next, heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 16 hours (preferably 8 to 14 hours). In this embodiment, heat treatment is performed at 570 ° C. for 14 hours. As a result, as shown in FIG. 10C, crystal nuclei are generated in the catalytic element addition region 55, and crystallization proceeds in a direction substantially parallel to the substrate (in the direction indicated by the arrow) starting from the crystal nuclei. Thus, the crystalline silicon film 57 in which the crystal growth directions are aligned macroscopically is formed. At this time, the nickel 54 existing on the mask 53 is blocked by the mask film 53 and does not reach the underlying a-Si film, and the a-Si film 52 is crystallized only by the nickel introduced in the region 55. Done. The obtained crystalline silicon film may be improved in crystallinity by irradiation with laser light as shown in FIG.
[0186]
The crystallization method of this embodiment can be applied to all the crystallization steps described above. According to this crystallization method, it is possible to form a high-performance TFT that requires further current driving capability.
[0187]
(Example 6)
An arrangement example of gettering regions in the semiconductor layer will be described with reference to FIGS. 11 and 12. The arrangement example of this embodiment can be applied to the n-channel TFT and / or the p-channel TFT in each of the embodiments described above. Note that in the case where both an n-channel TFT and a p-channel TFT are formed on the same substrate, the area of the gettering region in the active region of the n-channel TFT is set to be equal to that of the gettering region in the active region of the p-channel TFT. It is preferable that the distance is approximately equal to the area and the distance from the gettering region to the channel region is approximately equal. By doing so, the gettering efficiency of the catalytic element can be made uniform between the n-channel TFT and the p-channel TFT.
[0188]
Here, the meaning that the areas of the gettering region in the active region of the n-channel TFT and the gettering region in the active region of the p-channel TFT are approximately equal means that in each TFT, the active region (channel region) The width S of the active region (channel region) and the ratio S / W of the area S of the gettering region are approximately equal in the n-channel TFT and the p-channel TFT. That is.
[0189]
Hereinafter, an example of the shape of the gettering region formed in the active region of this embodiment will be described.
[0190]
FIG. 11A shows a position where gettering regions 1203a and 1204a containing a rare gas element at a high concentration are separated from a channel formation region formed in an active region under the gate electrode 1205a (outer edge portion of the active region). In addition, an example is shown in which a rectangular shape having a long side in the direction parallel to the gate electrode 1205a is arranged so that the corner portion of the rectangle extends over the corner portion of the active region.
[0191]
FIG. 11B illustrates a case where the gettering regions 1203b and 1204b extend in a direction perpendicular to the gate electrode 1205b at a position away from the channel formation region formed in the active region below the gate electrode 1205b (outer edge portion of the semi-active region). In this example, the sides are rectangular, and the corners of the rectangles are placed on the corners of the active region.
[0192]
FIG. 11C illustrates that the gettering regions 1203c and 1204c are separated from the channel formation region formed in the active region below the gate electrode 1205c (the outer edge portion of the active region), and the long side is parallel to the gate electrode 1205c. In this example, a rectangular shape is combined with a rectangular shape having a long side in the vertical direction, and the corner portion of the shape is arranged so as to hang over the corner portion of the active region. In the case of such an arrangement, the area of the gettering region can be increased as compared with the arrangement example shown in FIG. 11A or FIG. 11B, and the gettering efficiency for the catalytic element can be further increased. .
[0193]
In any of the above arrangement examples, the gettering region is a contact portion formed in the source region or the drain region (the portion where the wiring electrically connecting each TFT is connected to the active region is referred to in this specification). , Which is referred to as a contact portion). That is, the gettering regions 1203a and 1204a in FIG. 11A are arranged at positions that do not hinder current flowing between the contact portion 1206a formed in the source region 1201a and the contact portion 1207a formed in the drain region 1202a. Has been.
[0194]
The gettering regions 1203b and 1204b in FIG. 11B are arranged at positions that do not hinder current flowing between the contact portion 1206b connected to the source region 1201b and the contact portion 1207b formed in the drain region 1202b. Yes.
[0195]
The gettering regions 1203c and 1204c in FIG. 11C are arranged at positions that do not hinder current flowing between the contact portion 1206c formed in the source region 1201c and the contact portion 1207c formed in the drain region 1202c. Yes.
[0196]
In FIG. 11D, the area of the gettering regions 1203d and 1204d is further expanded in order to increase the gettering efficiency of the gettering regions 1203d and 1204d, compared to the arrangement example of FIG. Shows an arrangement example in which a part of the contact portion 1206d overlaps. There is no significant problem even if the gettering regions 1203d and 1204d overlap with a part of the contact portions 1206d and 1207d, but an increase in the area of the overlap portion is not preferable because an increase in contact resistance cannot be ignored. For this reason, it is preferable that the area of the overlap portion is at most half of the area of the contact portions 1206d and 1207d. Note that the design distance between the contact portions 1206d and 1207d and the gettering regions 1203d and 1204d needs to be set in consideration of the alignment accuracy of the exposure apparatus used in the photolithography process corresponding to each region formation.
[0197]
The position of the gettering region 1204C is not limited to the position shown in FIGS. 11A to 11D as long as the current between the source region and the drain region is not inhibited during the on-operation of the TFT, and can be arbitrarily set. .
[0198]
Reference is now made to FIGS.
[0199]
In FIG. 12A, a plurality of gate electrodes 1205e cross the active region, and a plurality of channel formation regions are formed below the active region. A source region 1201e (or drain region 1202e), a gettering region 1208e, and a contact portion 1209e are formed between the plurality of gate electrodes. 11A to 11D, gettering regions 1203e and 1204e are formed in the outer edge portion of the active region, and source regions 1201e or drain regions 1202e and contact portions 1206e and 1207e are formed inside the gettering regions 1203e and 1204e. ing. In the arrangement example shown in FIG. 12A, the gettering region 1203e may overlap with part of the contact portion 1206e. However, it is necessary to pay attention so that the area of the overlap portion is at most half of the contact portions 1206e and 1207e.
[0200]
FIG. 12B also illustrates an arrangement example in which a plurality of gate electrodes 1205f crosses the active region and a plurality of channel formation regions are formed therebelow. In one example of FIG. 12B, three TFTs share an active region, and source / drain regions are connected in series. This arrangement example is used when a contact portion is not formed in each connecting portion and it is not necessary to take out an electrical signal from the connecting portion. The TFT having such a configuration is actually used in a circuit such as a clocked inverter or a latch circuit. A source region 1201f (or drain region 1202f) and a gettering region 1208f are formed between the plurality of gate electrodes.
[0201]
11A to 11D, gettering regions 1203f and 1204f are formed in the outer edge portion of the active region, and source regions 1201f or drain regions 1202f and contact portions 1206f and 1207f are formed inside the gettering regions 1203f and 1204f. Has been. In the connection portion region, the gettering region 1208f is arranged at a position that does not at least prevent the current flowing from the contact portion 1206f to the contact portion 1207f.
[0202]
The shape and size of the active region of the TFT are appropriately designed according to the amount of current required for the TFT. 11 (A) to 11 (D) and FIG. 12 (A) show an active region having a wedge shape in which the width of the channel region is narrower than that of the source / drain regions, and FIG. An active region having a shape in which the widths of the source / drain regions and the channel region are the same is shown. The shape of the active region is arbitrary.
[0203]
Due to the heat treatment for gettering, the catalytic element moves to the gettering region. ¹⁹ / Cm ^Three It becomes the above density.
[0204]
(Example 7)
As described above, the semiconductor device according to the present invention is suitably used for an active matrix display device. In other words, the present invention can be applied to all electronic devices including a display device that operates in active matrix driving in a display portion. Electronic devices to which the present invention can be applied include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ) And the like.
[0205]
Hereinafter, an example of an electronic apparatus including the semiconductor device of the present invention will be described with reference to FIGS. 13, 14, and 15.
[0206]
First, referring to FIG. A personal computer illustrated in FIG. 13A includes a main body 2001, an image input portion 2002, a display portion 2003, and a keyboard 2004.
[0207]
An electronic device illustrated in FIG. 13B is a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106.
[0208]
An electronic device illustrated in FIG. 13C is a mobile computer, and includes a main body 2201, a camera portion 2202, an image receiving portion 2203, an operation switch 2204, and a display portion 2205.
[0209]
An electronic device illustrated in FIG. 13D is a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 2303.
[0210]
An electronic device illustrated in FIG. 13E is a player and a player that uses a recording medium (hereinafter, referred to as a recording medium) in which data or a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, and a recording medium. 2404 and an operation switch 2405 are provided. This player reproduces a DVD or CD as a recording medium, and enables music indoors and outdoors, movie appreciation, games, and the Internet.
[0211]
An electronic device illustrated in FIG. 13F is a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, and an image receiving portion (not illustrated).
[0212]
By applying the semiconductor device according to the present invention to the drive unit of the electronic device, a crystalline silicon film having good crystallinity using a catalytic element can be formed, and the catalytic element can be sufficiently gettered. The characteristics of the n-channel TFT and the p-channel TFT can be improved, and a high-reliability, stable circuit characteristic and good CMOS driving circuit can be realized. In addition, even in a switching TFT in a pixel in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch portion, etc., the generation of a leakage current considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, it is possible to realize the electronic device as described above that can perform good display without display unevenness.
[0213]
An electronic device illustrated in FIG. 14A is a front projector, and includes a projection device 2601 and a screen 2602.
[0214]
An electronic device illustrated in FIG. 14B is a rear projector, and includes a main body 2701, a projection device 2702, a mirror 2703, and a screen 2704.
[0215]
FIG. 14C shows an example of the internal structure of the projection devices 2601 and 2702 shown in FIGS. 14A and 14B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0216]
FIG. 14D illustrates an example of an internal structure of the light source optical system 2801 illustrated in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 14D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0217]
Although the projector shown in FIG. 14 is configured using a transmissive liquid crystal display device, a reflective liquid crystal display device or other display devices may be used.
[0218]
By applying the present invention to the above electronic device, a crystalline silicon film having good crystallinity using a catalytic element can be formed, and the catalytic element can be sufficiently gettered. The TFT of the sampling circuit of the analog switch unit can suppress the occurrence of a leak current considered to be due to segregation of the catalytic element, and can realize a projector capable of good display without display unevenness. Further, since there is no display unevenness, it becomes easy to control the light source, and low power consumption can be realized.
[0219]
An electronic device illustrated in FIG. 15A is a mobile phone, and includes a display panel 3001 manufactured using the semiconductor device according to the present invention and an operation panel 3002 having various operation keys. The display panel 3001 and the operation panel 3002 are connected by a connection unit 3003. An angle θ between the surface of the connection portion 3003 on which the display portion 3004 of the display panel 3001 is provided and the surface on which the operation key 3006 of the operation panel 3002 is provided is approximately 0 ° to 180 ° depending on the connection portion 3003. It can be arbitrarily changed within the range.
[0220]
This mobile phone has an audio output unit 3005, operation keys 3006, a power switch 3007, and an audio input unit 3008.
[0221]
An electronic device illustrated in FIG. 15B is a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, an operation switch 3105, and an antenna 3106.
[0222]
An electronic device illustrated in FIG. 15C is a display (display device), and includes a main body 3201, a support base 3202, and a display portion 3203.
[0223]
By applying the present invention to the above electronic device, a crystalline silicon film having good crystallinity using a catalytic element can be formed, and the catalytic element can be sufficiently gettered. The characteristics of the TFT and the p-channel TFT can be improved, and a CMOS drive circuit with high reliability and stable circuit characteristics can be realized. In addition, even in a switching TFT in a pixel in which a leakage current during an off operation is a problem, a TFT in a sampling circuit of an analog switch portion, etc., the generation of a leakage current considered to be due to segregation of a catalytic element can be sufficiently suppressed. As a result, a good display without display unevenness is possible. In addition, because it is a good display with no display unevenness, it is not necessary to use a light source more than necessary, and it is possible to reduce wasteful power consumption and to reduce power consumption (cell phones, portable books, displays) ) Can be realized.
[0224]
As described above, the application range of the present invention is extremely wide and can be applied to all electronic devices.
[0225]
【The invention's effect】
According to the present invention, a catalytic element in an element region of a crystalline semiconductor film having a good crystallinity manufactured using a catalytic element, particularly, a channel forming region or a channel forming region and a junction between the channel forming region and the source / drain region. It is possible to sufficiently reduce the concentration of the catalytic element.
[0226]
In addition, since the gettering efficiency of the catalytic element can be made uniform between the n-channel TFT and the p-channel TFT, sufficient gettering can be performed for each of the n-channel TFT and the p-channel TFT, which is favorable. A crystalline semiconductor film can be obtained. If a TFT using such a semiconductor film is used, the generation of leakage current can be suppressed, the reliability can be improved, and a high-performance semiconductor element having stable characteristics with little characteristic variation can be obtained. realizable.
[0227]
According to the present invention, the number of additional steps for gettering can be reduced, and the manufacturing process can be simplified. As a result, the yield rate can be greatly improved and the manufacturing cost of the semiconductor device can be reduced.
[0228]
According to the present invention, a semiconductor device in which TFTs having excellent performance are integrated at a high density can be provided by a simple manufacturing process.
[0229]
In particular, when the present invention is applied to a liquid crystal display device, the improvement of the switching characteristics of the pixel switching TFT required for the active matrix substrate and the high performance and high integration required for the TFT constituting the peripheral drive circuit section are simultaneously achieved. Satisfactory, in a driver monolithic active matrix substrate in which the active matrix portion and the peripheral drive circuit portion are formed on the same substrate, the module can be made compact, high performance, and low cost.
[Brief description of the drawings]
FIGS. 1A to 1G are process cross-sectional views illustrating an embodiment of the present invention.
FIGS. 2A to 2E are process cross-sectional views illustrating an embodiment of the present invention. FIGS.
FIGS. 3A to 3D are process cross-sectional views illustrating an embodiment of the present invention. FIGS.
FIG. 4 is a cross-sectional view showing an embodiment of the present invention.
FIG. 5 is a plan view showing an embodiment of the present invention.
FIG. 6 is a cross-sectional view showing an embodiment of the present invention.
7A is a top view showing an embodiment of the present invention, and FIG. 7B is a cross-sectional view thereof.
FIG. 8 is a plan view showing an embodiment of the present invention.
FIG. 9 is a plan view showing an embodiment of the present invention.
FIGS. 10A to 10D are process cross-sectional views illustrating an example of the present invention. FIGS.
11A to 11D are plan views showing an embodiment of the present invention.
FIGS. 12A and 12B are plan views showing an embodiment of the present invention. FIGS.
FIGS. 13A to 13F are diagrams showing examples of electronic devices to which the present invention is applied. FIGS.
FIGS. 14A to 14D are diagrams illustrating an example of an electronic apparatus to which the present invention is applied.
FIGS. 15A to 15C are diagrams showing examples of electronic devices to which the present invention is applied. FIGS.
[Explanation of symbols]
11 Glass substrate
12 Underlying insulating film made of silicon nitride film
13 Intrinsic (type I) amorphous silicon film (a-Si film)
13a Crystalline silicon film
13b Crystalline silicon film
14 Nickel
15 Laser light
16 Island-like crystalline silicon film
17 Gate insulation film
18 Gate electrode
19 Mask
20 Noble gas elements
21 Gettering area

Claims (14)

Preparing an amorphous silicon film to which a catalytic element for promoting crystallization is added at least in part;
Wherein by performing the first heat treatment with respect to the amorphous silicon film, wherein at least a portion of the amorphous silicon film is crystallized, to thereby obtain a semiconductor film containing a crystalline region,
Forming a plurality of island-like semiconductor layers each having a crystalline region by patterning the semiconductor film;
A step of selectively adding a rare gas element to a part of the island-shaped semiconductor layer other than a region to be a channel region, a source region, and a drain region to form a gettering region;
By performing the second heat treatment, a step of moving at least a part of the previous SL catalyst element of the island-like semiconductor layers in the gettering region,
It encompasses,
The catalytic element is nickel;
A method for manufacturing a semiconductor device, wherein the gettering region is formed at a position adjacent to a region that becomes a source region or a drain region of a thin film transistor in the island-shaped semiconductor layer and not adjacent to a region that becomes a channel region . Before performing the second heat treatment, the method further includes a step of doping an n-type impurity and / or a p-type impurity into the source region, the drain region, and the gettering region of the island-shaped semiconductor layer. The manufacturing method according to claim 1 . Forming a gate insulating film on the island-like semiconductor layer;
Forming a gate electrode on the gate insulating film;
Doping an n-type impurity and / or a p-type impurity into a region of the island-shaped semiconductor layer that is not covered with the gate electrode;
The process according to claim 1 including. The step of preparing the amorphous silicon film includes
Forming a mask having an opening on the amorphous silicon film;
The process according to the step of adding the catalyst element to a selected region of the amorphous silicon film through the opening in any of including claims 1 to 3. The gettering region, the production method according to claims 1, electrons or holes Ru is formed in a region other than the region to be moved to one of the 4. The gettering region is any one of claims 1 to 5, which is formed on the outer edge near the position of the island-shaped semiconductor layer of the center of the contact region for electrically connecting the line and the island-shaped semiconductor layer The manufacturing method as described in. The manufacturing method according to claim 6 , wherein the gettering region partially overlaps the contact region. The process according to any one of claims 1 to 7 to adjust the concentration of the rare gas element in the gettering region in the range of ^{1 × 10 19 ~3 × 10 21} atoms / cm 3. The manufacturing method according to claim 1, wherein the rare gas element is at least one element selected from the group consisting of Ar, Kr, and Xe. The manufacturing method according to claim 1, further comprising a step of irradiating the semiconductor film with laser light after the first heat treatment. The manufacturing method according to claim 2 , wherein the impurity doped in the island-shaped semiconductor layer is activated by the second heat treatment. The plurality of island-shaped semiconductor layers include an island-shaped semiconductor layer for an n-channel thin film transistor and an island-shaped semiconductor layer for a p-channel thin film transistor,
  The ratio S / W of the area S of the gettering region to the width W of the island-shaped semiconductor layer in the island-shaped semiconductor layer for the n-channel thin film transistor is the island-shaped semiconductor layer in the island-shaped semiconductor layer for the p-channel thin film transistor. The area S of the gettering region with respect to the width W of The manufacturing method according to any one of claims 1 to 11, which is substantially equal to the ratio S / W. The plurality of island-shaped semiconductor layers include an island-shaped semiconductor layer for an n-channel thin film transistor and an island-shaped semiconductor layer for a p-channel thin film transistor,
  The distance L from the junction between the region that becomes the source region or the drain region and the region that becomes the channel region in the island-like semiconductor layer for the n-channel type thin film transistor to the gettering region is an island shape for the p-channel type thin film transistor. 13. The manufacturing method according to claim 1, wherein a distance L from a junction between a region to be the source region or the drain region and a region to be the channel region in the semiconductor layer to the gettering region is approximately equal. The manufacturing method according to claim 3, wherein the gate electrode is made of at least one material selected from the group consisting of W, Ta, Ti, and Mo.

Images