JP4288912B2

JP4288912B2 - Wiring board, semiconductor package substrate, semiconductor package, and manufacturing method thereof

Info

Publication number: JP4288912B2
Application number: JP2002231310A
Authority: JP
Inventors: 修嶋田; 俊昌名越; 和久鈴木; 満男菊地
Original assignee: Hitachi Chemical Co Ltd; Showa Denko Materials Co Ltd; Resonac Corp
Current assignee: Resonac Corp
Priority date: 2002-08-08
Filing date: 2002-08-08
Publication date: 2009-07-01
Anticipated expiration: 2022-08-08
Also published as: JP2004071946A

Description

【０００１】
【発明の属する技術分野】
本発明は、配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法に関するものである。
【０００２】
【従来の技術】
電子機器の小型化や高性能化への要求に伴い、半導体の集積度は年々向上し入出力端子が増加している。それに伴って、半導体を搭載する半導体パッケージも多くの入出力端子を必要とするようになり、また、同時に小型化も要求されているため高密度化が進行している。このような要求にこたえる半導体パッケージとして、従来の周辺にしか端子が配置できないリードフレームタイプのＳＯＰ（ＳｍａｌｌＯｕｔｌｉｎｅＰａｃｋａｇｅ）やＱＦＰ（ＱｕａｄＦｌａｔＰａｃｋａｇｅ）に変わって、端子を面上に配置できるＢＧＡ（ＢａｌｌＧｒｉｄＡｒｒａｙ）が使用されるようになった。また、最近では、さらに小型な半導体パッケージが必要とされる分野には、チップの外形とほぼ同サイズのＣＳＰ（ＣｈｉｐＳｉｚｅＰａｃｋａｇｅ）が開発され用いられている。これらＢＧＡやＣＳＰは、チップを搭載する基板として、インターポーザと呼ばれる配線基板を用いており、より小型で高密度、かつ低コストな半導体パッケージ用の配線基板が望まれている。
【０００３】
このような要求を満たす配線基板の例として、特開２００２−０４３４６７号公報に報告されているような、接続端子用導体と、接続端子用導体間を埋める樹脂と、接続端子の搭載される面と反対面に設けられた回路用導体からなる配線基板がある。
一方、近年、半導体パッケージの集積度をより向上させるため、１つのパッケージ内に複数のチップをパッケージングしたＭＣＰ（ＭｕｌｔｉＣｈｉｐＰａｃｋａｇｅ）が開発され、また、ＳＩＰ（ＳｙｓｔｅｍＩｎＰａｃｋａｇｅ）と呼ばれる従来ボード上で実現してきたシステムを１つのパッケージにて実現しようとする試みが広がっている。このようなパッケージの形成方法として、チップと配線基板を接続後に、樹脂で埋めその上に配線を形成し積層していく方法がある。
以上のような情勢において、近年、凹凸の有る部材や中間体に対し、絶縁樹脂で埋める工程が増えつつある。しかし、無機、有機物質が複雑に組み合わさっている半導体パッケージや配線板では、樹脂と銅配線、半導体チップ等の異なる材料間の接着性が重要であり、また、同時にそりやうねりのない高い平坦性が要求されている。
【０００４】
【発明が解決しようとする課題】
しかしながら、樹脂層を形成する方法として、樹脂シートをプレスして形成する場合、上記のような凹凸ある部材に対し、樹脂の追随性が問題となる。また、チップを埋める場合には、チップへかかる圧力によりチップの割れが心配される。
本発明は、半導体パッケージ用基板やその他の配線板の製造に用いられる凹凸のある部材に対し、簡便に樹脂層を形成する方法を提案するものである。そして、通常、配線部材、特に導電性突起を有する部材に樹脂層を形成する場合、未硬化状態の樹脂を塗布し硬化すると、樹脂の収縮や、部材と樹脂との熱膨張差に起因してそりやうねりが発生する。また、そりやうねりを抑える方法として、無機粒子を高比率配合させた低収縮の樹脂を用いる方法があるが、その方法では樹脂と部材との接着性が悪くなる問題があった。本発明は、さらに、樹脂層の形成方法に加え、接着性が良く、そりやうねりが発生しない樹脂層を形成する方法をも提供するものである。
【０００５】
【課題を解決するための手段】
本発明は、１．導電性突起を有した金属箔に樹脂層を形成し、その後、研磨で導電性突起を露出させる工程により製造される半導体パッケージ用基板、配線板、２．導電性突起を有した導体と絶縁樹脂からなる配線部材に樹脂層を形成し、その後、研磨で導電性突起を露出させる工程により製造される半導体パッケージ用基板、配線板、３．チップや受動部品を配線基板に実装した後に樹脂で埋め込み、樹脂層を形成し、その上に配線を設ける、素子内蔵型の半導体パッケージ、又は配線板、の３つのものに樹脂層を形成する方法として、ワニス状態にある樹脂を印刷により塗布し、硬化することで形成する方法を提案する。
【０００６】
即ち、本発明は、下記の（１）〜（２１）に関する。
（１）表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を硬化させる硬化工程、及び、絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を含む配線板の製造方法。
（２）配線板が半導体パッケージ用基板である（１）記載の配線板の製造方法。
（３）配線部材が、表面に複数の導電性突起を有する金属箔である（１）又は（２）に記載の配線板の製造方法。
（４）配線部材が、絶縁樹脂層、絶縁樹脂層両面上の層間接続された導体層、及び絶縁樹脂層の少なくとも片面上に導電性突起を有するものである（１）又は（２）に記載の配線板の製造方法。
（５）硬化工程の後に研磨工程を行なう（１）〜（４）いずれかに記載の配線板の製造方法。
【０００７】
（６）表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥する乾燥工程、半硬化した状態まで乾燥した絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程、研磨後に絶縁樹脂を完全に硬化させる硬化工程を含む（１）〜（４）いずれかに記載の配線板の製造方法。
（７）配線部材の導電性突起を有する面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、導電性突起が絶縁樹脂で埋め込まれる厚みに形成する工程、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層を研磨して導電性突起の先端を露出させる研磨工程を含む（１）〜（４）いずれかに記載の配線板の製造方法。
【０００８】
（８）硬化工程を研磨工程の後に行なう（７）に記載の配線板の製造方法。
（９）多層絶縁樹脂層を形成する工程において、絶縁樹脂（１）として配線部材と接着性の良い絶縁樹脂を用い、絶縁樹脂（２）の層及び絶縁樹脂（３）の層を含む第２層以上の層に、作製された配線板のそりを低減させる特性を有した絶縁樹脂を使用した（７）又は（８）に記載の配線板の製造方法。
（１０）（７）又は（８）に記載の半硬化状態で樹脂を積層する工程において、無機又は有機粒子の含有率が異なる樹脂、又は基本樹脂構造が異なる樹脂、を印刷により任意の位置、形状、厚みで形成し、その後、樹脂を積層することにより、絶縁樹脂中に性質の異なる樹脂を任意の箇所に混在させた樹脂層を形成する方法。
（１１）（１）〜（１０）いずれかに記載の方法により製造された配線板。
（１２）（１）〜（１０）いずれかに記載の方法により製造された半導体パッケージ用基板。
（１３）（１２）に記載の半導体パッケージ用基板を用いた半導体パッケージ。
【０００９】
（１４）電子部品を配線板に実装した後に絶縁樹脂で埋め込み、絶縁樹脂層を形成し、その絶縁樹脂層の上に配線を設ける、素子内蔵型の配線板の製造方法であって、電子部品を配線板に実装した後、硬化前の流動状のワニス状態にある絶縁樹脂を印刷により塗布して電子部品を埋めこみ、印刷した絶縁樹脂を硬化させて絶縁樹脂層を形成することを特徴とする製造方法。
（１５）電子部品が半導体チップであり、素子内蔵型の配線板が素子内蔵型の半導体パッケージである（１４）に記載の方法。
（１６）配線板の電子部品実装面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、電子部品が絶縁樹脂で埋め込まれる厚みに形成する工程、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層上に配線を設ける工程を含む（１４）又は（１５）に記載の配線板の製造方法。
（１７）多層絶縁樹脂層を形成する工程の後、多層絶縁樹脂層の表面を平坦に研磨した後に硬化工程を行なう（１６）に記載の方法。
【００１０】
（１８）多層絶縁樹脂層を形成する工程において、絶縁樹脂（１）として配線板及び電子部品と接着性の良い絶縁樹脂を用い、絶縁樹脂（２）の層及び絶縁樹脂（３）の層を含む第２層以上の層に、作製された素子内蔵型の配線板のそりを低減させる特性を有した絶縁樹脂を使用した（１６）〜（１８）いずれかに記載の配線板の製造方法。
（１９）（１６）〜（１８）いずれかに記載の半硬化状態で樹脂を積層する工程において、無機又は有機粒子の含有率が異なる樹脂、又は基本樹脂構造が異なる樹脂、を印刷により任意の位置、形状、厚みで形成し、その後、樹脂を積層することにより、絶縁樹脂中に性質の異なる樹脂を任意の箇所に混在させた樹脂層を形成する方法。
（２０）（１４）〜（１９）いずれかに記載の方法により製造された素子内蔵型の配線板。
（２１）（１４）〜（１９）いずれかに記載の方法により製造された素子内蔵型の半導体パッケージ。
【００１１】
また、樹脂層の形成方法として、１）配線部材と接着性の良い絶縁樹脂を硬化前の流動性のあるワニス状態で薄く塗布し、塗布後、流動性がなくなるが完全に硬化していない半硬化状態に乾燥して第１層とする工程、２）流動性がなく半硬化状態にある第１層の樹脂層の上から、そりやうねりが発生しないように配合した樹脂を、未硬化でワニス状態にある液状のまま塗布し、同様に流動性がなくなる半硬化状態に乾燥して第２層とする工程、３）樹脂層のバランスを取るために、第１層と同一、又は異なる樹脂を第２層の上に流動状のワニス状態で塗布し、塗布後、流動性のなくなる半硬化状態に乾燥して第３層とする工程、４）半硬化状態にある全ての樹脂層を、一括して完全な硬化の状態に硬化する工程、よりなる製造法を提供する。
【００１２】
【発明の実施の形態】
本発明の配線板の製造方法は、表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を硬化させる硬化工程、及び、絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を含む。
本発明の方法で製造される配線板としては、例えば、半導体パッケージに用いられるインターポーザーとしての半導体パッケージ用基板、半導体パッケージやその他の電子部品を搭載するマザーボード等のその他の配線板が挙げられる。
本発明で用いられる表面に複数の導電性突起を有する配線部材としては、例えば、下記のものが挙げられる。
【００１３】
１．表面に導電性突起を有する金属箔。例えば、第１、第３の金属層が第２の金属層とエッチング条件の異なる金属層である３層の金属箔を、ドライフィルムレジストを用いたエッチングにより第１の金属層を柱状バンプとした金属箔、及び、上記の３層の金属箔を、ドライフィルムレジストを用いたエッチングにより第１の金属層を柱状バンプとし、次いで第２の金属層を、柱状バンプの下部を除いて第３の金属層が露出するまでエッチング除去した金属箔がある。このときの第１、３の金属層が銅、銅合金の場合には、第２の金属層としては、ニッケル、ニッケル合金、チタン、クロム、錫、亜鉛等がある。
２．導電性突起を有した導体と絶縁樹脂からなる配線部材。例えば、配線部材が、絶縁樹脂層、絶縁樹脂層両面上の層間接続された導体層、及び絶縁樹脂層の少なくとも片面上に導電性突起を有するもの。例えば、上記金属箔に、柱状バンプの端面を露出させて樹脂層を形成したものの樹脂層形成面に上記３層金属箔を加熱圧着し、その後、同様に第１層の金属層を柱状バンプとしたものがある。また、一般的な両面配線板の表面に、銀ペースト等の導電性ペーストを印刷して導電性突起を形成したもの、めっきレジスト等を使用して、めっき析出で金属突起を形成したものも含む。
３．素子内蔵型の半導体パッケージ、又は配線板における中間部材。
【００１４】
本発明で使用する絶縁樹脂の例としては、ポリイミド樹脂、ポリアミドイミド樹脂、シリコーン樹脂、フェノール樹脂、ビスマレイミドトリアジン樹脂、エポキシ樹脂、アクリル樹脂等の熱硬化性樹脂、ポリフェニレンサルファイド樹脂、感光性ポリイミド樹脂、アクリルエポキシ樹脂、エチレン、プロピレン、スチレン、ブタジエン等の熱可塑性エラストマー、液晶ポリマー等がある。また、これらの樹脂に有機粒子や無機粒子を配合したものも使用することができる。樹脂に配合することができる有機粒子の例としては、前述の樹脂の硬化物、無機粒子の例としてはアルミナ粒子、二酸化ケイ素（シリカ）、ガラス繊維等がある。これらの有機又は無機粒子の粒径は、平均粒径が０．１〜２０μｍであることが好ましい。
本発明においては、硬化前の流動状のワニス状態にある絶縁樹脂を、配線部材の導電性突起を有する表面に、導電性突起が絶縁樹脂で埋め込まれる厚みに、印刷により塗布する。流動状のワニス状態にある絶縁樹脂は、印刷時に粘度が３〜７０Ｐａ・ｓであることが好ましい。印刷方法としては、メッシュスクリーンマスク、メタルマスク等を用いたスクリーン印刷法、及び配線部材上に直接スキージ、ブレード等を用いて、すり切り又は隙間を空けて均一な厚みに樹脂を塗布する方法、及び樹脂をドラム又はボード等に塗布した後、配線部材上に樹脂を転写する方法等がある。また、これら作業を真空下で行なう方法も、未充填箇所をなくすには有効である。
【００１５】
印刷工程の後、硬化工程の後に研磨工程を行ってもよい。また、研磨工程の後に硬化工程を行ってもよい。その場合、研磨工程の前に、絶縁樹脂を、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥する乾燥工程を行い、次いで、半硬化した状態まで乾燥した絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を行い、その後、絶縁樹脂を完全に硬化させる硬化工程を行う。この後者の方法では、完全に硬化した樹脂より柔らかいため、研磨効率が向上する。
【００１６】
絶縁樹脂層を形成する配線部材に応じて、各層の樹脂の配合成分、樹脂種類、厚み、或いは層数を変えることで、全体のそり量を制御できる。絶縁樹脂としては、１種類のみを用いて単層の樹脂層を形成してもよいし、２種類以上の絶縁樹脂、同一組成の樹脂にフィラー等の充填率を変えたものも含めて、これらを用いて、多層絶縁樹脂層を形成してもよい。また、多層絶縁樹脂層とする場合、第１層の樹脂を、部材の種類、表面状態に合わせ選択することで接着性の良い層とすることができる。
例えば、配線部材の導電性突起を有する面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、導電性突起が絶縁樹脂で埋め込まれる厚みに形成する。その後、研磨工程の前又は後に硬化工程を行ない、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる。
【００１７】
好ましくは、１）配線部材と接着性の良い絶縁樹脂を硬化前の流動性のあるワニス状態で薄く塗布し、塗布後、流動性がなくなるが完全に硬化していない半硬化状態に乾燥して第１層とする工程、２）流動性がなく半硬化状態にある第１層の樹脂層の上から、そりやうねりが発生しないように配合した絶縁樹脂を、未硬化でワニス状態にある液状のまま塗布し、同様に流動性がなくなる半硬化状態に乾燥して第２層とする工程、３）多層絶縁樹脂層のバランスを取るために、第１層と同一、又は異なる絶縁樹脂を第２層の上に流動状のワニス状態で塗布し、塗布後、流動性のなくなる半硬化状態に乾燥して第３層とする工程により、多層絶縁樹脂層を形成する。次いで、研磨工程の前又は後に、４）半硬化状態にある全ての樹脂層を、一括して完全な硬化の状態に硬化する工程を行なう。
【００１８】
一般的に、樹脂を低収縮、低熱膨張にするためには、無機粒子を高い比率で配合させるが、その場合、樹脂と部材との接着力が低下する。そのため、接着界面の第１層を無機粒子の含まない、又は少量、例えば絶縁樹脂中１〜２０重量％含む樹脂層とし、第２層に無機粒子を第１層に対して高い比率、例えば絶縁樹脂中２０重量％より多く９０重量％以下で配合した樹脂層とする。このことにより、接着性の良い状態で低収縮、低熱膨張の樹脂層を形成することができる。多層絶縁樹脂層が３層構造である場合、第３層には、第１層と同じ絶縁樹脂を用いることが好ましい。
また、本発明は、無機、有機粒子等のフィラー成分を多く含有した樹脂を任意の開口を設けたステンシルマスクを通して印刷して乾燥し、繰り返し印刷、乾燥を行うことで、絶縁樹脂中に無機、有機粒子成分を任意の箇所に混在させる方法としても利用できる。この際、同一樹脂を使用することは、各層間との密着信頼性を向上する上で望ましい。
【００１９】
研磨工程における研磨方法としては、ロールペーパー研磨、サンドブラスト法、ホーニング、ラッピング等があり、また刃物を使用した機械加工法、例えばルータ加工等でもよい。また、絶縁樹脂を半硬化状態で研磨をすることは、硬化状態に比べ硬度が低いため、研磨効率を上げることができる。
なお、記載されている樹脂の半硬化状態とは、流動性がなくなり、研磨可能な状態に硬化されたもので完全な硬化に至っていない樹脂の状態を指す。熱硬化性樹脂ではＢステージ状態と呼ばれ、樹脂により異なるが、一般的に硬化率が３０〜８０％のものを指す。この硬化率は、ＤＳＣ（示差走査熱分析）により測定することが可能である。絶縁樹脂の半硬化状態までの乾燥、及び、完全硬化は、絶縁樹脂が熱硬化性樹脂の場合、加熱により行ない、研磨時の室温（５〜３５℃）に戻した状態において、流動性がなく、外力を加えた際に弾性変形又は塑性変形し、外圧をなくすと弾性変形の場合は元の状態に戻り、塑性変形した場合には変形した状態を維持するような状態が研磨可能な状態である。
溶剤希釈タイプの熱可塑性材料の場合、溶剤分を適度に除去することにより、半硬化状態にすることができる。溶剤分を除去する方法としては、加熱又は減圧する方法等がある。熱硬化性樹脂と同様、研磨可能な状態とは、流動性がなく、外力を加えた際に、弾性変形又は塑性変形し、外圧をなくすと弾性変形の場合は元の状態に戻り、塑性変形した場合は変形した状態を維持するような状態である。
【００２０】
感光性ポリイミド等、感光性樹脂を使用する場合、紫外線照射量により硬化量を制御することができる。また、感光性樹脂の場合は、導電性突起上部をマスキング等により紫外線が当たらないようにし、導電性突起部以外の部分の紫外線照射量より紫外線照射量を低減し、導電性突起上部が他の部分より未硬化の状態にすることで、導電性突起上部をより集中して研磨ができ、研磨効率を上げることができる。さらに、この感光性樹脂が露光部分とそれ以外の部分とを薬液で除去できるタイプであれば、導電性突起上部とそれ以外の部分の紫外線照射量を変えることで、導電性突起上部の樹脂のみ薬液で除去することができ、研磨なし、又はわずかな研磨で導電性突起上部の頭出しができる。
また、本発明の方法により表面に導電性突起を有する金属箔を用いて半導体パッケージ用基板を製造する場合、表面にある金属箔のシート状部分を選択的にエッチングして回路パターンを形成してもよい。また、金属箔の導電性突起を有する表面の平坦部に半導体チップを搭載し、導電性突起と共に絶縁樹脂中に埋め込んでもよい。また、半導体パッケージ用基板の導電性突起の端面が露出した面又は回路面に、更に半導体パッケージ用基板を積層して、多層構造の半導体パッケージ用基板としてもよい。
【００２１】
本発明の半導体パッケージは、本発明の方法によって作製された半導体パッケージ用基板を用いたものである。例えば、半導体パッケージ用基板の回路パターンを有する面に、半導体チップをダイボンド材等で固定して回路パターンと半導体チップをワイヤーボンディングでボンディングするか、または、半導体チップをフリップチップボンディングして回路パターンと接続する。次いで、半導体パッケージ用基板の半導体チップ搭載面を封止材で封止することにより、半導体パッケージが得られる。
【００２２】
本発明の素子内蔵型の配線板の製造方法では、電子部品を配線板に実装した後、硬化前の流動状のワニス状態にある絶縁樹脂を印刷により塗布して電子部品を埋めこみ、印刷した絶縁樹脂を硬化させて絶縁樹脂層を形成し、絶縁樹脂層の上に配線を設ける。電子部品としては、半導体チップ、受動部品等、特に制限はなく用いられる。配線板としては、本発明の製造方法によって得られる配線板を含む各種の配線板を使用することができる。また、配線板の製造方法と同様に、絶縁樹脂層は、単層としてもよいし、多層絶縁樹脂層としてもよい。使用可能な樹脂は、配線板の製造方法について記載したものと同様である。
例えば、まず、配線板の電子部品実装面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、電子部品が絶縁樹脂で埋め込まれる厚みに形成する。その後、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層上に配線を設ける工程を行なう。
多層絶縁樹脂層を形成する場合の絶縁樹脂の組み合わせの例も、配線板の製造方法について記載したものと同様である。
【００２３】
【実施例】
以下、本発明の実施例及びその比較例によって本発明を更に具体的に説明するが、本発明はこれらの実施例に限定されるものではない。
【００２４】
実施例１
図に基づいて本発明の一実施例を説明する。図１は導電性突起を有した金属箔への多層樹脂層を形成する各工程における断面を示した図である。図１（ａ）に導電性突起Ａを有した金属箔７と接着性の良い第１樹脂層１を形成する工程を示す。ここで、導電性突起Ａを有する金属箔７は、以下のようにして作製した。厚さ７０μｍの銅層、０．２μｍのニッケル層、１０μｍの銅層からなる３層金属箔（日本電解（株）製）を、フォトドライフィルムＨ−Ｋ３５０（日立化成工業（株）製）を用いてパターンを形成し、メルテックス社製エープロセス液（アンモニア銅錯塩２０〜３０重量％、塩化アンモニウム１０〜２０重量％及びアンモニア１〜１０重量％含有）からなるアルカリエッチング液で７０μｍ銅層を選択的にエッチングして、露出したニッケル層の表面に銅からなる金属柱を形成した。このとき、金属柱はφ２５０μｍの円柱となるようにした。次いで、ニッケル層の金属柱下以外の部分を、硝酸・過酸化水素水溶液からなるエッチング液で選択的に除去することにより、銅及びニッケルからなるφ２５０μｍの円柱状の導電性突起Ａを形成した。露出した１０μｍの銅層表面に、樹脂との密着性を良くするために化学リン系処理を施した。
【００２５】
第１樹脂層１の形成には、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）を用いた。流動状のワニス状態の粘度４０Ｐａ・ｓの上記樹脂を、印刷機ＶＥ−５００（東レエンジニアリング（株）製）で印刷した。１８はマスクを、１７はスキージを示す。印刷後、８０℃で３０分、乾燥し流動性がなくなった半硬化状態とし第１樹脂層１を形成した。乾燥後の第１樹脂層１の厚さ（水平部分での厚み；以下同様）は、２０μｍであった。
次に、ＫＳ６６００に無機粒子（二酸化ケイ素）を７５％含有させた樹脂を、流動状のワニス状態で第１樹脂層１の上に印刷した。第１樹脂層１と同様、８０℃で３０分、乾燥し流動性がなくなった半硬化状態の第２樹脂層２を形成した（図１（ｂ）。乾燥後の第２樹脂層２の厚さは３０μｍであった。
図１（ｃ）に示すように、第２樹脂層２の上に、流動状のワニス状態のＫＳ６６００を印刷した。塗布後、８０℃、３０分で乾燥し流動性がなくなった半硬化状態に半硬化し第３樹脂層３とした。乾燥後の第３樹脂層３の厚さは２５μｍであった。
【００２６】
金属箔７に第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる３層の半硬化状態の樹脂層を形成後、図１（ｄ）に示すように、埋め込まれた導電性突起Ａの端面を絶縁樹脂層表面に露出させるため、絶縁樹脂層が半硬化状態のまま、市販用研磨紙で研磨した。研磨時間は、２５０ｍｍｘ２５０ｍｍの金属箔上の絶縁樹脂層表面を＃４００の研磨紙で３０分／枚で研磨することができた。比較として行った絶縁樹脂層を完全に硬化した部材を研磨した場合は、同研磨紙で６０分／枚であった。
図１（ｅ）に示すように、研磨後、１８０℃で３０分間、２２０℃で１０分間加熱して、半硬化状態にある３層の樹脂層を完全に硬化し硬化樹脂層４、５、６とした。
硬化樹脂層を形成した後の半導体パッケージ用の本部材は、樹脂を完全に硬化させた後もそりやうねりがなく平坦であった。また、得られた部材を用いて、金属箔表面（導電性突起と反対面）を、メルテックス社製エープロセス液を用いてエッチングし、回路形成した。その後、回路表面及び導電性突起の露出面に電解ニッケル／金メッキを施すことにより、半導体パッケージ用基板を作製した。得られた半導体パッケージ用基板も同様に平坦であった。また、樹脂層と銅のピール強度も１．２ｋｇ／ｃｍと、無機粒子を高比率（６０重量％）で配合させた樹脂と銅のピール強度０．５ｋｇ／ｃｍに比べ強かった。
【００２７】
実施例２
図２に本実施例の工程の断面図を示す。以下、工程に沿って説明する。
図２（ａ）の、導電性突起Ａを有する金属箔７は、以下のようにして作製した。厚さ１００μｍの銅層、０．２μｍのニッケル層、５μｍの銅層からなる３層金属箔（日本電解（株）製）を、フォトドライフィルムＨ−Ｋ３５０（日立化成工業（株）製）を用いてパターンを形成し、メルテックス社製エープロセス液（アンモニア銅錯塩２０〜３０重量％、塩化アンモニウム１０〜２０重量％及びアンモニア１〜１０重量％含有）からなるアルカリエッチング液で１００μｍ銅層を選択的にエッチングして、露出したニッケル層の表面に銅からなる金属柱を形成した。このとき、金属柱はφ２５０μｍの円柱となるようにした。次いで、ニッケル層の金属柱下以外の部分を、硝酸・過酸化水素水溶液からなるエッチング液で選択的に除去することにより、銅及びニッケルからなるφ２５０μｍの円柱状の導電性突起Ａを形成した。露出した５μｍの銅層表面に、樹脂との密着性を良くするために化学リン系処理を施した。
準備した導電性突起を有する金属箔７にサイズ６．５ｘ６．５ｍｍ、厚さ０．０５０ｍｍの半導体チップ１０を、Ａｌ電極Ｂが導電性突起Ａの形成されていない銅箔面に接するように、ダイボンディングペーストＥＮ−Ｘ５０Ｎ（日立化成工業（株）製）１９を用いて固定した。この際、半導体チップのパッド部にダイボンディングペーストが付着しないようにした。
【００２８】
図２（ｂ）は、実施例１と同様に、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）及びこの樹脂と無機粒子からなる樹脂を用いて半硬化状態にある第１樹脂層１、第２樹脂層２及び第３樹脂層３の３層からなる絶縁樹脂層を形成したのち、樹脂が半硬化の状態で研磨を行い、埋め込んだ導電性突起を露出させた後、３層の樹脂を完全に硬化させたときの断面図である。なお、乾燥後の各樹脂層の厚さは、第１樹脂層１が３０μｍ、第２樹脂層２が４０μｍ、第３樹脂層３が３５μｍであった。
図２（ｃ）は、厚さ５μｍの銅層を選択的にエッチングして回路Ｃを形成した形成を行った断面図である。その際、半導体チップ１０搭載部分の銅箔は、チップのパッド部分のみ露出するようにエッチングを行った。
【００２９】
図２（ｄ）に示すのは、露出した半導体チップのＡｌ電極Ｂを、形成した回路Ｃとの接続を行うため、Ａｌ電極Ｂ部分に導電性ペーストのドーデント（ニホンハンダ（株）製）２０を穴埋め印刷し、その後、１８０℃、３０分で硬化させた断面図である。
図２（ｅ）は、実施例１と同様の工程で導電性突起を有した金属箔に３層の半硬化状態の絶縁樹脂層を形成した部材を準備している。
図２（ｆ）は、図２（ｄ）に示す部材に、図２（ｅ）で準備した部材を真空プレス装置により、真空下で加熱圧着した断面図である。加熱することにより半硬化状態の図２（ｃ）の部材の樹脂が一旦軟化し、加圧することにより樹脂が回路間に押し込まれ、図２（ｄ）の部材に接着する。層間の接続は埋め込まれた銅からなる導電性突起Ａと５μｍの銅層から形成した回路Ｃとの間で行っている。
【００３０】
図２（ｆ）の場合、層間の接続は周りの樹脂の接着力で導電性突起Ａと回路Ｃとが接触している状態であるが、より接続信頼性を上げるためには、導電性突起Ａの露出部と回路Ｃとに金めっきを施し、密着性を上げたり、同様箇所に、はんだめっきを施して、プレス接続時又はプレス後にはんだ溶融温度以上に加熱しはんだ接続したり、プレス前に導電性突起Ａの露出部又は回路Ｃの接続部又は両方の部位に導電性接着剤を塗布しておき、プレス時に同時に接着硬化する方法が考えられる。
図２（ｇ）は、加熱圧着した部材の第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる絶縁樹脂層を完全に硬化して、硬化樹脂層１、硬化樹脂層２及び硬化樹脂層３からなる層とした後の断面図である。
硬化後、電解ニッケル／金めっき（大和電機工業（株）製）を行い図２（ｇ）に示すような断面構造を持つ半導体チップが内蔵された半導体パッケージ用基板を作製した。
【００３１】
実施例３
図３に本実施例を行った工程の断面図を示す。ベース基板として、ガラスエポキシ基材１４を絶縁層とする両面配線板を作製し（図３（ａ））、この両面配線板の配線８上に端子部に金バンプ９を備えるＬＳＩ素子１０（厚み５０μｍ）を搭載して、金バンプ９と配線８とを、熱圧着により相互接続させた（図３（ｂ））。このようにして作製された組み立て体を、実施例１と同様にして、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）を及びこの樹脂と無機充填材とからなる樹脂を用いて半硬化状態にある第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる３層の絶縁樹脂層を形成した（図３（ｃ））。なお、乾燥後の各樹脂層のソルダーレジスト１２上の厚さは、第１樹脂層１が４０μｍ、第２樹脂層２が６０μｍ、第３樹脂層３が４０μｍであった。半硬化させた後、研磨を行い、ついで、絶縁樹脂層の樹脂を完全に硬化させた。
研磨及び完全硬化して表面が平坦な絶縁樹脂層を形成後、層間接続用のビアをあけ無電解銅めっきを用いたアディティブ法により多層配線を形成し、その上にソルダーレジスト１２を形成して配線パターン１１を形成した（図３（ｄ））。その後、形成した配線パターン１１上に、金バンプ９を備えるＬＳＩ素子１０を搭載して、金バンプ９と配線パターン１１とを、熱圧着により相互接続させ、ＬＳＩ素子１０とソルダーレジスト１２との間には液状エポキシ樹脂（アンダーフィル材）１３をフィルして硬化させ、素子内蔵型３次元半導体パッケージを得た（図３（ｅ））。
【００３２】
【発明の効果】
本発明では、金属箔や配線板用の部材、半導体パッケージ用基板に、特に凹凸のある場合に、密着性の良い樹脂層を、そりやうねりを発生させずに形成することができる。また、該部材を用いて平坦な半導体パッケージや配線板を提供することができる。
【図面の簡単な説明】
【図１】本発明の方法により、導電性突起を有した金属箔に樹脂層を形成する工程の断面図。
【図２】本発明の方法により、導電性突起有した金属箔に半導体チップを埋め込んだ後、樹脂層を形成する工程、及び半導体チップを埋め込んだ後、半導体パッケージ用基板とする工程の断面図。
【図３】本発明の方法を、複数の半導体チップを内蔵した３次元半導体パッケージの製造方法に適用する工程の断面図。
【符号の説明】
１第１樹脂層
２第２樹脂層
３第３樹脂層
４硬化第１樹脂層
５硬化第２樹脂層
６硬化第３樹脂層
７導電性突起を有した金属箔
Ａ導電性突起
８配線
９金バンプ
１０半導体チップ（ＬＳＩ素子）
ＢＡｌ電極
Ｃ回路
１１アディティブ法により形成した配線パターン
１２ソルダーレジスト
１３アンダーフィル材
１４ガラスエポキシ基材
１５スルーホールめっき接続部
１６ニッケル／金めっきパッド
１７スキージ
１８マスク
１９ダイボンディングペースト
２０導電性ペースト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring board, a substrate for a semiconductor package, a semiconductor package, and a manufacturing method thereof.
[0002]
[Prior art]
With the demand for miniaturization and high performance of electronic devices, the degree of integration of semiconductors has improved year by year and the number of input / output terminals has increased. Along with this, a semiconductor package on which a semiconductor is mounted requires a large number of input / output terminals, and at the same time, miniaturization is required. As a semiconductor package that meets such demands, BGA (Ball) in which terminals can be arranged on the surface is replaced with lead frame type SOP (Small Outline Package) or QFP (Quad Flat Package) in which terminals can be arranged only in the periphery. Grid Array) has been used. Recently, a CSP (Chip Size Package) having the same size as the outer shape of a chip has been developed and used in a field where a smaller semiconductor package is required. These BGAs and CSPs use a wiring board called an interposer as a board on which a chip is mounted, and a wiring board for a semiconductor package with a smaller size, higher density, and lower cost is desired.
[0003]
As an example of a wiring board that satisfies such requirements, a connection terminal conductor, a resin that fills between the connection terminal conductors, and a surface on which the connection terminal is mounted, as reported in Japanese Patent Application Laid-Open No. 2002-043467. There is a wiring substrate made of a circuit conductor provided on the opposite surface.
On the other hand, in recent years, MCP (Multi Chip Package) in which a plurality of chips are packaged in one package has been developed in order to further improve the degree of integration of semiconductor packages, and on a conventional board called SIP (System In Package). Attempts to implement the system that has been realized in 1 package in one package are spreading. As a method for forming such a package, there is a method in which after a chip and a wiring board are connected, they are filled with a resin, and wiring is formed and laminated thereon.
Under the circumstances as described above, in recent years, a process of filling an uneven member or intermediate with an insulating resin is increasing. However, in semiconductor packages and wiring boards with complex combinations of inorganic and organic substances, adhesion between different materials such as resin and copper wiring and semiconductor chips is important, and at the same time, high flatness without warping and undulation Sex is required.
[0004]
[Problems to be solved by the invention]
However, as a method of forming the resin layer, when the resin sheet is formed by pressing, the followability of the resin becomes a problem with respect to the uneven member as described above. Further, when filling the chip, there is a concern about cracking of the chip due to the pressure applied to the chip.
The present invention proposes a method for easily forming a resin layer on an uneven member used for manufacturing a semiconductor package substrate or other wiring board. Usually, when a resin layer is formed on a wiring member, particularly a member having conductive protrusions, when an uncured resin is applied and cured, the resin contracts or the thermal expansion difference between the member and the resin results. Sledge and undulation occur. Further, as a method of suppressing warpage and undulation, there is a method of using a low shrinkage resin in which a high ratio of inorganic particles is blended, but this method has a problem that the adhesion between the resin and the member is deteriorated. In addition to the method for forming a resin layer, the present invention also provides a method for forming a resin layer that has good adhesion and does not generate warpage or undulation.
[0005]
[Means for Solving the Problems]
The present invention provides: 1. a substrate for a semiconductor package, a wiring board manufactured by a step of forming a resin layer on a metal foil having conductive protrusions and then exposing the conductive protrusions by polishing; 2. a semiconductor package substrate, a wiring board manufactured by a step of forming a resin layer on a wiring member made of a conductor having conductive protrusions and an insulating resin and then exposing the conductive protrusions by polishing; A method of forming a resin layer on three components: a semiconductor package with built-in element or a wiring board, in which a chip or passive component is mounted on a wiring board and then embedded with resin, a resin layer is formed, and wiring is provided thereon. A method of forming a resin by applying a resin in a varnish state by printing and curing is proposed.
[0006]
That is, the present invention relates to the following (1) to (21).
(1) A printing process in which an insulating resin in a fluid varnish state before curing is applied to a wiring member having a plurality of conductive protrusions on the surface by printing to a thickness in which the conductive protrusions are embedded with the insulating resin, printing A method of manufacturing a wiring board, comprising: a curing step of curing the insulating resin, and a polishing step of polishing the insulating resin to expose the tips of the conductive protrusions.
(2) The method for manufacturing a wiring board according to (1), wherein the wiring board is a substrate for a semiconductor package.
(3) The method for manufacturing a wiring board according to (1) or (2), wherein the wiring member is a metal foil having a plurality of conductive protrusions on the surface.
(4) The wiring member has an insulating resin layer, a conductor layer connected on both sides of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. (1) or (2) Method for manufacturing a wiring board.
(5) The method for manufacturing a wiring board according to any one of (1) to (4), wherein a polishing step is performed after the curing step.
[0007]
(6) Printing process in which an insulating resin in a fluid varnish state before curing is applied to a wiring member having a plurality of conductive protrusions on the surface by printing to a thickness in which the conductive protrusions are embedded with the insulating resin, printing Although the fluidity of the insulating resin is lost, the drying process of drying to a semi-cured state before polishing until it completely cures, polishing to polish the insulating resin dried to the semi-cured state to expose the tips of the conductive protrusions The manufacturing method of the wiring board in any one of (1)-(4) including the hardening process which hardens | cures insulation resin completely after a process and grinding | polishing.
(7) Print the insulating resin (1) in a fluid varnish state on the surface of the wiring member having conductive protrusions, and the fluidity will be lost, but it will be dried to a semi-cured state before complete curing. Furthermore, the component is different from the insulating resin (1) and is in a fluid varnish state. The insulating resin (2) is different from the component in the fluid varnish state, and at least of the insulating resin (3) in a fluid varnish state. Two kinds of insulating resins are printed in this order, and the fluidity is lost. However, by drying to a semi-cured state before complete curing, the insulating resin (1) layer, insulating resin ( A step of forming a multilayer insulating resin layer comprising at least three layers of the layer 2) and the insulating resin (3) in a thickness in which the conductive protrusions are embedded with the insulating resin, and all insulating resins in the multilayer insulating resin layer Curing process for complete curing at the same time, and multilayer The manufacturing method of the wiring board in any one of (1)-(4) including the grinding | polishing process which grind | polishes an insulating resin layer and exposes the front-end | tip of an electroconductive protrusion.
[0008]
(8) The method for manufacturing a wiring board according to (7), wherein the curing step is performed after the polishing step.
(9) In the step of forming the multilayer insulating resin layer, the insulating resin (1) is an insulating resin having good adhesion to the wiring member, and includes a second layer including the insulating resin (2) layer and the insulating resin (3) layer. The method for producing a wiring board according to (7) or (8), wherein an insulating resin having a characteristic of reducing warpage of the produced wiring board is used for a layer equal to or more than one layer.
(10) In the step of laminating the resin in the semi-cured state according to (7) or (8), a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is printed at any position, A method of forming a resin layer in which resins having different properties are mixed in an insulating resin by forming the shape and thickness and then laminating the resins.
(11) A wiring board manufactured by the method according to any one of (1) to (10).
(12) A semiconductor package substrate manufactured by the method according to any one of (1) to (10).
(13) A semiconductor package using the semiconductor package substrate according to (12).
[0009]
(14) A method of manufacturing an element-embedded wiring board, in which an electronic component is mounted on a wiring board, embedded with an insulating resin, an insulating resin layer is formed, and wiring is provided on the insulating resin layer. After mounting on the wiring board, the insulating resin in a fluid varnish state before curing is applied by printing to embed the electronic component, and the printed insulating resin is cured to form an insulating resin layer. Production method.
(15) The method according to (14), wherein the electronic component is a semiconductor chip, and the element-embedded wiring board is an element-embedded semiconductor package.
(16) The insulating resin (1) in a fluid varnish state is printed on the electronic component mounting surface of the wiring board, and the fluidity is lost, but it is dried to a semi-cured state before complete curing. The insulating resin (1) has a component different from that of a fluid varnish, and the insulating resin (2) has a component different from that of a fluid varnish and has a fluid varnish state (3). Insulating resins (1) and (2) are printed in this order, and the fluidity is lost. By drying to a semi-cured state before complete curing, the insulating resin (1) layer, insulating resin (2) And a step of forming a multilayer insulating resin layer comprising at least three layers of the insulating resin (3) to a thickness in which the electronic component is embedded with the insulating resin, and completely insulating all the insulating resins in the multilayer insulating resin layer simultaneously. Curing process for curing and multilayer insulating resin The manufacturing method of the wiring board as described in (14) or (15) including the process of providing wiring on a layer.
(17) The method according to (16), wherein after the step of forming the multilayer insulating resin layer, the curing step is performed after the surface of the multilayer insulating resin layer is polished flat.
[0010]
(18) In the step of forming the multilayer insulating resin layer, an insulating resin having good adhesion to the wiring board and the electronic component is used as the insulating resin (1), and the insulating resin (2) layer and the insulating resin (3) layer are formed. The method for manufacturing a wiring board according to any one of (16) to (18), wherein an insulating resin having a characteristic of reducing warpage of the produced wiring board with a built-in element is used for the second layer or more.
(19) In the step of laminating the resin in the semi-cured state according to any one of (16) to (18), any resin having a different content of inorganic or organic particles or a resin having a different basic resin structure may be printed by printing. A method of forming a resin layer in which resin having different properties is mixed in an insulating resin by forming the position, shape, and thickness and then laminating the resin.
(20) An element-embedded wiring board manufactured by the method according to any one of (14) to (19).
(21) A device built-in type semiconductor package manufactured by the method according to any one of (14) to (19).
[0011]
In addition, as a method for forming the resin layer, 1) thinly apply an insulating resin having good adhesiveness to the wiring member in a fluid varnish state before curing, and after application, the fluidity is lost but the resin is not completely cured. Step of drying into a cured state to form a first layer, 2) Resin blended so as not to cause warpage or undulation from the top of the resin layer of the first layer that is not fluid and semi-cured, A process in which it is applied in a liquid state in a varnish state and dried to a semi-cured state in which the fluidity is lost to form a second layer. 3) Resin that is the same as or different from the first layer in order to balance the resin layer Is applied to the second layer in a fluid varnish state, and after application, the step of drying to a semi-cured state with no fluidity to form a third layer, 4) all the resin layers in the semi-cured state, Provided is a manufacturing method comprising a step of curing to a completely cured state collectively.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
In the method for manufacturing a wiring board according to the present invention, an insulating resin in a fluid varnish state before curing is printed on a wiring member having a plurality of conductive protrusions on the surface, and the conductive protrusions are embedded with the insulating resin by printing. A printing process applied to the substrate, a curing process for curing the printed insulating resin, and a polishing process for polishing the insulating resin to expose the tips of the conductive protrusions.
Examples of the wiring board manufactured by the method of the present invention include other wiring boards such as a substrate for a semiconductor package as an interposer used for a semiconductor package and a motherboard on which a semiconductor package and other electronic components are mounted.
Examples of the wiring member having a plurality of conductive protrusions on the surface used in the present invention include the following.
[0013]
1. Metal foil having conductive protrusions on the surface. For example, three metal foils in which the first and third metal layers are metal layers having different etching conditions from the second metal layer are formed into columnar bumps by etching using a dry film resist. The metal foil and the above-mentioned three layers of metal foil are etched using a dry film resist to form the first metal layer as columnar bumps, and then the second metal layer is removed by removing the lower part of the columnar bumps. There is a metal foil that is etched away until the metal layer is exposed. When the first and third metal layers at this time are copper or a copper alloy, examples of the second metal layer include nickel, a nickel alloy, titanium, chromium, tin, and zinc.
2. A wiring member comprising a conductor having conductive protrusions and an insulating resin. For example, the wiring member has an insulating resin layer, a conductor layer connected on both sides of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. For example, the end face of the columnar bump is exposed to the metal foil, and the resin layer is formed on the resin layer forming surface by thermocompression bonding. Then, similarly, the first metal layer is used as the columnar bump. There is what I did. Also included are those in which conductive protrusions are formed by printing a conductive paste such as silver paste on the surface of a general double-sided wiring board, and metal protrusions are formed by plating deposition using a plating resist or the like. .
3. An intermediate member in an element-embedded semiconductor package or wiring board.
[0014]
Examples of the insulating resin used in the present invention include polyimide resins, polyamideimide resins, silicone resins, phenol resins, bismaleimide triazine resins, epoxy resins, acrylic resins and other thermosetting resins, polyphenylene sulfide resins, and photosensitive polyimide resins. , Acrylic epoxy resins, thermoplastic elastomers such as ethylene, propylene, styrene, and butadiene, and liquid crystal polymers. Moreover, what mix | blended organic particle | grains and inorganic particle | grains with these resin can also be used. Examples of organic particles that can be blended into the resin include cured products of the aforementioned resins, and examples of inorganic particles include alumina particles, silicon dioxide (silica), glass fibers, and the like. These organic or inorganic particles preferably have an average particle size of 0.1 to 20 μm.
In the present invention, the insulating resin in a fluid varnish state before curing is applied by printing on the surface of the wiring member having the conductive protrusions to a thickness where the conductive protrusions are embedded with the insulating resin. The insulating resin in a fluid varnish state preferably has a viscosity of 3 to 70 Pa · s during printing. As a printing method, a screen printing method using a mesh screen mask, a metal mask, etc., and a method of applying a resin to a uniform thickness by using a squeegee, a blade, etc. directly on a wiring member, leaving a gap or a gap, and There is a method of transferring a resin onto a wiring member after applying the resin to a drum or a board. Moreover, the method of performing these operations under vacuum is also effective in eliminating unfilled portions.
[0015]
You may perform a grinding | polishing process after a hardening process after a printing process. Moreover, you may perform a hardening process after a grinding | polishing process. In that case, before the polishing process, Absolute The edge resin loses its fluidity, but a drying process is performed to dry it to a semi-cured state before it completely cures.Then, the insulating resin dried to the semi-cured state is polished to remove the tip of the conductive protrusion. A polishing step for exposing is performed, and then a curing step for completely curing the insulating resin is performed. Since the latter method is softer than a completely cured resin, the polishing efficiency is improved.
[0016]
Depending on the wiring member forming the insulating resin layer, the total warpage amount can be controlled by changing the resin composition, resin type, thickness, or number of layers in each layer. As an insulating resin, a single resin layer may be formed using only one type, including two or more types of insulating resins, and resins having the same composition but with a different filling rate such as filler. May be used to form a multilayer insulating resin layer. Moreover, when setting it as a multilayer insulation resin layer, it can be set as a layer with favorable adhesiveness by selecting resin of 1st layer according to the kind of member, and a surface state.
For example, the insulating resin (1) in a fluid varnish state is printed on the surface of the wiring member having the conductive protrusion, and the fluidity is lost, but it is dried to a semi-cured state before complete curing, Further, the insulating resin (1) has a component different from that of the insulating resin (2) in a fluid varnish state and the insulating resin (2) has a component different from that of the insulating resin (2) and is in a fluid varnish state. Each type of insulating resin is printed in this order, and the fluidity is lost. However, the insulating resin (1) layer, the insulating resin (2 ) And an insulating resin (3) layer are formed to a thickness at which the conductive protrusions are embedded with the insulating resin. Thereafter, a curing step is performed before or after the polishing step, and all the insulating resins in the multilayer insulating resin layer are completely cured simultaneously.
[0017]
Preferably, 1) Insulating resin with good adhesion to the wiring member is thinly applied in a varnish state with fluidity before curing, and after application, the fluidity is lost but dried to a semi-cured state that is not completely cured Step of forming the first layer 2) An insulating resin blended so as not to cause warpage or undulation from the top of the resin layer of the first layer which is not fluid and semi-cured, and is in an uncured and varnished liquid state Applying as is, and drying to a semi-cured state in which the fluidity disappears to form the second layer, 3) In order to balance the multilayer insulating resin layer, the same or different insulating resin as the first layer is used A multi-layer insulating resin layer is formed by applying a liquid varnish on the two layers and then drying to a semi-cured state with no fluidity to form a third layer. Then, before or after the polishing step, 4) a step of collectively curing all the resin layers in a semi-cured state to a completely cured state.
[0018]
In general, in order to make the resin low shrinkage and low thermal expansion, the inorganic particles are blended at a high ratio, but in this case, the adhesive force between the resin and the member is lowered. Therefore, the first layer of the adhesive interface is a resin layer that does not contain inorganic particles or a small amount, for example, 1 to 20% by weight in the insulating resin, and the second layer has a high ratio of inorganic particles to the first layer, for example, insulation. It is set as the resin layer mix | blended with more than 20 weight% and 90 weight% or less in resin. As a result, a resin layer having low shrinkage and low thermal expansion can be formed with good adhesiveness. When the multilayer insulating resin layer has a three-layer structure, it is preferable to use the same insulating resin as the first layer for the third layer.
In addition, the present invention prints and drys a resin containing a large amount of filler components such as inorganic and organic particles through a stencil mask provided with an arbitrary opening, and repeats printing and drying, so that the insulating resin is inorganic. It can also be used as a method of mixing organic particle components in arbitrary locations. In this case, it is desirable to use the same resin in order to improve the adhesion reliability with each layer.
[0019]
As a polishing method in the polishing step, there are roll paper polishing, sand blasting, honing, lapping and the like, and a machining method using a blade such as router processing may be used. In addition, polishing the insulating resin in a semi-cured state can increase the polishing efficiency because the hardness is lower than that in the cured state.
The semi-cured state of the described resin refers to the state of the resin that has lost fluidity and has been cured to a polishable state and has not yet been completely cured. A thermosetting resin is called a B stage state, and generally differs depending on the resin, but generally indicates a curing rate of 30 to 80%. This curing rate can be measured by DSC (Differential Scanning Calorimetry). When the insulating resin is a thermosetting resin, drying and semi-curing of the insulating resin to a semi-cured state are performed by heating, and there is no fluidity in a state where the temperature is returned to room temperature (5-35 ° C.) during polishing. When the external force is applied, it is elastically deformed or plastically deformed.When the external pressure is removed, the elastic deformed state returns to the original state, and when it is plastically deformed, the deformed state is maintained in a state that can be polished. is there.
In the case of a solvent-diluted thermoplastic material, a semi-cured state can be obtained by appropriately removing the solvent. As a method for removing the solvent, there is a method of heating or depressurizing. Like the thermosetting resin, the state that can be polished is not fluid, and elastically deforms or plastically deforms when external force is applied, and returns to the original state in the case of elastic deformation when the external pressure is removed. In such a case, the deformed state is maintained.
[0020]
When a photosensitive resin such as photosensitive polyimide is used, the amount of curing can be controlled by the amount of ultraviolet irradiation. In the case of a photosensitive resin, the upper part of the conductive protrusion is not exposed to ultraviolet rays by masking or the like, the ultraviolet irradiation amount is reduced from the ultraviolet irradiation amount of the part other than the conductive protrusion part, and the upper part of the conductive protrusion is the other part. By making the part uncured from the part, the conductive protrusion upper part can be polished more concentratedly, and the polishing efficiency can be increased. Furthermore, if this photosensitive resin is a type that can remove the exposed part and other parts with a chemical, only the resin on the upper part of the conductive protrusion can be obtained by changing the amount of UV irradiation on the upper part of the conductive protrusion and the other part. It can be removed with a chemical solution, and the top of the conductive protrusion can be cleaved without polishing or with slight polishing.
Further, when a semiconductor package substrate is manufactured using a metal foil having conductive protrusions on the surface by the method of the present invention, a circuit pattern is formed by selectively etching the sheet-like portion of the metal foil on the surface. Also good. Further, a semiconductor chip may be mounted on a flat portion of the surface having conductive protrusions of the metal foil and embedded in the insulating resin together with the conductive protrusions. Further, a semiconductor package substrate may be formed by further stacking a semiconductor package substrate on the surface or circuit surface of the semiconductor package substrate where the end face of the conductive protrusion is exposed.
[0021]
The semiconductor package of the present invention uses a semiconductor package substrate produced by the method of the present invention. For example, a semiconductor chip is fixed to a surface having a circuit pattern of a substrate for a semiconductor package with a die bond material or the like, and the circuit pattern and the semiconductor chip are bonded by wire bonding, or the semiconductor chip is flip-chip bonded and the circuit pattern and Connecting. Next, a semiconductor package is obtained by sealing the semiconductor chip mounting surface of the semiconductor package substrate with a sealing material.
[0022]
In the method for manufacturing a wiring board with a built-in element of the present invention, after mounting an electronic component on the wiring board, an insulating resin in a fluid varnish state before curing is applied by printing to embed the electronic component, and the printed insulation The resin is cured to form an insulating resin layer, and wiring is provided on the insulating resin layer. As the electronic component, a semiconductor chip, a passive component or the like is used without particular limitation. As the wiring board, various wiring boards including the wiring board obtained by the manufacturing method of the present invention can be used. Further, similarly to the method for manufacturing a wiring board, the insulating resin layer may be a single layer or a multilayer insulating resin layer. Usable resins are the same as those described for the method of manufacturing a wiring board.
For example, first, the insulating resin (1) in a fluid varnish state is printed on the electronic component mounting surface of the wiring board, the fluidity is lost, but it is dried to a semi-cured state before complete curing, Further, the insulating resin (1) has a component different from that of the insulating resin (2) in a fluid varnish state and the insulating resin (2) has a component different from that of the insulating resin (2) and is in a fluid varnish state. Each type of insulating resin is printed in this order, and the fluidity is lost. However, the insulating resin (1) layer, the insulating resin (2 ) And an insulating resin (3) layer are formed to a thickness at which the electronic component is embedded with the insulating resin. Thereafter, a curing process for completely curing all the insulating resins in the multilayer insulating resin layer simultaneously and a process for providing wiring on the multilayer insulating resin layer are performed.
The example of the combination of the insulating resins when forming the multilayer insulating resin layer is the same as that described for the method of manufacturing the wiring board.
[0023]
【Example】
Hereinafter, the present invention will be described more specifically with reference to examples of the present invention and comparative examples thereof, but the present invention is not limited to these examples.
[0024]
Example 1
An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a view showing a cross section in each step of forming a multilayer resin layer on a metal foil having conductive protrusions. FIG. 1A shows a process of forming the metal foil 7 having the conductive protrusion A and the first resin layer 1 having good adhesion. Here, the metal foil 7 having the conductive protrusion A was produced as follows. A three-layer metal foil (manufactured by Nippon Electrolytic Co., Ltd.) consisting of a 70 μm thick copper layer, a 0.2 μm nickel layer, and a 10 μm copper layer, and a photo dry film H-K350 (manufactured by Hitachi Chemical Co., Ltd.) A pattern is used to form a 70 μm copper layer with an alkaline etching solution consisting of an A-process solution (containing 20-30 wt% ammonia copper complex salt, 10-20 wt% ammonium chloride and 1-10 wt% ammonia) manufactured by Meltex. The metal pillar which consists of copper was formed in the surface of the exposed nickel layer by selectively etching. At this time, the metal pillar was a cylinder having a diameter of 250 μm. Next, a portion of the nickel layer other than under the metal pillar was selectively removed with an etching solution made of nitric acid / hydrogen peroxide aqueous solution to form a cylindrical conductive protrusion A having a diameter of 250 μm made of copper and nickel. The exposed surface of the 10 μm copper layer was subjected to chemical phosphorus treatment to improve the adhesion to the resin.
[0025]
For forming the first resin layer 1, KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of silicone-modified polyamideimide resin was used. The above resin having a viscosity of 40 Pa · s in a fluid varnish state was printed with a printing machine VE-500 (manufactured by Toray Engineering Co., Ltd.). Reference numeral 18 denotes a mask, and 17 denotes a squeegee. After printing, the first resin layer 1 was formed by drying at 80 ° C. for 30 minutes to obtain a semi-cured state in which the fluidity was lost. The thickness of the first resin layer 1 after drying (thickness in the horizontal portion; the same applies hereinafter) was 20 μm.
Next, a resin containing 75% inorganic particles (silicon dioxide) in KS6600 was printed on the first resin layer 1 in a fluid varnish state. Similar to the first resin layer 1, it was dried at 80 ° C. for 30 minutes to form a semi-cured second resin layer 2 that lost fluidity (FIG. 1 (b). Thickness of the second resin layer 2 after drying) The thickness was 30 μm.
As shown in FIG. 1C, a fluid varnish KS6600 was printed on the second resin layer 2. After the application, the resin was dried at 80 ° C. for 30 minutes to be semi-cured into a semi-cured state in which the fluidity disappeared to obtain a third resin layer 3. The thickness of the third resin layer 3 after drying was 25 μm.
[0026]
After forming three semi-cured resin layers composed of the first resin layer 1, the second resin layer 2 and the third resin layer 3 on the metal foil 7, as shown in FIG. In order to expose the end face of the protrusion A to the surface of the insulating resin layer, the insulating resin layer was polished with a commercially available abrasive paper while the insulating resin layer was in a semi-cured state. As the polishing time, the surface of the insulating resin layer on the 250 mm × 250 mm metal foil could be polished with # 400 polishing paper at 30 minutes / sheet. In the case where a member obtained by completely curing the insulating resin layer as a comparison was polished, the polishing paper was 60 minutes / sheet.
As shown in FIG. 1 (e), after polishing, the resin layers are heated at 180 ° C. for 30 minutes and at 220 ° C. for 10 minutes to completely cure the three resin layers in a semi-cured state, and cured resin layers 4, 5, It was set to 6.
This member for a semiconductor package after forming the cured resin layer was flat without warping or undulation even after the resin was completely cured. Further, using the obtained member, the surface of the metal foil (the surface opposite to the conductive protrusion) was etched using an A-process solution manufactured by Meltex to form a circuit. Then, the substrate for semiconductor packages was produced by performing electrolytic nickel / gold plating on the circuit surface and the exposed surface of the conductive protrusion. The obtained semiconductor package substrate was also flat. Also, the peel strength between the resin layer and copper was 1.2 kg / cm, which was stronger than the 0.5 kg / cm peel strength between the resin and copper in which inorganic particles were blended at a high ratio (60 wt%).
[0027]
Example 2
FIG. 2 shows a cross-sectional view of the process of this example. Hereinafter, it demonstrates along a process.
The metal foil 7 having the conductive protrusion A in FIG. 2A was produced as follows. A three-layer metal foil (made by Nippon Electrolytic Co., Ltd.) consisting of a 100 μm thick copper layer, a 0.2 μm nickel layer, and a 5 μm copper layer, a photo dry film H-K350 (manufactured by Hitachi Chemical Co., Ltd.) A pattern is used to form a 100 μm copper layer with an alkaline etching solution consisting of an A-process solution (20-30 wt% ammonia copper complex salt, 10-20 wt% ammonium chloride and 1-10 wt% ammonia) manufactured by Meltex. The metal pillar which consists of copper was formed in the surface of the exposed nickel layer by selectively etching. At this time, the metal pillar was a cylinder having a diameter of 250 μm. Next, a portion of the nickel layer other than under the metal pillar was selectively removed with an etching solution made of nitric acid / hydrogen peroxide aqueous solution to form a cylindrical conductive protrusion A having a diameter of 250 μm made of copper and nickel. The exposed surface of the 5 μm copper layer was subjected to chemical phosphorus treatment to improve the adhesion to the resin.
A semiconductor chip 10 having a size of 6.5 × 6.5 mm and a thickness of 0.050 mm is applied to the prepared metal foil 7 having conductive protrusions so that the Al electrode B is in contact with the copper foil surface on which the conductive protrusions A are not formed. The die bonding paste EN-X50N (manufactured by Hitachi Chemical Co., Ltd.) 19 was used for fixing. At this time, the die bonding paste was prevented from adhering to the pad portion of the semiconductor chip.
[0028]
FIG. 2 (b) shows a first semi-cured state using KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamideimide resin and a resin made of this resin and inorganic particles, as in Example 1. After forming an insulating resin layer composed of the resin layer 1, the second resin layer 2, and the third resin layer 3, the resin is polished in a semi-cured state to expose the embedded conductive protrusions. It is sectional drawing when 3 layers of resin is hardened | cured completely. In addition, as for the thickness of each resin layer after drying, the 1st resin layer 1 was 30 micrometers, the 2nd resin layer 2 was 40 micrometers, and the 3rd resin layer 3 was 35 micrometers.
FIG. 2C is a cross-sectional view in which a circuit C is formed by selectively etching a copper layer having a thickness of 5 μm. At that time, the copper foil on the semiconductor chip 10 mounting portion was etched so that only the pad portion of the chip was exposed.
[0029]
FIG. 2 (d) shows a conductive paste dodent (manufactured by Nihon Solder Co., Ltd.) 20 on the Al electrode B portion in order to connect the exposed Al electrode B of the semiconductor chip to the formed circuit C. It is sectional drawing which carried out hole filling printing, and was hardened | cured at 180 degreeC and 30 minutes after that.
In FIG. 2E, a member is prepared in which three semi-cured insulating resin layers are formed on a metal foil having conductive protrusions in the same process as in the first embodiment.
FIG. 2F is a cross-sectional view of the member shown in FIG. 2D and the member shown in FIG. By heating, the resin in the semi-cured member of FIG. 2C is once softened, and by applying pressure, the resin is pushed between the circuits and bonded to the member of FIG. The connection between the layers is made between a conductive protrusion A made of embedded copper and a circuit C formed from a 5 μm copper layer.
[0030]
In the case of FIG. 2 (f), the connection between the layers is in a state where the conductive protrusion A and the circuit C are in contact with each other due to the adhesive force of the surrounding resin. Gold plating is applied to the exposed part of A and the circuit C to improve adhesion, or solder plating is applied to the same part, and the solder is connected by heating to a temperature higher than the solder melting temperature at the time of press connection or after press. A method is conceivable in which a conductive adhesive is applied to the exposed portion of the conductive protrusion A, the connection portion of the circuit C, or both portions, and the adhesive is simultaneously cured during pressing.
FIG. 2 (g) shows a cured resin layer 1 and a cured resin layer 2 obtained by completely curing the insulating resin layer composed of the first resin layer 1, the second resin layer 2 and the third resin layer 3 of the heat-pressed member. And FIG. 3 is a cross-sectional view after a layer made of a cured resin layer 3 is formed.
After curing, electrolytic nickel / gold plating (manufactured by Daiwa Denki Kogyo Co., Ltd.) was performed to produce a semiconductor package substrate in which a semiconductor chip having a cross-sectional structure as shown in FIG.
[0031]
Example 3
FIG. 3 shows a cross-sectional view of the process in which this embodiment was performed. As a base substrate, a double-sided wiring board having a glass epoxy base material 14 as an insulating layer is produced (FIG. 3A), and an LSI element 10 (thickness) having gold bumps 9 at terminals on the wiring 8 of this double-sided wiring board. 50 μm) was mounted, and the gold bumps 9 and the wirings 8 were interconnected by thermocompression bonding (FIG. 3B). In the same manner as in Example 1, the assembly thus produced was used with KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamideimide resin and a resin made of this resin and an inorganic filler. A three-layer insulating resin layer composed of the first resin layer 1, the second resin layer 2, and the third resin layer 3 in a semi-cured state was formed (FIG. 3C). The thickness of each resin layer after drying on the solder resist 12 was 40 μm for the first resin layer 1, 60 μm for the second resin layer 2, and 40 μm for the third resin layer 3. After semi-curing, polishing was performed, and then the resin of the insulating resin layer was completely cured.
After polishing and completely curing to form an insulating resin layer having a flat surface, vias for interlayer connection are opened, a multilayer wiring is formed by an additive method using electroless copper plating, and a solder resist 12 is formed thereon. A wiring pattern 11 was formed (FIG. 3D). Thereafter, an LSI element 10 having gold bumps 9 is mounted on the formed wiring pattern 11, and the gold bumps 9 and the wiring pattern 11 are interconnected by thermocompression bonding, and between the LSI element 10 and the solder resist 12. A liquid epoxy resin (underfill material) 13 was filled and cured to obtain a device built-in type three-dimensional semiconductor package (FIG. 3E).
[0032]
【The invention's effect】
In the present invention, a resin layer having good adhesion can be formed without causing warpage or undulation, particularly when the metal foil, the wiring board member, or the semiconductor package substrate is uneven. In addition, a flat semiconductor package or wiring board can be provided using the member.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a step of forming a resin layer on a metal foil having conductive protrusions by the method of the present invention.
FIG. 2 is a cross-sectional view of a step of forming a resin layer after embedding a semiconductor chip in a metal foil having conductive protrusions by the method of the present invention, and a step of forming a semiconductor chip after embedding the semiconductor chip. .
FIG. 3 is a cross-sectional view of a process in which the method of the present invention is applied to a method for manufacturing a three-dimensional semiconductor package incorporating a plurality of semiconductor chips.
[Explanation of symbols]
1 First resin layer
2 Second resin layer
3 Third resin layer
4 Cured first resin layer
5 Cured second resin layer
6 Cured third resin layer
7 Metal foil with conductive protrusions
A Conductive protrusion
8 Wiring
9 Gold bump
10 Semiconductor chip (LSI element)
B Al electrode
C circuit
11 Wiring pattern formed by additive method
12 Solder resist
13 Underfill material
14 Glass epoxy base material
15 Through-hole plating connection
16 Nickel / Gold plating pad
17 Squeegee
18 mask
19 Die bonding paste
20 Conductive paste

Claims

A printing process in which an insulating resin in a fluid varnish state before curing is applied to a wiring member having a plurality of conductive protrusions on the surface by printing to a thickness in which the conductive protrusions are embedded with the insulating resin, and the printed insulating resin In a method for manufacturing a wiring board, including a curing step of curing the insulating resin and a polishing step of polishing the insulating resin to expose the tips of the conductive protrusions, the surface of the wiring member having the conductive protrusions is in a fluid varnish state. A certain insulating resin 1 is printed and the fluidity is lost, but it is dried to a semi-cured state before being completely cured, and further, the insulating resin 2 is different from the insulating resin 1 and has a fluid varnish state. Insulating resin 2 has a different component and is in a fluid varnish state. At least two types of insulating resins in this order are printed in this order, and the fluidity is lost. Semi-cured Forming a multilayer insulating resin layer comprising at least three layers of an insulating resin 1 layer, an insulating resin 2 layer, and an insulating resin 3 layer to a thickness at which the conductive protrusions are embedded with the insulating resin by drying to a state. A method of manufacturing a wiring board, comprising: a curing step of completely curing all insulating resins in the multilayer insulating resin layer simultaneously; and a polishing step of polishing the multilayer insulating resin layer to expose the tips of the conductive protrusions .

The method for manufacturing a wiring board according to claim 1, wherein the wiring board is a substrate for a semiconductor package.

The method for manufacturing a wiring board according to claim 1 or 2, wherein the wiring member is a metal foil having a plurality of conductive protrusions on the surface.

The method of manufacturing a wiring board according to claim 1 or 2, wherein the wiring member has an insulating resin layer, a conductor layer connected on both sides of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. .

The manufacturing method of the wiring board in any one of Claims 1-4 which performs a grinding | polishing process after a hardening process.

The manufacturing method of the wiring board in any one of Claims 1-4 which performs a hardening process after a grinding | polishing process.

In the step of forming the multilayer insulating resin layer, an insulating resin having good adhesion to the wiring member was used as the insulating resin 1 , and the insulating resin 2 and the second layer including the insulating resin 3 layer were produced. The method for manufacturing a wiring board according to claim 1 or 6 , wherein an insulating resin having a characteristic of reducing warpage of the wiring board is used.

In the step of laminating a resin in a semi-cured state according to claim 1 or 6 , a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is formed by printing at an arbitrary position, shape, and thickness. Then, a method of forming a resin layer in which resins having different properties are mixed in an insulating resin by laminating the resins.

The wiring board manufactured by the method in any one of Claims 1-8 .

The board | substrate for semiconductor packages manufactured by the method in any one of Claims 1-8 .

A semiconductor package using the semiconductor package substrate according to claim 10 .

A method for manufacturing a wiring board with a built-in element, in which an electronic component is mounted on a wiring board, embedded with an insulating resin, an insulating resin layer is formed, and wiring is provided on the insulating resin layer. after mounting, the buried electronic component an insulating resin in a fluidized varnish state before curing is applied by printing, the production method made you form an insulating resin layer to cure the printed insulating resin, the wiring board The insulating resin 1 in a fluid varnish state is printed on the electronic component mounting surface, and the fluidity is lost, but it is dried to a semi-cured state before it is completely cured. Unlike the insulating resin 2 in the fluid varnish state and the insulating resin 2, at least two kinds of insulating resins, that is, the insulating resin 3 in the fluid varnish state, are printed in this order. Sex is gone, but perfect By drying to a semi-cured state before conversion into a semi-cured state, a multilayer insulating resin layer composed of at least three layers of an insulating resin 1 layer, an insulating resin 2 layer, and an insulating resin 3 layer is formed. A method for manufacturing a wiring board, comprising: a step of forming a thickness to be embedded; a curing step of completely curing all insulating resins in the multilayer insulating resin layer simultaneously; and a step of providing wiring on the multilayer insulating resin layer .

The method according to claim 12 , wherein the electronic component is a semiconductor chip, and the wiring board with a built-in element is a semiconductor package with a built-in element.

The method according to claim 12 or 13 , wherein after the step of forming the multilayer insulating resin layer, the curing step is performed after the surface of the multilayer insulating resin layer is polished flat.

In the step of forming the multilayer insulating resin layer, the insulating resin 1 is made of an insulating resin having good adhesion to the wiring board and the electronic component, and the insulating resin 2 layer and the insulating resin 3 layer including the layer of the insulating resin 3 are used. The method of manufacturing a wiring board according to any one of claims 12 to 14 , wherein an insulating resin having a characteristic of reducing warpage of the produced element-embedded wiring board is used.

The step of laminating a resin in a semi-cured state according to any one of claims 12 to 14 , wherein a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is printed at any position, shape, and thickness. And then laminating the resin to form a resin layer in which the resin having different properties is mixed in the insulating resin at an arbitrary location.

Device embedded wiring board manufactured by the method according to any one of claims 12 to 16.

Device embedded semiconductor package produced by the method according to any one of claims 12 to 16.