CN101106094A - Embedded chip package structure and process thereof - Google Patents

Abstract

A process for manufacturing an embedded chip package, comprising: providing a first substrate having a first patterned circuit layer thereon, and disposing a first chip on the first patterned circuit layer and electrically connecting with the first patterned circuit layer. And providing a second substrate with a second patterned circuit layer thereon, and disposing a second chip on the second patterned circuit layer and electrically connecting to the second patterned circuit layer. Then covering a dielectric material on the first patterned circuit layer and the first wafer; then, a pressing step is performed to cover the second substrate on the dielectric material, and the second patterned circuit layer on the second substrate and the second wafer are embedded in the dielectric material.

Description

Embedded chip packaging structure and its manufacturing process

technical field

The present invention relates to a chip packaging structure and its manufacturing process, and in particular to an embedded chip packaging structure and its manufacturing process.

Background technique

In recent years, with the rapid development of electronic technology and the emergence of high-tech electronic industries, electronic products with more humanization and better functions are constantly being introduced, and are designed towards the trend of light, thin, short and small. A circuit substrate is usually arranged in these electronic products, and the circuit substrate is used to carry a single chip or multiple chips as a data processing unit of the electronic product. The chip is embedded in the circuit substrate, which has become the current key technology.

FIG. 1 is a cross-sectional view of a conventional embedded chip package structure. Please refer to FIG. 1 , the embedded chip package structure 30 includes a substrate 300 , a plurality of chips 310 , a dielectric layer 330 , an anti-oxidation layer 360 and a solder resist layer 370 . Wherein, a plurality of chips 310 are located on the substrate 300 , and a dielectric layer 330 is formed on the substrate 300 and covers the plurality of chips 310 . In addition, the bonding pad 320 of each chip 310 is connected to the conductive hole 340 , and the conductive hole 340 is connected to the corresponding conductive plug 350 to form an embedded chip package structure 30 .

It can be seen from the conventional embedded chip packaging structure 30 that the chips 310 are arranged on the same plane. If the number of chips 310 is to be increased, the area of the corresponding substrate 300 must also be increased accordingly. Under such limitations, if the performance of the embedded chip packaging structure is to be improved, the volume of the embedded chip packaging structure must be increased to accommodate more chips, but this does not conform to the current trend of light and compact products. On the contrary, if it is desired to reduce the volume of the embedded chip packaging structure to meet the requirements of the product, more chips cannot be configured, so that the performance of the embedded chip packaging structure is reduced.

Contents of the invention

The purpose of the present invention is to provide an embedded chip packaging structure and its manufacturing process, which can insert a larger number of chips without increasing the area of the embedded chip packaging structure.

In order to achieve the above or other purposes, the present invention proposes an embedded chip packaging process. Firstly, a first substrate is provided, and a first patterned circuit layer is provided on the first substrate. The first patterned circuit layer has at least one The first bonding pad is configured with a first chip on the bonding pad and is electrically connected with the first patterned circuit layer. Next, a second substrate is provided, on which there is a second patterned circuit layer, the second patterned circuit layer has at least one second bonding pad, a second chip is arranged on the second bonding pad and connected to the second The patterned circuit layer is electrically connected. Afterwards, a dielectric material is covered on the first patterned circuit layer and the first wafer. Then a pressing step is performed to cover the second substrate on the dielectric material, and the second patterned circuit layer and the second chip on the second substrate are embedded in the dielectric material.

In an embodiment of the present invention, the method of disposing the first chip on the first patterned circuit layer and the second chip on the second patterned circuit layer is flip-chip bonding.

In an embodiment of the present invention, the above-mentioned dielectric material includes a film, and the film is made of semi-cured resin material.

In an embodiment of the present invention, after the above pressing step, a curing step is further included to cure the dielectric material.

In an embodiment of the present invention, after the above curing step, further includes removing the first substrate and the second substrate.

In an embodiment of the present invention, after removing the first substrate and the second substrate, it further includes forming at least one conductive via hole in the dielectric material, so that the first patterned circuit layer is electrically connected to the second patterned circuit layer. line layer.

In an embodiment of the present invention, wherein the first patterned circuit layer is provided with a first contact corresponding to one end of the conductive via, and the second patterned circuit layer is provided with a second contact corresponding to the other end of the conductive via, And the first contact and the second contact are connected to each other through the conductive through hole.

To achieve the above or other purposes, the present invention further proposes an embedded chip packaging structure, comprising a dielectric material layer, a first patterned circuit layer, a first chip, a second patterned circuit layer and a second wafer. Wherein the first patterned circuit layer is embedded in one side of the dielectric material layer, including at least one first pad and at least one first contact. The first chip is buried in the dielectric material layer and electrically connected with the first welding pad. The second patterned circuit layer is embedded in the other side of the dielectric material layer, and includes at least one second pad and at least one second contact. The second chip is embedded in the dielectric material layer and electrically connected with the second welding pad. In addition, there is at least one conductive through hole in the dielectric material layer, which respectively connects the first contact and the second contact.

In an embodiment of the present invention, the electrical connection between the above-mentioned first chip and the first patterned circuit layer and between the second chip and the second patterned circuit layer is flip-chip bonding.

In an embodiment of the present invention, the material of the above-mentioned dielectric material includes glass epoxy resin, bismaleimide or epoxy resin.

In the present invention, chips are arranged in the embedded chip package structure by adopting a stacked configuration method. Compared with the conventional ones, more chips can be placed in the substrate of the same area, so that the embedded chip package structure Both the reduction in size and the increase in the number of chips can be taken into account, thereby improving the performance of the embedded chip packaging structure.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional embedded chip package structure.

2A to 2E are schematic diagrams of the manufacturing process of the embedded chip package according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of an embedded chip package circuit board according to another embodiment of the present invention.

30, 150: Embedded chip package structure

100: first substrate

102: first adhesive layer

104: the first patterned circuit layer

104a, 204a: Welding pads

104b: first contact

106, 206: bump

108: First Wafer

120: Dielectric material

130: Conductive through hole

140a: first dielectric layer

140b: second dielectric layer

160: Embedded chip package circuit board

170, 172, 174: conductive holes

180: solder ball

200: second substrate

202: Second adhesive layer

204: the second patterned circuit layer

204b: second contact

208: second chip

300: Substrate

310: chip

320: welding pad

330: dielectric layer

340: contact window

350: plug

360: anti-oxidation layer

370: Solder Mask

Detailed ways

2A to 2E are schematic diagrams of the manufacturing process of the embedded chip package according to an embodiment of the present invention. 2A, a first substrate 100 and a second substrate 200 are provided, and the first substrate 100 has a first adhesive layer 102 and a first patterned circuit layer 104, and the second substrate 200 has a second adhesive layer 100. layer 202 and a second patterned wiring layer 204 . Wherein, the first patterned circuit layer 104 is attached to the first adhesive layer 102, and has a plurality of pads 104a and at least one first contact 104b; and the second patterned circuit layer 204 is attached to the second adhesive layer 202, It also has a plurality of welding pads 204a and at least one second contact 204b.

In this embodiment, the adhesive-backed copper foil can be pre-formed on the first and second substrates 100, 200. The adhesive-backed copper foil is composed of a copper foil layer and an adhesive layer, and is made through a pressing step. The copper foil layer is respectively attached to the first substrate 100 and the second substrate 200 through the adhesive layer. A patterning process is then performed to form the first patterned circuit layer 104 and the second patterned circuit layer 204 respectively.

Please continue to refer to FIG. 2B , a first wafer 108 with a plurality of bumps 106 formed thereon is disposed on the first substrate 100 , and each bump 106 is correspondingly connected to a plurality of welding pads on the first patterned circuit layer 104 104 a , electrically connecting the first wafer 108 to the first patterned circuit layer 104 . Similarly, the second chip 208 with a plurality of bumps 206 is also disposed on the second substrate 200, and correspondingly connected to a plurality of pads 204a on the second patterned circuit layer 204, so that the second chip 208 and the second The second patterned circuit layer 204 is electrically connected.

In this embodiment, the first chip 108 is connected to the first substrate 100 using a Flip Chip (F/C) process, which includes bump fabrication, wafer dicing, die bonding, Steps such as reflow, glue filling, and curing are not repeated here. Similarly, the process of disposing the second chip 208 on the second substrate 200 is also the same.

Please continue to refer to FIG. 2C and FIG. 2D , in FIG. 2C , a lamination step is performed, and a dielectric material 120 is first formed on the first patterned circuit layer 104 and the first wafer 108 . Then, the second substrate is covered on the dielectric material and pressed, so that the second patterned circuit layer and the second chip on the second substrate are embedded in the dielectric material. After the above pressing step, the dielectric material 120 can be evenly filled between the first patterned circuit layer 104 and the second patterned circuit layer 204 , as shown in FIG. 2D .

In this embodiment, the method of forming the above-mentioned dielectric material 120 on the surface of the first substrate 100 is to use a resin material in a semi-cured (prepreg) state, which can be gelled through monomer polymerization (polymerization) reaction. To form a film, the dielectric material 400 in this state is compressible and can be attached to the surface of the first wafer carrier 110 .

After performing the above pressing step, this embodiment further includes performing a curing step to completely cure the semi-cured dielectric material 120 into a solid state. In this embodiment, this curing step is a thermal curing method that heats the package structure in FIG. Photocuring method in which light is the light source.

In the above-mentioned curing step, the polymerization reaction (polymerization) between the dielectric materials 120 is used, so that the dielectric materials 120 obtain an energy after being irradiated or heated, which is enough to make the molecules of each dielectric material 120 carry out polymerization (polymerize). ) to crosslink with each other, and then become a cured dielectric material 120 .

Please refer to FIG. 2E , in this embodiment, after forming the package structure as shown in FIG. 2D , subsequent steps may be performed, including removing the first substrate 100, the first adhesive layer 102, and the second substrate 200 by using a lift-off method. and the second adhesive layer 202 . Then a laser is used to penetrate the first contact 104b, and penetrate the dielectric material 120, and then fill in the conductive material to form a conductive via 130 between the first contact 104b and the second contact 204b. The conductive via 130 can electrically connect the first patterned circuit layer 104 and the second patterned circuit layer 204 to form an embedded chip package structure 150 . Then use lamination or build up to connect with other lines to form a complete product.

FIG. 3 is a cross-sectional view of an embedded chip package circuit board 160 according to another embodiment of the present invention. Please refer to FIG. 3 , the embedded chip package circuit board 160 of this embodiment is based on the embedded chip package structure 150 shown in FIG. 2E in the previous embodiment, and is obtained through subsequent processes. Therefore, in the embedded chip package circuit board 160 of this embodiment, the same components as those in the previous embodiment and their relative relationship will not be described again.

Different from the previous embodiments, in this embodiment, after lamination, curing, removal of the substrate and formation of the conductive via 130, etc., the first patterned circuit layer 104 and the second patterned circuit layer 104 and the second patterned A first dielectric layer 140a and a second dielectric layer 140b are respectively formed on the outside of the circuit layer 204 . After that, conductive holes 170 are formed in the first dielectric layer 140a corresponding to the first contacts 104b and solder balls 180 are implanted. In addition to using the conductive via 130 to connect the upper and lower chips 108, 208, a plurality of conductive holes 172, 174 may also be formed in the first dielectric layer 140a and the second dielectric layer 140b to electrically connect the first pad 104a respectively. And the second pad 204a, so that the upper and lower chips 108, 208 can be connected to each other through other circuits (not shown).

From the embedded chip packaging circuit board 160 of this embodiment, it can be seen that the first chip 108 and the second chip 208 are electrically connected through the conductive through hole 130, and the conductive through hole 130 is connected to other components through the conductive hole 170 and the solder ball 180. Electrical system connection. Therefore, compared with the conventional embedded chip package structure 30 , the required number of conductive holes can be significantly reduced, which will help to simplify the manufacturing process.

In this embodiment, the first substrate and the second substrate (not shown above) can be printed circuit substrates (Printed Circuit Substrate, PCS), and in other embodiments, they can also be made of glass, insulating materials and metal materials. constitute. In addition, in this embodiment, the bumps 106 and the solder balls 180 are made of lead-tin alloy, but in other embodiments, they can also be nickel-gold alloy or gold. In addition, in this embodiment, the material of the dielectric material 120 is, for example, glass epoxy resin (FR-4, FR-5), bismaleimide-Triazine (BT) or epoxy resin. Resin (epoxy resin).

In the manufacturing method of the embedded chip package structure of the present invention, the stacking method is used to join the two chip carrier boards in a pressing manner, so that the number of chips in the embedded chip package structure can be increased. In addition, compared with the conventional one, the embedded chip packaging structure of the present invention can have more chips with the same substrate area. Therefore, if the embedded chip packaging structure of the present invention is compared with the conventional one, it can have better performance. In addition, after the embedded chip package circuit board is formed through the subsequent process, the design of the patterned circuit layer can be used to electrically connect with the conductive through hole, thereby reducing the number of conductive holes and simplifying the process.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. modification, so the protection scope of the present invention should be defined by the following claims.

Claims (11)

1. An embedded chip packaging process, characterized in that it comprises: A first substrate is provided, on which there is a first patterned circuit layer, the first patterned circuit layer has at least one first pad, a first chip is arranged on the first pad and connected to the first pad The first patterned circuit layer is electrically connected; A second substrate is provided, and the second substrate has a second patterned circuit layer, and the second patterned circuit layer has at least one second bonding pad, and a second chip is arranged on the second bonding pad and connected to the second bonding pad. the second patterned circuit layer is electrically connected; covering the first patterned circuit layer and the first wafer with a dielectric material; and A pressing step is performed to cover the second substrate on the dielectric material, and the second patterned circuit layer and the second wafer on the second substrate are embedded in the dielectric material. 2. The embedded chip packaging process according to claim 1, wherein the method of disposing the first chip on the first patterned circuit layer and the second chip on the second patterned circuit layer is flip chip join. 3. The embedded chip packaging process according to claim 1, wherein the dielectric material comprises a film, and the film is formed by gelling a semi-cured resin material. 4. The embedded chip packaging process according to claim 1, further comprising a curing step to cure the dielectric material after the pressing step. 5. The embedded chip packaging process according to claim 4, further comprising removing the first substrate and the second substrate after the curing step. 6. The embedded chip packaging process according to claim 5, further comprising forming at least one conductive via in the dielectric material after removing the first substrate and the second substrate, so that the first A patterned circuit layer is electrically connected to the second patterned circuit layer. 7. The embedded chip packaging process according to claim 6, wherein a first contact is disposed on one end of the first patterned circuit layer corresponding to the conductive via, and the second patterned circuit layer corresponds to the A second contact is arranged at the other end of the conductive through hole, and the first contact and the second contact are connected to each other through the conductive through hole. 8. The embedded chip packaging process according to claim 6, further comprising: after removing the first substrate and the second substrate: forming a first dielectric layer on the first patterned circuit layer; forming at least one first conductive hole in the first dielectric layer and electrically connecting the first pad; forming a second dielectric layer on the second patterned circuit layer; and At least one second conductive hole is formed in the second dielectric layer and electrically connected to the second welding pad. 9. An embedded chip packaging structure, characterized in that it comprises: a layer of dielectric material; A first patterned circuit layer, embedded in one side of the dielectric material layer, including at least one first pad and at least one first contact; a first chip embedded in the dielectric material layer and electrically connected to the first pad; a second patterned circuit layer embedded in the other side of the dielectric material layer, including at least one second pad and at least one second contact; and A second chip is embedded in the dielectric material layer and electrically connected to the second pad, wherein the dielectric material layer has at least one conductive through hole, and the conductive through hole is respectively connected to the first contact and the second contact. 10. The embedded chip package structure according to claim 9, characterized in that the first chip is electrically connected to the first patterned circuit layer and the second chip is electrically connected to the second patterned circuit layer For flip chip bonding. 11. The embedded chip package structure according to claim 9, wherein the material of the dielectric material layer comprises glass epoxy resin, bismaleimide or epoxy resin.

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