JP4252563B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4252563B2 JP4252563B2 JP2005195940A JP2005195940A JP4252563B2 JP 4252563 B2 JP4252563 B2 JP 4252563B2 JP 2005195940 A JP2005195940 A JP 2005195940A JP 2005195940 A JP2005195940 A JP 2005195940A JP 4252563 B2 JP4252563 B2 JP 4252563B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 238000007789 sealing Methods 0.000 claims description 37
- 230000005540 biological transmission Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 description 18
- 239000011347 resin Substances 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000007767 bonding agent Substances 0.000 description 7
- 238000000926 separation method Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052863 mullite Inorganic materials 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 241000272168 Laridae Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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Description
こうした底面端子型の半導体装置については、下記特許文献に開示されている。
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。
タブの露出部分を接地電源用外部端子として用いるため、リードを外部端子として用いていた従来の半導体装置と比較して、伝送経路が短縮され、その断面積が増加するため、低インダクタンス・低インピーダンス化を図ることが可能となる。なお、従来の半導体装置にも、半導体チップを搭載するタブを封止体から露出させているものがあるが、それらの半導体装置ではタブを放熱板としても利用しているに過ぎず、単に放熱性を考慮しているに留まり、高周波特性の点は考慮されていない。
(1)本発明によれば、伝送経路が短縮され、その断面積が増加するため、接地伝送経路の低インダクタンス・低抵抗化を図ることが可能となるという効果がある。
(2)本発明によれば、ボンディングワイヤの短縮によって低インピーダンス化を図ることが可能となるという効果がある。
(3)本発明によれば、上記効果(1)(2)により、アイソレーション特性が向上するという効果がある。
(4)本発明によれば、上記効果(2)(1)により、RF特性が格段に向上するという効果がある。
なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
図1は本発明の一実施の形態であるQFP型半導体装置を封止体を透過して示す平面図であり、図1中のa‐a線に沿った縦断面図を基板実装状態として図2に示してある。
図7は本発明の他の実施の形態であるQFN型半導体装置を封止体を透過して示す平面図であり、図7中のa‐a線に沿った縦断面図を基板実装状態として図8に示してある。
Claims (1)
- タブと、
前記タブの上面に搭載された半導体チップと、
前記タブの周囲に配置された複数のリードと、
前記半導体チップの複数のパッドと前記複数のリードの各々の上面とを電気的に接続する複数のボンディングワイヤと、
前記タブ、前記半導体チップ、前記複数のリード、及び前記複数のボンディングワイヤを封止する封止体とを有し、
前記複数のリードは、前記ボンディングワイヤが接続される前記上面とは反対側の底面が前記封止体の底面から露出して外部端子となる半導体装置において、
前記複数のリードは、前記タブに接続一体化され、前記半導体チップの前記複数のパッドの中の接地電源用パッドと電気的に接続された接地電源用リードを含み、
前記タブの前記上面とは反対側の底面は、前記封止体の前記底面から露出して接地電源用外部端子となり、
前記接地電源用リードは、前記接地電源用リードの前記底面側であって、前記ボンディングワイヤが接続される部分と前記タブとの間が部分的にエッチングされた構造になっていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005195940A JP4252563B2 (ja) | 2005-07-05 | 2005-07-05 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005195940A JP4252563B2 (ja) | 2005-07-05 | 2005-07-05 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000296380A Division JP2002110889A (ja) | 2000-09-28 | 2000-09-28 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005294871A JP2005294871A (ja) | 2005-10-20 |
JP4252563B2 true JP4252563B2 (ja) | 2009-04-08 |
Family
ID=35327379
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005195940A Expired - Fee Related JP4252563B2 (ja) | 2005-07-05 | 2005-07-05 | 半導体装置 |
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JP (1) | JP4252563B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5173654B2 (ja) * | 2007-08-06 | 2013-04-03 | セイコーインスツル株式会社 | 半導体装置 |
KR100939153B1 (ko) | 2007-12-11 | 2010-01-28 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US8093707B2 (en) * | 2009-10-19 | 2012-01-10 | National Semiconductor Corporation | Leadframe packages having enhanced ground-bond reliability |
JP5616839B2 (ja) * | 2011-04-19 | 2014-10-29 | 株式会社豊田中央研究所 | 高周波装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05291483A (ja) * | 1992-04-10 | 1993-11-05 | Toshiba Corp | 半導体装置 |
JP3947292B2 (ja) * | 1998-02-10 | 2007-07-18 | 大日本印刷株式会社 | 樹脂封止型半導体装置の製造方法 |
JPH1174404A (ja) * | 1997-08-28 | 1999-03-16 | Nec Corp | ボールグリッドアレイ型半導体装置 |
JP3458057B2 (ja) * | 1998-03-12 | 2003-10-20 | 松下電器産業株式会社 | 樹脂封止型半導体装置 |
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- 2005-07-05 JP JP2005195940A patent/JP4252563B2/ja not_active Expired - Fee Related
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JP2005294871A (ja) | 2005-10-20 |
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