JP4235092B2 - 配線基板およびこれを用いた半導体装置 - Google Patents
配線基板およびこれを用いた半導体装置 Download PDFInfo
- Publication number
- JP4235092B2 JP4235092B2 JP2003397309A JP2003397309A JP4235092B2 JP 4235092 B2 JP4235092 B2 JP 4235092B2 JP 2003397309 A JP2003397309 A JP 2003397309A JP 2003397309 A JP2003397309 A JP 2003397309A JP 4235092 B2 JP4235092 B2 JP 4235092B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- conductor layer
- insulating
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structure Of Printed Boards (AREA)
Description
1b:絶縁層
2a:第1の導体層
2b:第2の導体層
2c:第3の導体層
2d:第4の導体層
3:半導体素子
G1:導体層2a,2b間の間隙
G2:導体層2c,2d間の間隙
Claims (2)
- 複数の絶縁層が積層されて成り、半導体素子が搭載される搭載部を有する絶縁基板と、前記絶縁基板内に形成された信号用配線導体と、前記絶縁層の第1の層間にて、第1間隙を介して隣接する、第1導体層及び第2導体層と、前記第1の層間とは異なる前記絶縁層の第2の層間にて、第2間隙を介して隣接する、前記第1導体層に電気的に接続された第3導体層及び前記第2導体層に電気的に接続された第4導体層と、を具備しており、
第1導体層及び第2導体層は、接地用又は電源用であり、
前記第1導体層乃至前記第4導体層は、前記絶縁層を介して前記信号用配線導体と対向しており、
前記第1間隙及び前記第2間隙に、前記絶縁層の一部が充填されており、
前記第1間隙は、前記第1導体層を取り囲むように、環状に形成されており、
前記第2間隙は、前記第3導体層を取り囲むように、環状に形成されており、
前記第2間隙は、平面視にて、前記第1間隙と離間しつつ、前記第1間隙を取り囲んでいることを特徴とする配線基板。 - 請求項1記載の配線基板と、前記配線基板の前記搭載部に搭載されている前記半導体素子と、を具備することを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003397309A JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003397309A JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005159133A JP2005159133A (ja) | 2005-06-16 |
JP4235092B2 true JP4235092B2 (ja) | 2009-03-04 |
Family
ID=34722495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003397309A Expired - Fee Related JP4235092B2 (ja) | 2003-11-27 | 2003-11-27 | 配線基板およびこれを用いた半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4235092B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009239137A (ja) * | 2008-03-28 | 2009-10-15 | Toppan Printing Co Ltd | 配線基板 |
JP5696549B2 (ja) | 2011-03-22 | 2015-04-08 | 富士通セミコンダクター株式会社 | 配線基板 |
JP6418864B2 (ja) * | 2014-09-18 | 2018-11-07 | 日立オートモティブシステムズ株式会社 | 電子制御装置 |
JP6626781B2 (ja) * | 2016-05-27 | 2019-12-25 | 京セラ株式会社 | 配線基板 |
-
2003
- 2003-11-27 JP JP2003397309A patent/JP4235092B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
---|---|
JP2005159133A (ja) | 2005-06-16 |
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