JP4232222B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, an organic antireflection film is formed on a resist underlayer to pattern a conductor layer, and the organic antireflection film is not damaged without damaging the base film of the organic antireflection film. The present invention relates to a method for manufacturing a semiconductor device capable of removing a protective film.
[0002]
[Prior art]
With the high integration of semiconductor devices, the minimum processing dimension is miniaturized, and the light source used for the photolithography technology is from g-line (436 nm) of mercury lamp, i-line (365 nm), KrF excimer laser (248 nm), and ArF. Shortening of wavelength is progressing to excimer laser (193 nm). In contrast to conventional photolithography using a mercury lamp as a light source, photolithography using a light source with a shorter wavelength is generically referred to as DUV (Deep UV) lithography.
[0003]
In photolithography using g-line or i-line, the reflectivity of polysilicon, various silicides, oxide films or nitride films is low, and reflection from these layers usually does not cause a problem. Therefore, in photolithography using g-line or i-line, only reflection from a metal wiring layer such as Al, which has a high reflectance even in the visible light region, becomes a problem.
However, in the wavelength region of DUV lithography, the reflectivity increases in almost all layers such as polysilicon, various silicides, oxide films or nitride films, which causes deterioration of the pattern. Therefore, reflection from layers other than the metal wiring layer such as Al is also a problem.
[0004]
Further, the resist for DUV itself is susceptible to the influence of the base (for example, halation from the base step). When patterning using resist as a mask, if there is a step in the underlying shape, the notch (positive type resist) or bridge (negative type resist) is locally generated in the resist due to reflection from the stepped portion, and the pattern deteriorates. It becomes easy to do.
Further, when the film thickness and the wavelength of the light source are close to each other, the standing wave effect (multiple interference effect) becomes conspicuous due to the multiple reflection at the interface of the base film, and the resist size varies to reduce the exposure margin. This makes it impossible to perform good patterning using a resist as a mask.
[0005]
In miniaturizing a semiconductor device, the problem as described above is solved, and a stable pattern without dimensional variation is formed. Therefore, the importance of the antireflection technology is increasing.
As a method for preventing light reflection, there is a method of forming an antireflection film on an upper layer or a lower layer of a resist. A method of forming an antireflection film on the upper layer of the resist (ARCOR: anti-reflecting coating on resist, or TAR; top anti-reflector) is effective for suppressing the standing wave effect, but for reducing the halation from the base step portion. Almost no effect. On the other hand, a method of forming an antireflection film below the resist (BARC: bottomant-reflective coating) is effective for both the suppression of the standing wave effect and the reduction of halation from the base, and is widely used.
[0006]
There are both inorganic and organic antireflection films formed under the resist, and these film materials are applied or vacuum-formed (sputtering or CVD; chemical vapor deposition) on the substrate before applying the resist. An antireflection film is formed. Thereafter, a resist is applied to the upper layer of the antireflection film.
As the inorganic antireflection film, there are amorphous carbon, titanium nitride (TiN) film, silicon oxynitride (SiON) film, and the like. However, it is necessary to form the film by dry rather than coating, and the film formation cost is generally high. Further, the inorganic antireflection film is not removed by the ashing process, and it is necessary to perform wet etching to remove it.
[0007]
A variety of materials have been developed as an organic coating film for antireflection. These organic coating films have the following two functions for incident light. One is that the organic antireflection film itself absorbs and weakens light. Another function is to attenuate light by causing interference between the light reflected by the surface of the organic antireflection film and the light reflected by the base film of the organic antireflection film so as to cancel each other.
At present, the most commonly used resist for KrF excimer laser is a chemically amplified positive resist. When the above-mentioned organic antireflection film is formed under this type of resist, light reflection is effectively prevented. Is done.
[0008]
A process of forming an organic antireflection film and patterning the gate electrode will be described below with reference to FIGS.
First, as shown in FIG. 18, a gate oxide film 22 and a polysilicon layer 23 are stacked on a Si substrate 21, and an organic antireflection film 24 is applied thereon. A resist 25 is applied to the upper layer, and the resist 25 is patterned.
Next, as shown in FIG. 19, the organic antireflection film 24 other than the gate electrode is removed by, for example, ECR etching. Prior to DUV, organic antireflective coatings for g and i rays could be removed by dissolving them in a developer. However, organic antireflective coatings for DUV are often made of materials that can be removed by dry etching. .
[0009]
Subsequently, as shown in FIG. 20, the polysilicon layer 23 is anisotropically etched using the resist 25 as a mask to process the polysilicon layer 23 into a predetermined gate pattern.
Thereafter, as shown in FIG. 21, the resist 25 is removed by an ashing process using oxygen plasma. Further, the organic antireflection film 24 is removed by dry etching. Thereby, a gate electrode is formed as shown in FIG.
[0010]
[Problems to be solved by the invention]
In the above-described conventional method for manufacturing a semiconductor device, the organic antireflection film used in the DUV lithography technique cannot usually be removed with a developer at the time of resist patterning. Therefore, in addition to the resist patterning step shown in FIG. 18, a step of etching the organic antireflection film 24 as shown in FIG. 19 is required. The organic antireflection film is etched by plasma generated by supplying oxygen gas, but the etching gas is chlorine for the purpose of protecting the resist sidewall (controlling and adjusting the high reactivity of oxygen plasma). Gas is also added.
This causes a phenomenon that the polysilicon layer under the organic antireflection film is eroded by Cl radicals and Cl ions generated from chlorine gas in the plasma. In particular, in the region where the line / space interval is close, the erosion of the base film due to Cl radicals and Cl ions as described above becomes significant.
[0011]
As shown in FIG. 19, when the polysilicon layer 23 to be the gate electrode is damaged in the etching process for removing the organic antireflection film 24 thereabove, and a notch (recess) 26 is formed on the surface, FIG. In the step of etching the polysilicon layer 23 shown, the etching rate of the notch portion 26 is increased as compared with the surrounding area. Therefore, as shown in FIG. 21, the gate oxide film 22 is excessively etched at the notch portion of the polysilicon layer 23 (notch 27 in FIG. 21).
[0012]
In order to prevent excessive etching of the organic antireflection film into the lower layer as described above, a method for removing the organic antireflection film that does not affect the underlying film is desired.
As a method for removing the organic antireflection film, for example, in Japanese Patent Application Laid-Open No. 8-153704, the resist is used as a mask to etch the organic antireflection film under the resist and the conductive film or insulating film provided thereunder. A method of performing is disclosed. Prior to JP-A-8-153704, Chris A. et al. A method of performing RIE of an organic antireflection film using gas plasma based on oxygen gas has been disclosed by Mack et al. (J. Vac Sci Tech B9 (6), 3143 (1991)).
[0013]
According to the method of Chris et al. Mainly using oxygen gas, the reactivity of oxygen radicals generated from oxygen gas to the organic antireflective film and the resist is extremely high, so the side walls of the organic antireflective film and resist are also etched. There was a problem of being. According to this method, since the pattern of the resist and the organic antireflection film becomes thinner at the time of completion of etching as compared with the time of forming the resist pattern (that is, the time of starting etching), a desired pattern cannot be obtained and the semiconductor device is manufactured. It was difficult to apply to.
[0014]
In contrast to the problem that the pattern of the resist and the organic antireflection film in the method of Chris et al. Is etched in the lateral direction, the method described in JP-A-8-153704 is reactive to the organic antireflection film and the resist. However, by using a gas lower than oxygen gas, pattern thinning is suppressed.
According to the method described in JP-A-8-153704, nitrogen gas, a mixed gas obtained by adding a small amount of oxygen gas to nitrogen gas, or carbon dioxide gas is used as an etching gas to be converted into plasma. As a result, nitrogen radicals having a lower reactivity than oxygen radicals act on the pattern side walls of the organic antireflection film, so that excessive etching does not occur.
[0015]
On the other hand, in the gas plasma, an ion sheath is formed by the self-bias voltage, so that ions in the vicinity of the film surface are accelerated. Therefore, ions in the gas plasma have a property of being incident perpendicular to the film surface. Thereby, in the vertical direction (film thickness direction) of the organic antireflection film, an ion-assisted etching reaction in which ions and radicals act in a complementary and synergistic manner proceeds, and lateral etching is suppressed.
[0016]
The method described in Japanese Patent Laid-Open No. 8-153704 can be applied to the case where the base film of the organic antireflection film is either a conductive film or an insulating film. And alloys are also included.
An example in which an insulating film (silicon oxide film) such as TEOS is provided under the organic antireflection film by the method described in Japanese Patent Application Laid-Open No. 8-153704 is shown in FIGS.
[0017]
As shown in FIG. 22, an oxide film 32 having a LOCOS step is formed on a Si substrate 31, and a conductive layer 33 and a second oxide film 34 are stacked thereon. Since the organic antireflection film 35 is formed in the lower layer of the resist 36, the pattern collapse due to reflection from the step surface of the lower layer is suppressed when the resist 36 is patterned.
When the resist 36 and the organic antireflection film 35 are removed after the conductive layer 33 is subjected to predetermined patterning using the resist 36 as a mask, the structure shown in FIG. 23 is obtained.
[0018]
The method described in JP-A-8-153704 is effective for suppressing etching of the pattern side wall portion of the organic antireflection film. However, the polysilicon layer under the organic antireflection film described above is effective. An effective solution to the problem of erosion is not shown.
In the method described in Japanese Patent Laid-Open No. 8-153704, there is no feature in the selection of the base film of the organic antireflection film, and the etching method of the present invention is applied in accordance with the structure of the semiconductor device to be manufactured. Has been. Even when an insulating film is formed as a base film of the organic antireflection film, the insulating film forms a part of the semiconductor device such as an interlayer insulating film on which a contact is formed.
Therefore, after patterning the conductive film and the like, films other than the resist and the organic antireflection film are not removed.
[0019]
The present invention has been made in view of the above problems. Therefore, the present invention forms an organic antireflection film under the resist and performs patterning, and then damages the underlying film of the organic antireflection film. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which an organic antireflection film can be removed without giving.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention includes a step of forming a conductor layer on a semiconductor substrate, and a step of forming a conductor layer on the conductor layer. Made of silicon nitride film A step of forming an etching stopper layer, a step of forming an organic antireflection film on the etching stopper layer, a step of forming a resist of a predetermined pattern on the organic antireflection film, and the resist The method includes a step of etching and removing the organic antireflection film as a mask, and a step of etching and removing the etching stopper layer and the conductor layer using the resist as a mask.
In the method of manufacturing a semiconductor device according to the present invention, preferably, the conductor layer is made of polysilicon. Alternatively, the semiconductor device manufacturing method of the present invention is preferably characterized in that the conductor layer is made of amorphous silicon.
[0021]
Accordingly, in the step of etching the organic antireflection film using the resist as a mask, it is possible to prevent the conductor layer under the organic antireflection film from being etched and damage such as notches from occurring. Therefore, it is possible to prevent further damage from occurring in the gate oxide film or the substrate formed in the lower layer of the conductor layer due to the damage generated in the conductor layer.
[0022]
In the method of manufacturing a semiconductor device according to the present invention, preferably, the etching stopper layer is made of a silicon oxide film. More preferably, in the method of manufacturing a semiconductor device of the present invention, the step of forming the silicon oxide film is a step of cleaning the surface of the conductor layer using a solution containing hydrogen peroxide. And Alternatively, in the semiconductor device manufacturing method of the present invention, it is more preferable that the step of forming the silicon oxide film is a step of oxidizing the surface of the conductor layer using oxygen plasma.
[0023]
The manufacturing method of the semiconductor device of the present invention is as follows. Good Suitably, the etching stopper layer is formed thin with a thickness within a range that can be removed under the same etching conditions as the conductor layer. In the semiconductor device manufacturing method of the present invention, more preferably, the thickness of the etching stopper layer is 3 nm or less.
Accordingly, an etching stopper layer that can be easily removed can be formed in the step of patterning the conductor layer, and an increase in the number of steps can be suppressed.
[0024]
In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of etching the organic antireflection film is a step of etching the organic antireflection film by converting a mixed gas of oxygen gas and chlorine gas into plasma. It is characterized by being.
Alternatively, in the method of manufacturing a semiconductor device according to the present invention, preferably, the step of etching the organic antireflection film comprises etching the organic antireflection film by converting a mixed gas of oxygen gas and nitrogen gas into plasma. It is a process.
As a result, the concentration of oxygen plasma having extremely high reactivity with respect to the organic antireflection film and the resist can be adjusted, and the phenomenon that the pattern side wall is excessively etched mainly by oxygen plasma can be suppressed. Therefore, even when the semiconductor device is miniaturized, a desired pattern can be formed on the conductor layer or the like.
[0025]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film on a semiconductor substrate, a step of forming a conductor layer on the gate insulating film, and the conductor On the layer Made of silicon nitride film Forming an etching stopper layer; forming an organic antireflection film on the etching stopper layer; forming a resist having a predetermined pattern on the organic antireflection film; and using the resist as a mask Etching and removing the organic antireflection film, etching and removing the etching stopper layer and the conductor layer by using the resist as a mask, and forming a gate electrode of a field effect transistor on the surface of the semiconductor substrate And a step of forming source / drain regions at a predetermined interval.
As a result, it is possible to prevent the conductor layer from being damaged in the step of etching away the organic antireflection film, and to form the gate electrode of the field effect transistor with good characteristics by patterning the conductor layer without damage. can do.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view of a semiconductor device that has been patterned by the semiconductor device manufacturing method of this embodiment. A gate oxide film 2 is formed on the Si substrate 1, and a patterned conductive film 3 and insulating film 4 are stacked thereon. The gate oxide film 2 and the Si substrate 1 are not damaged such as notches.
[0027]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 2, pyrogenic oxidation (H ₂ / O ₂ 850 ° C.), the gate oxide film 2 is formed with a film thickness of, for example, 3.8 nm. On the upper layer, a polysilicon layer 3 is formed with a film thickness of, for example, 250 nm by, eg, CVD.
Further, an insulating film 4 to be an etching stopper layer is formed. As the insulating film 4, the surface of the polysilicon layer 3 is made of hydrochloric acid / hydrogen peroxide (HCl / H ₂ O ₂ ) A chemical oxide film (silicon oxide film) having a thickness of, for example, about 1 nm formed by washing with a mixed solution can be used.
A chemical oxide film is less dense than a thermal oxide film. Therefore, it can be easily removed in the step of etching away the polysilicon layer 3 described later.
[0028]
An organic antireflection film 5 is applied on the insulating film 4 so as to have a film thickness of 70 nm by, for example, spin coating. The organic antireflection film 5 is formed by coating the resin in a state containing a solvent, followed by baking to crosslink the resin. In this embodiment, for example, a resin (AR2; manufactured by Shipley Co., Ltd.) mainly composed of an acrylic polymer and a substituted glycol / uril resin is applied as the organic antireflection film 5, and propylene glycol monomethyl ether is used as the solvent.
A resist 6 is deposited on the organic antireflection film 5 to a thickness of, for example, 720 nm, and the resist 6 is patterned.
[0029]
As the resist 6, a chemically amplified positive resist most widely used in the DUV lithography technology (particularly for KrF excimer laser) can be suitably used. The positive type resist is a resist in which a reaction occurs using an acid generated by light as a catalyst, and the exposed resin is soluble in an alkaline aqueous solution as a developer to form a pattern. Positive resists are broadly classified into two-component resists that utilize the removal of protecting groups for insolubilization and three-component resists that utilize a reaction that eliminates the effects of dissolution inhibiting components.
[0030]
Examples of the two-component positive resist include a resin in which polyvinyl phenol is used as a main chain and the hydroxyl group of phenol is protected by a t-BOC group (t-butoxycarbonyloxy group). When the t-BOC group which is a protecting group is eliminated by addition of an acid, the resin becomes soluble in the developer.
Three-component positive resists are mixed with dissolution inhibitors such as naphthalene-t-butylcarboxylate, naphthyl-t-butyl carbonate, and biphenyl-t-butyl ether in the resin, and these dissolution inhibitors are decomposed. Then, the resin becomes soluble in the developer.
[0031]
A material that generates an acid by light, such as an onium salt, is added to the above-described two-component or three-component positive resist.
Further, as the resist 6, it is also possible to use a chemically amplified negative resist in which a pattern is formed by the cross-linking reaction of the resin at the exposed portion, instead of the chemical amplified positive type.
[0032]
After patterning of the resist 6, as shown in FIG. ₂ / O ₂ The organic antireflection film 5 is removed by ECR etching using a gas. By etching the organic antireflection film 5 under conditions where the insulating film (chemical oxide) 4 is not etched away, the polysilicon layer 3 under the insulating film 4 is protected from etching.
[0033]
Subsequently, anisotropic etching is performed on the polysilicon layer 3 using the resist 6 as a mask to form a gate electrode pattern. As a result, the structure shown in FIG. 5 is obtained after the structure shown in FIG.
Since the insulating film 4 is a thin film of about 1 nm and is a chemical oxide film having a low film density, it can be removed during a breakthrough in this etching process. Therefore, even when an etching stopper layer (insulating film 4) is provided, an increase in the number of manufacturing steps can be suppressed.
[0034]
Etching of the insulating film 4 and the polysilicon layer 3 is, for example, ECR etching, and during breakthrough, Cl ₂ Etching is performed under the condition of = 120 sccm. Etching conditions in the process of etching the polysilicon layer (main etching) after removing the insulating film 4 are, for example, Cl ₂ : HBr: O ₂ = 30: 80: 5. Overetching conditions are Cl ₂ : HBr: O ₂ = 90: 20: 10.
Thereafter, an ashing process is performed using oxygen plasma, and the resist 6 and the organic antireflection film 5 on the gate electrode are removed. As a result, the structure shown in FIG. 1 is obtained.
[0035]
According to the manufacturing method of the semiconductor device of the present embodiment, since the insulating film 4 is formed as the etching stopper layer when the polysilicon layer 3 is patterned, the polysilicon layer 3 is damaged such as notches. It can be prevented from occurring. Therefore, the gate oxide film 2 under the polysilicon layer 3 is not excessively etched, and the reliability of the semiconductor device can be improved.
[0036]
(Embodiment 2)
FIG. 6 is a cross-sectional view of a gate electrode portion of an n-channel field effect transistor (NMOS) formed by the semiconductor device manufacturing method of this embodiment.
A gate oxide film 2 is formed on a Si substrate 1, and a patterned conductive film (polysilicon layer) 3 is laminated thereon. An LDD sidewall 10 is formed on the side wall of the gate electrode, and an LDD 8 is formed on the Si substrate below the LDD sidewall 10. A source / drain region 11 containing impurities at a concentration higher than that of LDD 8 is formed in connection with LDD 8. A titanium silicide layer 13 is formed on the surfaces of the source / drain regions 11 and the polysilicon layer (gate electrode) 3 for the purpose of reducing resistance.
[0037]
As in the first embodiment (FIG. 1), the gate oxide film 2 and the Si substrate 1 of the semiconductor device shown in FIG.
In the first embodiment, the etching stopper layer is formed by cleaning with hydrochloric acid / hydrogen peroxide solution. However, as shown in the present embodiment, the etching stopper layer is formed by removing the resist when removing the resist. ₂ It can also be done by ashing.
[0038]
A method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
First, as shown in FIG. 7, pyrogenic oxidation (H ₂ / O ₂ 850 ° C.), the gate oxide film 2 is formed with a film thickness of, for example, 3.8 nm. On the upper layer, a polysilicon layer 3 is formed with a film thickness of, for example, 250 nm by, eg, CVD.
Thereafter, in order to introduce an n-type impurity into the element formation region, a resist 7 covering the element isolation region is formed. Using the resist 7 as a mask, for example, phosphorus (P) as an n-type impurity has an ion energy of 15 keV and an introduction amount of 5 × 10 ¹⁵ / Cm ² Ions are implanted into the Si substrate 1 under the following conditions.
[0039]
Next, the resist 7 which is an n-type impurity ion implantation mask is removed by an ashing process using oxygen plasma. In this ashing process, as shown in FIG. 8, an insulating film (SiO 2 having a thickness of about 1 nm is formed on the polysilicon layer 3. _x Film) 4 is formed.
Subsequently, as shown in FIG. 9, an organic antireflection film 5 is applied to the upper layer of the insulating film 4 with a film thickness of 70 nm by, for example, spin coating. The organic antireflection film 5 is formed by coating the resin in a state containing a solvent, followed by baking to crosslink the resin. In this embodiment, for example, a resin (AR2; manufactured by Shipley Co., Ltd.) mainly composed of an acrylic polymer and a substituted glycol / uril resin is applied as the organic antireflection film 5, and propylene glycol monomethyl ether is used as the solvent.
[0040]
Further, after a resist 6 is deposited on the organic antireflection film 5 with a film thickness of, for example, 720 nm, the resist 6 is patterned so that the gate electrode portion remains as shown in FIG.
Here, the organic antireflection film 5 used in the DUV lithography technique is not removed by development at the time of resist patterning, unlike the organic antireflection film for g-line and i-line, and has a structure as shown in FIG. Become.
[0041]
Next, as shown in FIG. 10, the organic antireflection film 5 in portions other than the gate electrode is removed by, for example, ECR etching. Etching conditions are, for example, Cl ₂ / O ₂ = 40/20 sccm. In the etching process of the organic antireflection film 5, since the insulating film 4 is formed in the lower layer, the polysilicon layer 3 is protected from etching.
Subsequently, by performing anisotropic etching on the polysilicon layer 3 using the resist 6 as a mask, a gate electrode is formed as shown in FIG. This etching can be performed under the same conditions as in the first embodiment. Further, since the insulating film 4 is a thin film of about 1 nm, it is removed at the time of breakthrough in this etching process.
[0042]
Next, as shown in FIG. 12, after removing the resist 6 and the organic antireflection film 5 by an ashing process using oxygen plasma, an n-type LDD 8 is formed in the NMOS formation region. The LDD 8 uses a resist (not shown) as a mask and an n-type impurity such as arsenic (As) with an ion energy of 20 keV and an introduction amount of 5 × 10. ¹³ / Cm ² It is formed by ion implantation under the conditions of
[0043]
In order to form the LDD sidewall 10 on the gate electrode, a silicon nitride film (SiN) is formed on the entire surface as shown in FIG. _x A film 9 is deposited with a film thickness of 200 nm by, for example, a low pressure CVD method. Thereafter, as shown in FIG. 14, RIE is performed so that the silicon nitride film 9 remains only on the side surface of the gate electrode, thereby forming the LDD sidewall 10.
Further, as shown in FIG. 15, source / drain regions 11 are formed in a self-aligned manner by ion-implanting n-type impurities using the LDD sidewall 10 as a mask. In the source / drain region 11, for example, arsenic (As) has an ion energy of 20 keV and an introduction amount of 3 × 10 6. ¹⁵ / Cm ² Ion implantation is performed under the following conditions.
[0044]
Next, as shown in FIG. 16, as a refractory metal layer, for example, a titanium layer 12 is formed on the entire surface by sputtering.
Subsequently, heat treatment (for example, RTA for 30 seconds at 650 ° C .; rapid thermal annealing) is performed. As a result, as shown in FIG. 17, the titanium layer 12 on the source / drain region 11 and the polysilicon layer 3 of the gate electrode is silicided to form a titanium silicide layer 13.
[0045]
Then, sulfuric acid / hydrogen peroxide solution (H ₂ SO _Four / H ₂ O ₂ ) The field oxide film (not shown) and the unreacted titanium layer 12 on the surface of the LDD sidewall 10 are removed by the treatment. As a result, the structure shown in FIG. 6 is obtained.
Further, a second RTA (for example, 800 ° C., 30 seconds) is performed to reduce the resistance of the titanium silicide layer 13. In the first RTA process (650 ° C., 30 seconds) shown in FIG. 17, first, a silicidation reaction takes place at the metal-silicon interface. _Five Si _Three The composition contains. When the second RTA process at a higher temperature is performed, the silicide shifts to a phase called a final phase, and TiSi ₂ The composition is close to that of low resistance.
[0046]
Subsequently, an interlayer insulating film covering the entire surface is formed, and a contact hole is formed in the interlayer insulating film. A wiring material such as Al is buried in the contact hole, and wiring of the gate electrode, source region, and drain region is performed to form a MOS circuit. Further, a p-channel MOS transistor (PMOS) may be formed adjacent to the NMOS transistor having the above-described configuration to form a CMOS.
[0047]
According to the method of manufacturing a semiconductor device of the present embodiment, as shown in FIG. 7, since an n-type impurity is ion-implanted in advance into the Si substrate 1 in the NMOS formation region, the NMOS transistor in which gate depletion is suppressed Can be formed.
Further, in the step of ashing and removing the resist 7 which is a mask for ion implantation shown in FIG. Therefore, it is possible to prevent the polysilicon layer 3 from being damaged such as notches while suppressing the number of steps.
[0048]
The method for manufacturing a semiconductor device of the present invention is not limited to the above embodiment.
For example, the insulating film 4 serving as an etching stopper layer is formed by cleaning with hydrochloric acid / hydrogen peroxide solution in the first embodiment and ashing treatment of the resist in the second embodiment. However, a thin insulating film that can be easily removed can be formed.
[0049]
For example, after the polysilicon layer 3 is formed in a CVD apparatus, N ₂ / O ₂ By supplying gas into the apparatus, a thin natural oxide film of about 1 nm can be formed on the surface of the polysilicon layer 3, and this natural oxide film can be used as an etching stopper layer. In this case, it is not necessary to use another apparatus for forming the insulating film on the wafer, and an increase in the number of processes can be suppressed.
Also, a silicon nitride thin film can be used as the etching stopper layer instead of the silicon oxide film. In addition, various modifications can be made without departing from the scope of the present invention.
[0050]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, in the step of etching the organic antireflection film using the resist as a mask, the conductor layer under the organic antireflection film is etched, and damage such as notches occurs. Can be prevented. As a result, it is possible to prevent further damage to the gate oxide film or the substrate formed below the conductor layer due to the damage generated in the conductor layer.
Therefore, according to the method for manufacturing a semiconductor device of the present invention, a highly reliable semiconductor device in which a desired miniaturized pattern is formed can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device manufacturing method according to the first embodiment of the present invention;
3 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG.
4 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG.
5 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG.
6 is a cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to Embodiment 2 of the present invention; FIG.
FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor device manufacturing method according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor device manufacturing method according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a manufacturing step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 11 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 15 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 16 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 17 is a cross-sectional view showing a manufacturing step in the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 18 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 19 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 20 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 21 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 22 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
FIG. 23 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.
[Explanation of symbols]
1, 21, 31 ... Si substrate, 2, 22 ... gate insulating film, 3, 23, 33 ... polysilicon layer, 4 ... insulating film (etching stopper layer), 5, 24, 35 ... organic antireflection film, 6 7, 25, 36 ... Photoresist, 8 ... LDD (lightly doped drain), 9, 32, 34 ... Insulating film, 10 ... LDD sidewall, 11 ... Source / drain region, 12 ... Titanium layer, 13 ... Titanium silicide Layer, 26 ... notch in the polysilicon layer, 27 ... notch in the gate oxide film and the Si substrate.

Claims (11)

Forming a conductor layer on a semiconductor substrate;
Forming an etching stopper layer made of a silicon nitride film on the conductor layer;
Forming an organic antireflection film on the etching stopper layer;
Forming a resist with a predetermined pattern on the organic antireflection film;
Etching the organic antireflection film using the resist as a mask; and
And a step of etching and removing the etching stopper layer and the conductor layer using the resist as a mask. The method for manufacturing a semiconductor device according to claim 1, wherein the conductor layer is made of polysilicon. The method for manufacturing a semiconductor device according to claim 1, wherein the conductor layer is made of amorphous silicon. The method of manufacturing a semiconductor device according to claim 1, wherein the etching stopper layer is made of a silicon oxide film. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the silicon oxide film is a step of cleaning the surface of the conductor layer using a solution containing hydrogen peroxide. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the silicon oxide film is a step of oxidizing the surface of the conductor layer using oxygen plasma. The method for manufacturing a semiconductor device according to claim 1, wherein the etching stopper layer is formed thin with a film thickness within a range that can be removed under the same etching conditions as the conductor layer. The method for manufacturing a semiconductor device according to claim 7 , wherein the thickness of the etching stopper layer is 3 nm or less. The method of manufacturing a semiconductor device according to claim 1, wherein the step of etching the organic antireflection film is a step of etching the organic antireflection film by converting a mixed gas of oxygen gas and chlorine gas into plasma. The method of manufacturing a semiconductor device according to claim 1, wherein the step of etching the organic antireflection film is a step of etching the organic antireflection film by converting a mixed gas of oxygen gas and nitrogen gas into plasma. Forming a gate insulating film on the semiconductor substrate;
Forming a conductor layer on the gate insulating film;
Forming an etching stopper layer made of a silicon nitride film on the conductor layer;
Forming an organic antireflection film on the etching stopper layer;
Forming a resist with a predetermined pattern on the organic antireflection film;
Etching the organic antireflection film using the resist as a mask; and
Using the resist as a mask, etching away the etching stopper layer and the conductor layer to form a gate electrode of a field effect transistor;
Forming a source / drain region at a predetermined interval on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device.

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