JP4174665B2 - Information processing apparatus and memory check method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus in which a program for controlling a processor is stored in a memory such as a RAM, and the processor is controlled by the program stored in the RAM, and in particular, the content of the program written in the RAM is The present invention relates to a memory check method for checking whether data has been rewritten.
[0002]
[Prior art]
In a memory such as a RAM used for storing data, it is required to correctly hold the written data. However, there is a phenomenon that the written data is destroyed due to the influence of alpha rays generated from radioactive elements contained in trace amounts of semiconductor materials and secondary cosmic ray neutrons generated when cosmic rays jump into the atmosphere. It has been pointed out. This phenomenon is called soft error, and measures such as lowering the impurity concentration of the semiconductor material and coating the semiconductor chip are taken.
[0003]
In recent years, the progress of processors (DSPs (Digital Signal Processors) and CPUs (Central Processing Units)) has been remarkable, but with the advancement of processes and the lowering of voltage, the probability of occurrence of the above-mentioned soft errors has increased, and the internal memory Operational problems have become prominent.
[0004]
Conventionally, it has been pointed out that a soft error is likely to occur in a DRAM that stores data in a capacitor element. However, in recent years, it is known that a soft error may occur not only in a DRAM (Dynamic Random Access Memory) but also in an SRAM (Static Random Access Memory) that stores data without using a capacitive element. (For example, refer nonpatent literature 1.).
[0005]
In recent years, in information processing apparatuses, a program is stored in an internal memory such as a RAM, and a processor is controlled by the program stored in the internal memory. For this reason, when a soft error occurs in such an information processing apparatus and the contents of the program stored in the internal memory are rewritten, a situation occurs in which the worst system stops due to the program running away.
[0006]
If the contents of the program are rewritten in this way, even if the system is reset, the program itself is destroyed and cannot be restored normally, and the program is written again to the internal memory such as RAM. Is required.
[0007]
In particular, it becomes a problem in a device that is required to operate continuously, such as a radio base station device. In addition, even if a failure or the like occurs in such an apparatus, it is required to quickly restore the normal operation by shortening the time during which the system is stopped as much as possible.
[0008]
In order to prevent malfunction of the program and prevent the system from shutting down, there is a method that can be easily performed by periodically checking the memory with software and overwriting and correcting the part where the memory was rewritten. . However, the more severely the correction is made, the more processing is required for the software, and there is a demerit that the normal operation is affected and the operating program itself cannot be checked.
[0009]
Further, an information processing apparatus has been proposed in which the content of a program written in a RAM is checked by a CPU, and when there is an abnormality, the program is reloaded into the RAM (see, for example, Patent Document 1). .)
[0010]
In the information processing apparatus described in Patent Document 1, since the CPU itself checks the contents of the RAM, if the CPU itself malfunctions, it cannot return to normal operation. In addition, in this conventional information processing apparatus, a control program for performing normal operation and a diagnostic program for performing a memory check are switched, but it does not change that a memory check is performed by software. it means that over the burden to the software processing. In addition, a certain amount of time is required to perform processing for switching between the control program and the diagnostic program. For this reason, it is not always possible to check the contents of the program written in the RAM without placing a processing burden on the processor with the conventional technique described in Patent Document 1 described above.
[0011]
Furthermore, some recent DSPs and CPUs have their own internal memory with an FEC (Forward Error Correction) function. However, in order to realize the FEC function, the circuit configuration becomes complicated, and the processing of the DSP and CPU is burdened.
[0012]
[Patent Document 1]
JP 59-53952 A [Non-Patent Document 1]
Anthony Cataldo, “SRAM soft errors cause hard network problems”, [online], August 17, 2001, EE Times [searched March 11, 2001], Internet <URL: http://www.eetimes.com / story / OEG20010817S0073>
[0013]
[Problems to be solved by the invention]
The above-described conventional information processing apparatus has a problem that it is difficult to check the contents of a program written in the RAM without imposing a processing burden on the processor.
[0014]
It is an object of the present invention to check whether the contents of a program written in the RAM are rewritten without imposing a burden on the processing of the processor in a system in which a program for controlling the processor is stored in a volatile memory such as a RAM. To provide an information processing apparatus and a memory check method capable of checking and correcting the rewritten data when the contents of a program are rewritten.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, an information processing apparatus of the present invention has a RAM for storing a program therein, and performs a process based on the program stored in the RAM;
It has a memory area with excellent memory retention characteristics as compared with the RAM provided in the processor, and when a program is stored in the RAM inside the processor, the same data as the program is stored in the memory area. And when the processor is in an idle state in which processing is not performed, a memory check is performed to check whether the contents of the program written in the RAM have been rewritten using the data stored in the memory area. And a check and correction control unit that corrects the data at the address determined to have been destroyed by the memory check based on the data stored in the memory area.
[0016]
According to the present invention, when the processor is in an idle state, the check and correction control unit provided outside the processor checks the contents of the program stored in the RAM inside the processor. Memory check can be performed without applying. Further, when the contents of the RAM have been rewritten, the program stored in the RAM is corrected based on the data contents stored in the memory area. Can prevent the system from malfunctioning due to runaway.
[0017]
In the other information processing apparatus of the present invention, the check and correction control unit compares a checksum written in an internal RAM of the processor with a checksum of data stored in the memory area. The memory check may be performed, and if the checksums do not match, the data stored in the RAM may be compared with the data stored in the memory area.
[0018]
According to the present invention, when the memory check is performed, the checksums are first compared, and the data is compared only when the checksums do not match. Therefore, the interrupt time for the processor can be reduced.
[0019]
Furthermore, in another information processing apparatus of the present invention, a programmable power supply circuit having a function of controlling a power supply voltage supplied to the processor,
And a programmable clock circuit having a function of controlling a frequency of a clock signal supplied to the processor.
[0020]
According to the present invention, since a defective processor can be detected in advance by changing the power supply voltage and the frequency of the clock signal supplied to the processor, it is possible to prevent malfunction of the processor.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
(First embodiment)
FIG. 1 is a block diagram showing the configuration of the information processing apparatus according to the first embodiment of this invention.
[0023]
As shown in FIG. 1, the information processing apparatus according to the present embodiment includes a DSP 1, a check and correction control unit 2, a CPU 5 that controls the DSP 1 and other circuits, a RAM 6 and a ROM 7 that are memories for the CPU 5, and a CPU 5. And a CLK circuit 8 for generating CLK used in the DSP 1 and a common power supply circuit 9.
[0024]
In the information processing apparatus of the present embodiment, a description will be given using a case where a program is stored in an internal RAM and the processor controlled by the program is a DSP, but the present invention is limited to such a case. However, any processor that is controlled by a program stored in the RAM can be applied in the same manner.
[0025]
The DSP 1 that is the target of the memory check is controlled by the CPU 5. The DSP 1 normally operates by downloading a processor program via the CPU 5 and downloading the program.
[0026]
The DSP 1 has a RAM 10 for storing a program therein, and performs main arithmetic processing based on the program written in the RAM 10. The DSP 1 outputs a “Ready” signal to the check and correction circuit 2 when it enters an idle state in which processing is not performed, and stops outputting the “Ready” signal when the idle state ends.
[0027]
The CLK circuit 8 generates CLK used in the CPU 5 and the DSP 1. The common power supply circuit 9 supplies power to the DSP 1, the check and correction control unit 2, the CPU 5, the RAM 6, the ROM 7, and the CLK circuit 8.
[0028]
The CPU 5, the DSP 1, and the check and correction control unit 2 are connected to each other by a bus line. The DSP 1 and the check and correction control unit 2 are also connected by a bus line. In each bus line, address data and program data are transmitted.
[0029]
The check and correction control unit 2 performs memory check of the RAM 10 provided in the DSP 1, correction of the program stored in the RAM 10, and storage of the program stored in the RAM 10.
[0030]
The check and correction control unit 2 has a memory area with excellent memory retention characteristics as compared with the RAM 10 provided in the DSP 1. When the program is stored in the RAM 10 inside the DSP 1 from the CPU 5, Stores the same data as the program in the memory area.
[0031]
When the RAM 10 provided in the DSP 1 is an SRAM, the memory area of the check and correction control unit 2 is a nonvolatile memory, such as a ferroelectric memory (FeRAM: Ferroelectric RAM) or a flash memory, which is unlikely to generate a soft error. Is used. As described above, it is generally known that soft errors often occur in DRAMs and SRAMs. On the other hand, it is considered that a nonvolatile memory such as a ferroelectric memory or a flash memory has a low possibility of data being destroyed due to a soft error due to a structural reason for storing the data.
[0032]
When the “Ready” signal is input from the DSP 1 and the check and correction control unit 2 knows that the DSP 1 is in an idle state where no processing is performed, the check and correction control unit 2 uses the data stored in the memory area provided therein. Then, a memory check is performed to confirm whether or not the contents of the program written in the RAM 10 have been rewritten, and a “Check” signal is output to notify the DSP 1 that the memory check is to be performed. In this memory check, if it is determined that the contents of the program stored in the RAM 10 are destroyed, the check and correction control unit 2 stores the data at the address determined to be destroyed in the RAM 10. Modify based on data stored in memory area.
[0033]
Next, a method for checking and correcting a program stored in the RAM 10 inside the DSP 1 in the information processing apparatus of this embodiment will be described in detail with reference to the drawings.
[0034]
First, when a program is downloaded from the CPU 5 to the DSP 1 via the bus line, data having the same contents as the program is also transferred to the check and correction control unit 2 via the bus line. In the DSP 1, the downloaded program is stored in the RAM 10, and in the check and correction control unit 2, data having the same content as this program is stored in an internal memory area.
[0035]
Then, check and correction control section 2 performs a memory check RAM10 according to the flowchart shown in FIG.
[0036]
First, a value A that designates an address to be checked is set to 0 (step 101). Then, the check and correction control unit 2 determines whether or not the “Ready” signal from the DSP 1 is active (step 102), and waits until the “Ready” signal becomes active. Since the DSP 1 outputs a “Ready” signal to the check and correction circuit 2 when it enters the idle state, the check and correction control unit 2 continues to wait until the DSP 1 enters the idle state.
[0037]
In step 102, when the “Ready” signal becomes active, the check and correction control unit 2 makes the “Check” signal active and notifies the DSP 1 that a memory check is performed (step 103), and then the memory at address A in the RAM 10 The contents are checked (step 104). During the memory check, the check and correction control unit 2 performs an operation of applying “Wait” to the DSP 1 by outputting a “Check” signal to the DSP 1.
[0038]
Here, any memory check method may be used, but in order to reduce the interrupt time for the DSP 1, first, only the checksum for each word is checked, and the data can be rewritten by checking with the checksum. When it is determined that there is a possibility, a detailed memory check for comparing the data of the address is performed for the first time.
[0039]
Here, the checksum is a total value obtained by adding data at a certain address. By calculating the checksum in advance and storing it together with the data, it becomes possible to know whether data rewriting has occurred. Yes. When program data is transferred from the CPU 5 to the DSP 1 and the check and correction control unit 2, this checksum is also transferred.
[0040]
A specific example of this checksum is shown in FIG. For example, in FIG. 3, when the address “1000” data program data “0011 2233 4455 6678899 AABB CCDD EEFF” is added to a value “abcd”, this “abcd” becomes the checksum at this address.
[0041]
When performing a checksum check, the checksums for each address may be compared, or a checksum obtained by totaling the checksums for a certain address is prepared in advance. May be compared.
[0042]
Then, the check and correction control unit 2 identifies the location where the data is rewritten by comparing the data of the addresses whose checksums do not match.
[0043]
In step 105, if the result of the memory check is NG (when it is determined that the contents of the memory have been rewritten), the correct data is obtained from the check and correction control unit 2 for the address A that has become NG in the memory check. The data of address A is corrected by performing an operation of writing to the internal RAM 10 (step 106).
[0044]
Then, 1 is added to the value of A (step 107). However, if the program data of a plurality of addresses are simultaneously checked in one memory check, the value A is added for the addresses to be checked simultaneously.
[0045]
Finally, the check and correction control unit 2 confirms whether or not the “Ready” signal from the DSP 1 is active (step 108), and if it is active, proceeds to step 104 where the memory check is continued, If it is inactive, the “Check” signal is made inactive to end the memory check (step 109).
[0046]
The operation of the memory check of this embodiment is shown in the timing chart of FIG. Here, it is assumed that both the “Ready” signal and the “Check” signal are active low when they are low level.
[0047]
First, when shifting from the normal operation to the idle state, the DSP 1 sets “Ready” to the low level to be active (time t ₁ ). Then, the check and correction control unit 2 sets the “Check” signal to an active low level and starts a memory check (time t ₂ ).
[0048]
If the DSP 1 quits the idle state and returns to the normal operation while the check and correction control unit 2 is performing the memory check, the DSP 1 sets the “Ready” signal to the inactive high level (time t ₃ ). . Then, the check and correction control unit 2 stops the memory check and sets the “Check” signal to the inactive high level (time t ₄ ).
[0049]
By performing such processing, in the information processing apparatus according to the present embodiment, when the DSP 1 is in the idle state, the program stored in the RAM 10 inside the DSP 1 by the check and correction control unit 2 provided outside the DSP 1. Therefore, it is possible to perform a memory check without imposing a load on the DSP 1. When the contents of the RAM 10 have been rewritten, the program stored in the RAM 10 is corrected based on the data contents stored in the memory area provided in the check and correction control unit 2. Therefore, it is possible to prevent the system from malfunctioning due to the runaway of the processor in the worst case.
[0050]
(Second Embodiment)
Next, an information processing apparatus according to the second embodiment of this invention will be described. The information processing apparatus according to the second embodiment of the present invention adds a function to stop normal operation and inspect whether there is a malfunction of the DSP 1 with respect to the first information processing apparatus shown in FIG. Is.
[0051]
In some cases, the malfunction of the memory operation of the processor is difficult to occur unless the voltage is changed or the operation clock frequency is changed. This is because the retention characteristics of the memory used in the processor generally vary depending on the power supply voltage and frequency characteristics of the memory. For this reason, in this embodiment, a processor in which a soft error is easily generated by performing the memory check described in the first embodiment after changing the power supply voltage supplied to the processor and the frequency of the clock signal within the standard. Is detected in advance.
[0052]
By performing memory check in this way, detecting processors that are prone to soft errors and preventing them from being used in the actual system, the software stored in RAM is destroyed due to soft errors, causing the processor to malfunction. Thus, it is possible to prevent the occurrence of a problem that the system stops.
[0053]
As shown in FIG. 2, the information processing apparatus according to the second embodiment of the present invention is a dedicated power source for the DSP 1 and supplies the information to the DSP 1 with respect to the information processing apparatus according to the first embodiment shown in FIG. A programmable power supply circuit 3 having a function of controlling a power supply voltage and a circuit for generating a clock signal dedicated to the DSP1, and a programmable clock (CLK) circuit having a function of controlling the frequency of the clock signal supplied to the DSP1 4 is newly provided, and the CPU 5 is replaced with the CPU 25.
[0054]
The CPU 25 has a function of controlling the power supply voltage generated by the programmable power supply circuit 3 and a function of controlling the frequency of the clock signal generated by the programmable CLK circuit 4 in addition to the functions of the CPU 5 shown in FIG. It has.
[0055]
In the present embodiment, the DSP 1 is supplied with a power supply voltage from the programmable power supply circuit 3 instead of from the common power supply circuit 9. In the present embodiment, the DSP 1 operates by using the CLK signal from the programmable CLK circuit 4 instead of the CLK signal from the CLK circuit 8.
[0056]
In the information processing apparatus of the present embodiment, the CPU 25 changes the power supply voltage supplied to the DSP 1 by controlling the output voltage of the programmable power supply circuit 3. Further, the CPU 25 controls the clock frequency of the programmable CLK circuit 4 to change the frequency of the clock signal supplied to the DSP 1.
[0057]
In the information processing apparatus of this embodiment, the programmable power supply circuit 3 and the programmable CLK circuit 4 are controlled by the CPU 25 to change the power supply voltage supplied to the DSP 1 and the frequency of the clock signal, thereby detecting the defective DSP 1 in advance. Therefore, it is possible to prevent the DSP 1 from malfunctioning in actual operation.
[0058]
In the information processing apparatuses of the first and second embodiments, the case where the DSP 1 is used as a processor having a memory for storing a program therein is described, but the present invention is limited to such a case. The present invention can be applied in the same manner as long as it is a processor that has a memory for storing a program therein and performs processing by the program.
[0059]
In the first and second embodiments, the case where the RAM 10 is provided as a memory area for storing a program in the DSP 1 is described. However, the present invention is limited to such a case. However, the present invention can be similarly applied even when the program is stored in the external memory and the DSP 1 performs processing using the program stored in the external memory.
[0060]
【The invention's effect】
As described above, according to the present invention, in a system that stores a program for controlling a processor in a volatile memory such as a RAM, the contents of the program written in the RAM without imposing a burden on the processing of the processor. It is possible to obtain an effect that the rewritten data can be corrected when the contents of the program are rewritten.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an information processing apparatus according to a first embodiment of this invention.
FIG. 2 is a flowchart showing the operation of the information processing apparatus according to the present embodiment.
FIG. 3 is a diagram for explaining a checksum.
FIG. 4 is a timing chart showing an operation of the information processing apparatus according to the embodiment.
FIG. 5 is a block diagram illustrating a configuration of an information processing apparatus according to a second embodiment of this invention.
[Explanation of symbols]
1 DSP
2 Check and Correction Control Unit 3 Programmable Power Supply Circuit 4 Programmable CLK Circuit 5 CPU
6 RAM
7 ROM
8 CLK circuit 9 Common power supply circuit 10 RAM
25 CPU
101-109 steps

Claims (5)

A processor having a RAM for storing a program therein, and performing processing based on the program stored in the RAM;
It has a memory area with excellent memory retention characteristics as compared with the RAM provided in the processor, and when a program is stored in the RAM inside the processor, the same data as the program is stored in the memory area. And when the processor is in an idle state in which processing is not performed, a memory check is performed to check whether the contents of the program written in the RAM have been rewritten using the data stored in the memory area. An information processing apparatus comprising: a check and correction control unit that performs correction and corrects data at an address determined to have been destroyed by a memory check based on data stored in the memory area. The check and correction control unit performs a memory check by comparing a checksum written in an internal RAM of the processor with a checksum of data stored in the memory area, and the checksum does not match The information processing apparatus according to claim 1, wherein the data stored in the RAM is compared with the data stored in the memory area. A programmable power supply circuit having a function of controlling a power supply voltage supplied to the processor;
The information processing apparatus according to claim 1, further comprising a programmable clock circuit having a function of controlling a frequency of a clock signal supplied to the processor. A memory check method for checking whether the contents of a program written in the RAM have been rewritten in an information processing apparatus that performs processing of the processor based on a program stored in a RAM provided in the processor. And
When a program is stored in an internal RAM of the processor, storing data having the same contents as the program in a memory area having superior memory retention characteristics compared to the RAM;
When the processor is in an idle state in which processing is not performed, performing a memory check for confirming whether the contents of the program written in the RAM have been rewritten using the data stored in the memory area;
A memory check method comprising: correcting data at an address determined to have been destroyed by the memory check based on the data stored in the memory area. When the memory check is performed by comparing the checksum written in the internal RAM of the processor with the checksum of the data stored in the memory area, and the checksums do not match 5. The memory check method according to claim 4, wherein the data stored in the RAM is compared with the data stored in the memory area.

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