JPS60225954A - Storage device - Google Patents

Abstract

PURPOSE:To shorten the relief processing time of soft errors caused by the alpha-line of a storage element, by reading out the whole address spaces of a storage circuit at a cycle which is a fixed number times of the cycle of refreshing operation and operating the storage circuit in the pair of rewriting and refreshing operations. CONSTITUTION:A refresh interrupting signal 14 is generated by a refresh interruption controlling circuit 13 and inputted in an internal address generating circuit 15 through a multiplying circuit 25 to perform refreshing operations periodically. Then an address of a storage circuit 6 is read out and, when an error is found in the data, the rewriting operation is again performed to the same address through an error correction detecting circuit 8 and error correcting code generating circuit 4. The relief of soft errors generated in the whole address spaces of the storage circuit 6 can be performed effectively by performing ordinary refreshing operations thereafter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a memory device using a semiconductor die or a micro-type memory element, and particularly to a memory device having an error correction detection function.

"Prior art" Semiconductor technology 4. With the increase in the density of sun-type memory elements, in conventional memory devices, in order to remedy soft errors that are emitted from the case material and cause the destruction of stored information, It is equipped with a 1-bit correction-2 bit error detection function, and when a 1-bit error is detected during a read operation from an external device, the pit is corrected and transferred to the external device, and a 1-bit error ratio signal is also sent.

In this case, a method is adopted in which the external device interrupts the operation with an error signal, sends the received read data to the error address as write data to the storage device again, and executes the write operation. There is.

In this one-way system, the increase in interrupt control in the external device causes a drop in throughput between the storage device and the storage device, and soft errors occur at addresses that are not accessed in the storage device, and these errors occur at the same address. In this case, the chance of uncorrectable errors increases.゛An object of the present invention is to eliminate soft errors caused by alpha rays in the memory element by operating the entire address space of the memory circuit in a pair of read/rewrite operation and refresh operation at a constant multiple of the refresh operation period. It is an object of the present invention to provide a storage device which can shorten rescue processing time and perform it efficiently.

``Structure of the Invention'' A memory device that uses a semiconductor dynamic memory element, has a 1-bit error correction/2-bit error detection function, and is capable of reading and writing operations to any address,
The present invention includes means for switching between write data from an external device and data read from a storage circuit through a correction circuit, and means for transferring data obtained from the means to the storage circuit through a correction code generation circuit. , a means for issuing a refresh interrupt request to an external device, a refresh operation waiting control means, a means for decoding an operation designation from the external device, a means for generating a timing signal necessary for the operation based on a signal from the means, and a means for generating a timing signal from the external device. means for distributing the address signal from the refresh interrupt request means to the memory circuit; means for multiplying the signal from the refresh interrupt request means by a predetermined number of times; and means for generating an internal address to the memory circuit using the signal from the means. , means for inputting the address to the address distribution means; means for performing a pair of read/rewrite operations and refresh operations on the output of the timing generation means; and means for canceling the refresh interrupt request signal upon completion of the refresh interrupt request signal.

"Example" Next, the configuration and operation of the present invention will be explained with reference to the drawings. FIG. 1 is a component diagram of one embodiment,
FIG. 2 shows main signals on the time axis to help explain the operation of FIG. 1. First, in FIG. 1, write data 1 transferred from an external device and read data 9 transferred to the external device are input to a selection switching circuit 2, and one of them is sent as an output 3 to an error correction code generation circuit 4. is input. The output of the error correction code generation circuit 4 is transferred as write data 5 to the memory port 6. Read data 7 from storage circuit 6 is input to error correction detection circuit 8, and if circuit 8 detects a 1-bit error, that bit is corrected and transferred as read data 9 to an external device.

Either the external address data 10 transferred from the external device or the internal address data 16 output from the internal address signal generation circuit 15 is selected by the address selection switching distribution circuit 11, and the selected output is the address data 12.
The data is transferred to the storage circuit 6 as a.

The refresh interrupt control circuit 13 has a timer circuit necessary for performing refresh operations periodically, and the refresh interrupt signal 14 is inputted to the number multiplier circuit 25 and counted up to a predetermined time. The output 26 of the number multiplier circuit 25 is input to an internal address generation circuit 15 having a binary counting circuit.

Action designation data and action request signal 21 transferred from an external device are transferred to action designation decoding circuit 22 . The operation request signal 23 currently being output from the operation designation decoding circuit 22, the refresh interrupt request signal 14, and the even multiple output 26 of the refresh interrupt request signal are sent to the refresh waiting circuit 17.
is input.

When the refresh interrupt request signal 14 is not present, the refresh waiting circuit 17 performs control according to the operation designation from an external device if the operation request signal 2j is present, while the operation request compensation signal 23
If the refresh interrupt request signal 14 is present when the refresh interrupt request signal 14 is not present, the refresh operation is controlled for the memory circuit 6, and if the refresh interrupt request signal 14 and the operation request signal 23 are of a certain period type, the operation request signal 23 is is executed with priority, and a refresh operation is executed when the operation is completed.

The output signal 18 of the refresh waiting circuit 17 and the various operation/operation designation signals 24 output from the operation designation decoding circuit 22 are input to the timing generation circuit 19, which generates the control timing signal 20 necessary for each operation designation. , the timing signal 20 is mainly transferred to the storage circuit 6. This timing signal 20 is a row address strobe, a column address strobe, and a write timing signal.

In a memory device consisting of the above-mentioned functional elements, the relief process for soft errors caused by alpha rays in semiconductor dynamic memory elements is to correctly restore errors in information held in memory cells. The entire address space can be read out at an appropriate cycle, and if a 1-bit error is detected, it can be corrected and rewritten to the address.

In such a relief process, an internal address is generated every integral multiple of the refresh operation cycle, one address in the memory circuit 6 is read out, and the data is passed through the error correction detection circuit 8 and the error correction code generation circuit 6. If a rewrite operation is performed again to the same address and a normal refresh operation is performed following this operation, soft errors that may occur in the entire address space of the memory circuit 6 can be more effectively relieved. .

Figure 2 is a main time chart related to this operation, and A is the refresh interrupt signal 14 generated every cycle T1.
, B is a read operation accompanied by a rewrite operation that contributes to soft error relief, C is a normal refresh operation, and F operates at an integer multiple of the cycle using the refresh interrupt signal 14 of A as input. signal, Di and Di-1
-1 is internal address data 16 that indicates the entire address space of the storage circuit 6, which is generated by the signal F, and is added in binary every cycle NT. When El generates the refresh interrupt signal, it has already received the operation request signal 2 from the external device.
3, in which a normal operation from an external device is first performed, and then a rewrite operation and a refresh operation for soft error relief are performed. E2 shows an example where there is already an operation request from an external device when the refresh interrupt signal is generated. In this case, since F is logic "q", the normal operation from the external device is first requested. After executing , only a normal refresh operation is performed without performing a rewrite operation for soft error relief.

Conventionally, a read operation is performed on a storage device, and if a 1-bit error is detected as a result, a write operation is performed to the address again, so the sum of each cycle time of the read operation and the write operation is added to the interrupt processing of the external device. This adds time and reduces throughput, and if a soft error occurs in an address area that is not accessed in the storage device, or if it overlaps with an intermittent error in other control systems, it becomes an uncorrectable error. This increases the probability, but this invention can reduce it.

"Effects of the Invention" Based on the above explanation, the present invention has a circuit configuration in which soft error relief using alpha rays in a semiconductor memory element is performed by a pair of read hole write operation and refresh operation at a constant multiple of the refresh operation cycle. Depending on the situation, the soft error processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing an example of its operation.

Claims (1)

[Claims] (1) A memory device that uses a semiconductor memory element and a nermic type memory element, has a 1-bit error correction/2-bit error detection function, and is capable of writing, reading, and reading/rewriting operations to any address. means for switching between write data from an external device and data read from a storage circuit through a correction circuit; and means for transferring data obtained from the means to the storage circuit through a correction code generation circuit; means for issuing a refresh interrupt request to an external device; a refresh operation waiting control means; a means for decoding an operation designation from the external device; a means for generating a timing signal necessary for the operation based on a signal from the operation decoding means; means for distributing an address signal from the device to the memory circuit; means for multiplying the signal obtained from the refresh interrupt request means by a predetermined number of times; and an internal address to the memory circuit from the signal obtained by the means; means for generating a signal, means for inputting the address signal into the address distribution means, means for performing a pair of read/write operations and refresh operations as outputs of the timing generation means, and the pair of operations is completed. and means for canceling the refresh interrupt request signal at the time of the refresh operation or at the end of only the refresh operation.