JPH0689237A - Memory control system - Google Patents

Abstract

PURPOSE:To rewrite corrected data into a memory cell where an error occurs so as to improve the reliability of a memory by providing a function for switching a system to the next memory refresh when a one-bit error is detected and for rewriting data into the whole memory cells. CONSTITUTION:When the one-bit error occurs at the time of reading data from the memory 9, an ECC control circuit 8 corrects data outputted from the memory 9 and outputs it to a data bus 2. At the same time, the ECC control circuit 8 transmits a one-bit error detection signal (a) to a refresh/rewrite control circuit 7. Consequently, a memory refresh/rewrite signal (e) is inputted to a memory access control circuit 3 and memory refresh is executed. Then, the control circuit 3 transmits an ECC control signal (b) so that rewriting is executed. The ECC control circuit 8 reads data in accordance with the address of rewriting by receiving the signal (b), corrects data and rewrites it into the same address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory control system,
In particular, the present invention relates to a memory control system that rewrites the corrected data in the memory cell when an error occurs in the read data in the memory with ECC.

[0002]

2. Description of the Related Art A conventional memory control system uses an ECC.
(Error Checking and Corre
function, that is, a memory circuit with an ECC having a function of detecting and correcting a 1-bit error and a function of detecting a 2-bit error, if a 1-bit error occurs due to a soft error, the 1-bit error is corrected and read, The corrected data was rewritten in the memory cell of the same address.

[0003]

However, such a conventional memory control system as described above is performed only at this address only when a 1-bit error occurs at the time of reading. Therefore, due to a soft error at another address. Even if a 1-bit error occurs, the 1-bit error cannot be detected unless the address is read out, rewriting is not performed, and a 1-bit error occurs at an address with a low access frequency. However, since rewriting is not performed, there is a drawback in that the data is read after a 2-bit error and cannot be corrected.

[0004]

According to the memory control system of the present invention, a 1-bit error is detected in a memory configuration including an address generation circuit including a counter that is incremented by a memory refresh cycle signal in a memory circuit with an ECC. In this case, the memory refresh is switched from the next memory refresh to the memory refresh with rewriting, and all memory cells are rewritten.

[0005]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

The memory control system shown in FIG. 1 has an address bus 1, a data bus 2 and a memory access control which supplies an ECC control signal b corresponding to a memory access to an ECC control circuit and a memory control signal c to a memory. Circuit 3
A row address generation counter 4 for generating a row address at the time of memory refresh and a row address at the time of rewriting, a column address generation counter 5 for generating a column address at the time of rewriting, a row address, a column address and an address bus 1. An address selector 6 which selects an address supplied from the memory and supplies it as a memory address, a memory 9, and a refresh period signal g and a counter reset h signal which are a row address generation counter 4 and a column address generation counter 5. The memory refresh / rewrite control circuit 7 which supplies the memory refresh / rewrite signal e to the memory access control circuit 3 and the ECC control circuit which outputs the 1-bit error detection signal a and also controls the ECC during rewriting. The corrected data with correct data inputted from the memory 9 in accordance with the signal b memory 9
And an ECC control circuit 8 for sending to the.

Next, the operation of the embodiment shown in FIG. 1 will be described.

Normally, when no 1-bit error occurs,
The memory refresh operation is performed by the row address generation counter 4
Becomes the row address, and the memory cell indicated by the row address is refreshed. In this case, the well-known RAS
Only refresh is performed.

When a 1-bit error occurs when reading data from the memory 9, the ECC control circuit 8 corrects the data output from the memory 9 and outputs the corrected data to the data bus 2. At the same time, the ECC control circuit 8 sends the 1-bit error detection signal a to the refresh / rewrite control circuit 7.

Upon receiving the 1-bit error detection signal a, the refresh / rewrite control circuit 7 receives the counter reset signal h.
Is sent to the address generation counter 10, and the counter is initialized.

Next, when the refresh cycle signal g becomes valid, the memory refresh / rewrite signal e is input to the memory access control circuit 3, and normal memory refresh is first performed. Next, the memory access control circuit 3
The address selector control signal f, the memory control signal c, and the ECC control signal b are transmitted so that rewriting is performed without accepting another memory access request d.

The ECC control circuit 8 reads the data in accordance with the rewritten address, corrects it, and writes it back to the same address. This completes the first memory refresh operation with rewriting.

When the row address generation counter 4 overflows, the column address generation counter 5 counts up and the column address for the rewriting operation is switched. Then, when the column address generation counter 5 overflows, that is, when all memory cells are rewritten, the normal memory refresh operation is resumed.

As an example, the memory 9 shown in FIG. 1 has 10 bits for each row and column as a rewrite address. Therefore, after 2 ²⁰ times of memory refresh operation with rewrite,
It returns to the normal memory refresh operation.

[0016]

According to the memory control system of the present invention, by changing the refresh control circuit to a refresh rewrite control circuit, all memory cells can be rewritten after a 1-bit error is detected. Even if a 1-bit error due to a soft error occurs in addition to the address, the probability that the address will be corrected before being read can be improved and the probability of 2-bit error of an infrequently accessed address can be reduced. There is an effect that the property can be improved.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 address bus 2 data bus 3 memory access control circuit 4 row address generation counter 5 column address generation counter 6 address selector 7 refresh / rewrite control circuit 8 ECC control circuit 9 memory 10 address generation counter a 1 bit error detection signal b ECC control Signal c memory control signal d memory access request e memory refresh / rewrite signal f address selector signal g refresh cycle signal h counter reset signal i memory address

Claims (3)

[Claims] 1. A memory control system in a memory circuit with an ECC that outputs an error occurrence signal when an error occurs in data read from a memory, comprising an ECC control circuit and a counter that is counted up by a memory refresh cycle signal. An address generation circuit, a mechanism for automatically performing a rewriting operation for reading data from the address generated by the address generation circuit and writing the data corrected by ECC to the same address without intervention of a CPU, and a normal memory It has a mechanism to switch between the refresh operation and the memory refresh operation with rewrite operation, and when the error detection signal is output by the ECC control circuit, it switches from the next memory refresh operation to the memory refresh operation with rewrite operation, In a cell After uniformly rewriting were performed, the memory control system and controlling to return to the normal memory refresh operation. 2. When a 1-bit error detection signal is output from the ECC control circuit, a memory refresh / rewrite signal is generated, all memory cells in the memory are read out, and if any error is found, it must be corrected. A memory control system characterized by rewriting as it is. 3. When a refresh synchronization signal is supplied, a refresh operation is performed on memory cells designated by all different row addresses with the same column address, and when a 1-bit error detection signal is supplied,
A memory control system characterized by performing a refresh operation on all memory cells designated by different column addresses and row addresses.