CN118672822A - FPGA soft error resistance method and device - Google Patents

Abstract

A method and a device for resisting soft errors of an FPGA, the method comprises the following steps: after the FPGA is loaded, reading back loading data of the FPGA; performing readback verification on the loading data, wherein the readback verification comprises ECC verification and CRC verification; during the read-back verification, error correction is performed by triggering a reload event for the detected multi-bit error. By utilizing the scheme of the invention, the detection and the error correction of the FPGA soft errors can be effectively realized.

Description

FPGA soft error resistance method and device

Technical Field

The present invention relates to the field of FPGA (Field Programmable Gate Array) detection technology, and in particular to a method and device for FPGA soft error resistance.

Background Art

FPGA is a semi-customized circuit in application-specific integrated circuits. FPGA consists of logic units, RAM (Random Access Memory), multipliers and other hardware resources. By organizing these hardware resources reasonably, hardware circuits such as multipliers, registers, and address generators can be realized. FPGA has been widely used in the field of digital circuit design because of its rich wiring resources, repeatable programming, high integration, and low investment.

The design process of FPGA includes algorithm design, code simulation, design, and board debugging. Bitstream generation is a step in the FPGA design process, which generates a bitstream that can be downloaded to the FPGA chip, so that the corresponding circuit structure can be formed in the FPGA chip to achieve the expected circuit function. After the FPGA downloads the bitstream, soft errors may occur due to radiation in the application environment, specific interference to the FPGA, packaging materials and other inducements, that is, some bits in the bitstream are flipped, which will cause errors in the FPGA function. Therefore, accurately discovering soft errors in the bitstream and correcting them is the key to ensuring the function of the FPGA.

Summary of the invention

The embodiment of the present invention provides a method and device for FPGA soft error resistance, which can effectively realize the detection and correction of FPGA soft errors.

To this end, the embodiment of the present invention provides the following technical solutions:

In one aspect, an embodiment of the present invention provides a method for FPGA soft error resistance, the method comprising:

After the FPGA is loaded, read back the loaded data of the FPGA;

Performing a read-back check on the loaded data, the read-back check comprising an ECC check and a CRC check;

During the readback verification process, for detected multi-bit errors, error correction is performed by triggering a reload event.

Optionally, the correcting the detected multi-bit error by triggering a reload event includes:

Each time a multi-bit error is detected, the number of times the multi-bit error occurs is accumulated to obtain an accumulated value;

When the accumulated value reaches a set threshold, a reload event is triggered.

Optionally, the method further comprises: presetting a power-on mode, the power-on mode comprising: a power-on prohibition operation mode and a power-on permission operation mode;

After the FPGA is loaded, reading back the loaded data of the FPGA includes:

In the power-on disabled operation mode, after the FPGA is loaded, it waits for user instructions and reads back the loaded data of the FPGA after receiving the user's verification instruction;

In the power-on enabled operation mode, after the FPGA is loaded, the loaded data of the FPGA is read back immediately.

Optionally, the method further comprises: configuring an error correction mode;

During the readback verification process, error correction operations are performed according to the current error correction mode.

Optionally, configuring the error correction mode includes: writing data indicating the error correction mode into a control register;

The method further includes determining a current error correction mode by reading the control register.

Optionally, the error correction mode includes any one or more of the following: stop, continue, error correction and stop, error correction and continue;

The error correction operation performed according to the current error correction mode includes:

If the current error correction mode is the stop mode, when an error is detected in the current frame data, the readback check is stopped and the waiting state is entered until a reset event is triggered;

If the current error correction mode is the continue mode, when it is detected that the current frame data error is a 1-bit error, the readback check continues until a reset event or a reload event is triggered;

If the current error correction mode is error correction and stop, then when it is detected that the current frame data error is a 1-bit error, error correction write-back is performed, and after the current error correction write-back is completed, the system enters a waiting state until a reset event is triggered; when it is detected that the current frame data error is a multi-bit error, the system enters a waiting state until a reset event is triggered;

If the current error correction mode is error correction and continue, when it is detected that the current frame data error is a 1-bit error, error correction write-back is performed, and after the current error correction write-back is completed, read-back verification is continued until a reset event or a reload event is triggered.

Optionally, the method further comprises: providing an error prompt when an error in the current frame bit stream is detected.

Optionally, after the FPGA is loaded, reading back the loaded data of the FPGA includes: after the FPGA is loaded and the user configuration is completed, reading back the loaded data of the FPGA.

Optionally, the method further includes: after completing the user configuration, periodically triggering a refresh event.

Optionally, after a reload event is triggered, the FPGA is reloaded; after a reset event is triggered, the loaded data of the FPGA is read back anew; after a refresh event is triggered, the loaded data of the FPGA is refreshed.

Optionally, the method further includes: triggering a reload event after receiving a restart instruction from the user.

On the other hand, an embodiment of the present invention further provides a device for FPGA to resist soft errors, the device comprising:

Memory module, used to store the loading data of FPGA;

A read-back module, used to read back the loaded data of the FPGA from the memory module after the FPGA loading is completed;

A check module, used for performing a readback check on the loaded data, wherein the readback check includes an ECC check and a CRC check; during the readback check process, for a detected multi-bit error, error correction is performed by triggering a reload event;

The loading module is used to reload the FPGA after the verification module triggers a reloading event.

Optionally, each time the verification module detects a multi-bit error, it accumulates the number of times the multi-bit error occurs to obtain a cumulative value, and triggers a reload event when the cumulative value reaches a set threshold.

Optionally, the device further comprises: a register, configured to store configuration information, wherein the configuration information comprises: a power-on mode, and/or an error correction mode;

The readback module is used to read the register after the FPGA is loaded and the user configuration is completed, determine the current power-on mode, and perform a readback operation according to the current power-on mode;

The verification module is used to read the register after the FPGA is loaded and the user configuration is completed, determine the current error correction mode, and perform error correction operations according to the current error correction mode.

Optionally, the device further comprises: a refresh module, used for periodically refreshing the loaded data of the FPGA in the memory module.

On the other hand, an embodiment of the present invention further provides an FPGA chip, which executes the above-mentioned FPGA soft error resistance method after loading.

The method and device for FPGA soft error resistance provided by the embodiment of the present invention, after the FPGA is loaded, reads back the loaded data of the FPGA, performs ECC check and CRC check on the loaded data, and realizes the detection of any error and the correction of 1-bit error. In the read-back verification process, the detected 1-bit error can be directly corrected in the memory, and the detected multi-bit error can be corrected by triggering a reload event, thereby effectively improving the FPGA's ability to resist soft errors, ensuring the effectiveness and accuracy of the FPGA function, and providing strong technical support for the application of FPGA in various interference environments.

Furthermore, for multi-bit errors detected in the readback check, a reload event may be triggered when the cumulative number of multi-bit errors reaches a set threshold, which may further improve efficiency.

Furthermore, by setting different error correction modes and power-on modes, users can flexibly and conveniently apply various functions according to their needs, thereby enhancing the flexibility of the solution.

Furthermore, through the timed refresh function, multiple levels of readback verification and error correction can be achieved, better ensuring the effectiveness and accuracy of FPGA functions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart of a method for FPGA soft error resistance according to an embodiment of the present invention;

FIG2 is another flow chart of a method for FPGA soft error resistance according to an embodiment of the present invention;

FIG3 is a schematic diagram of a structure of a device for FPGA soft error resistance according to an embodiment of the present invention;

FIG4 is another schematic diagram of the structure of the device for FPGA anti-soft error according to an embodiment of the present invention;

FIG. 5 is another schematic diagram of the structure of the FPGA soft error resistance device according to an embodiment of the present invention.

DETAILED DESCRIPTION

The principle and spirit of the present invention will be described below with reference to the exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way.

In the error detection of FPGA bit stream, the most commonly used is the combination of CRC (Cyclic Redundancy Check) and ECC (Error Correction Code). Usually, the FPGA bit stream will have a CRC value. When the bit stream is downloaded to the FPGA, the CRC check function is turned on. The FPGA will start to read back the bit stream to calculate the CRC. After the calculation is completed, it will be compared with the CRC value in the bit stream to detect whether there is an error. In addition, in the FPGA bit stream, each frame of the bit stream will have an ECC. ECC is usually based on the Hamming code algorithm and is used to detect and correct single-bit memory errors. In the prior art, considering the complexity of hardware implementation and chip cost, ECC checking can usually only achieve one correction and two detection, that is, it can detect 1-bit and 2-bit errors in each frame of the bit stream, but can only correct 1-bit errors.

Based on the limitations of the ECC error detection and correction capabilities, the embodiments of the present invention provide a method and device for FPGA soft error resistance, which detects any error in the FPGA bit stream through the CRC algorithm, and detects and corrects 1-bit errors and detects multiple-bit errors through ECC verification of each frame of data. On this basis, by reloading and/or regularly refreshing the FPGA bit stream, the FPGA's soft error resistance capability is effectively improved, ensuring the effectiveness and accuracy of the FPGA function after loading the bit stream.

As shown in FIG. 1 , it is a flow chart of a method for FPGA soft error resistance according to an embodiment of the present invention, comprising the following steps:

Step 101, after the FPGA loading is completed, read back the loaded data of the FPGA.

FPGA loading refers to the process of writing the corresponding bit stream into the FPGA. The FPGA loading method and process are the same as those in the prior art and will not be described in detail here.

Step 102: performing a read-back check on the loaded data, wherein the read-back check includes an ECC check and a CRC check.

It should be noted that, in the embodiment of the present invention, the ECC check and the CRC check are performed simultaneously. Although the CRC check value is for the entire FPGA bit stream, the CRC calculation needs to be performed for each frame of the read-back bit stream. In other words, for each frame of the read-back bit stream, the CRC calculation and the ECC check need to be performed simultaneously.

Step 103 : During the readback verification process, for the detected multi-bit errors, error correction is performed by triggering a reload event.

It should be noted that for a 1-bit error detected in the readback check, error correction can be performed directly in the FPGA memory. For a multi-bit error detected in the readback check, in a non-limiting embodiment, a reload event may be triggered for error correction each time a multi-bit error occurs; in another non-limiting embodiment, the number of multi-bit errors occurring may be accumulated when a multi-bit error occurs to obtain a cumulative value; when the cumulative value reaches a set threshold (for example, the threshold is 3), a reload event is triggered, and this embodiment of the present invention does not limit this.

In addition, the multi-bit errors described in the embodiments of the present invention include the following situations:

(1) In the current frame bit stream data check, 2-bit errors are detected by ECC check. Of course, some errors of more than 2 bits can be detected by optimizing and improving ECC check.

(2) After all frame bit stream data is read back, multiple bit errors are detected by CRC check.

In order to avoid the problem that in the second method mentioned above, i.e., triggering a reloading event according to the number of occurrences of multi-bit errors, when the cumulative number of all multi-bit errors detected in all data of the FPGA is less than the set threshold, it is impossible to correct errors by triggering a reloading event, in another embodiment of the present invention, a refresh event can be triggered periodically, i.e., refreshing the loaded data in the FPGA. Specifically, the FPGA reads the FPGA bit stream data from the external storage space and refreshes the SRAM (Static Random-Access Memory) inside the FPGA.

It should be noted that the set threshold can be set according to application needs and the interval of regular refresh. For example, if the interval of regular refresh is small, the set threshold can be set larger; conversely, if the interval of regular refresh is large, the set threshold can be set smaller.

The FPGA anti-soft error method provided by the embodiment of the present invention performs a readback check on the loaded data of the FPGA, and during the readback check process, ECC check and CRC check are performed simultaneously. Since multi-bit errors cannot be directly corrected in the FPGA memory in the ECC check, for this reason, the embodiment of the present invention uses a reloading method to correct errors. Since the soft error is not an error in the bit stream itself written into the FPGA, but is caused by the radiation in the application environment, the FPGA being subjected to specific interference, the packaging material and other inducements, causing the data written into the FPGA to be flipped, the bit stream stored in the FPGA external memory is reloaded into the FPGA memory by reloading, and the multi-bit errors that occur are corrected to ensure the correctness of the FPGA function.

Of course, new soft errors may be generated during the reloading process, but by reading back and verifying the bit stream after reloading, the soft errors can be eliminated.

In actual applications, in order to meet the needs of different users in various environments, in a non-limiting embodiment, different error correction modes may be pre-configured. Accordingly, when performing a readback check, corresponding operations are performed according to the current error correction mode.

For example, in a specific application, the error correction mode may include but is not limited to any one or more of the following: halt, continue, correct and halt, correct and continue. The error correction operations corresponding to the various error correction modes are as follows:

If the current error correction mode is the stop mode, when a data error is detected in the current frame, the readback check is stopped and the state enters the waiting state until a reset event is triggered. The data error here includes not only a 1-bit error, but also a multi-bit error. That is to say, in the stop mode, whether a 1-bit error or a multi-bit error is detected, the readback check is stopped and the state enters the waiting state until a reset event is triggered.

If the current error correction mode is the continue mode, when it is detected that the current frame data error is a 1-bit error, it is not corrected, but the readback check is continued. When it is detected that the current frame error is a multi-bit error, the number of multi-bit errors is accumulated; until a reset event or a reload event is triggered.

If the current error correction mode is error correction and stop, then when it is detected that the current frame data error is a 1-bit error, error correction write-back is performed, and after the current error correction write-back is completed, the system enters a waiting state until a reset event is triggered; when it is detected that the current frame data error is a multi-bit error, the system enters a waiting state until a reset event is triggered;

If the current error correction mode is error correction and continue, when it is detected that the current frame data error is a 1-bit error, error correction write-back is performed, and read-back verification continues after the current error correction write-back is completed; when it is detected that the current frame data error is a multi-bit error, the number of multi-bit errors is accumulated until a reset event or a reload event is triggered.

It should be noted that in the above-mentioned various error correction modes, for the detected multi-bit errors, it is only necessary to accumulate the number of occurrences of the multi-bit errors, and as long as the waiting state is not entered, the detection of multi-bit errors is carried out all the time until a reset event or a reload event is triggered.

Of course, the above-mentioned error correction modes are only examples. In practical applications, other error correction modes may be set according to application requirements, which is not limited in the embodiments of the present invention.

In order to facilitate the use requirements of different users, in actual applications, the above reloading event can be manually triggered and/or automatically triggered when certain conditions are met, which is not limited in the embodiment of the present invention. After the reloading event is triggered, the FPGA loading is restarted, and after the loading is completed, the loading data of the FPGA is read back for readback verification.

It should be noted that in order to facilitate the user's configuration of different error correction modes, the FPGA external register can be used to write the data used to indicate the error correction mode into the control register. In addition, a configuration interface can be provided, and the user can complete the write operation on the corresponding control register in the configuration interface.

Accordingly, during the read-back verification process, the current error correction mode selected by the user can be determined by reading the control register, and then the error correction operation is performed according to the error correction method described above.

Accordingly, before performing the read-back verification, user configuration needs to be completed, as shown in FIG. 2 .

As shown in FIG. 2 , another flow chart of the method for FPGA soft error resistance according to an embodiment of the present invention includes the following steps:

Step 201, loading FPGA.

Step 202: Perform user configuration.

Step 203: After the user configuration is completed, the error correction mode is determined according to the user configuration, and the loaded data of the FPGA is read back.

Step 204: perform a read-back check on the loaded data, wherein the read-back check includes an ECC check and a CRC check.

Step 205 : During the readback verification process, when a 1-bit error and/or a multi-bit error is detected, an error correction operation is performed according to an error correction mode.

The error correction operations under various error correction modes have been described in detail above and will not be repeated here.

It should be noted that in the above embodiments, when a 1-bit error is detected, an error prompt may be given, such as by a prompt message or an indicator light. Of course, when multiple-bit errors are detected, corresponding errors may also be given, and the accumulated number of multiple-bit errors may also be displayed.

By utilizing the solution of the present invention, the readback verification and error correction of the FPGA loaded data can be automatically completed after the FPGA is loaded, and specific error correction operations can also be performed according to the user's configuration information, thereby meeting the various needs of different users in different application scenarios.

It should be noted that, in the embodiments shown in FIG. 1 and FIG. 2 above, a reload event is triggered after the cumulative value of the number of occurrences of multi-bit errors reaches a set threshold. In another non-limiting embodiment, the reload event can also be triggered by user control. For example, a corresponding restart switch can be set, and the user sends a restart instruction through the restart switch. Accordingly, after the application receives the user's restart instruction, a reload event is triggered.

Furthermore, in order to facilitate the user's control of the FPGA, a variety of different power-on modes can be set. For example, in a non-limiting embodiment, the power-on mode can include: a power-on disabled operation mode and a power-on enabled operation mode. The specific operation methods of these two power-on modes are as follows:

In the power-on disabled operation mode, after the FPGA is loaded, it waits for user instructions and reads back the loaded data of the FPGA after receiving the user's verification instruction;

In the power-on enabled operation mode, after the FPGA is loaded, the loaded data of the FPGA is read back immediately.

The above-mentioned different power-on modes can be realized by setting corresponding switches or enabling signals, etc., which is not limited in the embodiment of the present invention.

In the power-on disabled operation mode, you can manually decide whether to read back and verify the data loaded on the FPGA. In the power-on enabled operation mode, after the FPGA is loaded, the data loaded on the FPGA can be automatically read back and verified. This greatly facilitates the needs in different application environments and scenarios and improves the flexibility of the solution.

It should be noted that if the error correction mode needs to be configured, then no matter it is the power-on disabled operation mode or the power-on enabled operation mode, a read-back check needs to be performed after the user configuration is completed.

In order to further ensure the correct function of the FPGA, in another non-limiting embodiment, the FPGA can also be read back and checked by means of a timed refresh, thereby avoiding soft errors during the loading or application of the FPGA.

It should be noted that if user configuration is not required, a refresh event can be triggered periodically after the FPGA is loaded; if user configuration is required, a refresh event should be triggered periodically after the user configuration is completed.

After the refresh event is triggered, the FPGA reads the FPGA bit stream data from the external storage space and refreshes the SRAM inside the FPGA.

To further illustrate the differences between various events, the reload event, reset event, and refresh event mentioned above are further explained as follows:

After the reload event is triggered, reload the FPGA;

After the reset event is triggered, the loaded data in the FPGA is read back again;

After the refresh event is triggered, the loaded data in the FPGA is refreshed.

It should be noted that although the above reload event and refresh event are two different events, the processing results of the two events are the same, that is, rewriting the SRAM of the FPGA. In other words, the two events are different in nature, but the processing operations after the triggering event are the same.

The FPGA soft error resistance method provided by the embodiment of the present invention performs ECC and CRC checks on the loaded data by reading back the loaded data of the FPGA after the FPGA is loaded, thereby realizing the detection of any error and the correction of 1-bit error. During the readback verification process, the detected 1-bit error can be directly corrected in the memory, and the detected multi-bit error can be corrected by triggering a reload event, thereby effectively improving the FPGA's ability to resist soft errors, ensuring the effectiveness and accuracy of the FPGA function, and providing strong technical support for the application of FPGA in various interference environments.

Furthermore, by setting different error correction modes and power-on modes, users can flexibly and conveniently apply various functions according to their needs, thereby enhancing the flexibility of the solution.

Furthermore, through the timed refresh function, multiple levels of readback verification and error correction can be achieved, better ensuring the correctness of the FPGA function.

It should be noted that the FPGA soft error resistance method provided in the above embodiment of the present invention can be implemented in actual applications by software, or a combination of software and hardware. The implementation method is flexible and can be applied to a variety of scenarios with different requirements.

Correspondingly, an embodiment of the present invention further provides a device for FPGA soft error resistance, as shown in FIG3 , which is a structural schematic diagram of the device.

In this embodiment, the FPGA soft error resistance device 300 includes:

A memory module 30, used to store the loading data of the FPGA;

The read-back module 301 is used to read back the loaded data of the FPGA from the memory module 30 after the loading of the FPGA is completed;

A check module 302 is used to perform a readback check on the loaded data, wherein the readback check includes an ECC check and a CRC check; during the readback check process, for a detected multi-bit error, error correction is performed by triggering a reload event;

The loading module 303 is used to reload the FPGA after the verification module 302 triggers a reloading event, that is, to write the bit stream data stored in the external memory into the memory module 30 of the FPGA.

It should be noted that the check module 302 performs ECC check and CRC check simultaneously. Since the CRC check value is for the entire FPGA bit stream, and the ECC check value is for a segment of data, i.e., a frame of bit stream, during the check process, the check module 302 needs to perform CRC calculation and ECC check for each frame of bit stream data read back by the read-back module 301.

For a 1-bit error detected by the ECC check, error correction can be performed directly in the FPGA memory. For a multi-bit error detected by the ECC check, since error correction cannot be performed directly in the FPGA memory, in a non-limiting embodiment, the check module 302 can accumulate the number of multi-bit errors each time a multi-bit error is detected to obtain a cumulative value, and trigger a reload event when the cumulative value reaches a set threshold.

Furthermore, in order to facilitate the application requirements of different users, as shown in FIG4 , in another non-limiting embodiment of the FPGA soft error resistance device of the present invention, a register 401 may also be included for storing configuration information, wherein the configuration information includes: a power-on mode, and/or an error correction mode.

Accordingly, after the FPGA is loaded and the user configuration is completed, the readback module 301 can read the register 401 to determine the current power-on mode, and perform a readback operation according to the current power-on mode. Similarly, after the FPGA is loaded and the user configuration is completed, the check module 302 can read the register 401 to determine the current error correction mode, and perform an error correction operation according to the current error correction mode.

As shown in FIG. 5 , it is another schematic diagram of the structure of the FPGA soft error resistance device according to an embodiment of the present invention.

Different from the embodiment shown in FIG. 3 , in this embodiment, the FPGA soft error resistance device 300 further includes:

The refresh module 304 is used to refresh the loaded data of the FPGA in the memory module 30 at regular intervals.

By regularly refreshing the FPGA's loaded data, multiple levels of readback verification and error correction can be achieved, better ensuring the effectiveness and accuracy of the FPGA function.

For other related functions and implementation methods of the FPGA soft error resistance device 300, reference may be made to the related descriptions in the above method embodiments of the present invention, which will not be described in detail here.

Correspondingly, an embodiment of the present invention further provides an FPGA chip, which can execute all or part of the steps in the embodiment of the method of the present invention after loading is completed.

In a specific implementation, each module/unit included in each device or product described in the above embodiments may be a software module/unit or a hardware module/unit, or may be partly a software module/unit and partly a hardware module/unit.

For example, for each device or product applied to or integrated in a chip, each module/unit contained therein may be implemented in the form of hardware such as circuits, or at least some of the modules/units may be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules/units may be implemented in the form of hardware such as circuits; for each device or product applied to or integrated in a chip module, each module/unit contained therein may be implemented in the form of hardware such as circuits, and different modules/units may be located in the same component (such as a chip, circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented in the form of software programs. The element can be implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules/units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in the terminal, the various modules/units contained therein can be implemented in the form of hardware such as circuits, and different modules/units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal, or, at least some modules/units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal, and the remaining (if any) modules/units can be implemented in the form of hardware such as circuits.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (16)

1. A method for resisting soft errors in an FPGA, the method comprising:

After the FPGA is loaded, reading back loading data of the FPGA;

Performing readback verification on the loading data, wherein the readback verification comprises ECC verification and CRC verification;

during the read-back verification, error correction is performed by triggering a reload event for the detected multi-bit error.

2. The method of claim 1, wherein correcting errors for the detected multi-bit errors by triggering a reload event comprises:

When multi-bit errors are detected each time, the number of times of multi-bit errors is accumulated to obtain an accumulated value;

and triggering a reload event when the accumulated value reaches a set threshold.

3. The method according to claim 1, wherein the method further comprises: presetting a power-on mode, wherein the power-on mode comprises the following steps: a power-on prohibition operation mode and a power-on permission operation mode;

After the loading of the FPGA is completed, reading back the loading data of the FPGA comprises the following steps:

In the power-on prohibition operation mode, after the loading of the FPGA is completed, waiting for a user instruction, and after receiving a verification instruction of a user, reading back loading data of the FPGA;

In the power-on permission operation mode, after the loading of the FPGA is completed, the loading data of the FPGA is immediately read back.

4. The method according to claim 2, wherein the method further comprises: configuring an error correction mode;

And in the read-back verification process, performing error correction operation according to the current error correction mode.

5. The method of claim 4, wherein configuring the error correction mode comprises:

writing data indicating the error correction mode into a control register;

the method further comprises the steps of:

the current error correction mode is determined by reading the control register.

6. The method of claim 4, wherein the error correction mode comprises any one or more of: stopping, continuing, correcting and stopping, correcting and continuing;

The error correction operation according to the current error correction mode comprises the following steps:

if the current error correction mode is a stop mode, stopping the readback check to enter a waiting state until a reset event is triggered when the current frame data error is detected;

If the current error correction mode is a continuous mode, when detecting that the current frame data error is a 1-bit error, continuing to carry out read-back verification until a reset event or a reload event is triggered;

If the current error correction mode is error correction and stopping, performing error correction write-back when detecting that the current frame data error is 1 bit error, and entering a waiting state after the current error correction write-back is completed until a reset event is triggered; when detecting that the current frame data error is a multi-bit error, entering a waiting state until a reset event is triggered;

if the current error correction mode is error correction and continues, performing error correction write-back when detecting that the current frame data error is a 1-bit error, and continuing read-back verification after the current error correction write-back is completed until a reset event or a reload event is triggered.

7. The method of claim 6, wherein the method further comprises: and when the bit stream error of the current frame is detected, performing error prompt.

8. The method of claim 1, wherein reading back the loading data of the FPGA after the FPGA is loaded comprises:

and after the FPGA is loaded and the user configuration is completed, reading back the loaded data of the FPGA.

9. The method of claim 8, wherein the method further comprises:

After the user configuration is completed, a refresh event is triggered at regular time.

10. The method of claim 9, wherein the step of determining the position of the substrate comprises,

After triggering a reloading event, reloading the FPGA;

After triggering a reset event, restarting reading back the loaded data of the FPGA;

After the refresh event is triggered, the loading data of the FPGA is refreshed.

11. The method according to any one of claims 1 to 10, further comprising:

And triggering a reloading event after receiving a restarting instruction of the user.

12. An apparatus for soft error resistance of an FPGA, the apparatus comprising:

the memory module is used for storing loading data of the FPGA;

the read-back module is used for reading back the loading data of the FPGA from the memory module after the loading of the FPGA is completed;

The verification module is used for performing read-back verification on the loading data, wherein the read-back verification comprises ECC verification and CRC verification; in the read-back verification process, correcting errors of the detected multi-bit errors by triggering a reload event;

and the loading module is used for reloading the FPGA after the verification module triggers a reloading event.

13. The apparatus of claim 12, wherein the device comprises a plurality of sensors,

The check module accumulates the times of occurrence of multi-bit errors each time the multi-bit errors are detected, and obtaining an accumulated value, and triggering a reloading event when the accumulated value reaches a set threshold value.

14. The apparatus of claim 12, wherein the apparatus further comprises:

A register for storing configuration information, the configuration information comprising: a power-up mode, and/or an error correction mode;

the read-back module is used for reading the register after the FPGA is loaded and the user configuration is completed, determining the current power-on mode and performing read-back operation according to the current power-on mode;

And the verification module is used for reading the register after the FPGA is loaded and the user configuration is completed, determining the current error correction mode and carrying out error correction operation according to the current error correction mode.

15. The apparatus according to any one of claims 12 to 14, further comprising:

And the refreshing module is used for regularly refreshing the loading data of the FPGA in the memory module.

16. An FPGA chip, characterized in that the chip performs the method of preventing soft errors of an FPGA according to any of claims 1 to 11 after loading is completed.