JP4155389B2 - LIGHT EMITTING DEVICE, ITS DRIVE METHOD, AND ELECTRONIC DEVICE - Google Patents

Description

【０２８４】
(M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.)
【０２８５】
上記の論文により報告された有機発光材料（Ｐｔ錯体）の分子式を以下に示す。
【０２８６】
【化２】

【０２８７】
(M.A.Baldo, S.Lamansky, P.E.Burrrows, M.E.Thompson, S.R.Forrest, Appl.Phys.Lett.,75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
【０２８８】
上記の論文により報告された有機発光材料（Ｉｒ錯体）の分子式を以下に示す。
【０２８９】
【化３】

【０２９０】
以上のように三重項励起子からの燐光発光を利用できれば原理的には一重項励起子からの蛍光発光を用いる場合より３〜４倍の高い外部発光量子効率の実現が可能となる。
【０２９１】
なお、本実施例の構成は、実施例１〜実施例１１のいずれの構成とも自由に組み合わせて実施することが可能である。
【０２９２】
（実施例１３）
本実施例では、本発明の発光装置の封止の様子について、図２５を用いて説明する。
【０２９３】
図２５は、トランジスタが形成された素子基板をシーリング材によって封止することによって形成された発光装置の上面図であり、図２５（Ｂ）は、図２５（Ａ）のＡ−Ａ’における断面図、図２５（Ｃ）は図２５（Ａ）のＢ−Ｂ’における断面図である。
【０２９４】
基板４００１上に設けられた画素部４００２と、信号線駆動回路４００３と、第１及び第２の第１走査線駆動回路４００４ａ、ｂとを囲むようにして、シール材４００９が設けられている。また画素部４００２と、信号線駆動回路４００３と、第１及び第２の第１走査線駆動回路４００４ａ、ｂとの上にシーリング材４００８が設けられている。よって画素部４００２と、信号線駆動回路４００３と、第１及び第２の第１走査線駆動回路４００４ａ、ｂとは、基板４００１とシール材４００９とシーリング材４００８とによって、充填材４２１０で密封されている。
【０２９５】
また基板４００１上に設けられた画素部４００２と、信号線駆動回路４００３と、第１及び第２の第１走査線駆動回路４００４ａ、ｂとは、複数のＴＦＴを有している。図２５（Ｂ）では代表的に、下地膜４０１０上に形成された、信号線駆動回路４００３に含まれる駆動ＴＦＴ（但し、ここではｎチャネル型ＴＦＴとｐチャネル型ＴＦＴを図示する）４２０１及び画素部４００２に含まれるトランジスタＴｒ２ ４２０２を図示した。
【０２９６】
本実施例では、駆動ＴＦＴ４２０１には公知の方法で作製されたｐチャネル型ＴＦＴまたはｎチャネル型ＴＦＴが用いられ、トランジスタＴｒ２ ４２０２には公知の方法で作製されたｐチャネル型ＴＦＴが用いられる。また、画素部４００２には保持容量（図示せず）が設けられる。
【０２９７】
駆動ＴＦＴ４２０１及びトランジスタＴｒ２ ４２０２上には層間絶縁膜（平坦化膜）４３０１が形成され、その上にトランジスタＴｒ２ ４２０２のドレインと電気的に接続する画素電極（陽極）４２０３が形成される。画素電極４２０３としては仕事関数の大きい透明導電膜が用いられる。透明導電膜としては、酸化インジウムと酸化スズとの化合物、酸化インジウムと酸化亜鉛との化合物、酸化亜鉛、酸化スズまたは酸化インジウムを用いることができる。また、前記透明導電膜にガリウムを添加したものを用いても良い。
【０２９８】
そして、画素電極４２０３の上には絶縁膜４３０２が形成され、絶縁膜４３０２は画素電極４２０３の上に開口部が形成されている。この開口部において、画素電極４２０３の上には有機発光層４２０４が形成される。有機発光層４２０４は公知の有機発光材料または無機発光材料を用いることができる。また、有機発光材料には低分子系（モノマー系）材料と高分子系（ポリマー系）材料があるがどちらを用いても良い。
【０２９９】
有機発光層４２０４の形成方法は公知の蒸着技術もしくは塗布法技術を用いれば良い。また、有機発光層の構造は正孔注入層、正孔輸送層、発光層、電子輸送層または電子注入層を自由に組み合わせて積層構造または単層構造とすれば良い。
【０３００】
有機発光層４２０４の上には遮光性を有する導電膜（代表的にはアルミニウム、銅もしくは銀を主成分とする導電膜またはそれらと他の導電膜との積層膜）からなる陰極４２０５が形成される。また、陰極４２０５と有機発光層４２０４の界面に存在する水分や酸素は極力排除しておくことが望ましい。従って、有機発光層４２０４を窒素または希ガス雰囲気で形成し、酸素や水分に触れさせないまま陰極４２０５を形成するといった工夫が必要である。本実施例ではマルチチャンバー方式（クラスターツール方式）の成膜装置を用いることで上述のような成膜を可能とする。そして陰極４２０５は所定の電圧が与えられている。
【０３０１】
以上のようにして、画素電極（陽極）４２０３、有機発光層４２０４及び陰極４２０５からなるＯＬＥＤ４３０３が形成される。そしてＯＬＥＤ４３０３を覆うように、絶縁膜４３０２上に保護膜４２０９が形成されている。保護膜４２０９は、ＯＬＥＤ４３０３に酸素や水分等が入り込むのを防ぐのに効果的である。
【０３０２】
４００５ａは電源線に接続された引き回し配線であり、トランジスタＴｒ２ ４２０２のソース領域に電気的に接続されている。引き回し配線４００５ａはシール材４００９と基板４００１との間を通り、異方導電性フィルム４３００を介してＦＰＣ４００６が有するＦＰＣ用配線４２０６に電気的に接続される。
【０３０３】
シーリング材４００８としては、ガラス材、金属材（代表的にはステンレス材）、セラミックス材、プラスチック材（プラスチックフィルムも含む）を用いることができる。プラスチック材としては、ＦＲＰ（Ｆｉｂｅｒｇｌａｓｓ−Ｒｅｉｎｆｏｒｃｅｄ Ｐｌａｓｔｉｃｓ）板、ＰＶＦ（ポリビニルフルオライド）フィルム、マイラーフィルム、ポリエステルフィルムまたはアクリル樹脂フィルムを用いることができる。また、アルミニウムホイルをＰＶＦフィルムやマイラーフィルムで挟んだ構造のシートを用いることもできる。
【０３０４】
但し、ＯＬＥＤからの光の放射方向がカバー材側に向かう場合にはカバー材は透明でなければならない。その場合には、ガラス板、プラスチック板、ポリエステルフィルムまたはアクリルフィルムのような透明物質を用いる。
【０３０５】
また、充填材４２１０としては窒素やアルゴンなどの不活性な気体の他に、紫外線硬化樹脂または熱硬化樹脂を用いることができ、ＰＶＣ（ポリビニルクロライド）、アクリル、ポリイミド、エポキシ樹脂、シリコーン樹脂、ＰＶＢ（ポリビニルブチラル）またはＥＶＡ（エチレンビニルアセテート）を用いることができる。本実施例では充填材として窒素を用いた。
【０３０６】
また充填材４２１０を吸湿性物質（好ましくは酸化バリウム）もしくは酸素を吸着しうる物質にさらしておくために、シーリング材４００８の基板４００１側の面に凹部４００７を設けて吸湿性物質または酸素を吸着しうる物質４２０７を配置する。そして、吸湿性物質または酸素を吸着しうる物質４２０７が飛び散らないように、凹部カバー材４２０８によって吸湿性物質または酸素を吸着しうる物質４２０７は凹部４００７に保持されている。なお凹部カバー材４２０８は目の細かいメッシュ状になっており、空気や水分は通し、吸湿性物質または酸素を吸着しうる物質４２０７は通さない構成になっている。吸湿性物質または酸素を吸着しうる物質４２０７を設けることで、ＯＬＥＤ４３０３の劣化を抑制できる。
【０３０７】
図２５（Ｃ）に示すように、画素電極４２０３が形成されると同時に、引き回し配線４００５ａ上に接するように導電性膜４２０３ａが形成される。
【０３０８】
また、異方導電性フィルム４３００は導電性フィラー４３００ａを有している。基板４００１とＦＰＣ４００６とを熱圧着することで、基板４００１上の導電性膜４２０３ａとＦＰＣ４００６上のＦＰＣ用配線４２０６とが、導電性フィラー４３００ａによって電気的に接続される。
【０３０９】
本実施例の構成は、実施例１〜実施例１２に示した構成と自由に組み合わせて実施することが可能である。
【０３１０】
（実施例１４）
ＯＬＥＤを用いた発光装置は自発光型であるため、液晶ディスプレイに比べ、明るい場所での視認性に優れ、視野角が広い。従って、様々な電子機器の表示部に用いることができる。
【０３１１】
本発明の発光装置を用いた電子機器として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうるディスプレイを備えた装置）などが挙げられる。特に、斜め方向から画面を見る機会が多い携帯情報端末は、視野角の広さが重要視されるため、発光装置を用いることが望ましい。それら電子機器の具体例を図２６に示す。
【０３１２】
図２６（Ａ）はＯＬＥＤ表示装置であり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明の発光装置は表示部２００３に用いることができる。発光装置は自発光型であるためバックライトが必要なく、液晶ディスプレイよりも薄い表示部とすることができる。なお、ＯＬＥＤ表示装置は、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用表示装置が含まれる。
【０３１３】
図２６（Ｂ）はデジタルスチルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明の発光装置は表示部２１０２に用いることができる。
【０３１４】
図２６（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明の発光装置は表示部２２０３に用いることができる。
【０３１５】
図２６（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明の発光装置は表示部２３０２に用いることができる。
【０３１６】
図２６（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明の発光装置はこれら表示部Ａ２４０３、Ｂ２４０４に用いることができる。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【０３１７】
図２６（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明の発光装置は表示部２５０２に用いることができる。
【０３１８】
図２６（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９等を含む。本発明の発光装置は表示部２６０２に用いることができる。
【０３１９】
ここで図２６（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明の発光装置は表示部２７０３に用いることができる。なお、表示部２７０３は黒色の背景に白色の文字を表示することで携帯電話の消費電流を抑えることができる。
【０３２０】
なお、将来的に有機発光材料の発光輝度が高くなれば、出力した画像情報を含む光をレンズ等で拡大投影してフロント型若しくはリア型のプロジェクターに用いることも可能となる。
【０３２１】
また、上記電子機器はインターネットやＣＡＴＶ（ケーブルテレビ）などの電子通信回線を通じて配信された情報を表示することが多くなり、特に動画情報を表示する機会が増してきている。有機発光材料の応答速度は非常に高いため、発光装置は動画表示に好ましい。
【０３２２】
また、発光装置は発光している部分が電力を消費するため、発光部分が極力少なくなるように情報を表示することが望ましい。従って、携帯情報端末、特に携帯電話や音響再生装置のような文字情報を主とする表示部に発光装置を用いる場合には、非発光部分を背景として文字情報を発光部分で形成するように駆動することが望ましい。
【０３２３】
以上の様に、本発明の適用範囲は極めて広く、あらゆる分野の電子機器に用いることが可能である。また、本実施例の電子機器は実施例１〜１３に示したいずれの構成の発光装置を用いても良い。
【０３２４】
【発明の効果】
【０３２５】
上述した構成によって、本発明の発光装置は温度変化に左右されずに一定の輝度を得ることができる。また、カラー表示において、各色毎に異なる有機発光材料を有するＯＬＥＤを設けた場合でも、温度によって各色のＯＬＥＤの輝度がバラバラに変化して所望の色が得られないということを防ぐことができる。
【図面の簡単な説明】
【図１】 本発明の発光装置の上面ブロック図。
【図２】 本発明の発光装置の画素の回路図。
【図３】 駆動における画素の概略図。
【図４】 アナログ駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図５】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図６】 駆動における画素の概略図。
【図７】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図８】 本発明の発光装置の画素の回路図。
【図９】 本発明の発光装置の画素の回路図。
【図１０】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図１１】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図１２】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図１３】 デジタル駆動法における書き込み期間と表示期間の出現するタイミングを示す図。
【図１４】 本発明の発光装置の作製方法を示す図。
【図１５】 本発明の発光装置の作製方法を示す図。
【図１６】 本発明の発光装置の作製方法を示す図。
【図１７】 本発明の発光装置の画素の上面図。
【図１８】 本発明の発光装置の画素の断面図。
【図１９】 本発明の発光装置の画素の上面図。
【図２０】 信号線駆動回路のブロック図。
【図２１】 デジタル駆動法における信号線駆動回路の詳細図。
【図２２】 デジタル駆動法における電流設定回路の回路図。
【図２３】 第１走査線駆動回路のブロック図。
【図２４】 デジタル駆動法における信号線駆動回路の詳細図。
【図２５】 本発明の発光装置の外観図及び断面図。
【図２６】 本発明の発光装置を用いた電子機器の図。
【図２７】 ＯＬＥＤの電圧電流特性を示す図。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an OLED panel in which a light emitting element formed on a substrate, for example, an OLED (Organic Light Emitting Diode) is enclosed between the substrate and a cover material. The present invention also relates to an OLED module in which an IC including a controller is mounted on the OLED panel. In this specification, the OLED panel and the OLED module are collectively referred to as a light emitting device. The present invention further relates to a driving method of a light emitting device and an electronic apparatus using the light emitting device.
[0002]
[Prior art]
The OLED emits light by itself and has high visibility, is not required for a backlight necessary for a liquid crystal display device (LCD), is optimal for thinning, and has no restriction on the viewing angle. Therefore, in recent years, light emitting devices using OLEDs have attracted attention as display devices that replace CRTs and LCDs.
[0003]
The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode layer, and a cathode layer. . Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.
[0004]
In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.
[0005]
[Problems to be solved by the invention]
A problem in putting a light-emitting device into practical use has been a decrease in luminance of the OLED due to deterioration of the organic light-emitting material.
[0006]
Organic light-emitting materials are vulnerable to moisture, oxygen, light, and heat, and their deterioration is accelerated by these materials. Specifically, the speed of deterioration depends on the structure of the device that drives the light emitting device, the characteristics of the organic light emitting material, the electrode material, the conditions in the manufacturing process, the driving method of the light emitting device, and the like.
[0007]
Even if the voltage applied to the organic light emitting layer is constant, if the organic light emitting layer is deteriorated, the luminance of the OLED is lowered and the displayed image becomes unclear. In the present specification, a voltage applied to the organic light emitting layer from a pair of electrodes is defined as an OLED drive voltage (Vel).
[0008]
In addition, in the color display method using three types of OLEDs corresponding to R (red), G (green), and B (blue), the organic light emitting material constituting the organic light emitting layer differs depending on the corresponding color of the OLED. . Therefore, the organic light emitting layer of the OLED may deteriorate at a different speed for each corresponding color. In this case, as the time passes, the luminance of the OLED varies from color to color, and an image having a desired color cannot be displayed on the light emitting device.
[0009]
In addition, the temperature of the organic light emitting layer depends on the outside air temperature, the heat generated by the OLED panel itself, etc., but in general, the value of the current flowing through the OLED varies depending on the temperature. FIG. 27 shows a change in voltage-current characteristics of the OLED when the temperature of the organic light emitting layer is changed. When the voltage is constant, the OLED driving current increases as the temperature of the organic light emitting layer increases. Since the OLED drive current and the luminance of the OLED are in a proportional relationship, the larger the OLED drive current, the higher the luminance of the OLED. Thus, since the luminance of the OLED changes depending on the temperature of the organic light emitting layer, it is difficult to display a desired gradation, and the current consumption of the light emitting device increases as the temperature rises.
[0010]
Furthermore, since the degree of change in the OLED drive current due to temperature changes generally differs depending on the type of organic light-emitting material, the luminance of the OLEDs of each color may vary depending on the temperature in color display. If the luminance balance of each color is lost, a desired color cannot be displayed.
[0011]
In view of the foregoing, it is an object of the present invention to provide a light-emitting device capable of obtaining a certain luminance without being affected by deterioration of the organic light-emitting layer and temperature change, and capable of performing a desired color display. And
[0012]
[Means for Solving the Problems]
The inventor of the present invention pays attention to the fact that the latter causes less decrease in the luminance of the OLED due to deterioration when the OLED drive voltage is kept constant and the light is emitted while the current flowing through the OLED is kept constant. did. In this specification, the current flowing through the OLED is referred to as an OLED drive current (Iel). And it was thought that the change of the brightness | luminance of OLED by deterioration of OLED could be prevented by controlling the brightness | luminance of OLED not by voltage but by electric current.
[0013]
Specifically, in the present invention, the drain current Id of the transistor provided in each pixel is controlled by the signal line driver circuit. Since the drain current Id of the transistor is controlled by the signal line driver circuit, the drain current Id becomes constant regardless of the value of the load resistance.
[0014]
When the drain current Id flows, a voltage is generated between the gate electrode and the drain region of the transistor. Then, while maintaining the voltage, the drain current of the transistor is allowed to flow to the OLED through one or more circuit elements. The drain current Id has such a magnitude that the transistor operates in the saturation region.
[0015]
With the above configuration, the value of the OLED drive current flowing through the OLED is controlled by the signal line drive circuit regardless of the value of the load resistance. In other words, the OLED drive current can be controlled to a desired value without being affected by differences in transistor characteristics, OLED degradation, or the like.
[0016]
In the present invention, the above configuration can suppress a decrease in luminance of the OLED even when the organic light emitting layer is deteriorated, and as a result, a clear image can be displayed. In the case of a light emitting device for color display using OLEDs corresponding to each color, even if the organic light emitting layer of the OLED deteriorates at a different speed for each corresponding color, the balance of luminance of each color is prevented from being lost. A desired color can be displayed.
[0017]
Further, the OLED drive current can be controlled to a desired value even if the temperature of the organic light emitting layer depends on the outside air temperature, the heat generated by the OLED panel itself, or the like. Therefore, since the OLED drive current and the luminance of the OLED are proportional, it is possible to suppress the change in the luminance of the OLED, and it is possible to prevent the consumption current from increasing as the temperature rises. Further, in the case of a light emitting device for color display, since it is possible to suppress changes in the brightness of the OLEDs of each color without being influenced by temperature changes, it is possible to prevent the balance of the brightness of each color from being lost and display a desired color. can do.
[0018]
Furthermore, since the degree of change in the OLED drive current due to temperature changes generally differs depending on the type of organic light-emitting material, the luminance of the OLEDs of each color may vary depending on the temperature in color display. However, in the light emitting device of the present invention, a desired luminance can be obtained without being influenced by a temperature change, so that it is possible to prevent the balance of the luminance of each color from being lost and display a desired color.
[0019]
In a general light-emitting device, since the wiring for supplying current to each pixel itself has a resistance, the potential slightly drops depending on the length of the wiring. The drop in potential varies greatly depending on the image to be displayed. In particular, in a plurality of pixels to which current is supplied from the same wiring, when the ratio of pixels having a high number of gradations is increased, the current flowing through the wiring is increased, and a potential drop is noticeable. When the potential drops, the voltage applied to the OLED of each pixel decreases, so the current supplied to each pixel decreases. Therefore, even if an attempt is made to display a certain gradation in a certain pixel, if the number of gradations of other pixels to which current is supplied from the same wiring changes, the current supplied to the certain pixel is accordingly changed. As a result, the number of gradations also changes. However, in the light emitting device of the present invention, the measured value and the reference value can be obtained for each image to be displayed, and the OLED current can be corrected. Therefore, even if the displayed image changes, the desired number of gradations is displayed by the correction. be able to.
[0020]
Note that in the light-emitting device of the present invention, a transistor used for a pixel may be a transistor formed using single crystal silicon, or a thin film transistor using polycrystalline silicon or amorphous silicon. Further, a transistor using an organic semiconductor may be used.
[0021]
Note that the transistor provided in the pixel of the light-emitting device of the present invention may have a single-gate structure, or a double-gate structure or a multi-gate structure having a gate electrode higher than that.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the OLED panel of the present invention. Reference numeral 100 denotes a pixel portion, and a plurality of pixels 101 are formed in a matrix. Reference numeral 102 denotes a signal line driving circuit, 103 denotes a first scanning line driving circuit, and 104 denotes a second scanning line driving circuit.
[0023]
In FIG. 1, the signal line driver circuit 102, the first scan line driver circuit 103, and the second scan line driver circuit 104 are formed over the same substrate as the pixel portion 100; however, the present invention is limited to this structure. Not. The signal line driver circuit 102, the first scan line driver circuit 103, and the second scan line driver circuit 104 may be formed over a different substrate from the pixel unit 100, and may be connected to the pixel unit 100 through an FPC or the like. . In FIG. 1, the signal line driver circuit 102, the first scan line driver circuit 103, and the second scan line driver circuit 104 are provided one by one, but the present invention is not limited to this configuration. The number of the signal line driving circuit 102, the first scanning line driving circuit 103, and the second scanning line driving circuit 104 can be arbitrarily set by a designer.
[0024]
In this specification, the connection means an electrical connection.
[0025]
In FIG. 1, the pixel portion 100 is provided with signal lines S1 to Sx, power supply lines V1 to Vx, first scanning lines Ga1 to Gay, and second scanning lines Gb1 to Gby. Note that the number of signal lines and power supply lines is not necessarily the same. The number of first scanning lines and the number of second scanning lines is not necessarily the same. The light emitting device of the present invention does not necessarily have all of these wirings, and other different wirings may be provided in addition to these wirings.
[0026]
The power supply lines V1 to Vx are kept at a predetermined potential. Although FIG. 1 shows the configuration of a light emitting device that displays a monochrome image, the present invention may be a light emitting device that displays a color image. In that case, the heights of the potentials of the power supply lines V1 to Vx need not be kept all the same, and may be changed for each corresponding color.
[0027]
FIG. 2 shows a detailed configuration of the pixel 101 shown in FIG. 2 includes a signal line Si (one of S1 to Sx), a first scanning line Gaj (one of Ga1 to Gay), and a second scanning line Gbj (one of Gb1 to Gby). 1) and a power supply line Vi (one of V1 to Vx).
[0028]
The pixel 101 includes a transistor Tr1 (current control transistor or first transistor), a transistor Tr2 (drive transistor or second transistor), a transistor Tr3 (first switching transistor or third transistor), a transistor Tr4 ( A second switching transistor or a fourth transistor), an OLED 106, and a storage capacitor 105.
[0029]
The gate electrodes of the transistors Tr3 and Tr4 are both connected to the first scanning line Gaj.
[0030]
One of the source region and the drain region of the transistor Tr3 is connected to the signal line Si, and the other is connected to the gate electrode of the transistor Tr1. One of the source region and the drain region of the transistor Tr4 is connected to the signal line Si, and the other is connected to the drain region of the transistor Tr1.
[0031]
The source region of the transistor Tr1 is connected to the power supply line Vi, and the drain region is connected to the source region of the transistor Tr2. The gate electrode of the transistor Tr2 is connected to the second scanning line Gbj. A drain region of the transistor Tr2 is connected to a pixel electrode included in the OLED 106.
[0032]
The OLED 106 has an anode and a cathode. In this specification, when the anode is used as a pixel electrode (first electrode), the cathode is called a counter electrode (second electrode), and the cathode is used as a pixel electrode. Refers to the anode as the counter electrode.
[0033]
The potential of the counter electrode is kept at a constant height.
[0034]
Note that the transistor Tr3 and the transistor Tr4 may be either an n-channel transistor or a p-channel transistor. However, the transistor Tr3 and the transistor Tr4 have the same polarity.
[0035]
The transistors Tr1 and Tr2 may be either n-channel transistors or p-channel transistors. However, the transistors Tr1 and Tr2 have the same polarity. When the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are n-channel transistors.
[0036]
The storage capacitor 105 is formed between the gate electrode of the transistor Tr1 and the power supply line Vi. The storage capacitor 105 is provided to maintain a voltage (gate voltage) between the gate electrode and the source region of the transistor Tr1, but is not necessarily provided.
[0037]
(Embodiment 2)
Next, driving of the light-emitting device illustrated in FIG. 2 will be described with reference to FIG. In this embodiment mode, the operation of each pixel of the light-emitting device illustrated in FIG. 2 is described by being divided into a writing period Ta and a display period Td.
[0038]
In the writing period Ta, the first scanning line Gaj is selected. When the first scanning line Gaj is selected, the transistors Tr3 and Tr4 whose gate electrodes are connected to the first scanning line Gaj are turned on. Note that in the writing period Ta, the second scanning line Gbj is not selected, and Tr2 is off.
[0039]
Based on the potential of the video signal input to the signal line driver circuit 102, a constant current Ic flows between the signal lines S1 to Sx and the power supply lines V1 to Vx. In this specification, the current Ic is referred to as a signal current.
[0040]
FIG. 3A is a schematic diagram of the pixel 101 in the case where a constant current Ic flows through the signal line Si in the writing period Ta. Reference numeral 107 denotes a constant current source included in the signal line driver circuit 102. Reference numeral 108 denotes a terminal for connection to a power source for applying a potential to the counter electrode.
[0041]
In the writing period Ta, the transistors Tr3 and Tr4 are in an on state. Therefore, when a constant current Ic flows through the signal line Si, the constant current Ic flows between the source region and the drain region of the transistor Tr1. At this time, the magnitude of the current Ic is controlled in the constant current source 107 so that the transistor Tr1 operates in the saturation region.
[0042]
In the saturation region, V _GS Is the potential difference (gate voltage) between the gate electrode and the source region, μ is the mobility of the transistor, C ₀ Is the gate capacitance per unit area, W / L is the ratio of the channel width W to the channel length L of the channel formation region, V _TH Is the threshold, μ is the mobility, and the drain current of the transistor Tr1 is Id.
[0043]
[Formula 1]
Id = μC ₀ W / L (V _GS -V _TH ) ² / 2
[0044]
In equation 1, μ, C ₀ , W / L, V _TH Are all fixed values determined by individual transistors. The drain current Id of the transistor Tr1 is kept at Id = Ic by the constant current source 107. Therefore, as can be seen from Equation 1, the gate voltage V of the transistor Tr1 _GS Is determined by the value of the signal current Ic.
[0045]
When the writing period Ta ends, the display period Td starts. In the display period Td, the first scanning line Gaj is not selected, and the second scanning line Gbj is selected.
[0046]
FIG. 3B is a schematic diagram of pixels in the display period Td. The transistors Tr3 and Tr4 are off. The transistor Tr2 is on.
[0047]
In the display period Td, the transistor Tr1 has the V V determined in the writing period Ta. _GS Is maintained as is. Therefore, the value of the drain current Id of the transistor Tr1 is maintained at the same value as the signal current Ic. Further, since the transistor Tr2 is on, the drain current Id flows to the OLED 106 via the transistor Tr2. Therefore, in the display period Td, an OLED drive current having the same magnitude as the signal current Ic flows to the OLED 106, and the OLED 106 emits light with a luminance corresponding to the magnitude of the OLED drive current.
[0048]
The writing period Ta and the display period Td appear in all the pixels. The appearance timing differs for each pixel of each line. Note that in this specification, of the plurality of pixels included in the pixel portion, all the pixels having the same first scanning line or the same second scanning line are referred to as pixels on the same line.
[0049]
In the case of a driving method using an analog video signal (analog driving method), the magnitude of Ic is determined by the analog video signal, and the OLED 106 emits light with a luminance corresponding to the magnitude of Ic. Is displayed. In this case, one image is displayed when one writing period Ta and one display period Td appear in all the pixels. A period from the start of the writing period Ta in any one pixel to the end of the display period Td in all pixels is referred to as a frame period. Successive frame periods overlap each other.
[0050]
FIG. 4 shows an example of a timing chart in the analog driving method. One frame period has y line periods, and each first scanning line is selected in each line period. In each line period, a predetermined signal current Ic (Ic1 to Icx) flows through each signal line. In FIG. 4, the values of signal currents flowing through the signal lines in the line period Lj (j = 1 to y) are represented as Ic1 [Lj] to Icx [Lj].
[0051]
The timing at which the writing period Ta and the display period Td are started is shifted for each pixel of each line, and the timing at which the writing period of the pixel of each line appears does not overlap.
[0052]
On the other hand, in the case of a time grayscale driving method (digital driving method) using a digital video signal, one image is displayed by repeatedly appearing a writing period Ta and a display period Td in one frame period in each pixel. It is possible. When an image is displayed by an n-bit video signal, at least n writing periods corresponding to each bit and n display periods are provided in one frame period. The n writing periods (Ta1 to Tan) and the n display periods (Td1 to Tdn) correspond to each bit of the video signal.
[0053]
FIG. 5 shows a timing at which n writing periods (Ta1 to Tan) and n display periods (Td1 to Tdn) appear in one frame period. The horizontal axis indicates time, and the vertical axis indicates the position of the first scanning line included in the pixel.
[0054]
Next to the writing period Tam (m is an arbitrary number from 1 to n), a display period corresponding to the same number of bits, in this case Tdm, appears. The writing period Ta and the display period Td are collectively called a subframe period SF. A subframe period having a writing period Tam and a display period Tdm corresponding to the m-th bit is SFm.
[0055]
The length of the display periods Td1 to Tdn is Td1: Td2:...: Tdn = 2 ⁰ : 2 ¹ : ...: 2 ^n-1 Meet.
[0056]
Note that a subframe period having a long display period may be divided into several parts in order to improve image quality on display. The specific division method is disclosed in Japanese Patent Application Laid-Open No. 2002-023696 and Japanese Patent Application No. 2001-257163, and can be referred to.
[0057]
In the driving method shown in FIG. 5, gradation is displayed by controlling the sum of the lengths of the display periods during which light is emitted in one frame period.
[0058]
In the present invention, the above configuration can suppress a decrease in luminance of the OLED even when the organic light emitting layer is deteriorated, and as a result, a clear image can be displayed. In the case of a light emitting device for color display using OLEDs corresponding to each color, even if the organic light emitting layer of the OLED deteriorates at a different speed for each corresponding color, the balance of luminance of each color is prevented from being lost. A desired color can be displayed.
[0059]
Further, the OLED drive current can be controlled to a desired value even if the temperature of the organic light emitting layer depends on the outside air temperature, the heat generated by the OLED panel itself, or the like. Therefore, since the OLED drive current and the luminance of the OLED are proportional, it is possible to suppress the change in the luminance of the OLED, and it is possible to prevent the consumption current from increasing as the temperature rises. Further, in the case of a light emitting device for color display, since it is possible to suppress changes in the brightness of the OLEDs of each color without being influenced by temperature changes, it is possible to prevent the balance of the brightness of each color from being lost and display a desired color. can do.
[0060]
Furthermore, since the degree of change in the OLED drive current due to temperature changes generally differs depending on the type of organic light-emitting material, the luminance of the OLEDs of each color may vary depending on the temperature in color display. However, in the light emitting device of the present invention, a desired luminance can be obtained without being influenced by a temperature change, so that it is possible to prevent the balance of the luminance of each color from being lost and display a desired color.
[0061]
In a general light-emitting device, since the wiring for supplying current to each pixel itself has a resistance, the potential slightly drops depending on the length of the wiring. The drop in potential varies greatly depending on the image to be displayed. In particular, in a plurality of pixels to which current is supplied from the same wiring, when the ratio of pixels having a high number of gradations is increased, the current flowing through the wiring is increased, and a potential drop is noticeable. When the potential drops, the voltage applied to the OLED of each pixel decreases, so the current supplied to each pixel decreases. Therefore, even if an attempt is made to display a certain gradation in a certain pixel, if the number of gradations of other pixels to which current is supplied from the same wiring changes, the current supplied to the certain pixel is accordingly changed. As a result, the number of gradations also changes. However, in the light emitting device of the present invention, the measured value and the reference value can be obtained for each image to be displayed, and the OLED current can be corrected. Therefore, even if the displayed image changes, the desired number of gradations is displayed by the correction. be able to.
[0062]
(Embodiment 3)
In this embodiment, an example of driving the light emitting device shown in FIG. 2 which is different from that in Embodiment 2 will be described with reference to FIGS. In this embodiment mode, the operation of each pixel of the light-emitting device illustrated in FIG. 2 is described by being divided into a writing period Ta, a display period Td, and a non-display period Te. Note that the operation of the pixel in the writing period Ta and the display period Td has already been described in Embodiment Mode 2, and thus the operation of the pixel in the non-display period Te will be described here.
[0063]
The non-display period Te appears after the display period Td ends and before the display period Td appears. In the non-display period Td, the first scanning line Gaj and the second scanning line Gbj are not selected.
[0064]
FIG. 6 shows a schematic diagram of pixels in the non-display period Te. The transistors Tr3 and Tr4 are off. The transistor Tr2 is also turned off. Therefore, the OLED drive current does not flow through the OLED 106 and the OLED 106 does not emit light.
[0065]
The non-display period Te does not necessarily appear after all the display periods Td. However, when the display period of the pixels on the first line ends before the writing period of the pixels of all lines ends, the non-display period appears after the display period.
[0066]
The driving method of this embodiment is mainly used in driving with a digital video signal. In a time grayscale driving method (digital driving method) using a digital video signal, one image can be displayed by repeatedly appearing a writing period Ta and a display period Td within one frame period in each pixel. Is possible. When an image is displayed using an n-bit video signal, at least n writing periods and n display periods are provided in one frame period. The n writing periods (Ta1 to Tan) and the n display periods (Td1 to Tdn) correspond to each bit of the video signal.
[0067]
FIG. 7 shows a timing at which n writing periods (Ta1 to Tan), n display periods (Td1 to Tdn), and l non-display periods (Te1 to Tel) appear in one frame period. Note that, in order to simplify the description, a case of l = n−3 will be described in the present embodiment. The horizontal axis indicates time, and the vertical axis indicates the position of the first scanning line included in the pixel. In addition, since the writing period is short, the start timing of the writing periods Ta1 to Tan corresponding to each bit is indicated by an arrow in order to make the drawing easier to see. Also, for each bit, the period from the start of the pixel writing period of the first line to the end of the pixel writing period of the y-th line is denoted by ΣTa1 to ΣTan.
[0068]
In the writing period Ta1, the drain current of the transistor Tr1 is controlled by the digital video signal of the first bit in order from the pixels of the first line. Then, when the display period Td1 is started next, the transistors Tr3 and Tr4 are turned off sequentially from the pixel on the first line, and the transistor Tr2 is turned on, whereby a drain current flows to the OLED 106. Therefore, the OLED 106 is in a light emitting or non-light emitting state.
[0069]
Then, the non-display period Te1 is started, and the transistors Tr3 and Tr4 are kept off and the transistor Tr2 is turned off in order from the pixel on the first line. Therefore, the drain current does not flow through the OLED 106, and the OLED 106 is turned off.
[0070]
Then, the writing period Ta2 is started, and the above-described operation is repeated until the non-display period Te (n-3) ends.
[0071]
When the non-display period Te (n-3) ends, the writing period Ta (n-2) starts, and the drain current of the transistor Tr1 is sequentially generated by the digital video signal of the (n-2) th bit in order from the pixels of the first line. Is controlled. Then, when the display period Td (n−2) is started next, the transistors Tr3 and Tr4 are turned off sequentially from the pixel on the first line, and the transistor Tr2 is turned on, so that a drain current flows to the OLED 106. Therefore, the OLED 106 is in a light emitting or non-light emitting state.
[0072]
Then, the writing period Ta (n−1) is started, and the above-described operation is repeated until the display period Tdn ends.
[0073]
After Tdn ends in the pixels on the first line, one frame period ends, and the writing period Ta1 of the next frame period starts again in the pixels on the first line. Then, the above-described operation is repeated again. The timing at which one frame period starts and the timing at which one frame period ends have a time difference for each pixel of each line.
[0074]
When the display period Tdn ends for all the pixels, one image can be displayed.
[0075]
Note that the length of the display period is Td1: Td2: Td3:...: Td (n−1): Tdn = 2. ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^(n-1) And 2 in combination with this display period ⁿ Of the gradations, a desired gradation display can be performed.
[0076]
【Example】
Examples of the present invention will be described below.
[0077]
(Example 1)
In this embodiment, a structure of a pixel different from that in FIG.
[0078]
Unlike the OLED panel shown in FIG. 1, the OLED panel included in the light emitting device of this embodiment does not have the second scanning line driving circuit. In the present embodiment, hereinafter, the first scanning line driving circuit is simply referred to as a scanning line driving circuit.
[0079]
The OLED panel of this embodiment includes a pixel portion in which a plurality of pixels are formed in a matrix, a signal line driver circuit, and a scanning line driver circuit.
[0080]
The signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion, or may be formed over different substrates and connected to the pixel portion through an FPC or the like. Further, the number of signal line driver circuits and scanning line driver circuits can be arbitrarily set by a designer.
[0081]
In the pixel portion, signal lines S1 to Sx, power supply lines V1 to Vx, and scanning lines G1 to Gy are provided. Note that the number of signal lines and power supply lines is not necessarily the same. The light emitting device of the present invention does not necessarily have all of these wirings, and other different wirings may be provided in addition to these wirings.
[0082]
The power supply lines V1 to Vx are kept at a predetermined potential. The potential levels of the power supply lines V1 to Vx are not necessarily the same.
[0083]
FIG. 8 shows a detailed configuration of the pixel of this embodiment. A pixel 201 illustrated in FIG. 8 includes a signal line Si (one of S1 to Sx), a scanning line Gj (one of G1 to Gy), and a power supply line Vi (one of V1 to Vx). Have.
[0084]
The pixel 201 includes a transistor Tr1 (current control transistor or first transistor), a transistor Tr2 (drive transistor or second transistor), a transistor Tr3 (first switching transistor or third transistor), a transistor Tr4 ( A second switching transistor or a fourth transistor), an OLED 206, and a storage capacitor 205.
[0085]
The gate electrodes of the transistors Tr3 and Tr4 are both connected to the scanning line Gj.
[0086]
One of the source region and the drain region of the transistor Tr3 is connected to the signal line Si, and the other is connected to the gate electrode of the transistor Tr1. One of the source region and the drain region of the transistor Tr4 is connected to the signal line Si, and the other is connected to the drain region of the transistor Tr1.
[0087]
The source region of the transistor Tr1 is connected to the power supply line Vi, and the drain region is connected to the source region of the transistor Tr2. The gate electrode of the transistor Tr2 is connected to the scanning line Gj. A drain region of the transistor Tr2 is connected to a pixel electrode included in the OLED 206.
[0088]
The OLED 206 has an anode and a cathode.
[0089]
The potential of the counter electrode is kept at a constant height.
[0090]
Note that the transistors Tr3 and Tr4 may be either n-channel transistors or p-channel transistors. However, the transistor Tr3 and the transistor Tr4 have the same polarity.
[0091]
Transistors Tr1 and Tr2 have opposite polarities to transistors Tr3 and Tr4. Therefore, Tr2 is off when the transistors Tr3 and Tr4 are on, and conversely, Tr2 is on when the transistors Tr3 and Tr4 are off.
[0092]
When the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are n-channel transistors.
[0093]
The storage capacitor 205 is formed between the gate electrode of the transistor Tr1 and the power supply line Vi. Although the storage capacitor 205 is provided to maintain a voltage (gate voltage) between the gate electrode and the source region of the transistor Tr1, it is not necessarily provided.
[0094]
The pixel shown in FIG. 8 operates with the driving method shown in Embodiment Mode 2. That is, as shown in FIG. 3, the operation can be described by being divided into a writing period and a display period. Note that Embodiment Mode 2 can be referred to for a detailed operation method of each pixel, and is omitted here.
[0095]
(Example 2)
In this example, a structure of a pixel different from those in FIGS. 2 and 8 in the light-emitting device of the present invention will be described.
[0096]
The OLED panel included in the light emitting device of this embodiment is similar to the OLED panel shown in FIG. 1, a pixel portion in which a plurality of pixels are formed in a matrix, a signal line driving circuit, a first scanning line driving circuit, And a second scanning line driving circuit.
[0097]
The signal line driver circuit, the first scan line driver circuit, and the second scan line driver circuit may be formed over the same substrate as the pixel portion, or may be formed over different substrates, via an FPC or the like. It may be connected to the pixel portion. Further, the number of the signal line driving circuit, the first scanning line driving circuit, and the second scanning line driving circuit can be arbitrarily set by the designer.
[0098]
The pixel portion is provided with signal lines S1 to Sx, power supply lines V1 to Vx, first scanning lines Ga1 to Gay, and second scanning lines Gb1 to Gby. Note that the number of signal lines and power supply lines is not necessarily the same. Further, the number of the first scanning lines and the number of the second scanning lines are not necessarily the same. The light emitting device of the present invention does not necessarily have all of these wirings, and other different wirings may be provided in addition to these wirings.
[0099]
The power supply lines V1 to Vx are kept at a predetermined potential. The potential levels of the power supply lines V1 to Vx are not necessarily the same.
[0100]
FIG. 9 shows a detailed configuration of the pixel of this embodiment. The pixel 211 shown in FIG. 9 includes a signal line Si (one of S1 to Sx), a first scanning line Gaj (one of Ga1 to Gay), and a second scanning line Gbj (one of Gb1 to Gby). 1) and a power supply line Vi (one of V1 to Vx).
[0101]
The pixel 211 includes a transistor Tr1 (current control transistor or first transistor), a transistor Tr2 (drive transistor or second transistor), a transistor Tr3 (first switching transistor or third transistor), a transistor Tr4 ( A second switching transistor or a fourth transistor), a transistor Tr5 (an erasing transistor or a fifth transistor), an OLED 216, and a storage capacitor 215.
[0102]
The gate electrodes of the transistors Tr3 and Tr4 are both connected to the first scanning line Gaj.
[0103]
One of the source region and the drain region of the transistor Tr3 is connected to the signal line Si, and the other is connected to the gate electrode of the transistor Tr1. One of the source region and the drain region of the transistor Tr4 is connected to the signal line Si, and the other is connected to the drain region of the transistor Tr1.
[0104]
The source region of the transistor Tr1 is connected to the power supply line Vi, and the drain region is connected to the source region of the transistor Tr2. The gate electrode of the transistor Tr2 is connected to the first scanning line Gaj. A drain region of the transistor Tr2 is connected to a pixel electrode included in the OLED 216.
[0105]
The gate electrode of the transistor Tr5 is connected to the second scanning line Gbj. One of the source region and the drain region of the transistor Tr5 is connected to the power supply line Vi, and the other is connected to the gate electrode of the transistor Tr1.
[0106]
The OLED 216 has an anode and a cathode.
[0107]
The potential of the counter electrode is kept at a constant height.
[0108]
Note that the transistors Tr3 and Tr4 may be either n-channel transistors or p-channel transistors. However, the transistor Tr3 and the transistor Tr4 have the same polarity.
[0109]
Transistors Tr1 and Tr2 have opposite polarities to transistors Tr3 and Tr4. Therefore, Tr2 is off when the transistors Tr3 and Tr4 are on, and conversely, Tr2 is on when the transistors Tr3 and Tr4 are off.
[0110]
When the anode is used as the pixel electrode and the cathode is used as the counter electrode, the transistors Tr1 and Tr2 are p-channel transistors. Conversely, when the anode is used as the counter electrode and the cathode is used as the pixel electrode, the transistors Tr1 and Tr2 are n-channel transistors.
[0111]
The storage capacitor 215 is formed between the gate electrode of the transistor Tr1 and the power supply line Vi. Although the storage capacitor 215 is provided to maintain a voltage (gate voltage) between the gate electrode and the source region of the transistor Tr1, it is not necessarily provided.
[0112]
The pixel shown in FIG. 9 operates by the driving method shown in Embodiment Mode 3. However, in the case of the pixel shown in FIG. 9, the operation of the pixel in the non-display period is different from that shown in FIG. In the case of the pixel shown in FIG. 9, when the transistor Tr5 is turned on in the non-display period, the gate voltage of Tr1 is close to 0, and Tr1 is turned off. Since the transistor Tr2 is on, but Tr1 is off, the OLED drive current does not flow through the OLED 216, and the OLED 216 is turned off. Therefore, the operation can be described by being divided into a writing period, a display period, and a non-display period. Note that Embodiment Mode 3 can be referred to for detailed driving timing, and is omitted here.
[0113]
(Example 3)
In this example, the order in which the subframe periods SF1 to SFn appear in the driving method described in Embodiment 2 will be described.
[0114]
FIG. 10 shows the timing at which n writing periods (Ta1 to Tan) and n display periods (Td1 to Tdn) appear in one frame period. The horizontal axis indicates time, and the vertical axis indicates the position of the first scanning line included in the pixel. The detailed operation of each pixel may be referred to Embodiment Mode 2, and is omitted here.
[0115]
In the driving method of this embodiment, the subframe period (SFn in this embodiment) having the longest display period in one frame period is not provided at the beginning and end of one frame period. In other words, another subframe period included in the same frame period appears before and after the subframe period having the longest display period in one frame period.
[0116]
With the above-described configuration, it is possible to make it difficult for human eyes to recognize display unevenness that occurs due to adjacent display periods that emit light between adjacent frame periods when intermediate grayscale display is performed.
[0117]
The configuration of this embodiment is effective when n ≧ 3. In addition, this embodiment can be implemented by being freely combined with Embodiment 1.
[0118]
Example 4
In this embodiment, an example of a driving method different from that in Embodiment 3 will be described.
[0119]
FIG. 11 shows the timing at which n + 1 writing periods (Ta1 to Ta (n + 1)) and n + 1 display periods (Td1 to Td (n + 1)) appear in one frame period. The horizontal axis indicates time, and the vertical axis indicates the position of the first scanning line included in the pixel. The detailed operation of each pixel may be referred to Embodiment Mode 2, and is omitted here.
[0120]
In this embodiment, n + 1 subframe periods SF1 to SF (n + 1) are provided in one frame period corresponding to an n-bit digital video signal. The subframe periods SF1 to SF (n + 1) have n + 1 writing periods (Ta1 to Ta (n + 1)) and n + 1 display periods (Td1 to Td (n + 1)).
[0121]
A subframe period having a writing period Tam (m is an arbitrary number from 1 to n + 1) and a display period Tdm is SFm. Next to the writing period Tam, a display period corresponding to the same number of bits, in this case Tdm, appears.
[0122]
The subframe periods SF1 to SFn-1 correspond to each bit of the digital video signal of 1 to (n-1) bits. The subframe periods SFn and SF (n + 1) correspond to the nth bit digital video signal.
[0123]
In this embodiment, the subframe periods SFn and SF (n + 1) corresponding to the same bit digital video signal do not appear continuously. In other words, another subframe period is provided between subframe periods SFn and SF (n + 1) corresponding to digital video signals of the same bit.
[0124]
By repeatedly appearing the writing period Ta and the display period Td in one frame period, one image can be displayed.
[0125]
The length of the display periods Td1 to Td (n + 1) is Td1: Td2:...: (Tdn + Td (n + 1)) = 2 ⁰ : 2 ¹ : ...: 2 ^n-1 Meet.
[0126]
In the driving method of the present invention, gradation is displayed by controlling the sum of the lengths of the display periods during which light is emitted in one frame period.
[0127]
In the present embodiment, the display unevenness caused by the adjacent display periods in the adjacent frame periods when the display of the intermediate gray scale is performed by the above configuration is the driving shown in FIGS. 5 and 10. Compared with the method, it can be made difficult to be recognized by human eyes.
[0128]
In this embodiment, the case where there are two subframe periods corresponding to the same bit has been described, but the present invention is not limited to this. Three or more subframe periods corresponding to the same bit may be provided in one frame period.
[0129]
In this embodiment, a plurality of subframe periods corresponding to the most significant bit digital video signal are provided. However, the present invention is not limited to this. A plurality of subframe periods corresponding to digital video signals of bits other than the most significant bit may be provided. In addition, the number of bits provided with a plurality of corresponding subframe periods is not limited to one, and a configuration may be adopted in which a plurality of subframe periods correspond to some bits.
[0130]
The configuration of this embodiment is effective when n ≧ 2. Further, this embodiment can be implemented in combination with Embodiments 1 and 3.
[0131]
(Example 5)
In this example, the order of appearance of the driving method shown in Embodiment Mode 3 will be described. However, in this embodiment, a case where n = 6 and l = 5 will be described. Note that this embodiment describes an example of the driving method of the present invention, and the present invention is not limited to the configuration of the present embodiment with respect to the number of bits n and l of the corresponding digital video signal. The configuration of this embodiment is effective when the number of bits of the digital video signal is 3 or more.
[0132]
FIG. 12 shows the timing when the writing period, the display period, and the non-display period appear in the driving method of this embodiment. The horizontal axis indicates time, and the vertical axis indicates the positions of the first scanning line and the second scanning line that the pixel has. However, since the writing period is short, the start timing of the writing periods Ta1 to Ta6 corresponding to each bit is indicated by an arrow in order to make the drawing easier to see. Further, for each corresponding bit, a period (ΣTa1 to ΣTa6) from the start of the writing period of the pixel on the first line to the end of the writing period of the pixel on the yth line is indicated by an arrow.
[0133]
The detailed operation of the pixel can be referred to Embodiment Mode 3, and thus description thereof is omitted here.
[0134]
First, the writing period Ta4 starts in the pixels on the first line. When the writing period Ta4 is started, a 4-bit digital video signal is input to the pixels on the first line.
[0135]
When the writing period Ta4 ends in the pixels in the first line, the writing period Ta4 starts in order in the pixels in the second and subsequent lines. As in the case of the pixels on the first line, a 4-bit digital video signal is input to the pixels on each line.
[0136]
On the other hand, in parallel with the start of the writing period Ta4 in the pixels on the second and subsequent lines, the display period Td4 is started on the pixels in the first line. When the display period Td4 is started, the pixels on the first line display by the 4-bit digital video signal.
[0137]
Then, after the display period Td4 is started in the pixels on the first line, the writing period Ta4 is also sequentially ended in the pixels on and after the second line, and the display period Td4 is started. Then, the pixels of each line perform display by the 4-bit digital video signal.
[0138]
On the other hand, after the display period Td4 starts in the pixels of the second and subsequent lines, the display period Td4 ends and the non-display period Te4 starts in the pixels of the first line. In parallel with the start of the display period Td4 for pixels in the second and subsequent lines, the display period Td4 may end and the non-display period Te4 may start for the pixels of the first line.
[0139]
When the non-display period Te4 is started, the pixels on the first line no longer display.
[0140]
Next, after the non-display period Te4 is started in the pixels on the first line, the display period Td4 is also sequentially ended in the pixels on and after the second line, and the non-display period Te4 is started. Therefore, the pixels of each line do not display.
[0141]
On the other hand, in parallel with the start of the non-display period Te4 in the pixels of the second and subsequent lines, or after the non-display period Te4 has started in all the pixels, the write period Ta5 starts in the pixels of the first line Is done.
[0142]
When the writing period Ta5 is started in the pixels on the first line, a 5-bit digital video signal is input to the pixels on the first line. Then, when the writing period Ta5 ends in the pixels on the first line, the writing period Ta5 also starts in order in the pixels on and after the second line.
[0143]
On the other hand, after the writing period Ta5 ends for the pixels on the first line, the display period Td5 starts on the pixels on the first line in parallel with the writing period Ta5 starting on the pixels on the second and subsequent lines. Is done. In the display period Td5, as in the display period Td5, the pixels perform display using the digital video signal of the fifth bit.
[0144]
Then, after the display period Td5 is started in the pixels on the first line, the writing period Ta5 is sequentially ended in the pixels on and after the second line, and the display period Td5 is started.
[0145]
Next, after the display period Td5 is started in the pixels of all lines, the display period Td5 is ended and the writing period Ta2 is started in the pixels of the first line.
[0146]
When the writing period Ta2 starts in the pixels on the first line, the digital video signal of the second bit is input to the pixels on the first line.
[0147]
Then, when the writing period Ta2 ends in the pixels on the first line, the writing period Ta2 starts sequentially in the pixels on and after the second line. As in the case of the pixels on the first line, the digital video signal of the second bit is input to the pixels on each line.
[0148]
On the other hand, in parallel with the start of the writing period Ta2 in the pixels in the second and subsequent lines, the display period Td2 is started in the pixels in the first line. When the display period Td2 is started, the pixels on the first line perform display by the digital video signal of the second bit.
[0149]
Then, after the display period Td2 is started in the pixels on the first line, the writing period Ta2 is also sequentially ended in the pixels on and after the second line, and the display period Td2 is started. Then, the pixels of each line perform display by the digital video signal of the second bit.
[0150]
On the other hand, simultaneously with the start of the display period Td2 in the pixels of the second and subsequent lines, the display period Td2 ends and the non-display period Te2 starts in the pixels of the first line.
[0151]
When the non-display period Te2 is started, the pixels on the first line no longer display.
[0152]
Next, after the non-display period Te2 is started in the pixels on the first line, the display period Td2 is also sequentially ended in the pixels on and after the second line, and the non-display period Te2 is started. Therefore, the pixels of each line do not display.
[0153]
On the other hand, in parallel with the start of the non-display period Te2 in the pixels of the second and subsequent lines, or after the non-display period Te2 has started in all the pixels, the write period Ta3 starts in the pixels of the first line Is done.
[0154]
The above-described operation is repeated until the digital video signals of all the bits 1 to 6 are input to the pixels. For each pixel of each line, the writing period Ta, the display period Td, and the non-display period Te are set. Appears repeatedly.
[0155]
After all the display periods Td1 to Td6 are completed for the pixels on the first line, one frame period is completed for the pixels on the first line, and the first writing period (Ta4 in this embodiment) of the next frame period starts again. Is done. In addition, after the end of one frame period in the pixels on the first line, the end of the one frame period also occurs in the pixels on and after the second line, and the writing period Ta4 of the next frame period starts again.
[0156]
Then, the above-described operation is repeated again. The timing at which one frame period starts and the timing at which one frame period ends have a time difference for each pixel of each line.
[0157]
One image can be displayed at the end of one frame period for all lines of pixels.
[0158]
In this embodiment, the length of the display period is Td1: Td2:...: Td5: Td6 = 2. ⁰ : 2 ¹ : ...: 2 ^Four : 2 ^Five And 2 in combination with this display period ⁶ Of the gradations, a desired gradation display can be performed.
[0159]
By obtaining the sum of the lengths of the display periods during which the OLED emits light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example, in the case of this embodiment, assuming that the luminance when the pixel emits light in the entire display period is 100%, the luminance of 5% can be expressed when the pixel emits light at Td1 and Td2, and Td3 and Td5 are expressed as When selected, a luminance of 32% can be expressed.
[0160]
Note that since the writing periods of the pixels in each line do not overlap with each other, the writing period in the pixels on the first line is started after the writing period in the pixels on the y-th line ends.
[0161]
Further, in this embodiment, the length of the display period Td5 for the pixels in each line is the period from the start of the pixel writing period Ta5 for the first line to the end of the pixel writing period Ta5 for the y-th line ( It is important to be longer than ΣTa5).
[0162]
The display periods Td1 to Td6 may appear in any order. For example, in one frame period, it is possible to cause the display period to appear in the order of Td3, Td5, Td2,. However, it is necessary that the writing periods in the pixels of each line do not overlap each other.
[0163]
In the driving method of the present invention, the period from the start of the pixel writing period Ta for the first line to the end of the pixel writing period Ta for the y line, in other words, one bit of digital video for all pixels. The length of the display period of the pixels in each line can be made shorter than the period in which the signal is written. Therefore, even when the number of bits of the digital video signal is increased, the length of the display period corresponding to the lower bits can be shortened, so that a high-definition image can be displayed without flickering the screen. .
[0164]
In addition, the light emitting device of the present invention can obtain a certain luminance without being influenced by temperature change. In addition, in the color display, even when an OLED having different EL materials for each color is provided, it is possible to prevent a desired color from being obtained because the luminance of the OLED of each color varies depending on the temperature.
[0165]
In the driving method of this embodiment, the longest display period (Td6 in this embodiment) in one frame period is not provided at the beginning and end of one frame period. In other words, another display period included in the same frame period appears before and after the longest display period in one frame period.
[0166]
With the above-described configuration, it is possible to make it difficult for human eyes to recognize display unevenness that occurs due to adjacent display periods that emit light between adjacent frame periods when intermediate grayscale display is performed.
[0167]
In addition, this embodiment can be implemented in combination with Embodiment 2 freely.
[0168]
(Example 6)
In this embodiment, an example of a driving method using an n-bit digital video signal, which is different from that in Embodiment 5, will be described. However, in this embodiment, a case where l = n−2 will be described.
[0169]
The driving method of this embodiment has a display period Tdn and a display period Td (n + 1) corresponding to the same most significant bit digital video signal. A writing period Tan and a writing period Ta (n + 1) are provided corresponding to the display period Tdn and the display period Td (n + 1), respectively.
[0170]
In this embodiment, the display periods Tdn and Td (n + 1) corresponding to the digital video signal of the same bit do not appear continuously. In other words, another display period is provided between the display periods Tdn and Td (n + 1) corresponding to the digital video signal of the same bit.
[0171]
FIG. 13 shows timings at which the writing period, the display period, and the non-display period appear in the driving method of this embodiment. The horizontal axis indicates time, and the vertical axis indicates the positions of the first scanning line and the second scanning line that the pixel has. However, since the writing period is short, the start timing of the writing periods Ta1 to Ta (n + 1) corresponding to each bit is indicated by an arrow in order to make the drawing easier to see. In addition, for each corresponding bit, a period (ΣTa1 to ΣTa (n + 1)) from the start of the pixel writing period of the first line to the end of the pixel writing period of the yth line is indicated by an arrow.
[0172]
The detailed operation of the pixel is the same as that in the embodiment, and thus the description thereof is omitted here.
[0173]
The length of the display periods Td1 to Td (n + 1) is as follows: Td1: Td2:...: Td (n-1) :( Tdn + Td (n + 1)) = 2 ⁰ : 2 ¹ : ...: 2 ^n-1 Meet.
[0174]
By controlling the sum of the lengths of the display periods during which light is emitted during one frame period, gradation is displayed.
[0175]
In the present embodiment, the display unevenness caused by the adjacent display periods emitting light in adjacent frame periods when the display of the intermediate gray scale is performed by the above-described configuration is compared with the case of the second embodiment. Can be difficult to recognize.
[0176]
In this embodiment, the case where there are two display periods corresponding to the same bit has been described, but the present invention is not limited to this. Three or more display periods corresponding to the same bit may be provided in one frame period.
[0177]
In this embodiment, a plurality of display periods corresponding to the most significant bit digital video signal are provided. However, the present invention is not limited to this. A plurality of display periods corresponding to digital video signals of bits other than the most significant bit may be provided. In addition, the number of bits provided with a plurality of corresponding display periods is not limited to one, and a configuration in which a plurality of display periods correspond to some of the bits may be employed.
[0178]
The configuration of this embodiment is effective when n ≧ 2. In addition, this embodiment can be implemented by being freely combined with Embodiment 2 or 5.
[0179]
(Example 7)
In this example, a method for manufacturing a light-emitting device of the present invention will be described. Note that in this embodiment, a method for manufacturing the pixel illustrated in FIGS. Further, in this embodiment, only a cross-sectional view of the transistors Tr2 and Tr4 included in the pixel is shown, but the transistors Tr1 and Tr3 can also be formed by referring to the manufacturing method of this embodiment. In addition, a transistor included in another pixel (for example, the transistor Tr5 in the pixel illustrated in FIG. 9) can be formed in a similar manner. Further, in this embodiment, TFTs included in driving circuits (signal line driving circuit, first scanning line driving circuit, and second scanning line driving circuit) provided around the pixel portion are simultaneously formed on the same substrate as the TFT in the pixel portion. An example of forming is shown.
[0180]
First, as shown in FIG. 14A, a silicon oxide film is formed on a substrate 301 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass, or aluminoborosilicate glass. A base film 302 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 302a made of O is formed to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly SiH _Four , N ₂ A silicon oxynitride silicon film 302b formed from O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Although the base film 302 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked.
[0181]
The island-shaped semiconductor layers 303 to 306 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The island-like semiconductor layers 303 to 306 are formed to a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.
[0182]
In order to fabricate a crystalline semiconductor film by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four Use a laser. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The conditions for crystallization are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 400 [mJ / cm. ² ] (Typically 200-300 [mJ / cm ² ]). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 30 to 300 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm. ² ] (Typically 350-500 [mJ / cm ² ]) Then, a laser beam condensed linearly with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlay rate of the linear laser beam at this time is 50. Perform as ~ 90 [%].
[0183]
Next, a gate insulating film 307 covering the island-shaped semiconductor layers 303 to 306 is formed. The gate insulating film 307 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ And a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], a high frequency (13.56 [MHz]), and a power density of 0.5 to 0.8 [W / cm]. ² ] Can be formed by discharging. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].
[0184]
Then, a first conductive film 308 and a second conductive film 309 for forming a gate electrode are formed over the gate insulating film 307. In this embodiment, the first conductive film 308 is formed with Ta to a thickness of 50 to 100 [nm], and the second conductive film 309 is formed with W to a thickness of 100 to 300 [nm].
[0185]
The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed to a thickness of about 10 to 50 [nm] on the Ta base. It can be easily obtained.
[0186]
When forming a W film, it is formed by sputtering using W as a target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. Therefore, when using the sputtering method, a W target having a purity of 99.9999 [%] or a purity of 99.99 [%] is used, and sufficient consideration is given so that impurities are not mixed from the gas phase during film formation. By forming the W film, a resistivity of 9 to 20 [μΩcm] can be realized.
[0187]
In this embodiment, the first conductive film 308 is Ta and the second conductive film 309 is W. However, the present invention is not particularly limited, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As another example of a combination other than the present embodiment, a combination in which the first conductive film 308 is formed of tantalum nitride (TaN) and the second conductive film 309 is W is used. Is made of tantalum nitride (TaN), the second conductive film 309 is made of Al, the first conductive film 308 is made of tantalum nitride (TaN), and the second conductive film 309 is made of Cu. Can be mentioned. (Fig. 14 (A))
[0188]
Next, a resist mask 310 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four And Cl ₂ Then, 500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1 [Pa] to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ When W is mixed, the W film and the Ta film are etched to the same extent.
[0189]
Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the over-etching process. become. Thus, the first shape conductive layers 311 to 315 (the first conductive layers 311a to 315a and the second conductive layers 311b to 315b) formed of the first conductive layer and the second conductive layer by the first etching process. Form. At this time, in the gate insulating film 307, a region which is not covered with the first shape conductive layers 311 to 315 is etched and thinned by about 20 to 50 [nm]. The surface of the mask 310 was also etched by the above etching.
[0190]
Then, an impurity element imparting n-type is added by performing a first doping process. As a doping method, an ion doping method or an ion implantation method may be used. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁴ [atoms / cm ² The acceleration voltage is set to 60 to 100 [keV]. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 311 to 314 serve as a mask for the impurity element imparting n-type, and the first impurity regions 317 to 320 are formed in a self-aligning manner. The first impurity regions 317 to 320 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} [atoms / cm ^Three An impurity element imparting n-type is added in a concentration range of (Fig. 14B)
[0191]
Next, as shown in FIG. 14C, a second etching process is performed without removing the resist mask 310. CF as etching gas _Four And Cl ₂ And O ₂ Then, the W film is selectively etched. At this time, second shape conductive layers 325 to 329 (first conductive layers 325a to 329a and second conductive layers 325b to 329b) are formed by the second etching treatment. At this time, in the gate insulating film 307, a region that is not covered with the second shape conductive layers 325 to 329 is further etched by about 20 to 50 [nm] to form a thinned region.
[0192]
CF of W film and Ta film _Four And Cl ₂ The etching reaction by the mixed gas can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressure of fluoride and chloride of W and Ta, WF, which is fluoride of W ₆ Is extremely high, other WCl _Five , TaF _Five , TaCl _Five Are comparable. Therefore, CF _Four And Cl ₂ With this mixed gas, both the W film and the Ta film are etched. However, an appropriate amount of O is added to this mixed gas. ₂ When CF is added _Four And O ₂ Reacts to CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, O ₂ When Ta is added, the surface of Ta is oxidized. Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.
[0193]
Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV], and 1 × 10 ¹³ [atoms / cm ² A new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. 14B. Doping is performed using the second shape conductive layers 325 to 328 as masks against the impurity elements so that the impurity elements are also added to regions below the first conductive layers 325 a to 328 a. Thus, third impurity regions 332 to 335 are formed. The concentration of phosphorus (P) added to the third impurity regions 332 to 335 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 325a to 328a. Note that, in the semiconductor layer overlapping the tapered portions of the first conductive layers 325a to 328a, although the impurity concentration slightly decreases inward from the end portions of the tapered portions of the first conductive layers 325a to 328a, The concentration is similar.
[0194]
A third etching process is performed as shown in FIG. CHF as etching gas ₆ And using a reactive ion etching method (RIE method). By the third etching treatment, the tapered portions of the first conductive layers 325a to 329a are partially etched, and the region where the first conductive layer overlaps with the semiconductor layer is reduced. By the third etching treatment, third-shaped conductive layers 336 to 340 (first conductive layers 336a to 340a and second conductive layers 336b to 340b) are formed. At this time, in the gate insulating film 307, a region which is not covered with the third shape conductive layers 336 to 340 is further etched and thinned by about 20 to 50 [nm].
[0195]
By the third etching process, in the third impurity regions 332 to 335, the third impurity regions 332 a to 335 a overlapping with the first conductive layers 336 a to 339 a, the first impurity region, the third impurity region, Second impurity regions 332b to 335b are formed.
[0196]
Then, as shown in FIG. 15C, fourth impurity regions 343 to 348 having a conductivity type opposite to the first conductivity type are formed in the island-like semiconductor layers 303 and 306 forming the p-channel TFT. . Impurity regions are formed in a self-aligning manner using the third shape conductive layers 336b and 339b as masks against the impurity element. At this time, the island-shaped semiconductor layers 304 and 305 and the third-shaped conductive layer 340 forming the n-channel TFT are covered with a resist mask 350 in advance. Phosphorus is added to the impurity regions 343 to 348 at different concentrations, but diborane (B ₂ H ₆ ), And the impurity concentration in each region is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} [atoms / cm ^Three ] To be.
[0197]
Through the above steps, impurity regions are formed in each island-like semiconductor layer. The third shape conductive layers 336 to 339 overlapping with the island-shaped semiconductor layers function as gate electrodes. The third shape conductive layer 340 functions as a gate wiring.
[0198]
After removing the resist mask 350, a process of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for the third shape conductive layers 336 to 340 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done. Note that the third shape conductive layer 340 is a gate wiring, and part of the conductive layer 340 functions as a gate electrode of the transistor Tr1 (not shown), and the source region or the drain region of the transistor Tr3 (not shown). It is connected to the.
[0199]
Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100 [%] hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0200]
Next, as shown in FIG. 16A, a first interlayer insulating film 355 is formed with a thickness of 100 to 200 [nm] from a silicon oxynitride film. A second interlayer insulating film 356 made of an organic insulating material is formed thereon, and then contact holes are formed in the first interlayer insulating film 355, the second interlayer insulating film 356, and the gate insulating film 307. The connection wirings 357 to 363 are formed by patterning. Reference numeral 363 denotes a power supply line, and reference numeral 360 denotes a signal line.
[0201]
As the second interlayer insulating film 356, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 356 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably, it may be 1 to 5 [μm] (more preferably 2 to 4 [μm]).
[0202]
The contact holes are formed by dry etching or wet etching, contact holes reaching n-type impurity regions 317 to 319 or p-type impurity regions 345 and 348, contact holes reaching gate wiring 340, and capacitor wiring (not shown). ) Contact holes (not shown) are formed.
[0203]
Further, as the connection wirings 357 to 363, a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by a sputtering method is desired. The one patterned into a shape is used. Of course, other conductive films may be used.
[0204]
Next, the pixel electrode 365 in contact with the connection wiring (drain wiring) 362 is formed by patterning. Note that the connection wiring includes a source wiring and a drain wiring. The source wiring is a wiring connected to the source region of the active layer, and the drain wiring means a wiring connected to the drain region.
[0205]
Further, in this embodiment, an ITO film having a thickness of 110 [nm] is formed as the pixel electrode 365 and patterned. The pixel electrode 365 is placed in contact with the connection wiring 362 to make contact. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 365 becomes the anode of the OLED. (FIG. 16 (A))
[0206]
Next, as shown in FIG. 16B, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 [nm], and an opening is formed at a position corresponding to the pixel electrode 365. Then, a third interlayer insulating film 366 functioning as a bank is formed. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic light emitting layer due to the step becomes a significant problem, so care must be taken.
[0207]
Next, the organic light emitting layer 367 and the cathode (MgAg electrode) 368 are continuously formed by using a vacuum deposition method without being released to the atmosphere. The thickness of the organic light emitting layer 367 is 80 to 200 [nm] (typically 100 to 120 [nm]), and the thickness of the cathode 368 is 180 to 300 [nm] (typically 200 to 250 [nm]. nm]).
[0208]
In this step, an organic light emitting layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the organic light emitting layer has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic light emitting layer only at necessary portions.
[0209]
That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic light emitting layer that emits red light is selectively formed using the mask. Next, a mask that hides all but the pixels corresponding to green is set, and an organic light emitting layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light emitting organic light emitting layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.
[0210]
Here, a method of forming three types of OLEDs corresponding to RGB is used, but a method of combining a white light emitting OLED and a color filter, a blue or blue green light emitting OLED and a phosphor (fluorescent color conversion layer: CCM). ), A method of superimposing OLEDs corresponding to RGB using a transparent electrode as a cathode (counter electrode), or the like may be used.
[0211]
Note that a known material can be used for the organic light emitting layer 367. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic light emitting layer.
[0212]
Next, the cathode 368 is formed. In this embodiment, MgAg is used as the cathode 368, but the present invention is not limited to this. Other known materials may be used for the cathode 368.
[0213]
A portion where the pixel electrode 365, the organic light emitting layer 367, and the cathode 368 overlap corresponds to the OLED 375.
[0214]
Next, a protective electrode 369 is formed by vapor deposition. The protective electrode 369 may be formed continuously with the cathode 368 without opening to the atmosphere. The protective electrode 369 is effective for protecting the organic light emitting layer 367 from moisture and oxygen.
[0215]
The protective electrode 369 is provided in order to prevent the cathode 368 from being deteriorated, and a metal film mainly composed of aluminum is typically used. Of course, other materials may be used. Further, since the organic light emitting layer 367 and the cathode 368 are very sensitive to moisture, it is desirable that the protective electrode 369 is continuously formed without being released to the atmosphere to protect the organic light emitting layer from the outside air.
[0216]
Finally, a passivation film 370 made of a silicon nitride film is formed to a thickness of 300 [nm]. By forming the passivation film 370, the organic light emitting layer 367 can be protected from moisture and the like, and the reliability of the OLED can be further improved. Note that the passivation film 370 is not necessarily provided.
[0217]
Thus, a light emitting device having a structure as shown in FIG. 16B is completed. Reference numeral 371 denotes a p-channel TFT in the driver circuit section, reference numeral 372 denotes an n-channel TFT in the driver circuit section, reference numeral 373 denotes a transistor Tr4, and reference numeral 374 denotes a transistor Tr2.
[0218]
By the way, the light emitting device of this embodiment can exhibit extremely high reliability and improve the operation characteristics by arranging TFTs having an optimal structure not only in the pixel portion but also in the driving circuit. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. As a result, the drive frequency of the signal line driver circuit can be made 10 [MHz] or higher.
[0219]
Actually, when the state shown in FIG. 16B is completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and low degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the OLED is improved.
[0220]
In addition, when the airtightness is improved by processing such as packaging, a connector for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached.
[0221]
Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.
[0222]
This embodiment can be implemented by freely combining with Embodiments 1-6.
[0223]
(Example 8)
In this embodiment, a top view of a pixel formed in Embodiment 2 will be described. FIG. 17 shows a top view of the pixel of this embodiment. Note that FIG. 17 corresponds to a top view of the pixel at the time when the process of FIG. In FIG. 17, various insulating films such as an interlayer insulating film and a gate insulating film are omitted in order to clarify the positions of wirings and semiconductor layers. Further, wirings formed in the same layer are indicated by the same hatch.
[0224]
A cross-sectional view taken along a broken line AA ′ in FIG. 17 corresponds to a portion AA ′ in FIG. 18 is a cross-sectional view taken along broken line BB ′ in FIG.
[0225]
The pixel shown in FIG. 17 includes a connection wiring 360 (Si) functioning as a signal line, a first scanning line 380 (Gaj), a second scanning line 381 (Gbj), and a power supply line 363 (Vi) one by one. Have. Then, 382 and 327 which are parts of the first scanning line 380 correspond to the gate electrodes of the transistors Tr3 and Tr4, respectively.
[0226]
One of the source region and the drain region of the transistor Tr3 is connected to the signal line 360, and the other is connected to the gate wiring 340 through the connection wiring 383. A part 384 of the gate wiring 340 functions as a gate electrode of the transistor Tr1.
[0227]
One of the source region and the drain region of the transistor Tr4 is connected to the signal line 360, and the other is connected to the drain region of the transistor Tr1 and the source region of the transistor Tr2 through the connection wiring 361.
[0228]
The source region of the transistor Tr1 is connected to the power supply line 363. Further, the drain region of the transistor Tr2 is connected to the pixel electrode 365 through the connection wiring 362.
[0229]
A part 328 of the second scanning line 381 functions as a gate electrode of the transistor Tr2.
[0230]
The power supply line 363 overlaps the gate wiring 340 with the first and second interlayer insulating films interposed therebetween. The gate wiring 340 overlaps with the capacitor wiring 385 formed by adding an impurity to the semiconductor film with a gate insulating film (not shown) interposed therebetween. The power supply line 363 and the capacitor wiring 385 are connected through a contact hole. Note that a portion where the gate wiring 340 and the capacitor wiring 385 overlap with each other with the gate insulating film interposed therebetween corresponds to the storage capacitor 386. Further, a portion where the power supply line 363 overlaps the gate wiring 340 with the first and second interlayer insulating films interposed therebetween may be used as a storage capacitor.
[0231]
By forming the power supply line 363 above a partition wall (bank) that separates pixels, a storage capacitor and a power supply line can be formed without reducing the aperture ratio.
[0232]
The top view of the pixel shown in this embodiment is merely an example of the structure of the present invention, and the top view of the pixel shown in FIG. 17 is not limited to the structure shown in this embodiment. In addition, a present Example can be implemented combining freely with Examples 1-7.
[0233]
Example 9
In this embodiment, a top view of the pixel shown in FIG. 8 will be described. FIG. 19 shows a top view of the pixel of this embodiment. Note that FIG. 17 corresponds to a top view of the pixel in a stage before the formation of the pixel electrode and before the organic light emitting layer is formed. In FIG. 19, various insulating films such as an interlayer insulating film and a gate insulating film are omitted in order to clarify the positions of wirings and semiconductor layers. Further, wirings formed in the same layer are indicated by the same hatch.
[0234]
The pixel illustrated in FIG. 19 includes a connection wiring 560 (Si) functioning as a signal line, a scanning line 580 (Gj), and a power supply line 563 (Vi). Then, 582, 527, and 528, which are part of the scanning line 580, correspond to the gate electrodes of the transistors Tr3, Tr4, and Tr2, respectively.
[0235]
One of a source region and a drain region of the transistor Tr3 is connected to the signal line 560, and the other is connected to the gate wiring 540 through the connection wiring 583. A part 584 of the gate wiring 540 functions as a gate electrode of the transistor Tr1.
[0236]
One of the source region and the drain region of the transistor Tr4 is connected to the signal line 560, and the other is connected to the drain region of the transistor Tr1 and the source region of the transistor Tr2 through the connection wiring 561.
[0237]
A source region of the transistor Tr1 is connected to the power supply line 563. In addition, the drain region of the transistor Tr2 is connected to the pixel electrode 565 through a connection wiring 562.
[0238]
The power supply line 563 overlaps with the gate wiring 540 with the first and second interlayer insulating films interposed therebetween. The gate wiring 540 overlaps with the capacitor wiring 585 formed by adding an impurity to the semiconductor film with a gate insulating film (not shown) interposed therebetween. The power supply line 563 and the capacitor wiring 585 are connected via a contact hole. Note that a portion where the gate wiring 540 and the capacitor wiring 585 overlap with the gate insulating film interposed therebetween corresponds to the storage capacitor 586. Further, a portion where the power supply line 563 overlaps with the gate wiring 540 with the first and second interlayer insulating films interposed therebetween may be used as a storage capacitor.
[0239]
By forming the power supply line 563 above a partition wall (bank) that divides each pixel, a storage capacitor and a power supply line can be formed without reducing the aperture ratio.
[0240]
The top view of the pixel shown in this embodiment is merely an example of the structure of the present invention, and the top view of the pixel shown in FIG. 19 is not limited to the structure shown in this embodiment. In addition, a present Example can be implemented combining freely with Examples 1-7.
[0241]
(Example 10)
In this embodiment, a structure of a driver circuit (a signal line driver circuit and a first scan line driver circuit) included in the light-emitting device of the present invention driven using a digital video signal will be described.
[0242]
FIG. 20 is a block diagram illustrating the configuration of the signal line driver circuit 601. Reference numeral 602 denotes a shift register, reference numeral 603 denotes a storage circuit A, reference numeral 604 denotes a storage circuit B, and reference numeral 605 denotes a constant current circuit.
[0243]
A clock signal CLK and a start pulse signal SP are input to the shift register 602. A digital video signal (Digital Video Signals) is input to the memory circuit A 603, and a latch signal (Latch Signals) is input to the memory circuit B 604. A constant signal current Ic output from the constant current circuit 605 is input to the signal line.
[0244]
FIG. 21 shows a more detailed configuration of the signal line driver circuit 601.
[0245]
When the clock signal CLK and the start pulse signal SP are input to the shift register 602 from a predetermined wiring, a timing signal is generated. The timing signal is input to each of the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603. Note that at this time, the timing signal generated in the shift register 602 may be buffered and amplified by a buffer or the like and then input to the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603.
[0246]
When a timing signal is input to the memory circuit A 603, a 1-bit digital video signal input to the video signal line 610 is sequentially input to each of the plurality of latches A (LATA — 1 to LATA_x) in synchronization with the timing signal. Written and retained.
[0247]
In this embodiment, when the digital video signal is taken into the memory circuit A603, the digital video signal is sequentially input to the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603. It is not limited to. A plurality of stages of latches included in the memory circuit A 603 may be divided into several groups, and so-called divided driving may be performed in which digital video signals are input simultaneously in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.
[0248]
The time until the digital video signal is completely written to the latches of all the stages of the memory circuit A 603 is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.
[0249]
When one line period ends, a latch signal (Latch Signal) is supplied to the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B604 through the latch signal line 609. At this moment, digital video signals held in the plurality of latches A (LATA_1 to LATA_x) included in the memory circuit A603 are simultaneously written and held in the plurality of latches B (LATB_1 to LATB_x) included in the memory circuit B604. .
[0250]
After the digital video signal has been sent to the storage circuit B 604, the next 1-bit digital video signal is sequentially written on the basis of the timing signal from the shift register 602.
[0251]
During the second line period, the digital video signal written and held in the memory circuit B 604 is input to the constant current circuit 605.
[0252]
The constant current circuit 605 has a plurality of current setting circuits (C1 to Cx). When a digital video signal is input to each of the current setting circuits (C1 to Cx), a constant current Ic flows through the signal line according to 1 or 0 information of the digital video signal, or a power supply line through the signal line Either one of the potentials V1 to Vx is applied.
[0253]
FIG. 22 shows an example of a specific configuration of the current setting circuit C1. The current setting circuits C2 to Cx have the same configuration.
[0254]
The current setting circuit C1 includes a constant current source 631, four transmission gates SW1 to SW4, and two inverters Inb1 and Inb2. Note that the polarity of the transistor 650 included in the constant current source 631 is the same as the polarity of the transistors Tr1 and Tr2 included in the pixel.
[0255]
Switching of SW1 to SW4 is controlled by a digital video signal output from LATB_1 included in the memory circuit B604. The digital video signal input to SW1 and SW3 and the digital video signal input to SW2 and SW4 are inverted by Inb1 and Inb2. Therefore, SW2 and SW4 are off when SW1 and SW3 are on, and SW2 and SW4 are on when SW1 and SW3 are off.
[0256]
When SW1 and SW3 are on, a current Ic having a predetermined value other than 0 is input from the constant current source 631 to the signal line S1 via SW1 and SW3.
[0257]
Conversely, when SW2 and SW4 are on, the current Ic from the constant current source 631 is dropped to the ground via SW2. Further, the power supply potentials of the power supply lines V1 to Vx are applied to the signal line S1 through SW4, and Ic≈0.
[0258]
Referring to FIG. 21 again, the above operation is simultaneously performed in all the current setting circuits (C1 to Cx) included in constant current circuit 605 within one line period. Therefore, the value of the signal current Ic input to all the signal lines is selected by the digital video signal.
[0259]
Next, the configuration of the first scanning line driving circuit will be described.
[0260]
FIG. 23 is a block diagram showing a configuration of the first scanning line driving circuit 641.
[0261]
The first scan line driver circuit 641 includes a shift register 642 and a buffer 643, respectively. In some cases, a level shifter may be provided.
[0262]
In the first scan line driver circuit 641, the timing signal is generated by inputting the clock CLK and the start pulse signal SP to the shift register 642. The generated timing signal is buffered and amplified in the buffer 643 and supplied to the corresponding scanning line.
[0263]
The scanning lines are connected to the gate electrodes of the first switching transistor and the second switching transistor of pixels for one line. Since the first switching transistor and the second switching transistor of the pixels for one line must be turned on all at once, a buffer 643 that can flow a large current is used.
[0264]
The drive circuit used in the present invention is not limited to the configuration shown in this embodiment. Furthermore, the constant current circuit shown in this embodiment is not limited to the configuration shown in FIG. The constant current circuit used in the present invention can select any one of the binary values that can be taken by the signal current Ic by a digital video signal, and can cause any signal current having the selected value to flow through the signal line. You may have a structure.
[0265]
Further, the second scanning line driving circuit may have the same configuration as the first scanning line driving circuit.
[0266]
The structure of a present Example can be implemented in combination freely with Examples 1-9.
[0267]
(Example 11)
In this embodiment, a structure of a signal line driver circuit included in the light-emitting device of the present invention driven by an analog video signal will be described. Note that since the structure shown in FIG. 23 can be used as the structure of the scan line driver circuit, description thereof is omitted here.
[0268]
FIG. 24A shows a block diagram of the signal line driver circuit 401 of this embodiment. Reference numeral 402 denotes a shift register, 403 denotes a buffer, 404 denotes a sampling circuit, and 405 denotes a current conversion circuit.
[0269]
A clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402. When a clock signal (CLK) and a start pulse signal (SP) are input to the shift register 402, a timing signal is generated.
[0270]
The generated timing signal is amplified or buffer amplified in the buffer 403 and input to the sampling circuit 404. Note that a level shifter may be provided instead of the buffer to amplify the timing signal. Further, both a buffer and a level shifter may be provided.
[0271]
FIG. 24B illustrates specific structures of the sampling circuit 404 and the current conversion circuit 405. Note that the sampling circuit 404 is connected to the buffer 403 at a terminal 410.
[0272]
The sampling circuit 404 is provided with a plurality of switches 411. An analog video signal is input to the sampling circuit 404 from the video signal line 406, and the switch 411 samples the analog video signal in synchronization with the timing signal and inputs the analog video signal to the subsequent current conversion circuit 405. Note that in FIG. 24B, only the current conversion circuit connected to one of the switches 411 included in the sampling circuit 404 is shown as the current conversion circuit 405. However, in FIG. It is assumed that the current conversion circuit 405 as shown in FIG.
[0273]
In this embodiment, only one transistor is used for the switch 411. However, the switch 411 may be any switch that can sample an analog video signal in synchronization with the timing signal, and is not limited to the configuration of this embodiment.
[0274]
The sampled analog video signal is input to a current output circuit 412 included in the current conversion circuit 405. The current output circuit 412 outputs a current (signal current) having a value corresponding to the voltage of the input video signal. In FIG. 24, a current output circuit is formed by using an amplifier and a transistor. However, the present invention is not limited to this configuration, and a circuit that can output a current having a value corresponding to the voltage of an input signal. I just need it.
[0275]
The signal current is input to a reset circuit 417 included in the current conversion circuit 405. The reset circuit 406 includes two analog switches 413 and 414, an inverter 416, and a power source 415.
[0276]
A reset signal (Res) is input to the analog switch 414, and a reset signal (Res) inverted by the inverter 416 is input to the analog switch 413. The analog switch 413 and the analog switch 414 operate in synchronization with the inverted reset signal and the reset signal, respectively, and when one is on, one is off.
[0277]
When the analog switch 413 is on, the signal current is input to the corresponding signal line. Conversely, when the analog switch 414 is on, the potential of the power source 415 is applied to the signal line, and the signal line is reset. Note that the potential of the power supply 415 is preferably almost the same as the potential of the power supply line provided in the pixel, and the closer the current that can flow to the signal line when the signal line is reset, the better. .
[0278]
Note that the signal line is desirably reset during the return period. However, if it is outside the period during which the image is displayed, it can be reset to a period other than the blanking period as necessary.
[0279]
Note that the signal line driver circuit and the first scan line driver circuit for driving the light-emitting device of the present invention are not limited to the structures shown in this embodiment. The configuration of the present embodiment can be implemented by freely combining with the configurations shown in the first to tenth embodiments.
[0280]
(Example 12)
In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. Thereby, low power consumption, long life, and light weight of the OLED can be achieved.
[0281]
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown. (T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
[0282]
The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.
[0283]
[Chemical 1]

[0284]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
[0285]
The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.
[0286]
[Chemical 2]

[0287]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
[0288]
The molecular formula of the organic light-emitting material (Ir complex) reported by the above paper is shown below.
[0289]
[Chemical 3]

[0290]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.
[0291]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-11.
[0292]
(Example 13)
In this example, the state of sealing of the light-emitting device of the present invention will be described with reference to FIG.
[0293]
25 is a top view of a light-emitting device formed by sealing an element substrate over which a transistor is formed with a sealing material, and FIG. 25B is a cross-sectional view taken along line AA ′ in FIG. FIG. 25C is a cross-sectional view taken along the line BB ′ of FIG.
[0294]
A sealant 4009 is provided so as to surround the pixel portion 4002, the signal line driver circuit 4003, and the first and second first scan line driver circuits 4004a and 400b provided over the substrate 4001. Further, a sealing material 4008 is provided over the pixel portion 4002, the signal line driver circuit 4003, and the first and second first scan line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the signal line driver circuit 4003, and the first and second first scan line driver circuits 4004a and 400b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. ing.
[0295]
The pixel portion 4002, the signal line driver circuit 4003, and the first and second first scan line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. In FIG. 25B, typically, a driving TFT (here, an n-channel TFT and a p-channel TFT are illustrated) 4201 included in the signal line driver circuit 4003 formed over the base film 4010 and a pixel The transistor Tr2 4202 included in the portion 4002 is illustrated.
[0296]
In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driving TFT 4201, and a p-channel TFT manufactured by a known method is used for the transistor Tr2 4202. In addition, the pixel portion 4002 is provided with a storage capacitor (not illustrated).
[0297]
An interlayer insulating film (planarization film) 4301 is formed over the driving TFT 4201 and the transistor Tr2 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the transistor Tr2 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0298]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0299]
As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0300]
On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0301]
As described above, the OLED 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed on the insulating film 4302 so as to cover the OLED 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the OLED 4303.
[0302]
Reference numeral 4005a denotes a lead wiring connected to the power supply line, which is electrically connected to the source region of the transistor Tr2 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001, and is electrically connected to the FPC wiring 4206 included in the FPC 4006 through the anisotropic conductive film 4300.
[0303]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0304]
However, when the emission direction of light from the OLED is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0305]
As the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0306]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the OLED 4303 can be suppressed.
[0307]
As shown in FIG. 25C, the conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0308]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4206 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0309]
The configuration of the present embodiment can be implemented by freely combining the configurations shown in Embodiments 1 to 12.
[0310]
(Example 14)
Since a light emitting device using an OLED is a self-luminous type, it is superior in visibility in a bright place and has a wide viewing angle as compared with a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.
[0311]
As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, A portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, or the like), an image playback device equipped with a recording medium (specifically, a playback medium such as a digital video disc (DVD)) A device having a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.
[0312]
FIG. 26A illustrates an OLED display device which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The OLED display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.
[0313]
FIG. 26B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.
[0314]
FIG. 26C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.
[0315]
FIG. 26D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.
[0316]
FIG. 26E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A 2403, a display portion B 2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A 2403 and B 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0317]
FIG. 26F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention can be used for the display portion 2502.
[0318]
FIG. 26G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The light-emitting device of the present invention can be used for the display portion 2602.
[0319]
FIG. 26H shows a cellular phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0320]
If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.
[0321]
In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.
[0322]
Further, since the light emitting part consumes power in the light emitting device, it is desirable to display information so that the light emitting part is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.
[0323]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic apparatus of this embodiment may use the light-emitting device having any structure shown in Embodiments 1 to 13.
[0324]
【The invention's effect】
[0325]
With the above-described configuration, the light-emitting device of the present invention can obtain a certain luminance without being affected by temperature changes. Further, in color display, even when an OLED having a different organic light-emitting material for each color is provided, it is possible to prevent a desired color from being obtained because the luminance of each color OLED varies with temperature.
[Brief description of the drawings]
FIG. 1 is a top block diagram of a light-emitting device of the present invention.
FIG. 2 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 3 is a schematic diagram of a pixel in driving.
FIG. 4 is a diagram showing timings at which a writing period and a display period appear in the analog driving method.
FIG. 5 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
FIG. 6 is a schematic diagram of a pixel in driving.
FIG. 7 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
FIG. 8 is a circuit diagram of a pixel of the light emitting device of the present invention.
FIG. 9 is a circuit diagram of a pixel of the light-emitting device of the present invention.
FIG. 10 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
FIG. 11 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
FIG. 12 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
FIG. 13 is a diagram showing timings at which a writing period and a display period appear in the digital driving method.
14A to 14C illustrate a method for manufacturing a light-emitting device of the present invention.
FIGS. 15A to 15C illustrate a method for manufacturing a light-emitting device of the present invention. FIGS.
FIG. 16 illustrates a method for manufacturing a light-emitting device of the present invention.
FIG. 17 is a top view of a pixel of a light-emitting device of the present invention.
FIG. 18 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
FIG. 19 is a top view of a pixel of a light-emitting device of the present invention.
FIG. 20 is a block diagram of a signal line driver circuit.
FIG. 21 is a detailed diagram of a signal line driver circuit in a digital driving method.
FIG. 22 is a circuit diagram of a current setting circuit in the digital driving method.
FIG. 23 is a block diagram of a first scanning line driving circuit.
FIG. 24 is a detailed diagram of a signal line driver circuit in a digital driving method.
FIGS. 25A and 25B are an external view and a cross-sectional view of a light-emitting device of the present invention. FIGS.
FIG. 26 is a diagram of an electronic device using the light-emitting device of the present invention.
FIG. 27 is a graph showing voltage-current characteristics of an OLED.

Claims (12)

A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light emitting element, a power supply line, a signal line, a first scanning line, and a second scanning line. A light emitting device having a scanning line,
The second, the third and the gate electrode of the fourth transistor are both connected to the first scan line,
One of the source region and the drain region of the third transistor is connected to the signal line, and the other is connected to the gate electrode of the first transistor,
One of the source region and the drain region of the fourth transistor is connected to the signal line, and the other is connected to the drain region of the first transistor,
A source region of the first transistor is connected to the power line;
A source region and a drain region of the second transistor, to one drain region of said first transistor, and the other is connected to a pixel electrode to which the light emitting element has,
A gate electrode of the fifth transistor is connected to the second scanning line;
One of the source region and the drain region of the fifth transistor is connected to the power supply line, and the other is connected to the gate electrode of the first transistor. 2. The light emitting device according to claim 1, further comprising a storage capacitor provided between a gate electrode and a source region of the first transistor. The third and the fourth transistor, light emitting device according to claim 1 or claim 2, wherein the polarity is reversed of the second transistor. 3. The light emitting device according to claim 1, wherein the third transistor and the fourth transistor have the same polarity. The light emitting device according to claim 1 or 2, wherein the first transistor and the second transistor have the same polarity. An electronic apparatus using the light emitting device according to any one of claims 1 to 5 . A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light emitting element, a power supply line, a signal line, a first scanning line, and a second scanning line. A driving method of a light emitting device having a scanning line,
The second, the third and the gate electrode of the fourth transistor are both connected to the first scan line,
One of the source region and the drain region of the third transistor is connected to the signal line, and the other is connected to the gate electrode of the first transistor,
One of the source region and the drain region of the fourth transistor is connected to the signal line, and the other is connected to the drain region of the first transistor,
A source region of the first transistor is connected to the power line;
A source region and a drain region of the second transistor, to one drain region of said first transistor, and the other is connected to a pixel electrode to which the light emitting element has,
A gate electrode of the fifth transistor is connected to the second scanning line;
One of the source region and the drain region of the fifth transistor is connected to the power supply line, and the other is connected to the gate electrode of the first transistor,
A first period in which the third and fourth transistors are on and the fifth transistor is off within one frame period;
A second period in which the third and fourth transistors are off and the fifth transistor is off;
A third period in which the third and fourth transistors are off and the fifth transistor is on;
Is provided,
The second transistor is off in the first period, on in the second period, and on in the third period ;
In the first period, the luminance of the light-emitting element in the second period is controlled by controlling the magnitude of the drain current of the first transistor with an analog video signal, and in the third period, A driving method of a light-emitting device, wherein the light- emitting element does not emit light . A first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light emitting element, a power supply line, a signal line, a first scanning line, and a second scanning line. A driving method of a light emitting device having a scanning line,
The second, the third and the gate electrode of the fourth transistor are both connected to the first scan line,
One of the source region and the drain region of the third transistor is connected to the signal line, and the other is connected to the gate electrode of the first transistor,
One of the source region and the drain region of the fourth transistor is connected to the signal line, and the other is connected to the drain region of the first transistor,
A source region of the first transistor is connected to the power line;
A source region and a drain region of the second transistor, to one drain region of said first transistor, and the other is connected to a pixel electrode to which the light emitting element has,
A gate electrode of the fifth transistor is connected to the second scanning line;
One of the source region and the drain region of the fifth transistor is connected to the power supply line, and the other is connected to the gate electrode of the first transistor,
Within one frame period, a first period, a second period, and a third period corresponding to each bit of the digital video signal are provided,
In the first period, the third及 beauty said fourth transistor is turned on, the second及 beauty the fifth transistor is turned off,
In the second period, the third及 beauty said fourth transistor is turned off, the second transistor is turned on, the fifth transistor is turned off,
In the third period, the third and the fourth transistor is off, the second and the fifth transistor is turned on,
Based on the information contained in previous SL digital video signals, whether light emission of the light emitting element in the second period is controlled,
The method for driving a light-emitting device , wherein the light-emitting element does not emit light in the third period . In claim 8,
A plurality of pixels including the first to fifth transistors and the light-emitting element are provided;
A driving method of a light-emitting device, wherein the first period of the pixels in the first line overlaps with the third period of the pixels in the second line. In claim 8,
The driving method of a light emitting device, wherein the longest second period among the plurality of second periods provided in the one frame period is not provided at the beginning and end of the one frame period. . In claim 8,
A method of driving a light emitting device, wherein a plurality of the second periods corresponding to the digital video signal of the most significant bit are provided within the one frame period. In claim 8,
A plurality of the second periods corresponding to the digital video signal of the most significant bit are provided in the one frame period, and the plurality of the second periods do not appear continuously. Driving method.

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