JP5639988B2 - Light emitting device - Google Patents

Description

  The present invention relates to an OLED panel in which an OLED (OLED: Organic Light Emitting Device) formed on a substrate is enclosed between the substrate and a cover material. The present invention also relates to an OLED module in which an IC including a controller is mounted on the OLED panel. In this specification, the OLED panel and the OLED module are collectively referred to as a light emitting device. The present invention further relates to an electronic apparatus using the light emitting device.

  In recent years, a technology for forming a TFT on a substrate has greatly advanced, and application development to an active matrix display device has been advanced. In particular, a TFT using a polysilicon film has higher field effect mobility (also referred to as mobility) than a conventional TFT using an amorphous silicon film, and thus can operate at high speed. For this reason, it is possible to control a pixel, which has been conventionally performed by a drive circuit outside the substrate, with a drive circuit formed on the same substrate as the pixel.

  Such an active matrix display device has various advantages such as a reduction in manufacturing cost, a reduction in size of the display device, an increase in yield, and a reduction in throughput by forming various circuits and elements on the same substrate. .

  In addition, active matrix light-emitting devices (hereinafter simply referred to as light-emitting devices) having OLEDs as self-luminous elements are being actively researched. The light emitting device is also called an organic EL display (OELD) or an organic light emitting diode (OLED).

  The OLED emits light by itself and has high visibility, is not required for a backlight necessary for a liquid crystal display device (LCD), is optimal for thinning, and has no restriction on the viewing angle. Therefore, in recent years, light emitting devices using OLEDs have attracted attention as display devices that replace CRTs and LCDs.

  The OLED has a layer (hereinafter, referred to as an organic light emitting layer) containing an organic compound (organic light emitting material) capable of obtaining luminescence generated by applying an electric field, an anode layer, and a cathode layer. . Luminescence in organic compounds includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. Any one of the above-described light emission may be used, or both light emission may be used.

  In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.

  In general, the pixel portion 1701 of the light-emitting device has a structure shown in FIG. The pixel portion 1701 is provided with a plurality of gate signal lines 1706, a plurality of source signal lines 1705, and a plurality of power supply lines 1707.

  A region having one of the gate signal lines 1706, one of the source signal lines 1705, and one of the power supply lines 1707 corresponds to the pixel 1702. In the pixel portion 1701, a plurality of pixels 1702 are arranged in a matrix. Each pixel 1702 is provided with an OLED 1703. The OLED 1703 has an anode and a cathode. In this specification, when the anode is used as a pixel electrode (first electrode), the cathode is called a counter electrode (second electrode), and when the cathode is used as a pixel electrode. Refers to the anode as the counter electrode.

  All the counter electrodes included in the OLED 1703 are given a predetermined voltage by a power source 1704 provided outside the OLED panel. In this specification, a voltage between the counter electrode and the pixel electrode is referred to as an OLED drive voltage.

  An enlarged view of the pixel 1702 is shown in FIG. The pixel 1702 includes an OLED 1703, a first TFT 1708 that functions as a switching element, a second TFT 1709 that controls the amount of current flowing between the pixel electrode and the counter electrode of the OLED 1703, and a capacitor (retention capacitor) 1710. Have.

  The gate electrode of the first TFT 1708 is connected to the gate signal line 1706. One of a source region and a drain region of the first TFT 1708 is connected to a source signal line 1705 to which a digital signal is input, and the other is connected to a gate electrode of the second TFT 1709.

  One of the source region and the drain region of the second TFT 1709 is connected to the power supply line 1707 and the other is connected to the pixel electrode of the OLED 1703. One of two electrodes of the capacitor 1710 is electrically connected to the power supply line 1707, and the other is electrically connected to the gate electrode of the second TFT 1709.

  Next, a driving method of the light emitting device shown in FIGS. 21 and 22 will be described. Here, an example in which gradation is displayed using an n-bit digital signal will be described.

  When display is performed using an n-bit digital signal, one frame period is divided into at least n subframe periods. Each subframe period can be divided into a period in which a digital signal is input to each pixel (writing period) and a period in which each pixel performs display (display period) in accordance with each bit of the written digital signal.

  First, in the writing period, the counter electrodes of all the OLEDs 1703 are maintained at the same height as the voltage of the power supply line 1707 by the power source 1704. A plurality of gate signal lines 1705 are sequentially selected, and the first TFT 1708 having the gate electrode connected to each gate signal line is sequentially turned on. Note that in this specification, selection of a signal line means that all TFTs whose gate electrodes are connected to the signal line are turned on.

  Then, when a digital signal is input to each of the plurality of source signal lines 1706, the digital signal is input to the gate electrode of the second TFT through the first TFT that is on. In addition, the voltage of the digital signal is held in the capacitor 1710.

  The digital signal has information of “0” or “1”. The digital signals of “0” and “1” mean signals having a voltage of either Hi or Lo, respectively.

  Then, all the gate signal lines 1706 are sequentially selected, and a digital signal is input to all the pixels. Note that inputting a digital signal to a pixel means inputting a digital signal to the gate electrode of the second TFT 1709. A period until a digital signal is input to all the pixels in the pixel portion 1701 is referred to as a writing period.

  When digital signals are input to all the pixels, the writing period ends and the display period starts. When the display period is started, the voltage of the counter electrodes of all the OLEDs 1703 is changed by the power source 1704, and a voltage is generated between the counter electrodes and the power supply line 1707.

  Note that in the case where the digital signal input to the pixel in the writing period includes information of “0”, the second TFT 1709 is turned off and the OLED 1703 does not emit light. On the other hand, when the information “1” is included, the second TFT 1709 is turned on. As a result, the voltage of the power supply line 1707 is applied to the pixel electrode of the OLED 1703. Therefore, a voltage generated between the counter electrode and the power supply line 1707 is applied between the pixel electrode and the counter electrode of the OLED 1703, and the OLED 1703 emits light.

  Note that the counter electrode voltage in the display period is high enough to apply a forward bias voltage to the OLED 1703 when the voltage of the power supply line 1707 is applied to the pixel electrode.

  In this manner, whether or not the OLED emits light is selected based on information included in the digital signal, and all the pixels perform display at the same time.

  In a display period included in each of the n subframe periods, a desired gray scale can be displayed by whether or not a pixel emits light.

  In the light-emitting device that performs display using a digital signal as described above, when the light-emitting device is enlarged, the number of pixels increases and a large current flows through the entire pixel portion. Since this current flows through a power source that controls the OLED driving voltage, the switch that controls the voltage of the counter electrode that the power source has needs to have a high current capability.

In the light emitting device, when obtaining a light emission amount of 200 cd / m ² , a current of several mA / cm ² is required. For example, when a 40-inch display device is made using an organic light emitting material of 5 mA / cm ^2, the current value necessary for display is about 25 A, which is enormous.

  In general, a standard for a predetermined current capability is defined for a power supply switch, and the upper limit of the current capability has hindered the increase in size of the light emitting device.

  In the above-described light emitting device, the number of divisions in one frame period increases as the number of gradations increases, and the drive circuit must be driven at a high frequency. On the other hand, the switch frequency characteristics of the power supply tend to decrease as the current capability increases. As a result, with the increase in size of the light emitting device, the frequency characteristics are degraded, and the number of possible gradations is reduced.

  An object of the present invention is to provide means for solving the above-described problems associated with the increase in size of a light emitting device. That is, the limitation of the current value due to the switch of the power source that controls the OLED drive voltage is removed, and the decrease in the frequency characteristic of the drive circuit due to the switch of the power source that controls the OLED drive voltage is prevented, and the number of gradations is reduced. The challenge is to prevent it.

  In the present invention, another TFT is newly provided between the power supply line and the pixel electrode of the OLED. Specifically, a third TFT for controlling the drain current of the TFT whose switching is controlled by a digital signal flows to the OLED is newly provided.

  The switching of the third TFT is controlled for each line.

  With the above configuration, the OLED drive voltage can be controlled even when a constant voltage is always applied to the counter electrode of the OLED. Therefore, in the light emitting device of the present invention, it is possible to remove the switch of the power source that controls the voltage of the counter electrode, and high current capability is not required even if the switch is provided.

  The switching of the third TFT can be controlled by the voltage applied to the gate electrode of the third TFT, and almost no current flows through the gate electrode of the third TFT.

  Therefore, an increase in the size of the light emitting device is not hindered by the upper limit of the current capability of the switch of the counter electrode power supply. In addition, since the value of the current flowing through the switch included in the power supply of the counter electrode can be suppressed, it is possible to prevent the frequency characteristics of the drive circuit from being deteriorated due to the switch and to prevent the number of gradations from decreasing.

  Note that in the light-emitting device of the present invention, a transistor formed using single crystal silicon instead of the TFT may be used. The TFT may use polycrystalline silicon or amorphous silicon. Further, a transistor using an organic semiconductor may be used.

  According to the present invention, the OLED drive voltage can be controlled by the above configuration even when a constant voltage is always applied to the counter electrode of the OLED. Therefore, in the light emitting device of the present invention, it is possible to remove the switch of the power source that controls the voltage of the counter electrode, and high current capability is not required even if the switch is provided.

  Further, the upper limit of the current capability of the switch included in the power source of the counter electrode does not hinder the increase in size of the light emitting device. In addition, since the value of the current flowing through the switch included in the power supply of the counter electrode can be suppressed, it is possible to prevent the frequency characteristics of the drive circuit from being deteriorated due to the switch and to prevent the number of gradations from decreasing.

FIG. 4 illustrates a circuit configuration of a light-emitting device of the present invention. FIG. 3 is a circuit diagram of a pixel portion of a light emitting device of the present invention. FIG. 3 is a circuit diagram of a pixel of a light emitting device of the present invention. 4 is a timing chart showing a method for driving the light emitting device of the present invention. FIG. 6 is a top view of a pixel of the light emitting device of the present invention. FIG. 3 is a circuit diagram of a pixel of a light emitting device of the present invention. FIG. 3 is a circuit diagram of a pixel of a light emitting device of the present invention. FIG. 3 is a circuit diagram of a pixel of a light emitting device of the present invention. FIG. 3 is a block diagram illustrating a structure of a drive circuit included in a light emitting device of the invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 4A and 4B illustrate a manufacturing process of a light-emitting device of the present invention. 2A and 2B are a top view and a cross-sectional view of a light-emitting device of the present invention. The circuit diagram of the source signal side drive circuit used by this invention. The top view of the latch circuit used by this invention. 4 is a timing chart showing a method for driving the light emitting device of the present invention. 4 is a timing chart showing a method for driving the light emitting device of the present invention. FIG. 6 is a top view of a pixel of the light emitting device of the present invention. FIG. 4 is a cross-sectional view of a pixel of a light-emitting device of the present invention. Electronic equipment using the light-emitting device of the present invention. The circuit diagram of the pixel part of the conventional light-emitting device. The circuit diagram of the pixel of the conventional light-emitting device.

  FIG. 1 shows a block diagram of a light emitting device of the present invention. The light emitting device in FIG. 1 includes a pixel portion 101, a source signal side driver circuit 102, a first gate signal side driver circuit 103a, and a second gate signal side driver circuit 103b. Note that the number of source signal side drive circuits, first gate signal side drive circuits, and second gate signal side drive circuits can be set as appropriate by the designer. The source signal side drive circuit, the first gate signal side drive circuit, and the second gate signal side drive circuit, which are drive circuits, may be formed on an OLED panel provided with a pixel portion, It may be formed separately and mounted on the OLED panel.

  FIG. 2 shows the structure of the pixel portion 101. The pixel portion 101 includes a first gate signal line (G1 to Gy), a second gate signal line (C1 to Cy), a source signal line (S1 to Sy), and a power supply line (V1 to Vx). Is provided. Note that the number of source signal lines and the number of power supply lines are not necessarily the same.

  A plurality of pixels 104 are arranged in a matrix in the pixel portion 101. Each pixel 104 includes one first gate signal line, one second gate signal line, one source signal line, and one power supply line.

  The first gate signal line Gj (j = 1 to y), the second gate signal line Cj (j = 1 to y), the source signal line Si (i = 1 to x), and the power supply line Vi (i = 3 is an enlarged view of the pixel 104 having 1 to x).

  In FIG. 3, the pixel 104 includes a first TFT 105, a second TFT 106, a third TFT 107, an OLED 108, and a capacitor 109.

  The gate electrode of the first TFT 105 is connected to the first gate signal line Gj. One of the source region and the drain region of the first TFT 105 is connected to the source signal line Si, and the other is connected to the gate electrode of the second TFT 106.

  One of the source region and the drain region of the second TFT 106 is connected to the power supply line Vi, and the other is connected to the source region or the drain region of the third TFT 107.

  The gate electrode of the third TFT is connected to the second gate signal line Cj. Of the source region and the drain region of the third TFT, the one not connected to the source region or the drain region of the second TFT 106 is connected to the pixel electrode of the OLED 108.

  The capacitor 109 is formed between the gate electrode of the second TFT 106 and the power supply line Vi. Note that the capacitor 109 is not necessarily provided.

  The OLED 108 includes an anode, a cathode, and an organic light emitting layer provided between the anode and the cathode.

  Note that the first TFT 105, the second TFT 106, and the third TFT 107 may be either n-channel TFTs or p-channel TFTs. However, it is desirable that the second TFT 106 and the third TFT 107 have the same polarity. When the anode is used as the pixel electrode, the third TFT is preferably a p-channel TFT. Conversely, when the cathode is used as the pixel electrode, the third TFT is preferably an n-channel TFT.

Next, a driving method of the light emitting device of the present invention shown in FIGS. 1 to 3 will be described. Here, a case where 2 ⁿ gradations are displayed using an n-bit digital signal will be described.

  In FIG. 4, the horizontal axis represents the time scale, and the vertical axis represents the position of the first gate signal line.

  First, the first gate signal line G1 is selected by the first gate signal side driving circuit 103a, and the first TFT 105 of the pixel on the first line in which the gate electrode is connected to the first gate signal line G1 is turned on. . In addition, the second gate signal line C1 is selected by the second gate signal side driving circuit 103b, and the third TFT 107 of the pixel on the first line in which the gate electrode is connected to the second gate signal line C1 is turned on. .

  Then, the first bit digital signal input from the source signal side driver circuit 102 to the source signal lines S1 to Sx is input to the gate electrode of the second TFT 106 via the first TFT 105. Note that in this specification, it is assumed that a digital signal is input to a pixel when a digital signal is input to the gate electrode of the second TFT 106 via the first TFT 105.

  The digital signal has information of “0” or “1”, and the digital signals of “0” and “1” are signals having a voltage of one of Hi and one of Lo. The second TFT 106 is turned on or off according to information “0” or “1” included in the digital signal.

  When the second TFT 106 is off, the voltage of the power supply line Vi is not applied to the pixel electrode of the OLED 108. As a result, the OLED 108 does not emit light.

  When the second TFT 106 is on, the third TFT 107 is on, so that the voltage of the power supply line Vi is applied to the pixel electrode of the OLED 108. As a result, the OLED 108 emits light.

  In the light-emitting device of the present invention, the voltage between the power supply line and the counter electrode of the OLED is always maintained at a constant value. The voltage between the power supply line and the counter electrode of the OLED is a height at which a forward bias voltage is applied to the OLED when the voltage of the power supply line is applied to the pixel electrode.

  Thus, when a digital signal is input to the pixels on the first line, whether or not the OLED 108 emits light is selected, and the pixels on the first line perform display. A period during which the pixels are displaying is referred to as a display period Tr. In particular, a display period that starts when a digital signal of the first bit is input to the pixel is referred to as Tr1.

  Next, when the selection of the first gate signal line G1 is completed, the first gate signal line G2 is selected while the second gate signal line C1 is selected, and the gate electrode is connected to the first gate signal line G2. The first TFT 105 of the second line pixel is turned on, and the first bit digital signal is input to the second line pixel from the source signal lines S1 to Sx. Then, the second gate signal line C2 is selected, and the display period Tr1 is started in the pixels on the second line.

  Similarly, all the remaining first gate signal lines G3 to Gy and second gate signal lines C3 to Cy are selected in order, and the display period Tr1 is started in order for the pixels on all the lines. The timing at which the display period of each line is started has a time difference. The period until the first bit digital signal is input to all the pixels is the writing period Ta1.

  On the other hand, before the first bit digital signal is input to all the pixels, in other words, before the writing period Ta1 ends, in parallel with the input of the first bit digital signal to the pixel, the second gate signal side The selection of the second gate signal line C1 is completed by the drive circuit 103b. Then, the third TFT 107 of the pixel on the first line in which the gate electrode is connected to the second gate signal line C1 is turned off. Accordingly, the voltage of the power supply line is not applied to the pixel electrode of the OLED 108, and all the OLEDs 108 included in the pixels on the first line do not emit light and display is not performed.

  A period in which the pixels do not display is called a non-display period Td. In the pixels on the first line, the display period Tr1 ends at the same time as the selection of the second gate signal line C1 ends, and the non-display period Td1 is entered.

  Then, in a state where the selection of the second gate signal line C1 is finished, the selection of the second gate signal line C2 is finished next, and the third pixel of the second line connected to the second gate signal line C2 is finished. The TFT 107 is turned off. Then, the third TFT 107 of the pixel on the second line is turned off. Therefore, the voltage of the power supply line is not applied to the pixel electrode of the OLED 108, and all the OLEDs 108 included in the pixels on the second line do not emit light and display is not performed.

  Similarly, the selection of the erase gate signals C3 to Cy is sequentially completed for all the remaining second gate signal lines. Similar to the display period, the timing at which the non-display period of each line is started has a time difference. A period until selection of all the second gate signal lines C1 to Cy is completed is an erasing period Te1.

  On the other hand, before or after the erasing period Td1 is started in the pixels of all the lines, in other words, before or after the erasing period Te1 ends, again, the first gate signal line G1 and the second gate signal line C1. Selection is started. Then, a 2-bit digital signal is input to the pixels on the first line. As a result, the pixels on the first line perform display again, so the non-display period Td1 ends and the display period Tr2 starts.

  Similarly, all the remaining first gate signal lines G2 to Gy and second gate signal lines C2 to Cy are sequentially selected, and the second bit digital signal is input to all pixels. A period until the second bit digital signal is completely input to all the pixels is referred to as a writing period Ta2.

  On the other hand, before the second bit digital signal is input to all the pixels, in other words, before the writing period Ta2 ends, the second gate signal is input in parallel with the input of the second bit digital signal to the pixels. The selection of line C2 ends. Therefore, all the OLEDs of the pixels on the first line do not emit light, and the pixels on the first line do not display. Therefore, the display period Tr2 ends in the pixels on the first line, and becomes a non-display period Td2.

  In turn, all the second gate signal lines C1 to Cy are selected, and the non-display period Td2 is started in all the pixels. In all the pixels, a period until the selection of the second gate signal line C2 is completed is an erasing period Te2.

  The above-described operation is repeated until the m-bit digital signal is input to the pixel, and the display period Tr and the non-display period Td appear repeatedly. The display period Tr1 is a period from the start of the writing period Ta1 to the start of the erasing period Te1. The non-display period Td1 is a period from the start of the erasing period Te1 to the start of the next writing period (in this case, the writing period Ta2). The display periods Tr2, Tr3,..., Tr (m-1) and the non-display periods Td2, Td3,..., Td (m-1) are written in the writing periods Ta1, respectively, as in the display periods Tr1 and Td1. .., Tam and the erasing period Te1, Te2,..., Te (m−1) determine the period.

  For ease of explanation, FIG. 4 shows an example where m = n−2, but it goes without saying that the present invention is not limited to this. In the present invention, m can be arbitrarily selected from 1 to n.

  m [n-2 (hereinafter, the inside of [] indicates m = n-2)] When the bit-th digital signal is input to the pixel on the first line, the pixel on the first line is displayed in the display period Trm. [N-2] is displayed. Until the next bit digital signal is input, the m [n-2] bit digital signal is held in the pixel. At this time, the second gate signal line remains selected.

  Then, when the (m + 1) [n−1] bit digital signal is input to the first line pixel, the m [n−2] bit digital signal held in the pixel is (m + 1). ) [N−1] bit digital signal is rewritten. At this time, the second gate signal line remains selected. The pixels on the first line are displayed during the display period Tr (m + 1) [n−1]. The digital signal of the (m + 1) [n−1] th bit is held in the pixel until the next bit digital signal is input.

  The above-described operation is repeated until the n-th digital signal is input to the pixel. The display period Trm [n-2],..., Trn is a period from the start of the write period Tam [n-2],.

  When all the display periods Tr1 to Trn are completed, one image can be displayed. In the present invention, a period during which one image is displayed is referred to as one frame period (F).

  After the end of one frame period, the first gate signal line G1 and the second gate signal line C1 are selected again. Then, the digital signal of the first bit is input to the pixel, and the pixel of the first line becomes the display period Tr1 again. Then, the above-described operation is repeated again.

  The light emitting device preferably has 60 or more frame periods per second. When the number of images displayed per second is less than 60, flickering of images may start to be noticeable visually.

In the present invention, it is important that the sum of the lengths of all the writing periods is shorter than one frame period. The length of the display period is Tr1: Tr2: Tr3: ...: Tr (n-1): Trn = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^(n-1) . It is necessary. A desired gradation display among 2 ⁿ gradations can be performed by combining the display periods.

  By obtaining the sum of the lengths of the display periods during which the OLED emits light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example, when n = 8 and the luminance when the pixel emits light in the entire display period is 100%, 1% luminance can be expressed when the pixel emits light in Tr1 and Tr2, and Tr3, Tr5, and Tr8 can be expressed. When is selected, a luminance of 60% can be expressed.

  It is important that the writing period Tam in which the m-bit digital signal is written to the pixel is shorter than the length of the display period Trm. Therefore, the value of the number of bits m needs to be a value from 1 to n such that the writing period Tam is shorter than the length of the display period Trm.

  The display periods Tr1 to Trn may appear in any order. For example, in one frame period, it is possible to cause the display period to appear in the order of Tr3, Tr5, Tr2,. However, the order in which the display periods Tr1 to Trn do not overlap each other is more preferable. Further, the erasing periods Te1 to Ten are more preferably in the order not overlapping each other.

  In the present invention, the above configuration does not hinder the increase in size of the light emitting device due to the upper limit of the current capability of the switch of the power supply of the counter electrode. In addition, since the value of the current flowing through the switch included in the power supply of the counter electrode can be suppressed, it is possible to prevent the frequency characteristics of the drive circuit from being deteriorated due to the switch and to prevent the number of gradations from decreasing.

  In the present invention, the display period and the writing period partially overlap. In other words, it is possible to display pixels even in the writing period. Therefore, the ratio (duty ratio) of the total length of the display periods in one frame period is not determined only by the length of the writing period.

  Note that although a capacitor is provided in this embodiment mode to hold a voltage applied to the gate electrode of the second TFT, the capacitor can be omitted. When the second TFT has an LDD region provided so as to overlap with the gate electrode through the gate insulating film, a parasitic capacitance generally called a gate capacitance is formed in the overlapping region. This gate capacitance may be positively used as a capacitor for holding the voltage applied to the gate electrode of the second TFT.

  Note that a plurality of TFTs whose gate electrodes are electrically connected to each other are connected in series, whereby one TFT can be used for the first TFT, the second TFT, or the third TFT. With the above structure of the first TFT, the off-state current of the first TFT can be reduced. In addition, when the second TFT and the third TFT have the above structure, deterioration of the second TFT or the third TFT due to heat can be suppressed.

  Since the capacitance value of the gate capacitance varies depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

  Examples of the present invention are shown below.

  In this embodiment, a top view of the pixel shown in FIG. 3 will be described.

  FIG. 5 shows a top view of the pixel of this embodiment. A region having the source signal line Si, the power supply line Vi, the first gate signal line Gj, and the second gate signal line Cj corresponds to the pixel 104.

  The gate electrode 201 included in the first TFT 105 is electrically connected to the first gate signal line Gj. One of a source region and a drain region included in the semiconductor film 202 included in the first TFT 105 is connected to the source signal line Si and the other is connected to the gate wiring 204 through the wiring 203.

  A part of the gate wiring 204 functions as the gate electrode 205 of the second TFT 106. One of a source region and a drain region included in the semiconductor film 206 included in the second TFT 106 is connected to the power supply line Vi and the other is connected to the wiring 207.

  The gate electrode 208 of the third TFT 107 is electrically connected to the second gate signal line Cj. One of a source region and a drain region included in the semiconductor film 209 included in the third TFT 107 is connected to the wiring 207, and the other is connected to the pixel electrode 210 through the wiring 250.

  Reference numeral 211 denotes a capacitor semiconductor film formed at the same time as the semiconductor films 202 and 206, and overlaps the gate wiring 204 with an insulating film (not shown) interposed therebetween to form a capacitor. The gate wiring 204 overlaps the power supply line Vi with an insulating film (not shown) interposed therebetween.

  Note that the structure of the pixel shown in FIG. 3 is not limited to that shown in FIG.

  In this embodiment, pixel arrangement of the light-emitting device of the present invention will be described.

  6 and 7 show circuit diagrams of the pixel of this embodiment.

  In FIG. 6A, a pixel 1200 and a pixel 1210 are provided adjacent to each other. The pixel 1200 includes a first TFT 1201, a second TFT 1204, a third TFT 1209, an OLED 1205, and a capacitor 1208. The pixel 1210 includes a first TFT 1211, a second TFT 1214, a third TFT 1219, an OLED 1215, and a capacitor 1218.

  The pixel 1200 includes a source signal line 1203, and the pixel 1210 includes a source signal line 1213. The pixel 1200 and the pixel 1210 share the first gate signal line 1202, the second gate signal line 1207, and the power supply line 1220.

  By sharing one power supply line between adjacent pixels, the number of power supply lines can be reduced compared to the configuration shown in FIG. If the number of wirings is small, the yield can be increased. Further, since the ratio of the area occupied by the entire pixel portion of the wiring is reduced, light shielding by the wiring can be suppressed when the wiring is provided in the light emitting direction of the organic light emitting layer.

  Next, FIG. 6B shows a different example of the pixel arrangement of the present invention. In FIG. 6B, a pixel 1300 and a pixel 1310 are provided adjacent to each other.

  The pixel 1300 includes a first TFT 1301, a second TFT 1304, a third TFT 1309, an OLED 1305, and a capacitor 1308. The pixel 1310 includes a first TFT 1311, a second TFT 1314, a third TFT 1319, an OLED 1315, and a capacitor 1318.

  The pixel 1300 includes a first gate signal line 1302 and the pixel 1310 includes a first gate signal line 1312. The pixel 1300 and the pixel 1310 share the source signal line 1303, the second gate signal line 1307, and the power supply line 1320.

  By sharing one first gate signal line between adjacent pixels, the number of first gate signal lines can be reduced compared to the configuration shown in FIG. If the number of wirings is small, the yield can be increased. Further, since the ratio of the area occupied by the entire pixel portion of the wiring is reduced, light shielding by the wiring can be suppressed when the wiring is provided in the light emitting direction of the organic light emitting layer.

  Next, FIG. 7A shows a different example of the pixel arrangement of the present invention. In FIG. 7A, a pixel 1400 and a pixel 1410 are provided adjacent to each other.

  The pixel 1400 includes a first TFT 1401, a second TFT 1404, a third TFT 1409, an OLED 1405, and a capacitor 1408. The pixel 1410 includes a first TFT 1411, a second TFT 1414, a third TFT 1419, an OLED 1415, and a capacitor 1418.

  The pixel 1400 has a source signal line 1403, and the pixel 1410 has a source signal line 1413. The pixel 1400 and the pixel 1410 share the first gate signal line 1402, the second gate signal line 1407, and the power supply line 1420.

  By sharing one second gate signal line between adjacent pixels, the number of second gate signal lines can be reduced compared to the configuration shown in FIG. If the number of wirings is small, the yield can be increased. Further, since the ratio of the area occupied by the entire pixel portion of the wiring is reduced, light shielding by the wiring can be suppressed when the wiring is provided in the light emitting direction of the organic light emitting layer.

  Next, FIG. 7B shows a different example of the pixel arrangement of the present invention. In FIG. 7B, a pixel 1500 and a pixel 1510 are provided adjacent to each other.

  The pixel 1500 includes a first TFT 1501, a second TFT 1504, a third TFT 1509, an OLED 1505, and a capacitor 1508. The pixel 1510 includes a first TFT 1511, a second TFT 1514, a third TFT 1519, an OLED 1515, and a capacitor 1518.

  The pixel 1500 has a first gate signal line 1502, and the pixel 1510 has a first gate signal line 1512. The pixel 1500 and the pixel 1510 share the source signal line 1503, the second gate signal line 1520, and the power supply line 1507.

  By sharing one second gate signal line between adjacent pixels, the number of second gate signal lines can be reduced compared to the configuration shown in FIG. If the number of wirings is small, the yield can be increased. Further, since the ratio of the area occupied by the entire pixel portion of the wiring is reduced, light shielding by the wiring can be suppressed when the wiring is provided in the light emitting direction of the organic light emitting layer.

  Note that. The present embodiment can be implemented by being freely combined with the first embodiment.

  In this embodiment, a structure of a pixel of the present invention, which is different from that in FIG. 3, will be described.

  In FIG. 8, the pixel 304 includes a first TFT 305, a second TFT 306, a third TFT 307, an OLED 308, and a capacitor 309.

  The gate electrode of the first TFT 305 is connected to the first gate signal line Gj. One of the source region and the drain region of the first TFT 305 is connected to the source signal line Si, and the other is connected to the gate electrode of the second TFT 306.

  One of the source region and the drain region of the second TFT 306 is connected to the pixel electrode of the OLED 308, and the other is connected to the source region or the drain region of the third TFT 307.

  The gate electrode of the third TFT is connected to the second gate signal line Cj. Of the source region and drain region of the third TFT, the one not connected to the source region or drain region of the second TFT 306 is connected to the power supply line Vi.

  The capacitor 309 is formed between the gate electrode of the second TFT 306 and the power supply line Vi. Note that the capacitor 309 is not necessarily provided.

  The OLED 308 has an anode, a cathode, and an organic light emitting layer provided between the anode and the cathode.

  Note that the first TFT 305, the second TFT 306, and the third TFT 307 may be either n-channel TFTs or p-channel TFTs. However, it is desirable that the second TFT 306 and the third TFT 307 have the same polarity. When the anode is used as the pixel electrode, the third TFT is preferably a p-channel TFT. Conversely, when the cathode is used as the pixel electrode, the third TFT is preferably an n-channel TFT.

  Note that. The present embodiment can be implemented by freely combining with the first or second embodiment.

  In this embodiment, detailed configurations of a source signal side driver circuit and a first gate signal side driver circuit used for driving the pixel portion of the light emitting device of the present invention will be described. Since the second gate signal side drive circuit can use the same configuration as the first gate signal side drive circuit, only the configuration of the first gate signal side drive circuit will be described as a representative here.

  FIG. 9 shows a block diagram of a driving circuit of the light emitting device of this embodiment. FIG. 9A shows a source signal side driver circuit 601, which includes a shift register 602, a latch (A) 603, and a latch (B) 604.

  In the source signal side driver circuit 601, a clock signal (CLK) and a start pulse (SP) are input to the shift register 602. The shift register 602 sequentially generates timing signals based on the clock signal (CLK) and the start pulse (SP), and sequentially inputs the timing signals to subsequent circuits through a buffer or the like (not shown).

  The timing signal from the shift register 602 is buffered and amplified by a buffer or the like. A wiring to which a timing signal is input has a large load capacitance (parasitic capacitance) because many circuits or elements are connected thereto. This buffer is provided in order to prevent “blunting” of the rising edge or falling edge of the timing signal caused by the large load capacity. Note that the buffer is not necessarily provided.

  The timing signal buffered and amplified by the buffer is input to the latch (A) 603. The latch (A) 603 includes a plurality of stages of latches that process n-bit digital signals. When the timing signal is input, the latch (A) 603 sequentially captures and holds n-bit digital signals input from the outside of the source signal side driver circuit 601.

  Note that when a digital signal is taken into the latch (A) 603, the digital signal may be sequentially input to latches of a plurality of stages included in the latch (A) 603. However, the present invention is not limited to this configuration. A plurality of stages of latches included in the latch (A) 603 may be divided into several groups, and so-called divided driving may be performed in which digital signals are input simultaneously in parallel for each group. Note that the number of groups at this time is called the number of divisions. For example, when the latches are divided into groups for every four stages, it is said that the driving is divided into four.

  The time until the writing of digital signals to all the latches of the latch (A) 603 is completed is called a line period. Actually, the line period may include a period in which a horizontal blanking period is added to the line period.

  When one line period ends, a latch signal (Latch Signal) is input to the latch (B) 604. At this moment, the digital signals written and held in the latch (A) 603 are sent all at once to the latch (B) 604 and are written and held in the latches of all stages of the latch (B) 604.

  The digital signal is sequentially written into the latch (A) 603 that has finished sending the digital signal to the latch (B) 604 based on the timing signal from the shift register 602.

  During the second line 1-line period, a digital signal written and held in the latch (B) 603 is input to the source signal line.

  FIG. 9B is a block diagram illustrating a configuration of the first gate signal side driver circuit.

  The first gate signal side driving circuit 605 includes a shift register 606 and a buffer 607, respectively. In some cases, it may have a level shift.

  In the first gate signal side driving circuit 605, the timing signal from the shift register 606 is input to the buffer 607 and input to the corresponding address gate signal line. The address gate signal line is connected to the gate electrode of the address TFT of one line of pixels. Since the address TFTs for the pixels for one line must be turned on all at once, a buffer that can flow a large current is used.

  This embodiment can be implemented by freely combining with the first to third embodiments.

  In the light-emitting device of the present invention, the material used for the organic light-emitting layer of the OLED is not limited to the organic light-emitting material, and can also be implemented using an inorganic light-emitting material. However, since current inorganic light-emitting materials have a very high driving voltage, a TFT having a withstand voltage characteristic that can withstand such a driving voltage must be used.

  Alternatively, if an inorganic light-emitting material with a lower driving voltage is developed in the future, it can be applied to the present invention.

  Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-4.

  In this embodiment, TFTs of a pixel portion of a light-emitting device of the present invention and a driver circuit portion (a source signal side driver circuit, a first gate signal side driver circuit, and a second gate signal side driver circuit) provided around the pixel portion are manufactured simultaneously. How to do will be described. However, in order to simplify the description, a CMOS circuit which is a basic unit is illustrated in the drive circuit portion. In this embodiment, only the first TFT and the second TFT in the pixel portion are shown; however, the third TFT can be formed at the same time as the first TFT and the second TFT.

First, as shown in FIG. 10A, a silicon oxide film on a substrate 5001 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass, A base film 5002 made of an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. For example, a silicon oxynitride film 5002a made of SiH ₄ , NH ₃ , and N ₂ O is formed by plasma CVD method to 10 to 200 [nm] (preferably 50 to 100 [nm]), and similarly, SiH ₄ and N _A silicon oxynitride silicon film 5002b formed from ₂ O is stacked to a thickness of 50 to 200 [nm] (preferably 100 to 150 [nm]). Although the base film 5002 is shown as a two-layer structure in this embodiment, it may be formed as a single-layer film of the insulating film or a structure in which two or more layers are stacked.

  The semiconductor films 5003 to 5006 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a laser crystallization method or a known thermal crystallization method. The semiconductor films 5003 to 5006 are formed to a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 300 [Hz] and the laser energy density is 100 to 400 [mJ / cm ² ] (typically 200 to 300 [mJ / cm ² ]). When using a YAG laser, the second harmonic is used and the pulse oscillation frequency is set to 30 to 300 [kHz], and the laser energy density is set to 300 to 600 [mJ / cm ² ] (typically 350 to 500 [mJ]. / cm ² ]). Then, a laser beam focused in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlay rate of the linear laser beam at this time is 50. Perform as ~ 90 [%].

Next, a gate insulating film 5007 is formed to cover the semiconductor films 5003 to 5006. The gate insulating film 5007 is formed of an insulating film containing silicon with a thickness of 40 to 150 [nm] by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to obtain a reaction pressure of 40 [Pa], a substrate temperature of 300 to 400 [° C.], and a high frequency (13.56). [MHz]), and can be formed by discharging at a power density of 0.5 to 0.8 [W / cm ² ]. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

  Then, a first conductive film 5008 and a second conductive film 5009 for forming a gate electrode are formed over the gate insulating film 5007. In this embodiment, the first conductive film 5008 is formed with Ta to a thickness of 50 to 100 [nm], and the second conductive film 5009 is formed with W to a thickness of 100 to 300 [nm].

  The Ta film is formed by sputtering, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is used as the gate electrode. It is unsuitable. In order to form an α-phase Ta film, tantalum nitride having a crystal structure close to Ta's α-phase is formed on a Ta base with a thickness of about 10 to 50 nm. It can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. In addition, it can also be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 [μΩcm] or less. Although the resistivity of the W film can be reduced by increasing the crystal grains, if the impurity element such as oxygen is large in W, the crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, a W target with a purity of 99.9999 [%] or 99.99 [%] is used, and W is carefully considered so that impurities are not mixed in the gas phase during film formation. A resistivity of 9 to 20 [μΩcm] can be realized by forming a film.

  Note that in this embodiment, the first conductive film 5008 is Ta and the second conductive film 5009 is W, but there is no particular limitation, and any of them is selected from Ta, W, Ti, Mo, Al, Cu, and the like. Or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As another example of a combination other than the present embodiment, a combination in which the first conductive film 5008 is formed of tantalum nitride (TaN) and the second conductive film 5009 is W is used. Is made of tantalum nitride (TaN), the second conductive film 5009 is made of Al, the first conductive film 5008 is made of tantalum nitride (TaN), and the second conductive film 5009 is made of Cu. Can be mentioned.

Next, a resist mask 5010 is formed, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ and Cl ₂ are mixed in an etching gas, and a coil type electrode of 500 [W] is applied at a pressure of 1 [Pa]. RF (13.56 [MHz]) power is applied to generate plasma. 100 [W] RF (13.56 [MHz]) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, by making the shape of the resist mask suitable, the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the overetching process. become. Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. At this time, in the gate insulating film 5007, a region which is not covered with the first shape conductive layers 5011 to 5016 is etched and thinned by about 20 to 50 [nm].
(Fig. 10 (A))

Then, an impurity element imparting n-type is added by performing a first doping process. As a doping method, an ion doping method or an ion implantation method may be used. The conditions of the ion doping method are a dose amount of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [keV]. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 5011 to 5015 serve as a mask for the impurity element imparting n-type, and the first impurity regions 5017 to 5025 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 5017 to 5025 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ]. (Fig. 10 (B))

Next, as shown in FIG. 10C, a second etching process is performed without removing the resist mask. The W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as an} etching gas. At this time, second shape conductive layers 5026 to 5031 (first conductive layers 5026a to 5031a and second conductive layers 5026b to 5031b) are formed by the second etching process. At this time, in the gate insulating film 5007, a region that is not covered with the second shape conductive layers 5026 to 5031 is further etched and thinned by about 20 to 50 [nm].

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, the increase in etching rate of Ta is relatively small even when F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since the Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the Ta film, and the etching rate of the W film can be made larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV], and the dose is 1 × 10 ¹³ [atoms / cm ² ], and a new impurity region is formed inside the first impurity region formed in the semiconductor film in FIG. An impurity region is formed. Doping is performed using the second shape conductive layers 5026 to 5030 as masks against the impurity elements so that the impurity elements are also added to the lower regions of the first conductive layers 5026a to 5030a. Thus, third impurity regions 5032 to 5036 are formed. The concentration of phosphorus (P) added to the third impurity regions 5032 to 5036 has a gradual concentration gradient according to the film thickness of the tapered portions of the first conductive layers 5026a to 5030a. Note that in the semiconductor film overlapping the tapered portions of the first conductive layers 5026a to 5030a, although the impurity concentration is slightly lower from the end of the tapered portions of the first conductive layers 5026a to 5030a to the inside, The concentration is similar.

A third etching process is performed as shown in FIG. CHF ₆ is used as an etching gas and a reactive ion etching method (RIE method) is used. By the third etching treatment, the tapered portions of the first conductive layers 5026a to 5031a are partially etched, and the region where the first conductive layer overlaps with the semiconductor film is reduced. Through the third etching treatment, third-shaped conductive layers 5037 to 5042 (first conductive layers 5037a to 5042a and second conductive layers 5037b to 5042b) are formed. At this time, in the gate insulating film 5007, regions that are not covered with the third shape conductive layers 5037 to 5042 are further etched by about 20 to 50 [nm] to form thin regions.

  By the third etching process, in the third impurity regions 5032 to 5036, the third impurity regions 5032a to 5036a overlapping with the first conductive layers 5037a to 5041a, the first impurity region, the third impurity region, Second impurity regions 5032b to 5036b are formed.

Then, as shown in FIG. 11C, fourth impurity regions 5043 to 5054 having a conductivity type opposite to the first conductivity type are formed in the semiconductor films 5004 and 5006 forming the p-channel TFT. Using the third shape conductive layers 5038b and 5041b as masks against the impurity element, impurity regions are formed in a self-aligning manner. At this time, the entire surfaces of the semiconductor films 5003 and 5005 and the wiring portion 5042 forming the n-channel TFT are covered with a resist mask 5200. Although phosphorus is added to the impurity regions 5043 to 5054 at different concentrations, the impurity regions 5043 to 5054 are formed by ion doping using diborane (B ₂ H ₆ ), and the impurity concentration is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / cm ³ ].

  Through the above steps, impurity regions are formed in the respective semiconductor films. The third shape conductive layers 5037 to 5041 overlapping with the semiconductor film function as gate electrodes. Reference numeral 5042 functions as an island-shaped source signal line.

  After the resist mask 5200 is removed, a step of activating the impurity element added to each semiconductor film is performed for the purpose of controlling the conductivity type. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.], In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for the third shape conductive layers 5037 to 5042 is weak against heat, activation is performed after an interlayer insulating film (mainly composed of silicon) is formed to protect the wiring and the like. Preferably it is done.

  Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor film. This step is a step of terminating dangling bonds in the semiconductor film with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  Next, as shown in FIG. 12A, a first interlayer insulating film 5055 is formed from a silicon oxynitride film to a thickness of 100 to 200 [nm]. A second interlayer insulating film 5056 made of an organic insulating material is formed thereon, and then contact holes are formed in the first interlayer insulating film 5055, the second interlayer insulating film 5056, and the gate insulating film 5007. After each wiring (including connection wiring and signal lines) 5057 to 5062 and 5064 is formed by patterning, a pixel electrode 5063 in contact with the connection wiring 5062 is formed by patterning.

  As the second interlayer insulating film 5056, a film made of an organic resin is used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used. In particular, since the second interlayer insulating film 5056 has a strong meaning of flattening, acrylic having excellent flatness is preferable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably it may be 1-5 [μm] (more preferably 2-4 [μm]).

  The contact hole is formed by dry etching or wet etching. The contact hole reaches the n-type impurity regions 5017, 5018, 5021, 5023 or the p-type impurity regions 5043 to 5054, the contact hole reaches the wiring 5042, and the power supply line. A contact hole reaching the gate electrode (not shown) and a contact hole reaching the gate electrode (not shown) are formed.

  Further, as wirings (including connection wirings and signal lines) 5057 to 5062 and 5064, a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering. A film obtained by patterning the laminated film having the three-layer structure into a desired shape is used. Of course, other conductive films may be used.

  In this embodiment, an ITO film having a thickness of 110 [nm] is formed as the pixel electrode 5063 and patterned. A contact is made by arranging the pixel electrode 5063 so as to be in contact with and overlapping with the connection wiring 5062. Alternatively, a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide may be used. This pixel electrode 5063 becomes the anode of the OLED. (Fig. 12 (A))

  Next, as shown in FIG. 12B, an insulating film containing silicon (silicon oxide film in this embodiment) is formed to a thickness of 500 [nm], and an opening is formed at a position corresponding to the pixel electrode 5063. Then, a third interlayer insulating film 5065 functioning as a bank is formed. When the opening is formed, a tapered sidewall can be easily formed by using a wet etching method. If the side wall of the opening is not sufficiently gentle, the deterioration of the organic light emitting layer due to the step becomes a significant problem, so care must be taken.

  Next, the organic light emitting layer 5066 and the cathode (MgAg electrode) 5067 are continuously formed by using a vacuum evaporation method without releasing to the atmosphere. The thickness of the organic light emitting layer 5066 is 80 to 200 [nm] (typically 100 to 120 [nm]), and the thickness of the cathode 5067 is 180 to 300 [nm] (typically 200 to 250 [nm]. nm]).

  In this step, an organic light emitting layer and a cathode are sequentially formed for a pixel corresponding to red, a pixel corresponding to green, and a pixel corresponding to blue. However, since the organic light emitting layer has poor resistance to a solution, it must be formed for each color individually without using a photolithography technique. Therefore, it is preferable to use a metal mask to hide other than the desired pixels and to selectively form the organic light emitting layer and the cathode only at necessary portions.

  That is, first, a mask that hides all pixels other than those corresponding to red is set, and an organic light emitting layer that emits red light is selectively formed using the mask. Next, a mask that hides all but the pixels corresponding to green is set, and an organic light emitting layer that emits green light is selectively formed using the mask. Next, similarly, a mask for hiding all but the pixels corresponding to blue is set, and a blue light emitting organic light emitting layer is selectively formed using the mask. Note that although all the different masks are described here, the same mask may be used.

  Here, a method of forming three types of OLEDs corresponding to RGB is used, but a method of combining a white light emitting OLED and a color filter, a blue or blue green light emitting OLED and a phosphor (fluorescent color conversion layer: CCM). ), A method of superimposing OLEDs corresponding to RGB using a transparent electrode as a cathode (counter electrode), or the like may be used.

  A known material can be used for the organic light emitting layer 5066. As the known material, it is preferable to use an organic material in consideration of the driving voltage. For example, a four-layer structure including a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer may be used as the organic light emitting layer.

  Next, a cathode 5067 is formed. In this embodiment, MgAg is used as the cathode 5067, but the present invention is not limited to this. Other known materials may be used for the cathode 5067.

  Finally, a passivation film 5068 made of a silicon nitride film is formed to a thickness of 300 [nm]. By forming the passivation film 5068, the organic light emitting layer 5066 can be protected from moisture and the like, and the reliability of the OLED can be further improved.

  Thus, a light emitting device having a structure as shown in FIG. 12B is completed. In the light emitting device manufacturing process in this embodiment, the source signal line is formed by Ta and W, which are materials forming the gate electrode, and the source and drain electrodes are formed due to the circuit configuration and the process. The first gate signal line is formed of Al, which is the wiring material being used, but a different material may be used.

  By the way, the light emitting device of this embodiment can exhibit extremely high reliability and improve operating characteristics by arranging TFTs having an optimum structure not only in the pixel portion but also in the drive circuit portion. In addition, it is possible to increase the crystallinity by adding a metal catalyst such as Ni in the crystallization step. Thereby, the drive frequency of the source signal side drive circuit can be increased to 10 [MHz] or more.

  First, a TFT having a structure that reduces hot carrier injection so as not to reduce the operating speed as much as possible is used as an n-channel TFT of a CMOS circuit that forms a drive circuit portion. Note that the driving circuit here includes a shift register, a buffer, a level shifter, a latch in line sequential driving, a transmission gate in dot sequential driving, and the like.

In this embodiment, the active layer of the n-channel TFT has an overlap LDD region ( _LOV region) that overlaps the gate electrode with the source region, drain region, and gate insulating film in between, and a gate insulating film in between. And an offset LDD region (L _OFF region) that does not overlap with the gate electrode and a channel formation region.

  In addition, since the p-channel TFT of the CMOS circuit is hardly concerned with deterioration due to hot carrier injection, it is not particularly necessary to provide an LDD region. Needless to say, it is possible to provide an LDD region as in the case of the n-channel TFT and take measures against hot carriers.

In addition, when the driving circuit uses a CMOS circuit in which a current flows bidirectionally in the channel formation region, that is, a CMOS circuit in which the roles of the source region and the drain region are switched, an n-channel TFT that forms the CMOS circuit In this case, it is preferable to form the LDD region in such a manner that the channel formation region is sandwiched between both sides of the channel formation region. An example of this is a transmission gate used for dot sequential driving. In the case where a CMOS circuit that needs to keep off current as low as possible is used in the driver circuit, the n-channel TFT forming the CMOS circuit preferably has a _LOV region. As such an example, there is a transmission gate used for dot sequential driving.

  In addition, when the state shown in FIG. 12B is actually completed, a protective film (laminate film, ultraviolet curable resin film, etc.) or a light-transmitting material having high hermeticity and low degassing so as not to be exposed to the outside air. It is preferable to package (enclose) with a sealing material. At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the OLED is improved.

  In addition, when the airtightness is improved by processing such as packaging, a connector (flexible printed circuit: FPC) for connecting the terminal drawn from the element or circuit formed on the substrate and the external signal terminal is attached. Completed as a product.

  Further, according to the steps shown in this embodiment, the number of photomasks necessary for manufacturing a light-emitting device can be suppressed. As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

  Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-5.

  In this example, an example in which a light-emitting device is manufactured using the present invention will be described with reference to FIGS.

  FIG. 13A is a top view of an OLED panel formed by sealing a TFT substrate on which a pixel portion is formed with a sealing material, and FIG. 13B is a cross-sectional view taken along line A- in FIG. FIG. 13C is a cross-sectional view taken along the line BB ′ of FIG. 13A.

    A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the source signal side driver circuit 4003, and the first and second gate signal side driver circuits 4004a and 400b. In addition, a sealing material 4008 is provided over the pixel portion 4002, the source signal side driver circuit 4003, and the first and second gate signal side driver circuits 4004a and 400b. Therefore, the pixel portion 4002, the source signal side driver circuit 4003, and the first and second gate signal side driver circuits 4004 a and 400 b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. Yes.

  Further, the pixel portion 4002, the source signal side driver circuit 4003, and the first and second gate signal side driver circuits 4004a and 400b provided over the substrate 4001 have a plurality of TFTs. In FIG. 13B, typically, a driver circuit TFT included in the source signal side driver circuit 4003 formed over the base film 4010 (here, an n-channel TFT and a p-channel TFT are illustrated). 4201 and the second TFT (TFT for controlling current to the OLED) 4202 included in the pixel portion 4002 are illustrated.

  In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driver circuit TFT 4201, and a p-channel TFT manufactured by a known method is used for the second TFT 4202. It is done. The pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the second TFT 4202.

    An interlayer insulating film (planarization film) 4301 is formed over the driver circuit TFT 4201 and the second TFT 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the second TFT 4202 is formed thereon. . As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.

  An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.

  As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.

  On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.

  As described above, the OLED 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4303 is formed on the insulating film 4302 so as to cover the OLED 4303. The protective film 4303 is effective in preventing oxygen, moisture, and the like from entering the OLED 4303.

  Reference numeral 4005 a denotes a lead wiring connected to the power supply line, which is electrically connected to the source region of the second TFT 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.

  As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  However, when the emission direction of light from the OLED is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

   Further, as the filler 4103, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

  Further, in order to expose the filler 4103 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the OLED 4303 can be suppressed.

  As shown in FIG. 13C, a conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.

  The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.

  Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-6.

  In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. Thereby, low power consumption, long life, and light weight of the OLED can be achieved.

Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)

The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.

  (M.A.Baldo, D.F.O'Brien, Y.You, A.Shoustikov, S.Sibley, M.E.Thompson, S.R.Forrest, Nature 395 (1998) p.151.)

  The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.

  (MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K .Nakamura, T.Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)

The molecular formula of the organic light-emitting material (Ir complex) reported by the above paper is shown below.

  As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.

  In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1-7.

  In this embodiment, the circuit diagram of the source signal side driver circuit 601 shown in FIG. 9 is shown as an example.

  In the source signal side driver circuit 601 shown in FIG. 14, a shift register 602, latches (A) (603), and latches (B) (604) are arranged as shown in the figure. In this embodiment, one set of latches (A) (603) and latches (B) (604) corresponds to the four source signal lines Si + 1 to Si + 3. In this embodiment, the level shift circuit for changing the amplitude range of the voltage of the signal is not provided. However, the designer may appropriately provide it.

  The clock signal CKb, the clock signal CKb in which the polarity of the clock signal CK is inverted, the start pulse signal SP, and the drive direction switching signal SL / R are respectively input to the shift register 602 from the wirings shown in the drawing. The digital signal VD input from the outside is input to the latch (A) (603) from the wiring shown in the figure. The signals S_LATb in which the polarities of the latch signals S_LAT and S_LAT are inverted are input to the latch (B) (604) from the wiring shown in the drawing.

  A detailed configuration of the latches (A) and (603) will be described by taking a part 608 of the latches (A) and (603) holding a digital signal corresponding to the source signal line Si as an example. A part 608 of the latch (A) (603) has two clocked inverters and two inverters.

  A top view of a portion 608 of the latch (A) (603) is shown in FIG. Reference numerals 831a and 831b are active layers of TFTs forming one of the inverters included in a part 608 of the latch (A) (603), and 836 is a common gate electrode of the TFTs forming one of the inverters. . 832a and 832b are active layers of TFTs forming another inverter included in a part 608 of the latch (A) (603), and 837a and 837b are gates provided on the active layers 832a and 832b, respectively. Electrode. Note that the gate electrodes 837a and 837b are electrically connected.

  Reference numerals 833a and 833b denote active layers of TFTs that form one of clocked inverters included in a part 608 of the latches (A) and (603). Gate electrodes 838a and 838b are provided on the active layer 833a to form a double gate structure. Gate electrodes 838b and 839 are provided on the active layer 833b to form a double gate structure.

  Reference numerals 834a and 834b denote active layers of TFTs that form another clocked inverter included in a part 608 of the latch (A) (603). Gate electrodes 839 and 840 are provided on the active layer 834a to form a double gate structure. Further, gate electrodes 840 and 841 are provided on the active layer 834b to form a double gate structure.

  In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 8. FIG.

  In this embodiment, the order in which the display periods Tr1 to Tr6 appear in the driving method using a 6-bit digital signal will be described.

  FIG. 16 is a timing chart showing the driving method of this embodiment. In FIG. 16, the horizontal axis indicates time, and the vertical axis indicates the position of the selected first gate signal line. The detailed driving method of the pixel may be referred to the embodiment mode, and is omitted here. In the driving method of this embodiment, the longest non-display period (Td1 in this embodiment) in one frame period is provided at the end of one frame period. With the above-described configuration, the human eyes see that there is a frame period separation between the non-display period Td1 and the first display period of the next frame period (Tr4 in this embodiment). This makes it difficult for human eyes to recognize display unevenness caused by adjacent display periods that emit light between adjacent frame periods when intermediate gray scale display is performed.

  In this embodiment, the case of a 6-bit digital signal has been described, but the present invention is not limited to this. This embodiment can be implemented without being limited to the number of bits of the digital signal.

  In addition, the structure of a present Example can be implemented in combination with any structure of Example 1- Example 9 freely.

  Next, a driving method using an n-bit digital signal that is effective in preventing the pseudo contour will be described with reference to FIG.

  In FIG. 17, the horizontal axis indicates time, and the vertical axis indicates the position of the selected first gate signal line. The detailed driving method of the pixel may be referred to the embodiment mode, and is omitted here.

  In this embodiment, two display periods Trn and Tr (n + 1) corresponding to an n-bit digital signal are provided. A display period corresponding to a digital signal of another bit is provided so that the two display periods do not appear continuously.

And the length of the display period is Tr1: Tr2: Tr3:...: Tr (n-1) :( Trn + Tr (n + 1)) = 2 ⁰ : 2 ¹ : 2 ² : ...: 2 ^(n-2) : 2 ^{( n-1)} . A desired gradation display among 1 to 2 ⁿ gradations can be performed by combining the display periods.

  In the driving method of the present embodiment, when displaying an intermediate gradation, the probability that a display period that emits light during one frame period and a display period that does not emit light alternately appear increases. Therefore, even if the human viewpoint moves slightly left and right and up and down, the probability of staring continuously only at pixels that the human viewpoint does not emit light, or contiguously staring only at pixels that are emitting light conversely Can be lowered. Therefore, it is possible to prevent the display disturbance such as the false contour that is noticeable in the time division driving by the binary code method from being visually recognized.

  In this embodiment, the n-bit digital signal is associated with two display periods, but this embodiment is not limited to this configuration. There may be three or more display periods corresponding to the nth bit digital signal. A plurality of display periods corresponding to digital signals of other bits may be provided. However, it is preferable to correspond to a plurality of display periods in order from the display period corresponding to the upper bits. The number of divisions of the display period can be selected as appropriate by the designer, but the extent to which the display period is divided is preferably determined by the balance between the driving speed of the display device and the required display quality of the image.

  In addition, it is desirable that the display periods corresponding to digital signals having the same bit have the same length, but the present invention is not limited thereto.

  In addition, the structure of a present Example can be implemented in combination with any structure of Example 1- Example 10 freely.

  In this example, a structure of the pixel included in the light-emitting device of the present invention, which is different from that in the embodiment mode, will be described.

  FIG. 18 is a top view of a pixel of the light emitting device of this embodiment. In addition, in order to make the configuration of the pixel easier to understand, an organic light emitting layer and a cathode manufactured in a process subsequent to the pixel electrode are not shown. 18A is a cross-sectional view taken along the line A-A ′ of FIG. 18, FIG. 19B is a cross-sectional view taken along the line B-B ′, and FIG. 19C is a cross-sectional view taken along the line C-C ′.

  The first TFT 501 is an n-channel TFT, the second TFT 502 is a p-channel TFT, and the third TFT 551 is a p-channel TFT.

  The first TFT 501 includes a semiconductor film 503, a first insulating film 520, first electrodes 504 and 505, a second insulating film 521, and second electrodes 506 and 507. The semiconductor film 503 has a first concentration one-conductivity type impurity region 508, a second concentration one-conductivity type impurity region 509, and channel formation regions 510 and 511.

  The first electrodes 504 and 505 and the channel formation regions 510 and 511 overlap each other with the first insulating film 520 interposed therebetween. The second electrodes 506 and 507 and the channel formation regions 510 and 511 overlap each other with the second insulating film 521 interposed therebetween.

  One of the two first-concentration one-conductivity type impurity regions 508 is connected to the source signal line Si and the other is connected to the wiring 540.

  The first electrodes 504 and 505 are part of the first gate signal line Gj, and the second electrodes 506 and 507 are part of the first lower layer wiring Gdj.

  The second TFT 551 includes a semiconductor film 530, a first insulating film 520, a first electrode 531, a second insulating film 521, and a second electrode 532. The semiconductor film 530 includes a first conductivity type impurity region 533 having a third concentration and a channel formation region 534.

  The first electrode 531 and the channel formation region 534 overlap with each other with the first insulating film 520 interposed therebetween. The second electrode 532 and the channel formation region 534 overlap with each other with the second insulating film 521 interposed therebetween.

  One of the two third-concentration one-conductivity type impurity regions 533 is connected to the power supply line Vi and the other is connected to the wiring 570.

  The first electrode 531 and the second electrode 532 are electrically connected through a wiring 540.

  The third TFT 502 includes a semiconductor film 560, a first insulating film 520, a first electrode 561, a second insulating film 521, and a second electrode 562. The semiconductor film 560 includes a first conductivity type impurity region 563 having a third concentration and a channel formation region 564.

  The first electrode 561 and the channel formation region 564 overlap each other with the first insulating film 520 interposed therebetween. The second electrode 562 and the channel formation region 564 overlap each other with the second insulating film 521 interposed therebetween.

  One of the two third-concentration one-conductivity type impurity regions 563 is connected to the pixel electrode 580 of the OLED via the wiring 591 and the other is connected to the wiring 570.

  The first electrode 561 is a part of the second gate signal line Cj, and the second electrode 562 is a part of the second lower layer wiring Cdj.

  Reference numeral 582 denotes a first capacitor wiring electrically connected to the first electrode 531 included in the second TFT 551, and reference numeral 583 denotes a capacitor electrically connected to the second electrode 532 included in the second TFT 551. The second wiring. The first wiring 582 and the second wiring 583 overlap with each other with the first insulating film 520 and the second insulating film 521 interposed therebetween. The power supply line Vi and the first wiring 582 are connected to the wiring 590 formed at the same time as the second wiring 583 and are electrically equivalent. A portion where the first wiring 582, the second wiring 583, the first insulating film 520, and the second insulating film 521 overlap with each other corresponds to the capacitor 581.

  In this manner, a larger capacity can be formed using the insulating film between the first electrode and the second electrode. This configuration can be used not only for pixels but also for other circuits.

  In this embodiment, the first TFT 501 and the third TFT 502 used as switching elements each apply a constant voltage close to the threshold voltage to the first electrode. By applying a constant voltage close to the threshold voltage to the first electrode, variation in threshold can be suppressed as compared with the case where there is one electrode, and off current can be suppressed.

  In addition, the second TFT 551 that is required to pass a larger current than the TFT used as the switching element electrically connects the first electrode and the second electrode. By applying the same voltage to the first electrode and the second electrode, the depletion layer spreads as fast as when the film thickness of the semiconductor film is substantially reduced, so that the subthreshold coefficient can be reduced. Further, the field effect mobility can be improved. Therefore, the on-current can be increased as compared with the case of one electrode. Therefore, the driving voltage can be lowered by using the TFT having this structure in the driving circuit. In addition, since the on-current can be increased, the TFT size (especially the channel width) can be reduced. Therefore, the integration density can be improved.

  Note that a TFT in which the first electrode and the second electrode are electrically connected like the second TFT 551 of this embodiment can obtain a relatively high on-current, so that a driver circuit, particularly a source signal line, It is suitable for controlling the voltage applied to the first and second gate signal lines.

  In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-11.

  Since the light-emitting device is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle compared to a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.

  As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, Play back a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine or electronic book), an image playback device (specifically a DVD (digital versatile disc)) equipped with a recording medium, A device having a display capable of displaying). In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.

  FIG. 20A illustrates an EL display device which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. Note that the EL display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.

  FIG. 20B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.

  FIG. 20C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.

  FIG. 20D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.

  FIG. 20E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 20F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention can be used for the display portion 2502.

  FIG. 20G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The light-emitting device of the present invention can be used for the display portion 2602.

  Here, FIG. 20H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can reduce power consumption of the mobile phone by displaying white characters on a black background.

  If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.

  In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.

  In addition, since the light emitting device consumes power in the light emitting portion, it is desirable to display information so that the light emitting portion is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any structure shown in Embodiments 1 to 12.

Claims (1)

A first transistor, a second transistor, a third transistor, a capacitor, and a self-luminous element;
The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a first semiconductor layer,
The first conductive layer has a function of becoming a first gate electrode of the first transistor;
The second conductive layer has a function of becoming a second gate electrode of the first transistor,
The first conductive layer is provided below the first semiconductor layer, and has a region overlapping the first semiconductor layer with the first insulating layer interposed therebetween,
The first semiconductor layer is provided between the first conductive layer and the second conductive layer,
The second conductive layer has a region overlapping with the first semiconductor layer through a second insulating layer,
The first semiconductor layer includes a channel formation region of the first transistor, a first region, and a second region ,
The first region and the second region are provided so as to sandwich a channel formation region of the first transistor,
The third conductive layer is provided above the third insulating layer and has a function of becoming one of a source electrode or a drain electrode of the first transistor,
The third conductive layer is electrically connected to the first region;
The fourth conductive layer is provided above the third insulating layer and has a function of becoming the other of the source electrode and the drain electrode of the first transistor,
The fourth conductive layer is electrically connected to the second region;
The second transistor includes a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, an eighth conductive layer, and a second semiconductor layer.
The fifth conductive layer has a function of serving as a first gate electrode of the second transistor,
The sixth conductive layer has a function of becoming a second gate electrode of the second transistor;
The fifth conductive layer is electrically connected to the fourth conductive layer;
The sixth conductive layer is electrically connected to the fourth conductive layer;
The fifth conductive layer is provided below the second semiconductor layer, and has a region overlapping the second semiconductor layer with the first insulating layer interposed therebetween,
The second semiconductor layer is provided between the fifth conductive layer and the sixth conductive layer,
The sixth conductive layer has a region overlapping with the second semiconductor layer with the second insulating layer interposed therebetween,
The second semiconductor layer includes a channel formation region of the second transistor, a third region, and a fourth region ;
The third region and the fourth region are provided so as to sandwich a channel formation region of the second transistor,
The seventh conductive layer is provided above the third insulating layer and has a function of becoming one of a source electrode and a drain electrode of the second transistor,
The seventh conductive layer is electrically connected to the third region;
The eighth conductive layer is provided above the third insulating layer and has a function of becoming the other of the source electrode and the drain electrode of the second transistor,
The eighth conductive layer is electrically connected to the fourth region;
The third transistor includes a ninth conductive layer, a tenth conductive layer, the eighth conductive layer, an eleventh conductive layer, and a third semiconductor layer,
The ninth conductive layer has a function of serving as a first gate electrode of the third transistor;
The tenth conductive layer has a function of becoming a second gate electrode of the third transistor,
The ninth conductive layer is provided below the third semiconductor layer, and has a region overlapping the third semiconductor layer with the first insulating layer interposed therebetween,
The third semiconductor layer is provided between the ninth conductive layer and the tenth conductive layer,
The tenth conductive layer has a region overlapping with the third semiconductor layer through the second insulating layer,
The third semiconductor layer includes a channel formation region of the third transistor, a fifth region, and a sixth region ;
The fifth region and the sixth region are provided so as to sandwich a channel formation region of the third transistor,
The eighth conductive layer is provided above the third insulating layer and has a function of becoming one of a source electrode and a drain electrode of the third transistor,
The eighth conductive layer is electrically connected to the fifth region;
The eleventh conductive layer is provided above the third insulating layer and has a function as the other of the source electrode and the drain electrode of the third transistor,
The eleventh conductive layer is electrically connected to the sixth region;
The eleventh conductive layer is electrically connected to the self-luminous element,
The capacitive element includes the sixth conductive layer and a twelfth conductive layer,
The twelfth conductive layer has a region overlapping with the sixth conductive layer through the first insulating layer and the second insulating layer,
The twelfth conductive layer is electrically connected to the thirteenth conductive layer through a first opening provided in the first insulating layer and the second insulating layer,
The thirteenth conductive layer is electrically connected to the seventh conductive layer through a second opening provided in the third insulating layer,
The capacitive element is provided below the seventh conductive layer,
The third conductive layer has a function as a first wiring for supplying a video signal,
The light emitting device according to claim 7, wherein the seventh conductive layer has a function of a second wiring for supplying a power supply voltage.

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