JP4112168B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to a device represented by a liquid crystal display device (mounted with a liquid crystal module) and an electronic device mounted with such a device as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.
[0003]
[Prior art]
In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.
[0004]
Conventionally, a liquid crystal display device is known as an image display device. Active matrix liquid crystal display devices are often used because high-definition images can be obtained compared to passive liquid crystal display devices. In an active matrix liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The optical modulation is recognized by the observer as a display pattern.
[0005]
Applications of such active matrix liquid crystal display devices are expanding, and demands for higher definition, higher aperture ratio, and higher reliability are increasing as the screen size increases. At the same time, demands for improved productivity and lower costs are increasing.
[0006]
[Problems to be solved by the invention]
Conventionally, when a TFT is manufactured using aluminum as the gate wiring material of the TFT, TFT malfunction and TFT characteristics are caused by the formation of protrusions such as hillocks and whiskers by heat treatment and diffusion of aluminum atoms into the channel formation region. Was causing a decline. Therefore, when using a metal material that can withstand heat treatment, typically a metal element having a high melting point, problems such as increased wiring resistance occur when the screen size is increased, resulting in increased power consumption. And so on.
[0007]
Accordingly, an object of the present invention is to provide a structure of a semiconductor device that realizes low power consumption even when the screen is enlarged and a manufacturing method thereof.
[0008]
[Means for Solving the Problems]
In the present invention, the surface of the source wiring of the pixel portion is plated to reduce the resistance of the wiring. Note that in the present invention, the source wiring of the pixel portion is manufactured in a different process from the source wiring of the driver circuit portion. Similarly, the electrode of the terminal portion is plated to reduce the resistance.
[0009]
In the present invention, it is desirable that the wiring before plating is formed of the same material as the gate electrode, and the surface of the wiring is plated to form the source wiring. Further, it is desirable to use a material film having a lower electrical resistance than the gate electrode as the material film to be plated. Therefore, the source wiring of the pixel portion becomes a low resistance wiring by the plating process.
[0010]
Further, the driver circuit is all formed by an NMOS circuit made of an n-channel TFT, and the TFT in the pixel portion is also formed by an n-channel TFT.
[0011]
In addition, when an n-channel TFT is combined to form an NMOS circuit, as shown in FIG. 10A, an enhancement TFT is formed (hereinafter referred to as an EEMOS circuit), and as shown in FIG. 10B. In some cases, the enhancement type and the depression type are combined (hereinafter referred to as an EDMOS circuit).
[0012]
In order to make an enhancement type and a depletion type separately, an element belonging to group 15 of the periodic table (preferably phosphorus) or an element belonging to group 13 of the periodic table (preferably boron) is appropriately added to the semiconductor that will be the channel formation region. do it.
[0013]
Further, in a display device with a small display area, when a driving circuit is formed with an NMOS circuit made of an n-channel TFT, power consumption is larger than that of a CMOS circuit. However, the present invention is particularly effective when the display area is large, and power consumption is not a problem in a stationary monitor or television having a large display area. In addition, there is no problem when all the gate side drive circuits are formed with NMOS circuits, but it is faster to form part of the source side drive circuits with external ICs than with all NMOS circuits. This is desirable because it can be driven.
[0014]
The configuration of the invention disclosed in this specification is as follows.
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, wherein the gate electrode A pixel portion including a first n-channel TFT having a source wiring that surrounds a wiring made of the same material and whose surface is covered with a material film having a lower resistance than the gate electrode;
A drive circuit comprising a circuit comprising a second n-channel TFT and a third n-channel TFT;
A semiconductor device comprising: a terminal portion surrounding a wiring made of the same material as the gate electrode and having a surface covered with a material film having a lower resistance than the gate electrode.
[0015]
The low-resistance material film is a material film mainly composed of Cu, Al, Au, Ag, or an alloy thereof.
[0016]
In addition, the configuration of another invention disclosed in this specification is as follows:
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a first n-channel TFT having a plated source wiring;
A drive circuit comprising a circuit comprising a second n-channel TFT and a third n-channel TFT;
And a plated terminal portion.
[0017]
The surface of the terminal portion and the surface of the source wiring of the pixel portion are covered with a thin film made of a material mainly composed of Cu, Al, Au, Ag, or an alloy thereof.
[0018]
In each of the above structures, the source wiring of the terminal portion and the pixel portion is plated at the same time or separately.
[0019]
In each of the above structures, the plated source wiring is obtained by plating a wiring obtained in the same process as the gate electrode.
[0020]
Further, in each of the above structures, the plated source wiring is obtained by plating a wiring made of a material having a lower resistance than the gate electrode. A wiring made of a material having a lower resistance than the gate electrode may be formed by patterning after forming a film using a sputtering method, but may be formed by a printing method. In the case of forming by a printing method, the number of masks can be reduced.
[0021]
In each of the above structures, an EEMOS circuit or an EDMOS circuit is formed by the second n-channel TFT and the third n-channel TFT.
[0022]
In each of the above structures, the first n-channel TFT includes a gate electrode and a channel formation region overlapping with the gate electrode, and the width of the channel formation region and the width of the gate electrode are the same. It is characterized by that.
[0023]
In each of the above structures, the first n-channel TFT includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. It is characterized by that. The first n-channel TFT preferably has three channel formation regions.
[0024]
In each of the above structures, the n-channel TFT of the driver circuit includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. It is characterized by that.
[0025]
In each of the above structures, the impurity concentration in the impurity region of the n-channel TFT is at least 1 × 10 6. ¹⁷ ~ 1x10 ¹⁸ / Cm ^Three In this range, a region having a concentration gradient is included, and the impurity concentration increases as the distance from the channel formation region increases.
[0026]
In each of the above structures, it is preferable that the first n-channel TFT according to any one of claims 1 to 15 includes a plurality of channel formation regions.
[0027]
In addition, the configuration of another invention disclosed in this specification is as follows:
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, wherein the gate electrode A semiconductor device having a terminal portion surrounding an electrode made of the same material and having at least a part of the surface covered with a low-resistance material film. This low resistance material film has a lower electrical resistance than the material of the gate electrode.
[0028]
In addition, the configuration of another invention disclosed in this specification is as follows:
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, wherein the gate electrode A terminal part that surrounds an electrode made of the same material and at least a part of the surface of which is covered with a low-resistance material film;
A semiconductor device comprising: a wiring that surrounds a wiring made of the same material as the gate electrode and is covered with a material film having a lower resistance than the gate electrode.
[0029]
In the above structure, the wiring is a source wiring.
[0030]
Further, the semiconductor device described in each of the above structures is a transmissive liquid crystal module or a reflective liquid crystal module.
[0031]
The configuration of the invention for realizing the above structure is as follows.
A method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer;
Forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film;
Adding an impurity element imparting n-type to the semiconductor layer using the first gate electrode as a mask to form an n-type first impurity region;
Etching the first gate electrode to form a tapered portion;
Adding an impurity element imparting n-type to the semiconductor layer through the tapered portion of the first gate electrode to form an n-type second impurity region;
Plating the source wiring of the pixel portion and the surface of the terminal portion;
Forming a second insulating film covering the source wiring and the terminal portion of the pixel portion;
Forming a gate wiring and a source wiring of a driving circuit on the second insulating film;
A method for manufacturing a semiconductor device having
[0032]
Further, the configuration of another invention for realizing the above structure is as follows:
A method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming a first insulating film on the semiconductor layer;
Forming a first gate electrode, a source wiring of a pixel portion, and an electrode of a terminal portion on the first insulating film;
Adding an impurity element imparting n-type to the semiconductor layer using the first gate electrode as a mask to form an n-type first impurity region;
Etching the first gate electrode to form a tapered portion;
Forming an n-type second impurity region by adding an impurity element imparting n-type to the semiconductor layer through the tapered portion of the first gate electrode;
Plating the surface of the source wiring of the pixel portion;
Plating the surface of the terminal portion;
Forming a second insulating film covering the source wiring and the terminal portion of the pixel portion;
Forming a gate wiring and a source wiring of a driving circuit on the second insulating film;
A method for manufacturing a semiconductor device having
[0033]
In each of the above manufacturing methods, the source wiring and the terminal portion of the pixel portion are made of a material whose main component is Cu, Al, Au, Ag, or an alloy thereof.
[0034]
In each of the above manufacturing methods, in the step of performing plating, the source wiring of the pixel portion is connected by wiring so as to have the same potential. In addition, the wiring connected so as to have the same electric potential is a laser beam (CO ₂ May be divided by a laser or the like, or may be divided at the same time as the substrate after plating.
[0035]
Further, instead of the n-channel TFT, all circuits may be formed by p-channel TFTs.
[0036]
Other aspects of the invention disclosed in this specification are:
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a first p-channel TFT having a source wiring that surrounds a wiring made of the same material as the gate electrode and whose surface is covered with a material film having a lower resistance than the gate electrode;
A drive circuit comprising a circuit comprising a second p-channel TFT and a third p-channel TFT;
A semiconductor device comprising: a terminal portion surrounding a wiring made of the same material as the gate electrode and having a surface covered with a material film having a lower resistance than the gate electrode.
[0037]
Other aspects of the invention disclosed in this specification are:
A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion having a first p-channel TFT having a plated source wiring;
A drive circuit comprising a circuit comprising a second n-channel TFT and a third p-channel TFT;
And a plated terminal portion.
[0038]
When the p-channel TFT is used, an EEMOS circuit or an EDMOS circuit is formed by the second p-channel TFT and the third p-channel TFT.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
[0040]
First, a base insulating film is formed over a substrate, and then a semiconductor layer having a desired shape is formed by a first photolithography process.
[0041]
Next, an insulating film (including a gate insulating film) is formed to cover the semiconductor layer. A first conductive film and a second conductive film are stacked over the insulating film. These stacked films are subjected to a first etching process by a second photolithography process, and a gate electrode including the first conductive layer and the second conductive layer, a source wiring of the pixel portion, and an electrode of the terminal portion are formed. Form. In the present invention, after the gate electrode is formed first, the gate wiring is formed on the interlayer insulating film.
[0042]
Next, an n-type impurity region (high concentration) is formed in a self-aligned manner by adding an impurity element imparting n-type to the semiconductor (phosphorus or the like) while keeping the resist mask formed in the second photolithography process as it is. ).
[0043]
Next, while the resist mask formed in the second photolithography step is left as it is, a second etching process is performed by changing etching conditions, and a first conductive layer (first width) having a tapered portion is formed. A second conductive layer (second width) is formed. Note that the first width is larger than the second width, and the electrode formed of the first conductive layer and the second conductive layer here becomes a gate electrode (first gate electrode) of the n-channel TFT.
[0044]
Next, after removing the resist mask, an impurity element imparting n-type conductivity is added to the semiconductor layer through the tapered portion of the first conductive layer using the second conductive layer as a mask. Here, a channel formation region is formed below the second conductive layer, and an impurity region (low concentration) in which the impurity concentration gradually increases as the distance from the channel formation region is formed below the first conductive layer. .
[0045]
Thereafter, the tapered portion is selectively removed in order to reduce the off current of the TFT in the pixel portion. Only the tapered portion of the gate electrode of the pixel portion may be removed by performing dry etching with the mask shown in FIG. In particular, it is not necessary to selectively remove the tapered portion. However, if it is not removed, it is desirable to reduce the off current as a triple gate structure as shown in FIG.
[0046]
Next, after the impurity element added to each semiconductor layer is activated, a plating process (electrolytic plating method) is performed to form a metal film on the surface of the source wiring in the pixel portion and the surface of the electrode in the terminal portion. The plating method is a method in which a direct current is passed through an aqueous solution containing metal ions to be formed by plating to form a metal film on the cathode surface. As the metal to be plated, a material having a lower resistance than the gate electrode, such as copper, silver, gold, chromium, iron, nickel, platinum, or an alloy thereof can be used. Since copper has a very low electric resistance, it is optimal for a metal film covering the surface of the source wiring of the present invention. Thus, in the present invention, since the source wiring of the pixel portion is covered with a low-resistance metal material, it can be driven at a sufficiently high speed even if the area of the pixel portion is increased.
[0047]
Further, the thickness of the metal film formed in the plating method can be appropriately set by the practitioner by controlling the current density and time.
[0048]
In the present invention, the metal film formed on the surface is also referred to as source wiring.
[0049]
Next, an interlayer insulating film is formed, and a transparent conductive film is formed. Next, the transparent conductive film is patterned by a third photolithography method to form pixel electrodes. Next, a contact hole is formed by a fourth photolithography process. Here, a contact hole reaching the impurity region, a contact hole reaching the gate electrode, and a contact hole reaching the source wiring are formed.
[0050]
Next, a conductive film made of a low-resistance metal material is formed, and an electrode that connects the gate wiring, the source wiring, and the impurity region, and an electrode that connects the pixel electrode and the impurity region are formed by a fifth photolithography step. . In the present invention, the gate wiring is electrically connected to the first gate electrode or the second gate electrode through a contact hole provided in the interlayer insulating film. The source wiring is electrically connected to the impurity region (source region) through a contact hole provided in the interlayer insulating film. An electrode connected to the pixel electrode is electrically connected to the impurity region (drain region) through a contact hole provided in the interlayer insulating film.
[0051]
Thus, a total of five photolithography steps, that is, a pixel portion having pixel TFTs (n-channel TFTs) with five masks and an EEMOS circuit (n-channel TFT) as shown in FIG. An element substrate including the driving circuit can be formed. Note that although an example in which a transmissive display device is manufactured is shown here, a reflective display device can also be manufactured by using a highly reflective material for a pixel electrode. In the case of manufacturing a reflective display device, an element substrate can be formed with four masks because it can be formed at the same time as a gate wiring.
[0052]
In the case of forming an EDMOS circuit as shown in FIG. 10B by combining the enhancement type and the depletion type, a mask is formed in advance before forming the conductive film, and a periodic table is formed on the semiconductor to be a channel formation region. An element belonging to Group 15 (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) may be selectively added. In this case, the element substrate can be formed with six masks.
[0053]
Although an example in which the source wiring of the pixel portion and the electrode of the terminal portion are formed simultaneously with the gate electrode is shown here, they may be formed separately. For example, after an impurity element is added to each semiconductor layer, an insulating film that protects the gate electrode is formed, the impurity element added to each semiconductor layer is activated, and a low resistance is formed on the insulating film by a photolithography process. You may form simultaneously the source wiring of the pixel part which consists of metal materials (typically material which has aluminum, silver, and copper as a main component), and the electrode of a terminal part. The source wiring of the pixel portion and the electrode of the terminal portion thus obtained are plated. In order to reduce the number of masks, the source wiring of the pixel portion may be formed by a printing method.
[0054]
Alternatively, a p-channel TFT may be used in place of the n-channel TFT, all the driver circuits may be formed by PMOS circuits made of p-channel TFTs, and the TFTs in the pixel portion may also be formed by p-channel TFTs.
[0055]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0056]
【Example】
[Example 1]
Here, a method of simultaneously manufacturing a pixel portion (n-channel TFT) and a TFT (EEMOS circuit including an n-channel TFT) constituting an NMOS circuit of a driver circuit provided around the pixel portion on the same substrate is shown in FIG. Description will be made with reference to FIG.
[0057]
First, in this embodiment, a substrate 100 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. The substrate 100 is not particularly limited as long as it has translucency, and a quartz substrate may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0058]
Next, a base film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 100. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 101, a plasma CVD method is used, and SiH _Four , NH _Three And N ₂ A silicon oxynitride film 101a formed using O as a reaction gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a silicon oxynitride film 101a having a film thickness of 50 nm (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) is formed. Next, as the second layer of the base film 101, a plasma CVD method is used, and SiH _Four And N ₂ A silicon oxynitride film 101b formed using O as a reaction gas is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, a silicon oxynitride film 101b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.
[0059]
Next, semiconductor layers 102 to 105 are formed over the base film. The semiconductor layers 102 to 105 are formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like), and then a known crystallization treatment (laser crystallization method, heat A crystalline semiconductor film obtained by performing a crystallization method or a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape. The semiconductor layers 102 to 105 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferably formed of silicon or a silicon germanium alloy. In this example, a 55 nm amorphous silicon film was formed by plasma CVD, and then a solution containing nickel was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (500 ° C., 1 hour), then thermally crystallized (550 ° C., 4 hours), and then laser annealing treatment is performed to improve crystallization. Thus, a crystalline silicon film was formed. Then, the semiconductor layers 102 to 105 were formed by patterning the crystalline silicon film using a photolithography method.
[0060]
In addition, after forming the semiconductor layers 102 to 105, a small amount of impurity element (boron or phosphorus) may be appropriately doped in order to make an enhancement type and a depletion type separately.
[0061]
When a crystalline semiconductor film is formed by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four A laser can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 400 mJ / cm. ² (Typically 200-300mJ / cm ² ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is 1 to 10 kHz, and the laser energy density is 300 to 600 mJ / cm. ² (Typically 350-500mJ / cm ² ) Then, when the laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%. Good.
[0062]
Further, FIG. 16 shows a simplified state of laser irradiation. Laser light emitted from the laser light source 1101 is applied to the large substrate by the optical system 1102 and the mirror 1103. Note that the arrow on the large substrate indicates the scanning direction of the laser beam. FIG. 16 shows an example in which six large 12.1 inches are formed on a large substrate 1105 of 650 × 550 mm.
[0063]
Next, a gate insulating film 106 that covers the semiconductor layers 102 to 105 is formed. The gate insulating film 106 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0064]
Next, as illustrated in FIG. 1A, a first conductive film 107 a with a thickness of 20 to 100 nm and a second conductive film 107 b with a thickness of 100 to 400 nm are stacked over the gate insulating film 106. In this example, a first conductive film 107a made of a TaN film with a thickness of 30 nm and a second conductive film 107b made of a W film with a thickness of 370 nm were stacked. The TaN film was formed by sputtering, and was sputtered in a nitrogen-containing atmosphere using a Ta target. The W film was formed by sputtering using a W target. In addition, tungsten hexafluoride (WF ₆ It can also be formed by a thermal CVD method using In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in the W film, the crystallization is hindered and the resistance is increased. Therefore, in this embodiment, sufficient consideration is given so that impurities are not mixed from the gas phase during film formation by sputtering using a target of high purity W (purity 99.9999% or 99.99%). By forming a W film, a resistivity of 9 to 20 μΩcm could be realized.
[0065]
In this embodiment, the first conductive film 107a is TaN and the second conductive film 107b is W. However, there is no particular limitation, and all of them are Ta, W, Ti, Mo, Al, Cu, Cr, Nd. You may form with the element selected from these, or the alloy material or compound material which has the said element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. In addition, the first conductive film is formed using a tantalum (Ta) film, the second conductive film is formed using a W film, the first conductive film is formed using a titanium nitride (TiN) film, and the second conductive film is formed. The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of an Al film, and the first conductive film is formed of a tantalum nitride (TaN) film. The second conductive film may be a combination of Cu films.
[0066]
Next, resist masks 108a to 112a are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used as the first etching condition, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ The gas flow ratio was 25/25/10 (sccm), and 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . As an etching gas, Cl ₂ , BCl _Three , SiCl _Four , CCl _Four Chlorine gas or CF represented by _Four , SF ₆ , NF _Three Fluorine gas such as O ₂ Can be used as appropriate. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition.
[0067]
Thereafter, the resist masks 108a to 112a are not removed and the etching conditions are changed to the second etching condition. _Four And Cl ₂ The gas flow ratio is 30/30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and etching for about 30 seconds. Went. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.
[0068]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.
[0069]
Thus, the first shape conductive layers 113 to 117 (the first conductive layers 113 a to 117 a and the second conductive layers 113 b to 117 b) composed of the first conductive layer and the second conductive layer by the first etching treatment. Form. (FIG. 1B) The width of the first conductive layer in the channel length direction here corresponds to the first width shown in the above embodiment mode. Although not shown, in the insulating film 106 to be a gate insulating film, a region that is not covered with the first shape conductive layers 113 to 117 is etched and thinned by about 10 to 20 nm.
[0070]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. (FIG. 1C) The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ /cm ² The acceleration voltage is set to 60 to 100 keV. In this embodiment, the dose is 1.5 × 10 ¹⁵ /cm ² The acceleration voltage was 80 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. In this case, the conductive layers 113 to 116 serve as a mask for the impurity element imparting n-type, and n-type impurity regions (high concentration) 118 to 121 are formed in a self-aligning manner. Impurity regions 118 to 121 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} /cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0071]
Next, a second etching process is performed without removing the resist mask. Here, SF is used as the etching gas. ₆ And Cl ₂ And O ₂ The gas flow ratio is 24/12/24 (sccm), and 700 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.3 Pa to generate plasma and perform etching. 25 seconds. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the insulating film 106, SiON The etching rate with respect to is 33.7 nm / min, and the selective ratio of W to TaN is 6.83. In this way, SF is used as the etching gas. ₆ Is used, the selectivity with respect to the insulating film 106 is high, so that film loss can be suppressed.
[0072]
By this second etching process, the taper angle of the second conductive layer (W) became 70 °. The second conductive layers 122b to 126b are formed by the second etching process. On the other hand, the first conductive layer is hardly etched, and the first conductive layers 122a to 126a are formed. Further, the masks 108a to 112a made of resist are deformed into masks 108b to 112b made of resist by the second etching process. (FIG. 1D) Although not shown, the width of the first conductive layer actually retreats by about 0.15 μm compared to before the second etching process, that is, the entire line width recedes by about 0.3 μm. . Further, the width of the second conductive layer in the channel length direction here corresponds to the second width shown in the embodiment mode.
[0073]
Note that an electrode formed using the first conductive layer 122a and the second conductive layer 122b serves as a gate electrode of an n-channel TFT of an NMOS circuit formed in a later step, and the first conductive layer 125a and the second conductive layer 122b The electrode formed with the second conductive layer 125b is one electrode of a storage capacitor formed in a later step.
[0074]
In the second etching process, CF _Four And Cl ₂ And O ₂ Can also be used as an etching gas. In that case, if each gas flow rate ratio is 25/25/10 (sccm), 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Good. 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ And O ₂ When W is used, the etching rate with respect to W is 124.62 nm / min, the etching rate with respect to TaN is 20.67 nm / min, and the selection ratio of W with respect to TaN is 6.05. Therefore, the W film is selectively etched. In this case, a region of the insulating film 106 that is not covered with the first shape conductive layers 122 to 126 is etched and thinned by about 50 nm.
[0075]
Next, after removing the resist mask, a second doping process is performed to obtain the state of FIG. Doping is performed using the second conductive layers 122b to 125b as masks against the impurity element so that the impurity element is added to the semiconductor layer below the tapered portion of the first conductive layer. In this embodiment, P (phosphorus) is used as the impurity element, and the doping condition is a dose of 1.5 × 10. ¹⁴ /cm ² , Acceleration voltage 90 keV, ion current density 0.5 μA / cm ² , Phosphine (PH _Three ) Plasma doping was performed with a 5% hydrogen dilution gas and a gas flow rate of 30 sccm. In this manner, impurity regions (low concentration) 127 to 136 overlapping with the first conductive layer are formed in a self-aligning manner. The concentration of phosphorus (P) added to the impurity regions 127 to 136 is 1 × 10 ¹⁷ ~ 1x10 ¹⁹ /cm ^Three And has a concentration gradient according to the film thickness of the tapered portion of the first conductive layer. Note that in the semiconductor layer overlapping the tapered portion of the first conductive layer, the impurity concentration (P concentration) gradually decreases from the end of the tapered portion in the first conductive layer toward the inside. That is, a concentration distribution is formed by this second doping process. Further, an impurity element is further added to the impurity regions (high concentration) 118 to 121 to form impurity regions (high concentration) 137 to 145.
[0076]
In the present embodiment, the width of the taper portion (width in the channel length direction) is preferably at least 0.5 μm, and the limit is 1.5 μm to 2 μm. Therefore, the width of the impurity region having a concentration gradient (low concentration) in the channel length direction is also limited to 1.5 μm to 2 μm although it depends on the film thickness. Here, the impurity region (high concentration) and the impurity region (low concentration) are illustrated as being separate, but actually there is no clear boundary and a region having a concentration gradient is formed. Similarly, there is no clear boundary between the channel formation region and the impurity region (low concentration).
[0077]
Next, a third etching process is performed with the portions other than the pixel portion covered with the mask 146 later. As the mask 146, a metal plate, a glass plate, a ceramic plate, or a ceramic glass plate may be used. A top view of the mask 146 is shown in FIG. In the third etching process, the tapered portion of the first conductive layer in the region not overlapping with the mask 146 is selectively dry etched so that the region overlapping with the impurity region of the semiconductor layer is eliminated. In the third etching process, Cl having a high selectivity to W as an etching gas is used. _Three And using an ICP etching apparatus. In this example, Cl _Three The gas flow ratio was set to 80 (sccm), 350 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1.2 Pa, plasma was generated, and etching was performed for 30 seconds. 50 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. By the third etching, the first conductive layers 124c and 126c are formed. (Fig. 2 (B))
[0078]
In this embodiment, an example in which the third etching process is performed has been described. However, if the third etching process is not necessary, it is not particularly necessary.
[0079]
Next, as shown in FIG. 2D, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, it may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. The activation treatment was performed by heat treatment. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0080]
Although not shown, the impurity element is diffused by this activation treatment, and the boundary between the n-type impurity region (low concentration) and the impurity region (high concentration) is almost eliminated.
[0081]
In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered to an impurity region containing high-concentration phosphorus, and nickel in a semiconductor layer mainly serving as a channel formation region The concentration is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0082]
Next, heat treatment is performed in a hydrogen atmosphere to hydrogenate the semiconductor layer. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be used.
[0083]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the hydrogenation.
[0084]
Next, the surface of the source wiring 126 in the pixel portion and the electrode surface in the terminal portion are plated. FIG. 7A shows a top view immediately after the plating process, and FIG. 7B shows a cross-sectional view thereof. In FIG. 7, reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. Further, FIG. 7 shows one TFT of the driver circuit portion for simplification, and only the source wiring 126 is shown in the pixel portion. In this example, the plating process was performed using a copper plating solution (manufactured by EEJA: Microfab Cu2200). In this plating, as shown in FIG. 12 as an example, wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, the electrodes are separated from each other when the substrate is divided. Moreover, you may form a short ring with a dummy pattern.
[0085]
Next, a first interlayer insulating film 155 is formed to cover the source wiring of the pixel. As the first interlayer insulating film 155, an inorganic insulating film containing silicon as a main component may be used.
[0086]
Next, a second interlayer insulating film 156 made of an organic insulating material is formed on the first interlayer insulating film 155. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed.
[0087]
Next, the pixel electrode 147 made of a transparent conductive film was patterned on the second interlayer insulating film using a photomask. The transparent conductive film used as the pixel electrode 147 is, for example, ITO (indium tin oxide alloy), indium zinc oxide alloy (In ₂ O _Three —ZnO), zinc oxide (ZnO), or the like may be used.
[0088]
Next, the second insulating film is selectively etched using a photomask to form contact holes reaching the impurity regions (137, 138, 149, 150, 151, 153, and 144) and the source wiring 126 in the pixel portion. A contact hole reaching, a contact hole reaching the gate electrode 124, and a contact hole reaching the electrode 125b are formed.
[0089]
Next, electrodes 157 to 160 that are electrically connected to the impurity regions (137, 138, 149, and 150) and the source wiring of the driver circuit, and electrodes 150 and 163 that are electrically connected to the impurity regions 144 and 153, respectively. The electrode (connection electrode) 161 that electrically connects the impurity region 151 serving as the source region and the source wiring 126 of the pixel portion, the gate wiring 162 that is electrically connected to the gate electrode 124, and the electrode 125b are electrically connected. A capacitor wiring 169 to be connected is formed.
[0090]
The pixel electrode 147 is electrically connected to the impurity region 153 of the pixel TFT 206 by an electrode 163 that is in contact with and overlaps with the pixel electrode 147, and is electrically connected to the impurity region 144 of the storage capacitor 207 by the electrode 150 that is in contact with and overlapping with the pixel electrode 147. Connected to.
[0091]
In this embodiment, the electrodes 150 and 163 are formed after the pixel electrode is formed. However, after forming the contact hole and forming the electrode, the pixel electrode made of a transparent conductive film so as to overlap the electrode is formed. May be formed.
[0092]
An impurity element imparting n-type conductivity is added to each of the impurity regions 135, 136, 144, and 145 that functions as one electrode of the storage capacitor 207. The storage capacitor 207 is formed of electrodes 125 a and 125 b connected to the capacitor wiring 169 and a semiconductor layer using the insulating film 106 as a dielectric.
[0093]
As described above, the driving circuit 201 including the NMOS circuit 202 including the n-channel TFT 203 and the n-channel TFT 204 and the pixel portion 205 including the pixel TFT 206 and the storage capacitor 207 including the n-channel TFT are formed over the same substrate. Can be formed. (FIG. 3B) In this specification, such a substrate is called an active matrix substrate for convenience.
[0094]
Note that in this embodiment, the n-channel TFT 203 and the n-channel TFT 204 are used to form the EEMOS circuit shown in FIG.
[0095]
A top view of a pixel portion of an active matrix substrate manufactured in this embodiment is shown in FIG. Note that the same reference numerals are used for portions corresponding to those in FIG. A chain line AA ′ in FIG. 3B corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. Further, a chain line BB ′ in FIG. 3B corresponds to a cross-sectional view taken along the chain line BB ′ in FIG. FIG. 4 shows a top view immediately after forming the source wiring 126 of the pixel.
[0096]
In the pixel structure of this embodiment, the end portion of the pixel electrode 147 overlaps with the source wiring 126 so that the gap between the pixel electrodes is shielded without using a black matrix.
[0097]
Further, according to the steps shown in this example, the number of photomasks necessary for manufacturing the active matrix substrate could be five.
[0098]
A process for manufacturing an active matrix liquid crystal display device from the active matrix substrate thus obtained will be described below. FIG. 6 is used for the description.
[0099]
After obtaining the active matrix substrate in the state of FIG. 3B, an alignment film 301 is formed over the active matrix substrate of FIG. 3B and a rubbing process is performed. In this embodiment, before the alignment film 301 is formed, columnar spacers for maintaining the substrate interval are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0100]
Next, the counter substrate 300 is prepared. The counter substrate is provided with a color filter in which a colored layer 302 and a light shielding layer are arranged corresponding to each pixel. A planarizing film 304 is provided to cover the color filter and the light shielding layer. Next, a counter electrode 305 made of a transparent conductive film was formed on the planarizing film 304 in the pixel portion, an alignment film 306 was formed on the entire surface of the counter substrate, and a rubbing process was performed.
[0101]
Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are attached to each other with a sealant 307. A filler is mixed in the sealing material 307, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 308 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 308. Then, the active matrix substrate or the counter substrate is divided into a desired shape. Here, the dummy pattern provided for the plating process is divided.
[0102]
FIG. 8A shows a top view after division, and FIG. 8B shows a cross-sectional view cut along a dotted line DD ′. In FIG. 8, reference numeral 400 denotes a terminal portion, and 401 denotes an electrode connected to an external terminal. Further, FIG. 8 shows one TFT of the driver circuit portion for simplification, and only the source wiring 126 is shown in the pixel portion. The electrode 401 is electrically connected to the wirings 157 to 160. In the terminal portion 400, a part of the plated electrode 401 is exposed, and a transparent conductive film 404 made of ITO is formed.
[0103]
Further, a polarizing plate 309 and the like were appropriately provided using a known technique. And FPC was affixed on the exposed part among terminal parts using a well-known technique. FIG. 8C shows a cross-sectional view of the FPC 405 after bonding.
[0104]
The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG. In addition, the same code | symbol was used for the part corresponding to FIG.
[0105]
The top view shown in FIG. 9 is a pixel portion, a drive circuit, an external input terminal 309 to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) 311 is attached, a wiring 310 for connecting the external input terminal to the input portion of each circuit, and the like. The active matrix substrate on which the substrate is formed and the counter substrate 300 provided with a color filter or the like are attached to each other with a sealant 307 interposed therebetween.
[0106]
A light shielding layer 303a is provided on the counter substrate side so as to overlap with the gate wiring side driving circuit 201a, and a light shielding layer 403b is formed on the counter substrate side so as to overlap with the source wiring side driving circuit 201b. In addition, the color filter 302 provided on the counter substrate side over the pixel portion 205 includes a light-shielding layer and a colored layer of each color of red (R), green (G), and blue (B) corresponding to each pixel. It has been. When actually displaying, a color display is formed with three colors of a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer. It shall be arbitrary.
[0107]
Here, the color filter 302 is provided on the counter substrate for colorization; however, there is no particular limitation, and when an active matrix substrate is manufactured, a color filter may be formed on the active matrix substrate.
[0108]
In addition, a light-shielding layer 303 is provided between adjacent pixels in the color filter, and shields light other than the display area. Further, a light shielding layer may be provided also in a region covering the driver circuit. The area that covers the drive circuit is not particularly provided with a light-blocking layer because it is covered with a cover when the liquid crystal display device is incorporated later as a display portion of an electronic device. Further, when the active matrix substrate is manufactured, a light shielding layer may be formed on the active matrix substrate.
[0109]
Further, an FPC 411 composed of a base film and wiring is bonded to the external input terminal with an anisotropic conductive resin. Furthermore, the mechanical strength is increased by the reinforcing plate.
[0110]
Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.
[0111]
The liquid crystal module manufactured as described above can be used as a display portion of various electronic devices. When this liquid crystal module is incorporated, a backlight 310 and a light guide plate 311 are provided and covered with a cover 312, the active matrix liquid crystal display device shown in FIG. 6 is completed. Note that the cover 312 and the liquid crystal module are bonded together using an adhesive or an organic resin. In addition, when the substrate and the counter substrate are bonded to each other, the organic resin may be filled between the frame and the substrate by being surrounded by a frame and bonded.
[0112]
[Example 2]
The n-channel TFT shown in Example 1 is obtained by adding an element belonging to Group 15 of the periodic table (preferably phosphorus) or an element belonging to Group 13 of the periodic table (preferably boron) to the semiconductor serving as a channel formation region. The enhancement type and the depression type can be created separately.
[0113]
When an NMOS circuit is formed by combining n-channel TFTs, an enhancement type TFT is formed (hereinafter referred to as an EEMOS circuit), and an enhancement type and a depression type are combined (hereinafter referred to as an EDMOS circuit). Called).
[0114]
Here, FIG. 10A shows an example of an EEMOS circuit, and FIG. 10B shows an example of an EDMOS circuit. In FIG. 10A, reference numerals 31 and 32 denote enhancement type n-channel TFTs (hereinafter referred to as E-type NTFTs). In FIG. 10B, 33 is an E-type NTFT, and 34 is a depletion type n-channel TFT (hereinafter referred to as a D-type NTFT).
[0115]
In FIGS. 10A and 10B, VDH is a power supply line to which a positive voltage is applied (positive power supply line), and VDL is a power supply line to which a negative voltage is applied (negative power supply line). . The negative power source line may be a ground potential power source line (ground power source line).
[0116]
Further, FIG. 11 shows an example in which a shift register is manufactured using the EEMOS circuit shown in FIG. 8A or the EDMOS circuit shown in FIG. In FIG. 11, reference numerals 40 and 41 denote flip-flop circuits. Reference numerals 42 and 43 denote E-type NTFTs. A clock signal (CL) is input to the gate of the E-type NTFT 42, and a clock signal (CL bar) having an inverted polarity is input to the gate of the E-type NTFT 43. Reference numeral 44 denotes an inverter circuit. As shown in FIG. 11B, the EEMOS circuit shown in FIG. 10A or the EDMOS circuit shown in FIG. 10B is used. Therefore, it is also possible to configure all the drive circuits of the display device with n-channel TFTs.
[0117]
Note that this embodiment can be freely combined with Embodiment 1.
[0118]
[Example 3]
The present invention is characterized in that the source wiring of the pixel portion is formed in a process different from the source wiring of the driver circuit. In this embodiment, differences from the prior art will be described in detail with reference to FIG. In FIG. 12, for simplification, only three source wirings 91 and three gate wirings 92 are shown in the pixel portion. In addition, the source wiring 91 of the pixel portion is a strip shape parallel to each other, and the interval is equal to the pixel pitch.
[0119]
FIG. 12 shows a block configuration for performing digital driving. In this embodiment, a source side driver circuit 93, a pixel portion 94, and a gate side driver circuit 95 are provided. Note that in this specification, a driving circuit is a generic term including a source side driving circuit and a gate side driving circuit.
[0120]
The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, a D / A converter 93d, and a buffer 93e. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.
[0121]
In this embodiment, as shown in FIG. 12, a contact portion exists between the source side driving circuit 93 and the pixel portion 94. This is because the source wiring of the source side driver circuit and the source wiring 91 of the pixel portion are formed by different processes. In the present invention, the source wiring of the pixel portion is formed by a process different from the source wiring of the source side driver circuit in order to perform plating on the wiring using the same material as the gate electrode and cover it with a low resistance material. Yes.
[0122]
Further, in order to perform the plating process, all the source wirings of the pixel portion are connected by a wiring pattern so as to have the same potential, and an electrode for the plating process is provided. Similarly, the terminal portions are connected by a wiring pattern, and electrodes for plating are provided. In FIG. 12, electrodes for plating are separately provided. However, they may be further connected by a wiring pattern and plated at one time. Moreover, the dotted line in FIG. 12 is a parting line of the substrate, and indicates a part to be cut after the plating process.
[0123]
The pixel portion 94 includes a plurality of pixels, and each of the plurality of pixels is provided with a TFT element. The pixel portion 94 is provided with a large number of gate wirings 92 connected to the gate side driving circuit in parallel with each other. In addition, it is desirable that the terminal portion is covered with a low resistance material by plating the electrode using the same material as the gate electrode.
[0124]
Note that a gate side driver circuit may be provided on the opposite side of the gate side driver circuit 95 with the pixel portion 94 interposed therebetween.
[0125]
In the case of analog driving, a sampling circuit may be provided instead of the latch circuit.
[0126]
Note that this embodiment can be freely combined with Embodiment 1 or Embodiment 2.
[0127]
[Example 4]
In the first embodiment, an example in which the tapered portion is selectively etched is shown, but this embodiment shows an example in which etching is not performed. Since only the pixel portion is different, only the pixel portion is shown in FIG.
[0128]
This embodiment is an example in which the third etching process of FIG. In FIG. 13A, a pixel electrode 700 made of a transparent conductive film is formed as the gate electrode of the pixel TFT 709 as in FIG.
[0129]
In FIG. 13A, the structure of the gate electrode is different from that in Embodiment 1, and the first conductive layers 707 and 708 have a tapered portion. Therefore, the first conductive layer 707 overlaps the impurity region with the insulating film interposed therebetween.
[0130]
Note that the first conductive layers 707 and 708 each having a tapered portion correspond to the first conductive layer 124a of the first embodiment.
[0131]
FIG. 13B shows an example of a triple gate structure. In FIG. 13B, the first conductive layer 804 overlaps with the impurity regions 803 and 805 with the insulating film interposed therebetween, and the first conductive layer 807 overlaps with the impurity regions 806 and 808 with the insulating film interposed therebetween. The conductive layer 810 overlaps with the impurity regions 809 and 811 with the insulating film interposed therebetween.
[0132]
In this example, off current can be reduced by adopting a triple gate structure. Further, the off-current may be further reduced by reducing the width of the gate electrode, for example, 1.5 μm.
[0133]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 3.
[0134]
[Example 5]
In Example 1, an example of manufacturing an active matrix substrate used for a transmissive liquid crystal display device is shown, but this example shows a reflective type. Since only the pixel portion is different, only the pixel portion is shown in FIG.
[0135]
As the substrate, a glass substrate, a quartz substrate, or a plastic substrate can be used. Furthermore, since this embodiment is a reflection type, it is not particularly limited, and a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed can also be used.
[0136]
In FIG. 14, according to the first embodiment, a plating process is performed to obtain a source wiring 1401, a second interlayer insulating film is formed, and then patterned using a photomask to form a contact hole, and each electrode and gate wiring This is an example in which a pixel electrode 1406 is formed. The pixel electrode 1406 is electrically connected to the impurity region 153. As the material of these electrodes and the pixel electrode 1406, a material having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof is used. In FIG. 14, the pixel TFT 1402 has a double gate structure and has two channel formation regions which overlap with the gate electrodes 1403 and 1404 with an insulating film interposed therebetween.
[0137]
In the manufacturing method for obtaining the structure of FIG. 14, since the pixel electrode and the gate wiring can be manufactured at the same time, the number of photomasks necessary for manufacturing the active matrix substrate can be four.
[0138]
Note that this embodiment can be freely combined with Embodiment 2.
[0139]
[Example 6]
In this embodiment, an example in which source wiring is formed in a process different from that in Embodiment 1 is shown in FIG.
[0140]
FIG. 15A illustrates an example in which the source wiring 903 in the pixel portion is plated, an interlayer insulating film is formed, a contact hole is formed in the interlayer insulating film, and then the terminal portion 900 is plated.
[0141]
First, the electrode 901 of the terminal portion is formed in the same process as the gate electrode 902 of the driver circuit portion. A source wiring 903 is formed in the same process as this electrode. First, only the source wiring 903 in the pixel portion is selectively plated. Thereafter, an interlayer insulating film is formed, and a contact hole is formed. When forming this contact hole, a part of the electrode 901 of the terminal portion 900 is exposed. Next, only the exposed region of the electrode 901 in the terminal portion is plated to form a plating film 904. Thereafter, lead wiring, source wiring, and drain wiring are formed. In the subsequent steps, the structure shown in FIG.
[0142]
However, the activation of the impurity element contained in the semiconductor layer is preferably performed before the plating film 904 is formed.
[0143]
Similarly to the first embodiment, when plating, wirings or electrodes to be plated are connected by a dummy pattern so as to have the same potential. In a later step, the electrodes are separated from each other when the substrate is divided. Moreover, you may form a short ring with these dummy patterns.
[0144]
FIG. 15B illustrates an example in which plating is performed in a step different from that in FIG. In this embodiment, the gate electrode 1002 is formed and the source wiring 1003 is not formed at the same time.
[0145]
After forming an insulating film for protecting the gate electrode 1002, the impurity element added to each semiconductor layer is activated, and a low-resistance metal material (typically aluminum, silver, copper) is formed on the insulating film by a photolithography process. The source wiring 1003 in the pixel portion and the electrode 1001 in the terminal portion are formed at the same time. As described above, in the present invention, since the source wiring of the pixel portion is formed of a low-resistance metal material, it can be driven sufficiently even if the area of the pixel portion is increased. Further, in order to reduce the number of masks, the source wiring may be formed by a printing method.
[0146]
Next, a plating process (electrolytic plating method) is performed to form a metal film on the surface of the source wiring 1003 in the pixel portion and the surface of the electrode 1001 in the terminal portion. In the subsequent steps, the structure shown in FIG.
[0147]
FIG. 15C illustrates an example of forming a source wiring in a step different from that in FIG.
[0148]
In this embodiment, the source wiring is formed by a printing method. In order to improve the positional accuracy of the source wiring of the pixel, a conductive layer was provided.
[0149]
In this example, the conductive layers 905a and 905b were formed in the same process as the gate electrode. Next, the impurity element was activated without covering the gate electrode with the insulating film. As activation, for example, thermal annealing is performed under reduced pressure in an inert atmosphere, thereby suppressing increase in resistance due to oxidation of the conductive layer. Next, a source wiring was formed using a printing method so as to fill the gap between the conductive layers. Further, by providing a conductive layer along the source wiring, it is possible to prevent disconnection that is likely to occur in the printing method (screen printing). In the subsequent steps, the structure shown in FIG.
[0150]
In screen printing, for example, a paste (diluent) mixed with metal particles (Ag, Al, etc.) or ink is used as a mask with a plate having an opening of a desired pattern as a mask. Then, a desired pattern of wiring is formed by performing thermal firing. Such a printing method is relatively inexpensive and suitable for the present invention because it can cope with a large area.
[0151]
In addition, a relief printing method using a rotating drum, an intaglio printing method, and various offset printing methods can be applied to the present invention instead of the screen printing method.
[0152]
As described above, the source wiring of the pixel portion can be formed by various methods.
[0153]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 5.
[0154]
[Example 7]
In this embodiment, FIG. 18 shows an example of a top view of a pixel in the case of a triple gate structure.
[0155]
In FIG. 18, 1201 is a semiconductor layer, 1202 is a gate electrode, 1203 is a capacitor electrode, 1204 is a source wire, 1205 is a gate wire, 1206 is a capacitor wire connected to the capacitor electrode, and 1207 is a connection between the semiconductor layer and the source wire. 1209 is a pixel electrode, and 1208 is an electrode connecting the semiconductor layer and the pixel electrode.
[0156]
In this embodiment, the gate electrode 1202 and the capacitor electrode 1203 are formed in the same step over the insulating film covering the semiconductor layer 1201. The source wiring 1204 is formed in the same process as these electrodes or in a different process. In this embodiment, after the impurity element of the semiconductor layer is added and the activation process is performed, it is formed on the gate insulating film in a separate process, and the surface is plated to reduce the resistance of the wiring. In this embodiment, the gate wiring 1205, the capacitor wiring 1206, and the electrodes 1207, 1208 are formed in the same process on the interlayer insulating film that covers the gate electrode 1202, the capacitor electrode 1203, and the source wiring 1204. In addition, an electrode 1208 is provided to partially overlap and overlap with a pixel electrode 1209 made of a transparent conductive film formed on the interlayer insulating film. As shown in FIG. 18, the capacitor 1206 is disposed between the electrode 1208 and the electrode 1207 when viewed from above.
[0157]
The gate electrode 1202 overlaps with the semiconductor layer 1201 at three positions with a gate insulating film interposed therebetween, and has a triple gate structure. A cross-sectional view in the vicinity of the gate electrode is substantially the same as FIG.
[0158]
FIG. 14 shows an example in which the capacitor of the pixel portion is formed of a semiconductor layer different from that of the pixel TFT. However, in FIG. 18, the capacitor is formed of a part of the semiconductor layer of the pixel TFT. In order to increase the capacity, the thickness of the insulating film may be reduced to about 80 nm.
[0159]
In this example, off current can be reduced by adopting a triple gate structure. Further, the off current may be further reduced by reducing the width of the gate electrode 1202, for example, 1.5 μm.
[0160]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 6.
[0161]
[Example 8]
In this embodiment, an example in which PPTA (Plural Pulse Thermal Annealing) is used as the heat treatment in Embodiment 1 will be described.
[0162]
PPTA means heating by a light source (halogen lamp, metal halide lamp, high-pressure mercury lamp, high-pressure sodium lamp, xenon lamp, etc.) and cooling by circulation of a refrigerant (nitrogen, helium, argon, krypton, xenon, etc.) into the processing chamber. This is a heat treatment in which the cycle is repeated a plurality of times. The light emission time per time of the light source is 0.1 to 60 seconds, preferably 0.1 to 20 seconds, and the light is irradiated a plurality of times. Note that the light source is lit in a pulsed manner by the power source and the control circuit so that the holding period of the semiconductor film is 0.5 to 5 seconds.
[0163]
By irradiating light that is selectively absorbed by the semiconductor film by PPTA from a light source provided on one side or both sides of the semiconductor film, the substrate itself is not heated so much. Is selectively heated (temperature increase rate: 100 to 200 ° C./second). Moreover, in order to suppress the temperature rise of a board | substrate, it cools from the periphery with a refrigerant | coolant (temperature fall rate 50-150 degree-C / sec).
[0164]
The example used for activation among the heat processing in Example 1 is shown below.
[0165]
After the insulating film 154 shown in FIG. 2C is formed, activation is performed with PPTA. Pulse light is irradiated from one side or both sides of the substrate using a tungsten halogen lamp as a light source. At this time, the flow rate of He is increased or decreased in synchronization with the blinking of the tungsten halogen lamp, and the semiconductor film is selectively heated.
[0166]
The PPTA activates the impurity element, and the metal element used for crystallization included in the semiconductor layer can be gettered from the channel formation region to the impurity region. Note that it is more effective that an impurity element imparting p-type is added to the impurity region in addition to phosphorus. Therefore, it is preferable to add a step of adding boron that imparts p-type after the first doping. Further, the PPTA treatment chamber may be in a reduced pressure state of 13.3 Pa or less to prevent oxidation and contamination.
[0167]
Note that this embodiment can be freely combined with any one of Embodiments 1 to 7.
[0168]
[Example 9]
The driver circuit and the pixel portion formed by implementing the present invention can be used for various modules (active matrix liquid crystal module, active matrix EL module, active matrix EC module). That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.
[0169]
Such electronic devices include video cameras, digital cameras, head mounted displays (goggles type displays), car navigation systems, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Can be mentioned. Examples of these are shown in FIGS.
[0170]
FIG. 19A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, a keyboard 2004, and the like. The present invention can be applied to the display portion 2003.
[0171]
FIG. 19B shows a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, a display unit 2205, and the like. The present invention can be applied to the display portion 2205.
[0172]
FIG. 19C shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.
[0173]
FIG. 20A illustrates a portable book (electronic book) which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, an antenna 3006, and the like. The present invention can be applied to the display portions 3002 and 3003.
[0174]
FIG. 20B shows a display, which includes a main body 3101, a support base 3102, a display portion 3103, and the like. The present invention can be applied to the display portion 3103 whose diagonal is 10 to 50 inches.
[0175]
As described above, the applicable range of the present invention is so wide that the present invention can be applied to methods for manufacturing electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-8.
[0176]
【The invention's effect】
According to the present invention, in a semiconductor device typified by an active matrix liquid crystal display device, a favorable display can be realized even if the area of a pixel portion is increased and the screen size is increased. Since the resistance of the source wiring of the pixel portion is greatly reduced, the present invention can be applied to, for example, a large screen with a diagonal of 40 inches or a diagonal of 50 inches.
[Brief description of the drawings]
FIGS. 1A to 1C are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of an AM-LCD. FIGS.
3A and 3B are diagrams illustrating a manufacturing process of an AM-LCD.
FIG. 4 is a top view of a pixel.
FIG. 5 is a top view of a pixel.
FIG. 6 is a diagram showing a cross-sectional structure of an active matrix liquid crystal display device.
FIG. 7 is a diagram showing a terminal portion.
FIG. 8 is a diagram showing a terminal portion.
FIG. 9 is a diagram illustrating an appearance of a liquid crystal module.
FIG. 10 is a diagram showing a configuration of an NMOS circuit.
FIG. 11 illustrates a structure of a shift register.
FIG. 12 shows a top view.
FIG. 13 is a cross-sectional view of a pixel portion.
FIG. 14 is a diagram showing a cross section of a pixel portion.
FIG. 15 is a diagram showing a terminal portion.
FIG. 16 is a simplified diagram showing a state of laser irradiation.
17 shows a mask 146. FIG.
FIG 18 is a top view of a pixel.
FIG 19 illustrates an example of an electronic device.
FIG. 20 illustrates an example of an electronic device.

Claims (26)

A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a TFT and a source wiring in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode;
A drive circuit;
A semiconductor device comprising: a terminal portion in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a source wiring in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode, and a first n-channel TFT;
A drive circuit comprising a second n-channel TFT;
A semiconductor device comprising: a terminal portion in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a source wiring in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode, and a first p-channel TFT;
A drive circuit comprising a second p-channel TFT;
A semiconductor device comprising: a terminal portion in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode.   4. The semiconductor device according to claim 1, wherein the low-resistance material film is a material film containing Cu, Al, Au, Ag, or an alloy thereof as a main component. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a source wiring in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a lower resistance than the gate electrode and a first n-channel TFT by plating ;
A drive circuit comprising a second n-channel TFT;
A semiconductor device comprising: a terminal portion whose surface of a wiring made of the same material as the gate electrode is covered with a material film having a lower resistance than the gate electrode by plating . A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A pixel portion including a source wiring and a first p-channel TFT in which a surface of a wiring made of the same material as the gate electrode is covered with a material film having a lower resistance than the gate electrode by plating ;
A drive circuit comprising a second p-channel TFT;
A semiconductor device comprising: a terminal portion whose surface of a wiring made of the same material as the gate electrode is covered with a material film having a lower resistance than the gate electrode by plating . 6. The method according to claim 5 , wherein the first n-channel TFT has a gate electrode and a channel formation region overlapping with the gate electrode, and the width of the channel formation region and the width of the gate electrode are the same. A featured semiconductor device. 6. The method according to claim 5 , wherein the first n-channel TFT includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. A featured semiconductor device. 9. The semiconductor device according to claim 8 , wherein the first n-channel TFT has three channel formation regions.   10. The second n-channel TFT according to claim 5, wherein the second n-channel TFT includes a gate electrode having a tapered portion, a channel formation region overlapping with the gate electrode, and an impurity region partially overlapping with the gate electrode. And a semiconductor device. In any one of claims 5 or 7 to 10, the impurity region of the first and second n-channel type TFT, the concentration gradient of the impurity in the range of at least ^{1 × 10 17 ~1 × 10 18} / cm 3 A semiconductor device including a region having an impurity concentration as the distance from a channel formation region increases in the region. In any one of claims 5 or 7 to 11, wherein the first n-channel TFT, and wherein a has a plurality of channel forming regions. In any one of claims 5 to 12, the surface of the source wiring of the surface and the pixel portion of the terminal portion is covered with a thin film made of a material mainly Cu, Al, Au, Ag, or an alloy thereof A semiconductor device characterized by that. In any one of claims 5 to 13, wherein a said source wiring terminal portion and the pixel portion are those plating simultaneously. In any one of claims 5 to 13, wherein a said source wiring terminal portion and the pixel portion are those plated treated separately. 16. The semiconductor device according to claim 1, wherein the driving circuit includes an EEMOS circuit or an EDMOS circuit. A semiconductor device comprising a TFT including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film,
A terminal portion in which at least a part of the surface of the wiring made of the same material as the gate electrode is covered with a material film having a lower resistance than the gate electrode ;
A semiconductor device comprising: a source wiring in which at least a part of a surface of a wiring made of the same material as the gate electrode is covered with a material film having a resistance lower than that of the gate electrode. The semiconductor device according to any one of claims 1 to 17, the transmission type semiconductor device which is a liquid crystal module. The semiconductor device according to any one of claims 1 to 17, the reflection-type semiconductor device which is a liquid crystal module. The semiconductor device according to any one of claims 1 to 17, a video camera, a digital camera, a car navigation, a personal computer, a semiconductor device which is a portable information terminal or electronic amusement devices. A method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming an insulating film on the semiconductor layer;
A gate electrode, a wiring that becomes a source wiring of the pixel portion, and a wiring that becomes a terminal portion are formed of the same material on the insulating film,
Plating the surface of the wiring to be the source wiring of the pixel portion and the wiring to be the terminal portion with a material having a lower resistance than the material of the gate electrode ;
A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device including a driver circuit, a pixel portion, and a terminal portion on an insulating surface,
Forming a semiconductor layer on the insulating surface;
Forming an insulating film on the semiconductor layer;
A gate electrode, a wiring that becomes a source wiring of the pixel portion, and a wiring that becomes a terminal portion are formed of the same material on the insulating film,
The surface of the wiring to be the source wiring of the pixel portion is plated with a material having a lower resistance than the material of the gate electrode ,
Plating the surface of the wiring to be the terminal portion with a material having a lower resistance than the material of the gate electrode ;
A method for manufacturing a semiconductor device. According to claim 21 or claim 22, low-resistance material than the material of the gate electrode, Cu, Al, Au, Ag, or of a semiconductor device characterized by comprising a material mainly containing these alloys, Manufacturing method. 24. The semiconductor device according to claim 21 , wherein in the step of performing the plating according to any one of claims 21 to 23 , the source wirings of the pixel portion are connected to each other so as to have the same potential. Manufacturing method. 25. The method for manufacturing a semiconductor device according to claim 24 , wherein the wiring connected to have the same potential is divided by laser light after plating. 25. The method for manufacturing a semiconductor device according to claim 24 , wherein the wiring connected to have the same potential is divided simultaneously with the substrate after the plating process.

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