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JPH02223924A - Display panel manufacturing method - Google Patents

Display panel manufacturing method

Info

Publication number
JPH02223924A
JPH02223924A JP1043004A JP4300489A JPH02223924A JP H02223924 A JPH02223924 A JP H02223924A JP 1043004 A JP1043004 A JP 1043004A JP 4300489 A JP4300489 A JP 4300489A JP H02223924 A JPH02223924 A JP H02223924A
Authority
JP
Japan
Prior art keywords
display panel
thin film
manufacturing
conductive thin
panel according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1043004A
Other languages
Japanese (ja)
Inventor
Junichi Owada
淳一 大和田
Yoshiaki Mikami
佳朗 三上
Keiji Nagae
慶治 長江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1043004A priority Critical patent/JPH02223924A/en
Publication of JPH02223924A publication Critical patent/JPH02223924A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing Of Electric Cables (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は液晶を用いた平面型ディスプレイパネルの形成
法に係り、詳しくは低抵抗電極配線の形成方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming a flat display panel using liquid crystal, and more particularly to a method for forming a low resistance electrode wiring.

〔従来の技術〕[Conventional technology]

ガラス等の透明基板」二に薄膜トランジスタ(TFT)
等のスイッチ素子を形成し、液晶等の電気光学物質と積
層してなる、いわゆる、アクティブマトリクスディスプ
レイは、大面積・高精細化に適したディスプレイとして
、アイ・イー・イー・イー、プロシーディング59 (
1971年)第1566頁(Proeeedings 
of IEEE、 59 、 p1566 (1971
)に提案されて以来、近年特に非晶質シリコン(a−8
i)を用いたTFTや多結晶シリコン(p−3i)を用
いたTFTが盛んに研究開発されている。この方式によ
り、対角寸法が10インチ以上のディスプレイまで開発
されている。
Transparent substrate such as glass” Second, thin film transistor (TFT)
The so-called active matrix display, which is formed by forming switch elements such as and laminated with electro-optical materials such as liquid crystal, is a display suitable for large area and high definition, as described in IEE, Proceedings 59. (
1971), page 1566 (Proeeedings
of IEEE, 59, p1566 (1971
), amorphous silicon (a-8
TFTs using i) and TFTs using polycrystalline silicon (p-3i) are being actively researched and developed. Using this method, displays with diagonal dimensions of 10 inches or more have been developed.

大面積化を考慮した場合には、製造プロセスの簡略化に
より、欠陥発生確立を小さく抑え、パネルの歩留り向上
が必要となる。また、パネルの特性から見た場合には、
配線における電圧の遅延の影響が大きくなるため、配線
抵抗の低減が必須となる。
In consideration of increasing the area, it is necessary to simplify the manufacturing process to reduce the probability of defect occurrence and improve the yield of panels. In addition, when looking at the characteristics of the panel,
Since the influence of voltage delay in wiring increases, it is essential to reduce wiring resistance.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この問題に対しては従来の構造では金属薄膜により電極
を形成していたが、このためには、蒸着。
To solve this problem, conventional structures used thin metal films to form electrodes, but for this purpose, vapor deposition was used.

スパッタ等の膜形成工程とその膜の加工工程とが必要と
なり、製造プロセスの簡略化に対して問題があった。
This requires a film forming process such as sputtering and a processing process for the film, which poses a problem in simplifying the manufacturing process.

本発明の目的は簡易なプロセスで低抵抗の電極配線構造
を提供することにある。
An object of the present invention is to provide a low-resistance electrode wiring structure using a simple process.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明では、パターニングし
た比較的抵抗の高い導体上に1選択的に電圧を印加する
ことにより、メツキ等を行い、低抵抗化するようにした
ものである。
In order to achieve the above object, in the present invention, a voltage is selectively applied to a patterned conductor having a relatively high resistance, thereby performing plating or the like to lower the resistance.

〔実施例〕〔Example〕

以下1本発明の一実施例を第1図により説明する。まず
、第1の導電性薄膜2をパターニングし。
An embodiment of the present invention will be described below with reference to FIG. First, the first conductive thin film 2 is patterned.

島状に分離された部分と互いに連結した部分とを形成す
る0次に、低抵抗化が必要な部分に電圧を印加し、電解
メツキや電着等の手法により、第2の導体層を部分的に
積層する。たとえば、第1の導電性薄膜としてI T 
O(Indium Tin 0xide)を用いれば、
ディスプレイの表示用電極と配線部とで、配線部のみに
第2の導体層を積層することにより、TIOのエツチン
グ工程を1回だけで済ませることができる。
The second conductor layer is partially formed by applying a voltage to the parts where low resistance is required to form island-like separated parts and mutually connected parts, and using methods such as electrolytic plating or electrodeposition. Laminated according to the purpose. For example, I T as the first conductive thin film.
If O (Indium Tin Oxide) is used,
By laminating the second conductor layer only on the display electrodes and wiring portions of the display, the TIO etching step can be completed only once.

第2図は第1図の実施例の変形例である。(a)まずガ
ラス基板上に第1の導電性薄膜としてシリコン薄膜5を
形成する。(b)次に第2の導体層として金属薄膜6を
メツキ法等で積層する。(Q)熱処理等によりシリコン
と金属薄膜の合金(シリサイド)7を形成する。(d)
余分な第2の導電層を除去する。
FIG. 2 is a modification of the embodiment shown in FIG. (a) First, a silicon thin film 5 is formed as a first conductive thin film on a glass substrate. (b) Next, a metal thin film 6 is laminated as a second conductor layer by a plating method or the like. (Q) An alloy (silicide) 7 of silicon and metal thin film is formed by heat treatment or the like. (d)
Remove excess second conductive layer.

この方法により1部分的にシリサイド等の合金を容易に
形成できる。
By this method, an alloy such as silicide can be easily formed partially.

第3図は第2図の変形例である。すなわち、第2の導体
層をメツキで形成するかねりに、印刷法により導体ある
いは導体を分散した混成物8を部分的に塗布して、熱処
理により、シリサイドあるいは高濃度のドーピングされ
たシリコン薄膜層を形成し、最後に第2の導体層8を除
去する方法である。この方法によると、メツキ等で電界
を印加するためのパターンの制約がなくなり、製造工程
が簡略化される。また第2の導体層8のパターン精度は
それほど精密でなくとも良いという利点もある。
FIG. 3 is a modification of FIG. 2. That is, instead of forming the second conductor layer by plating, a conductor or a conductor-dispersed composite 8 is partially applied by a printing method, and then a silicide or highly doped silicon thin film layer is formed by heat treatment. In this method, the second conductor layer 8 is formed and finally the second conductor layer 8 is removed. According to this method, there is no restriction on the pattern for applying an electric field by plating or the like, and the manufacturing process is simplified. Another advantage is that the pattern accuracy of the second conductor layer 8 does not need to be so precise.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、−回のパターニングで抵抗の異なる部
分が形成できるので製造プロセスが簡略化され、大面積
パネルの製造が容易になるという効果がある。
According to the present invention, since portions with different resistances can be formed by patterning twice, the manufacturing process is simplified and large-area panels can be easily manufactured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示す平面図および断面図
、第2図は、本発明の変形例を示す断面図、第3図は本
発明のさらに他の変形例を示す図である。 −13; 第2図
FIG. 1 is a plan view and a sectional view showing an embodiment of the invention, FIG. 2 is a sectional view showing a modification of the invention, and FIG. 3 is a diagram showing still another modification of the invention. be. -13; Figure 2

Claims (1)

【特許請求の範囲】 1、ガラス基板上にTFTと液晶とを積層してなるアク
ティブマトリクス液晶ディスプレイにおいて、第1の導
電性薄膜の一部分を電界を印加しながら、第2の導体層
を積層した構造の電極配線を用いたことを特徴とした表
示パネルの製造方法。 2、特許請求の範囲第1項において、第1の導電性薄膜
としてITO(Indium Tin Oxide)を
用いたことを特徴とする表示パネルの形成法。 3、特許請求の範囲第1項において、第1の導電性薄膜
としてシリコンを用い、第2の導体層として金属を用い
、積層後に熱処理によりシリコン合金(シリサイド)と
したことを特徴とする表示パネルの製造方法。 4、特許請求の範囲第3項において、第2の導体層とし
て、白金、ニッケル、モリブデン、タングステンのいず
れかを用いたことを特徴とする表示パネルの製造方法。
[Claims] 1. In an active matrix liquid crystal display in which a TFT and a liquid crystal are laminated on a glass substrate, a second conductive layer is laminated while applying an electric field to a portion of the first conductive thin film. A method of manufacturing a display panel characterized by using structured electrode wiring. 2. A method for forming a display panel according to claim 1, characterized in that ITO (Indium Tin Oxide) is used as the first conductive thin film. 3. A display panel according to claim 1, characterized in that silicon is used as the first conductive thin film, metal is used as the second conductive layer, and the silicon alloy (silicide) is formed by heat treatment after lamination. manufacturing method. 4. The method of manufacturing a display panel according to claim 3, characterized in that the second conductor layer is made of platinum, nickel, molybdenum, or tungsten.
JP1043004A 1989-02-27 1989-02-27 Display panel manufacturing method Pending JPH02223924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1043004A JPH02223924A (en) 1989-02-27 1989-02-27 Display panel manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1043004A JPH02223924A (en) 1989-02-27 1989-02-27 Display panel manufacturing method

Publications (1)

Publication Number Publication Date
JPH02223924A true JPH02223924A (en) 1990-09-06

Family

ID=12651851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1043004A Pending JPH02223924A (en) 1989-02-27 1989-02-27 Display panel manufacturing method

Country Status (1)

Country Link
JP (1) JPH02223924A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04305627A (en) * 1991-04-03 1992-10-28 Sharp Corp Production of active matrix substrate
JP2001021920A (en) * 1999-07-07 2001-01-26 Furontekku:Kk Thin film transistor substrate and liquid crystal display
JP2002182237A (en) * 2000-12-11 2002-06-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
US7459352B2 (en) 2000-12-11 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US7629618B2 (en) 2000-12-21 2009-12-08 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181071A (en) * 1983-03-30 1984-10-15 Hoxan Corp Method for forming surface electrodes of solar cells
JPS6085577A (en) * 1983-10-17 1985-05-15 Fuji Xerox Co Ltd Manufacture of thin film photoelectric conversion element
JPS60128615A (en) * 1983-12-15 1985-07-09 Sumitomo Electric Ind Ltd Electrolytic plating method for semiconductor wafers
JPS61113285A (en) * 1984-11-08 1986-05-31 Fuji Electric Co Ltd Manufacture of photovoltaic element
JPS61185723A (en) * 1985-02-13 1986-08-19 Sharp Corp liquid crystal display device
JPS63291428A (en) * 1987-05-23 1988-11-29 Matsushita Electric Works Ltd Formation of bumps for replication

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59181071A (en) * 1983-03-30 1984-10-15 Hoxan Corp Method for forming surface electrodes of solar cells
JPS6085577A (en) * 1983-10-17 1985-05-15 Fuji Xerox Co Ltd Manufacture of thin film photoelectric conversion element
JPS60128615A (en) * 1983-12-15 1985-07-09 Sumitomo Electric Ind Ltd Electrolytic plating method for semiconductor wafers
JPS61113285A (en) * 1984-11-08 1986-05-31 Fuji Electric Co Ltd Manufacture of photovoltaic element
JPS61185723A (en) * 1985-02-13 1986-08-19 Sharp Corp liquid crystal display device
JPS63291428A (en) * 1987-05-23 1988-11-29 Matsushita Electric Works Ltd Formation of bumps for replication

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04305627A (en) * 1991-04-03 1992-10-28 Sharp Corp Production of active matrix substrate
US6720211B2 (en) 1999-05-18 2004-04-13 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
US6750475B1 (en) 1999-05-18 2004-06-15 Sharp Kabushiki Kaisha Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
JP2001021920A (en) * 1999-07-07 2001-01-26 Furontekku:Kk Thin film transistor substrate and liquid crystal display
JP2002182237A (en) * 2000-12-11 2002-06-26 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacturing method
US7459352B2 (en) 2000-12-11 2008-12-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9059216B2 (en) 2000-12-11 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US9666601B2 (en) 2000-12-11 2017-05-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US10665610B2 (en) 2000-12-11 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof
US7629618B2 (en) 2000-12-21 2009-12-08 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US9231044B2 (en) 2000-12-21 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same
US9793335B2 (en) 2000-12-21 2017-10-17 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing the same

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