JP2513739Y2 - Thin film transistor substrate - Google Patents
Thin film transistor substrateInfo
- Publication number
- JP2513739Y2 JP2513739Y2 JP1984053267U JP5326784U JP2513739Y2 JP 2513739 Y2 JP2513739 Y2 JP 2513739Y2 JP 1984053267 U JP1984053267 U JP 1984053267U JP 5326784 U JP5326784 U JP 5326784U JP 2513739 Y2 JP2513739 Y2 JP 2513739Y2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- source electrode
- electrode lead
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 title claims description 21
- 239000010408 film Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000007769 metal material Substances 0.000 claims description 5
- 238000000605 extraction Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000002788 crimping Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Electrodes Of Semiconductors (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【考案の詳細な説明】 本考案は薄膜トランジスタ（Thin Film Transistor,T
FTと略称される）基板に関するものである。従来、薄膜
トランジスタ基板のソース電極及び引出し線は透明電極
または金属電極で構成されるのが一般的であった。透明
電極のみで構成した場合は、パネルの開口率が向上し、
透過照明表示またはTN液晶反射表示を行うときの画像の
明度向上という長所がある反面、外部回路との接続にワ
イアボンディング、金属端子圧着等の利用が困難なた
め、例えばヒートシール、金属端子圧接等特殊な接続法
に制約され、さもなければ、透明電極上に何らかの手段
で金属を積層させるという工夫が必要で、この場合製造
工程が複雑になるという欠点がある。[Detailed Description of the Invention] The present invention is a thin film transistor (TFT).
Abbreviated as FT) substrate. Conventionally, the source electrode and the lead wire of the thin film transistor substrate are generally composed of a transparent electrode or a metal electrode. If it is composed of transparent electrodes only, the aperture ratio of the panel is improved,
Although it has the advantage of improving the brightness of the image when using transillumination display or TN liquid crystal reflection display, it is difficult to use wire bonding, metal terminal crimping, etc. to connect to an external circuit, so heat sealing, metal terminal pressure welding, etc. There is a drawback that it is restricted by a special connection method, otherwise it is necessary to devise a method of laminating a metal on the transparent electrode by some means, in which case the manufacturing process becomes complicated.
一方、ソース電極及び引出し線を全面金属電極で構成
した場合には、外部回路との接続は便利に行なえるが、
表示パネルの開口率が小さくなり、透過照明またはTN液
晶で、反射型表示を行なう場合は、画像の明度が不足す
るという欠点がある。On the other hand, when the source electrode and the lead wire are formed of metal electrodes on the whole surface, connection with an external circuit can be performed conveniently.
The aperture ratio of the display panel becomes small, and there is a drawback that the brightness of the image is insufficient when the reflective display is performed with the transillumination or the TN liquid crystal.
本考案の目的は、従来のように透明電極膜あるいは金
属電極膜の単一構成より成る場合における欠点を克服
し、開口率を向上させると共に、外部回路との接続を容
易ならしめ、薄膜トランジスタ基板を利用した表示装置
の性能を向上させることにある。The object of the present invention is to overcome the drawbacks in the conventional case of a single structure of a transparent electrode film or a metal electrode film, improve the aperture ratio, facilitate the connection with an external circuit, and improve the thin film transistor substrate. It is to improve the performance of the display device used.
また、本考案の別な目的は、薄膜トランジスタ基板の
ゲート金属膜形成時に一括して、ソース電極引出し部が
AlまたはCr,NiCr,Ta等のメッキ可能な同一の金属材料膜
でつくられることにより、製造工程の簡略化および実装
接続を容易にし、ひいては薄膜トランジスタ基板の低コ
スト化、信頼性向上をはかることにある。Another object of the present invention is to provide a source electrode lead-out portion collectively when forming a gate metal film on a thin film transistor substrate.
By making the same metal material film that can be plated such as Al or Cr, NiCr, Ta, etc., it is possible to simplify the manufacturing process, facilitate mounting connection, and further reduce the cost of the thin film transistor substrate and improve reliability. is there.
すなわち、本考案による薄膜トランジスタ基板は、矩
形状の絶縁基板上に、それぞれがソース電極およびゲー
ト電極を有して複数個配列された薄膜トランジスタと、
上記基板の一辺に複数本配列されたソース電極引出し部
と、同じく他辺に複数本配列されたゲート電極引出し部
と、を有してなる薄膜トランジスタ基板において、上記
ソース電極引出し部と上記薄膜トランジスタのゲート電
極とは、同一金属材料の薄膜でつくられており、上記ソ
ース電極引出し部は、その端部の一部を残して他部が重
なりをもって透明導電膜により上記薄膜トランジスタの
ソース電極に接続されるとともに、上記ソース電極引出
し部の端部における上記一部は、上記透明導電膜と実質
的に同一の膜厚をもった金属膜で被覆されていることを
特徴とするものである。That is, the thin film transistor substrate according to the present invention includes a thin film transistor having a source electrode and a gate electrode arranged on a rectangular insulating substrate.
In a thin film transistor substrate having a plurality of source electrode lead-out portions arranged on one side of the substrate and a plurality of gate electrode lead-out portions similarly arranged on the other side, the source electrode lead-out portion and the gate of the thin film transistor The electrode is made of a thin film of the same metal material, and the source electrode lead-out portion is connected to the source electrode of the thin film transistor by a transparent conductive film with the other portion overlapping while leaving a part of the end portion thereof. The part of the end portion of the source electrode lead-out portion is covered with a metal film having substantially the same thickness as the transparent conductive film.
第１図は本考案に係る薄膜トランジスタ基板の一実施
例を示す概略図で、図中、１は薄膜トランジスタアレイ
部、２はその周辺に位置するゲート電極引出し部、３は
ソース電極引出し部である。FIG. 1 is a schematic view showing an embodiment of a thin film transistor substrate according to the present invention, in which 1 is a thin film transistor array portion, 2 is a gate electrode lead-out portion located in the periphery thereof, and 3 is a source electrode lead-out portion.
第２図はソース電極引き出し部上に本考案によるメッ
キ金属部を形成する前の態様を示す断面図である。図
中、Ｓは薄膜トランジスタアレイ基板、３はソース電極
引出し部、４はソース透明導電膜、５はゲート電極、６
はドレイン透明画素電極、７は薄膜半導体、８は絶縁膜
を示す。図示のように、ソース電極引出し部３は、その
端部の一部を残して他部がソース透明電極膜４の下に部
分的重なりをもって接続されていて、且つソース電極引
出し部３は、薄膜トランジスタのゲート電極と同一の金
属材料例えばアルミニウム等の金属薄膜でつくられてい
る。この構造においては、薄膜トランジスタアレイ部１
のソース電極は透明導電膜で形成されるため、薄膜トラ
ンジスタアレイ部１の開口率が向上し、また、薄膜トラ
ンジスタのゲート部５とソース電極引き出し部３とを同
じ金属で構成することにより、製造時にゲート部５とソ
ース電極引出し部３とを一括同時成形することが可能と
なり、製造工程を簡略化できる。しかしながら、ソース
電極引出し部３の透明導電膜下の重なり部分以外の露出
部は、透明導電膜との間に段差がつくため、実装時にお
けるボンディングの容易性や、ワイヤボンディング、金
属端子圧着等の従来実績のある高信頼度の接続性などで
稍々難点がある。FIG. 2 is a sectional view showing a state before forming a plated metal portion according to the present invention on the source electrode lead portion. In the figure, S is a thin film transistor array substrate, 3 is a source electrode lead-out portion, 4 is a source transparent conductive film, 5 is a gate electrode, 6
Is a drain transparent pixel electrode, 7 is a thin film semiconductor, and 8 is an insulating film. As shown in the figure, the source electrode lead-out portion 3 is connected to the source transparent electrode film 4 while partially overlapping the other portion of the source electrode lead-out portion 3, and the source electrode lead-out portion 3 is a thin film transistor. It is made of the same metal material as that of the gate electrode, for example, a metal thin film such as aluminum. In this structure, the thin film transistor array section 1
Since the source electrode of is formed of a transparent conductive film, the aperture ratio of the thin film transistor array portion 1 is improved, and the gate portion 5 and the source electrode lead portion 3 of the thin film transistor are made of the same metal, so that the gate is manufactured at the time of manufacturing. The part 5 and the source electrode lead-out part 3 can be simultaneously molded at the same time, and the manufacturing process can be simplified. However, since the exposed portion of the source electrode lead-out portion 3 other than the overlapping portion under the transparent conductive film has a step between the exposed portion and the transparent conductive film, easiness of bonding at the time of mounting, wire bonding, metal terminal crimping, etc. There are some difficulties with the highly reliable connectivity that has been proven in the past.
図中、Ａで示す部分は配線接続領域、Ｂで示す部分は
薄膜トランジスタ基板の有効領域である。In the figure, a portion indicated by A is a wiring connection region, and a portion indicated by B is an effective region of the thin film transistor substrate.
第３図は、本考案実施例の要部を示す断面図で、ソー
ス電極引出し部３の金属としてメッキ可能な金属を使用
したものを示す。その他の部分は第２図に示すものと同
じであるので、同じ符号によって指示して、その説明は
省略する。この実施例では、ソース電極引出し部３とゲ
ート電極５とを絶縁基板上に同一金属材料の薄膜として
同時に形成した後、ソース透明導電膜４をソース電極引
出し部３の端部を一部残して他部上に重ねて形成する。
その後にソース電極引出し部３の重なり部分以外の露出
部にメッキ金属部９をメッキにより露出部がソース透明
導電膜の膜厚と実質的に同一となるように形成したの
で、実装時のボンディングが極めて容易となり、ワイヤ
ボンディング、金属端子圧着等の従来実績のある高信頼
性の接続が可能となる。FIG. 3 is a cross-sectional view showing an essential part of the embodiment of the present invention, in which a plateable metal is used as the metal of the source electrode lead-out part 3. Since the other parts are the same as those shown in FIG. 2, they are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the source electrode lead-out portion 3 and the gate electrode 5 are simultaneously formed as a thin film of the same metal material on an insulating substrate, and then the source transparent conductive film 4 is left with a part of the end portion of the source electrode lead-out portion 3 left. It is formed by overlapping on other parts.
After that, the plated metal portion 9 is formed on the exposed portion other than the overlapping portion of the source electrode lead-out portion 3 by plating so that the exposed portion is substantially the same as the film thickness of the source transparent conductive film. It becomes extremely easy, and highly reliable connection such as wire bonding and metal terminal crimping, which has been proven in the past, is possible.
以上説明したように、本考案による薄膜トランジスタ
基板においては、ソース電極引出し部にアルミニウムま
たはメッキ可能な金属を用い、ゲート電極形成と一括し
て形成した後、ソース透明電極を形成する構造とするこ
とによって、表示装置として具備すべき開口率条件を向
上させ、且つ製造工程簡略化による低コスト化、及び接
続方法の自由度増加によ信頼性の高い接続法が採用可能
となる効果を有する。As described above, in the thin film transistor substrate according to the present invention, the source electrode lead-out portion is formed of aluminum or a metal that can be plated, and the source transparent electrode is formed after the gate electrode is formed at the same time. The effect of improving the aperture ratio condition to be provided as a display device, reducing the cost by simplifying the manufacturing process, and increasing the degree of freedom of the connecting method makes it possible to employ a highly reliable connecting method.
第１図は本考案による薄膜トランジスタ基板の一実施例
を示す概略図、第２図はソース電極引出し部上に本考案
によるメッキ金属部を形成する前の態様を示す断面図、
第３図は本考案の実施例を示す断面図である。 １……薄膜トランジスタアレイ部、２……ゲート電極引
出し部 ３……ソース電極引出し部、４……ソース透明導電膜 ５……ゲート電極、６……ドレイン透明画素電極 ７……薄膜半導体、８……絶縁膜 ９……メッキ金属部、Ｓ……薄膜トランジスタ基板 Ａ……配線接続領域、Ｂ……パネル有効領域FIG. 1 is a schematic view showing an embodiment of a thin film transistor substrate according to the present invention, and FIG. 2 is a sectional view showing a state before forming a plated metal portion according to the present invention on a source electrode lead-out portion,
FIG. 3 is a sectional view showing an embodiment of the present invention. 1 ... Thin film transistor array part, 2 ... Gate electrode lead-out part 3 ... Source electrode lead-out part, 4 ... Source transparent conductive film 5 ... Gate electrode, 6 ... Drain transparent pixel electrode 7 ... Thin film semiconductor, 8 ... … Insulating film 9 …… Plating metal part, S …… Thin film transistor substrate A… Wiring connection area, B… Panel effective area
Claims (1)
電極およびゲート電極を有して複数個配列された薄膜ト
ランジスタと、上記基板の一辺に複数本配列されたソー
ス電極引出し部と、同じく他辺に複数本配列されたゲー
ト電極引出し部と、を有してなる薄膜トランジスタ基板
において、 上記ソース電極引出し部と上記薄膜トランジスタのゲー
ト電極とは、同一金属材料の薄膜でつくられており、上
記ソース電極引出し部は、その端部の一部を残して他部
が重なりをもって透明導電膜により上記薄膜トランジス
タのソース電極に接続されるとともに、上記ソース電極
引出し部の端部における上記一部は、上記透明導電膜と
実質的に同一の膜厚をもった金属膜で被覆されているこ
とを特徴とする薄膜トランジスタ基板。1. A thin film transistor having a plurality of source electrodes and a gate electrode, each of which is arranged on a rectangular insulating substrate, a plurality of source electrode lead-out portions arranged on one side of the substrate, and the same. In a thin film transistor substrate having a plurality of gate electrode lead-out portions arranged on a side, the source electrode lead-out portion and the gate electrode of the thin film transistor are made of a thin film of the same metal material, and the source electrode The extraction part is connected to the source electrode of the thin film transistor by a transparent conductive film with the other part overlapping while leaving a part of the end part thereof, and the part at the end part of the source electrode extraction part is the transparent conductive film. A thin film transistor substrate, which is covered with a metal film having substantially the same film thickness as the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984053267U JP2513739Y2 (en) | 1984-04-11 | 1984-04-11 | Thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984053267U JP2513739Y2 (en) | 1984-04-11 | 1984-04-11 | Thin film transistor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60166162U JPS60166162U (en) | 1985-11-05 |
| JP2513739Y2 true JP2513739Y2 (en) | 1996-10-09 |
Family
ID=30573962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984053267U Expired - Lifetime JP2513739Y2 (en) | 1984-04-11 | 1984-04-11 | Thin film transistor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2513739Y2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002182237A (en) * | 2000-12-11 | 2002-06-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
| US7459352B2 (en) | 2000-12-11 | 2008-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US7629618B2 (en) | 2000-12-21 | 2009-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2719597B2 (en) * | 1988-09-13 | 1998-02-25 | 日本プレシジョン・サーキッツ 株式会社 | Method for manufacturing active matrix silicon thin film transistor substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5922030A (en) * | 1982-07-28 | 1984-02-04 | Matsushita Electric Ind Co Ltd | Production of matrix display panel |
-
1984
- 1984-04-11 JP JP1984053267U patent/JP2513739Y2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002182237A (en) * | 2000-12-11 | 2002-06-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
| US7459352B2 (en) | 2000-12-11 | 2008-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US8421135B2 (en) | 2000-12-11 | 2013-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US7629618B2 (en) | 2000-12-21 | 2009-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
| US8013346B2 (en) | 2000-12-21 | 2011-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60166162U (en) | 1985-11-05 |
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