JP4100931B2 - PWM inverter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PWM inverter that controls an output by alternately turning on and off two semiconductor switches, and in particular, a PWM inverter provided with a dead time mode for preventing a power supply short-circuit at a time point when a semiconductor switch is switched on. It is about.
[0002]
[Prior art]
FIG. 16 is a diagram showing a typical PWM inverter 9, a DC power supply 91, a switching circuit 92 connected in series between both terminals a 1 and a 2 (a 2 is a GND terminal) of the DC power supply 91, and the switching A control circuit 93 for sending an on / off control signal to the control terminal of the circuit 92, a reactor 94 (consisting of an inductance 94a and a resistor 94b) drawn from the switching circuit 92, and a capacitor connected between the reactor 94 and the ground GND 95. Then, inverter output terminals b1 and b2 (b2 is a GND terminal) are drawn from both terminals of the capacitor 95.
[0003]
In the example shown in FIG. 16, the switching circuit 92 includes two switching transistors Q1 and Q2, and commutation diodes D1 and D2 are connected between the drive terminals (emitter and collector) of the switching transistors Q1 and Q2. Yes. The diodes D1 and D2 compensate for the current path when the switching transistors Q1 and Q2 are off.
[0004]
In the PWM inverter 9 of FIG. 16, it is assumed that a power load is connected to the inverter output terminals b1 and b2, and an output current Io flows out from the output terminal. In the circuit of FIG. 16, as shown in FIG. 17, (1) Q1: ON, Q2: OFF, (2) Q1: OFF, Q2: OFF, (3) Q1: OFF, Q2: ON, (4) ▼ Q1: OFF, Q2: OFF are repeated in the order of (1) → (2) → (3) → (4) → (1) → (2) → (3) → (4) ... To be controlled.
[0005]
The modes {circle around (2)} and {circle around (4)} in FIG. 17 are for compensating that the switching transistors Q1 and Q2 are not simultaneously turned on, and the period in this mode is referred to as dead time d. The voltage values of the switching transistors Q1 and Q2 during the dead time depend on the current flowing through the reactor via the commutation diode D1 or D2. The output characteristic of the PWM inverter 9 may be deteriorated due to the dead time d.
[0006]
[Problems to be solved by the invention]
By the way, when the dead time is provided, the output tends to decrease. If an attempt is made to eliminate the output drop with high responsiveness while ensuring the dead time period, the current value must be increased. For example, it is assumed that positive feedback is adopted in which (Q1 ON time) / (Q2 ON time) is increased or decreased in accordance with increase or decrease in load current (output current Io). That is, when the load current increases, the ON time ratio of the switching transistors Q1 and Q2 is changed, thereby increasing the power supply from the power source (increasing the on time of Q1) and increasing the load current. I can respond.
[0007]
In the positive feedback control, the system is stable as long as the control is properly performed, but the system oscillates when the control is inappropriate. That is, when the load current becomes large, if a current corresponding to the load current is supplied from the power supply, the balance between the supply current and the load current is maintained, so that oscillation does not occur. However, when the load current increases, if the supply current exceeds even a little, the output voltage increases (the capacitor 95 is further charged), and the load current increases as the output voltage increases. If the load current increases, the power supply side further increases the current supplied to the load, so that the output voltage further increases, resulting in oscillation. In particular, in the PWM inverter 9 of FIG. 16, the average value of the current is used as a control parameter, and the effect of dead time is not considered at all in the ON time ratio of the switching transistors Q1 and Q2, which is the control amount. For this reason, negative feedback control with a slow response speed must be employed.
[0008]
An object of the present invention is to change the ON time of the semiconductor switch in a PWM inverter having a dead time mode in a control period in order to prevent a power supply short circuit according to a state in which switching based on the dead time cannot be operated. It is to provide a compensated PWM inverter.
[0009]
[Means for Solving the Problems]
The present invention adopts a reactor current instead of an average value as an output current value of a control parameter. However, since this reactor current cannot be measured, an estimated value is adopted.
[0010]
In addition, it is known that if the ON time of the switching transistors Q1 and Q2 is controlled in anticipation of the increase or decrease of the reactor current in the dead time, accurate control can be performed in consideration of the influence of the commutation current in the dead time. To obtain the present invention.
[0011]
The PWM inverter according to the present invention includes a DC power supply, a switching circuit including a first semiconductor switch and a second semiconductor switch each having a commutation diode connected to the DC power supply terminal in a forward direction, and each of the semiconductor switches. An inverter control circuit for outputting an ON / OFF control signal, a reactor having one terminal connected to a connection point of each semiconductor switch, and a capacitor connected to the other terminal of the reactor and a ground terminal of the DC power supply A smoothing circuit, which alternately turns ON / OFF the first semiconductor switch and ON / OFF the second semiconductor switch, and ON period of the first semiconductor switch and ON period of the second semiconductor switch It is assumed that both semiconductor switches are controlled by providing a period during which both semiconductor switches are OFF. The dead time compensation includes dead time compensation time setting means for estimating the reactor current from the output current value, the output voltage value, the power supply voltage value, and the pulse width and setting the ON time of each semiconductor switch based on the estimated value. It was made to have a circuit.
[0012]
In the PWM inverter of the present invention, the dead time compensation time setting means is configured such that the operation of the semiconductor switch that should originally be in the ON state is limited by the dead time, and the direction of the current flowing through the reactor during the dead time is When the direction of the current that should flow when the switch is turned ON is the same, the ON time of the semiconductor switch can be changed.
[0013]
In the PWM inverter of the present invention, the ON time of the first semiconductor switch, the dead time during which the first semiconductor switch transitions from the ON state, the ON time of the second semiconductor switch, and the second time When the sum of the dead time for transition from the ON state of the semiconductor switch is constant, the change in the ON time of each semiconductor switch is the same as the ON time of the first semiconductor switch while keeping the PWM frequency constant. The ratio of the second semiconductor switch to the ON time can be changed.
In the present invention, the dead time compensation circuit has a reactor current,
First pattern: When the maximum and minimum peaks are both positive
Second pattern: When the maximum peak is positive and the minimum peak is near zero
Third pattern: When the maximum peak is positive and the minimum peak is negative
Fourth pattern: When the maximum peak is near zero and the minimum peak is negative
5th pattern: When the maximum and minimum peaks are both negative
The dead time compensation time setting means can set the ON time of each semiconductor switch in accordance with the pattern determined by the pattern determination means.
[0014]
Specifically, the pattern determining means
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Vo: output voltage, Vs: power supply voltage, L: reactor inductance, ω: PWM carrier frequency,
First pattern: i_{1, 2}Ic
Second pattern: i_{2, 3}= I_{1, 2}− (Vs−Vo) × d / L ≦ ic <i_{1, 2}
Third pattern: i_{3, 4}=-(I_{1, 2}−Vo × d / L) ≦ ic <i_{2, 3}
Fourth pattern: i_4,5= -I_{1, 2}≦ ic <i_{3, 4}
5th pattern: ic <i_4,5
The pattern to which the average value (estimated value) ic of the reactor current belongs can be determined.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing an embodiment of a PWM inverter 1 of the present invention. In FIG. 1, a PWM inverter 1 includes a DC power supply 11, a switching circuit 12 connected in series between both terminals a1 and a2 (a2 is a GND terminal) of the DC power supply 11, and control of each semiconductor switch of the switching circuit 12. The control circuit 13 sends an on / off control signal to a terminal, a reactor 14 drawn from the switching circuit 12, and a capacitor 15 connected between the reactor 14 and the ground GND. Further, inverter output terminals b1 and b2 (b2 is a GND terminal) are drawn from both terminals of the capacitor 15.
[0016]
In FIG. 1, the switching circuit 12 comprises two switching transistors (here, FETs) Q1 and Q2, and commutation diodes D1 and D2 are connected between the drive terminals of the switching transistors Q1 and Q2. The commutation diodes D1 and D2 compensate the current path when the switching transistors Q1 and Q2 are off. Reactor 14 is shown as a connection circuit between inductor 14a and line resistor 14b.
[0017]
The control circuit 13 can take in the power supply voltage signal x, the inverter output voltage y, and the inverter output current of the DC power supply 11 and output a control signal to the control terminals (g1, g2) of the switching transistors Q1, Q2. The control circuit 13 includes a dead time compensation circuit 5 and a PWM control waveform generator 6 as will be described with reference to FIG.
[0018]
The current flowing through the reactor 14 is classified into five patterns (indicated by currents i1 to i5) as shown in FIG. 2 according to the characteristics of the load and the control state. In the present embodiment, the H period or L period of PWM is adjusted according to whether the reactor current belongs to the above pattern. In FIG. 2, the PWM control signal is indicated by a rectangular wave, and these signal states (states including dead time) are indicated by pwm.
[0019]
The reactor current rises in the Q1: ON, Q2: OFF mode (region I), and falls in the Q1: OFF, Q2: ON mode (region III). Further, the reactor current is Q1: OFF, Q2: OFF mode (region II: dead time) in which the previous mode is changed from Q1: ON, Q2: OFF (region I), or Q1: OFF, Q2: In the Q1: OFF and Q2: OFF mode (area IV) transitioned from ON (area III), it rises, falls, or transitions from rising to falling with a peak, or transitioning from falling to rising.
[0020]
The first pattern is a case where the maximum peak Pmax and the minimum peak Pmin of the reactor current i are both positive. The second pattern is a case where the maximum peak Pmax of the reactor current i is positive and the minimum peak Pmin is zero. The third pattern is a case where the maximum peak Pmax of the reactor current i is positive and the minimum peak Pmin is negative. The fourth pattern is a case where the maximum peak Pmax of the reactor current i is zero and the minimum peak Pmin is negative. The fifth pattern is a case where the maximum peak Pmax and the minimum peak Pmin of the reactor current i are both negative. In FIG. 2, α and β indicate the decay time and increase time of the reactor current i.
[0021]
First, a 1st pattern is demonstrated based on FIG. 3 and FIG. 4 (A)-(E). FIG. 3 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the first pattern.
[0022]
In FIG. 3, the time indicated by d is a dead time. In the first pattern, the dead time d is included in the decay time α. As described above, in the first pattern, the minimum peak Pmin ≧ 0.
[0023]
Assuming that the PWM repetition period, that is, the carrier frequency is ω, the average ic of the current value flowing through the reactor 14 is as follows: Pmin ≧ 0
ic ≧ Pmax / 2
It becomes. Further, if the slope of the reactor current i at the decay time α is A, and the slope of the reactor current i at the increase time β is B,
β = A / (A + B) × ω
Pmax ≧ β × B
It becomes. Therefore,
ic ≧ (1/2) × A × B × ω / (A + B)
Is required.
[0024]
The slope A at the decay time α and the slope B at the increase time β are detected from the voltages Vs and Vo applied to the reactor (inductance L) 14 as follows. Here, Vs is a power supply voltage, and Vo is an output voltage.
A = | di / dt | = Vo / L
B = | di / dt | = (Vs−Vo) / L
Therefore, when the average current ic satisfies the following condition, it belongs to the first pattern, and therefore the control corresponding to that (corresponding to the first pattern) is performed.
[0025]
ic ≧ ((1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Note that (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω is a current value that represents the boundary between the first pattern and the second pattern. Hereinafter, this current value is expressed as i._{1, 2}Represented by That is, the average current value ic is
ic ≧ (i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω, the control by the first pattern is performed.
[0026]
4A to 4E are time-series diagrams showing changes in current in the first pattern. When the mode of Q1: ON, Q2: OFF (area I) in FIG. 4 (A) is changed to the mode of Q1: OFF, Q2: OFF (area II: dead time d) in FIG. There is no time effect. That is, in the Q1: OFF and Q2: OFF modes, the current flows in the positive direction through the commutation diode regardless of the ON / OFF operation of Q2, and thus there is no influence of the dead time. Similarly, when the mode is changed from Q1: OFF, Q2: OFF mode (area II: dead time) in FIG. 4B to Q1: OFF, Q2: ON (area III) mode in FIG. 4C. But there is no effect of dead time.
[0027]
On the other hand, from the mode of Q1: OFF, Q2: ON (region III) in FIG. 4C, to the mode of Q1: OFF, Q2: OFF in FIG. 4D (region IV: dead time d). When it changes, it is necessary to consider the influence over the whole dead time d. That is, during the period of the dead time d, it is equivalent to the PWM signal being Low, so that the PWM H period corresponds to dh = d in accordance with this period (the whole area of the dead time d in the region IV). At the same time, the L period is decreased by that time.
[0028]
There is no influence of the dead time d when the mode is changed from the Q1: OFF, Q2: OFF mode (area IV: dead time) in FIG. 4 (D) to the Q1: ON, Q2: OFF mode in FIG. 4 (E). .
[0029]
The second pattern will be described with reference to FIGS. 5 and 6A to 6E. FIG. 5 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the second pattern. In FIG. 5, α and β indicate the decay time and increase time of the reactor current i. In the second pattern, one dead time (region II) d is included in the decay time α, and the other dead time (region IV) d is included in the decay time α and the increase time β. In the second pattern, the minimum peak Pmin is almost zero.
[0030]
In the second pattern, the current is adjusted at the dead time d in the region IV so that the increase in current when the PWM signal is H and the decrease in current when the PWM signal is L are balanced. Since the compensation value at the dead time d in the region IV is dh and the average of the reactor current i is ic, the compensation value dh is given by the following equation as will be understood from FIG. 5 (details will be described later).
dh = d− (i_{1, 2}-Ic) * L / (Vs-Vo)
As described above, the slope A at the decay time α and the slope B at the increase time β are as follows.
A = | di / dt | = Vo / L
B = | di / dt | = (Vs−Vo) / L
It is.
[0031]
As described in the first pattern, it is not necessary to compensate for the dead time d in the region II. That is, in this case, the problem that “the switching transistor Q1 that should originally be turned on cannot be turned on and the current flows to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side” does not occur.
In addition, the current value representing the boundary between the second pattern and the third pattern is i._{2, 3}Then,
i_{2, 3}= I_{1, 2}− (Vs−Vo) × d / L
[0032]
However, i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
It becomes. Therefore, the current ic flowing through the reactor 14 is as follows:
i_{2, 3}≦ ic <i_{1, 2}
When satisfying, since it belongs to the second pattern, control by the second pattern is performed.
[0033]
6A to 6E are time series diagrams showing changes in current in the second pattern. The operation in the region II shown in FIG. 6B is not affected by the dead time d. Also, the first half of the dead time d shown in FIG. 6D is not affected by the dead time d. However, in the latter half of the dead time d shown in FIG. 6 (D ′), the switching transistor Q1 that should be turned on cannot be turned on, and the current flows to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side. Therefore, it is necessary to consider the influence of the dead time d. The period affected by the dead time d is the compensation value dh described above. Therefore, it is necessary to increase the H period of PWM by the time corresponding to the compensation value dh, and at the same time, decrease the L period by the time.
[0034]
The third pattern will be described with reference to FIGS. 7 and 8A to 8E. FIG. 7 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the third pattern. In the operation of the third pattern, the Q1: OFF, Q2: OFF mode (area II: dead time in FIG. 8B) that has changed from the Q1: ON, Q2: OFF mode (area I) in FIG. 8 (A). In d), a situation such as “the switching transistor Q2 that should originally be turned on cannot be turned on and the current flows to the reactor 14 via the commutation diode D1 on the switching transistor Q1 side” does not occur. FIGS. 8C and 8C show how the current direction changes in region III. In addition, in Q1: OFF, Q2: OFF mode (area IV: dead time d), which is shifted from the Q1: OFF, Q2: ON mode (area III) in FIG. The situation where the switching transistor Q1 cannot be turned on and the current flows to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side does not occur. Therefore,
dh = 0
There is no need to compensate for dead time d.
Current value i that becomes the boundary with the fourth pattern_{3, 4}Is expressed as follows.
[0035]
i_{3, 4}=-(I_{1, 2}-Vo × d / L)
However, i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Therefore, when the current i flowing through the reactor 14 satisfies the following condition, the current i belongs to the third pattern, and therefore control by the third pattern (control without dead time compensation) is performed.
[0036]
i_{3, 4}≦ ic <i_{2, 3}
A 4th pattern is demonstrated based on FIG. 9 and FIG. 10 (A)-(E). FIG. 9 is a waveform diagram showing the correspondence between the PWM signal and the output current i4 of the PWM inverter 1 in the fourth pattern. In the operation of the fourth pattern, Q1: OFF, Q2: OFF second half mode (area II: transitioned from the Q1: ON, Q2: OFF mode (area I) in FIG. 10A). In the dead time d), a situation occurs such as “the switching transistor Q2 that should be turned on originally cannot be turned on, and the current flows to the reactor 14 via the commutation diode D1 on the switching transistor Q1 side”. Therefore, it is necessary to compensate for the dead time d in the region II. FIGS. 10E and 10E show how the current direction changes in region I. FIG.
[0037]
As can be seen from FIG. 9, the compensation value dh of the dead time d is
dh = (ic−i_{3, 4}) X L / Vo
It becomes.
[0038]
Further, in the fourth pattern, the current value i that becomes the boundary with the fifth pattern_4,5Is expressed as follows.
i_4,5= -I_{1, 2}
However, i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
[0039]
Therefore, when the current ic flowing through the reactor 14 satisfies the following condition, it belongs to the fourth pattern, so that the control by the fourth pattern is performed.
i_4,5≦ ic <i_{3, 4}
That is, the PWM L period is increased by the time corresponding to the compensation value dh, and at the same time, the H period is decreased by the time.
[0040]
The fifth pattern will be described with reference to FIGS. 11 and 12A to 12E. FIG. 11 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the fifth pattern. In the operation of the fifth pattern, Q1: OFF, Q2: OFF mode (area II: dead time in FIG. 12 (B) transitioned from the Q1: ON, Q2: OFF mode (area I) in FIG. 12 (A). In the entire region d), a situation occurs in which “the switching transistor Q2 that should originally be turned on cannot be turned on, and the current flows to the reactor 14 via the commutation diode D1 on the switching transistor Q1 side”. Therefore, it is necessary to compensate for the dead time d in the region II.
[0041]
In this case, the dead time compensation value dh is
dh = d
It becomes.
Therefore, the current ic flowing through the reactor 14 is as follows:
ic ≦ i_4,5
When satisfying, since it belongs to the fifth pattern, control by the second pattern is performed. That is, the PWM L period is increased by a time corresponding to the above dh = d, and at the same time, the H period is decreased by the time.
[0042]
As described above, the following PWM control can be performed. FIG. 13 shows the dead time compensation circuit 5 mounted on the control circuit 13. FIG. 14 shows processing in the control circuit 13. The dead time compensation circuit 5 includes a pattern determination unit 51 and a dead time compensation time setting unit 52. Pattern determining unit 51 includes a reactor current value estimating unit. The pattern determining unit 51 determines which current pattern corresponds to the current control state based on the output current value Io, the output voltage Vo, the power supply voltage Vs, and the carrier frequency ω (S01). Then, the dead time compensation time setting unit 52 determines a compensation value dh corresponding to the pattern determined by the pattern determination unit 51, and sends the compensation value dh to the PWM control waveform generation unit 6. The PWM control waveform generation unit 6 PWM control based on the control signal corresponding to the pattern is performed (S02).
[0043]
When performing control with the compensation value dh added to the ON time of the switching transistor Q1, for example, control is performed to subtract the ON time of the switching transistor Q2 by dh.
[0044]
  In this case, as described in the above embodiment, the compensation value dh varies depending on the reactor current pattern. That is, dh = d in the first pattern and the fifth pattern, and dh = 0 in the third pattern. In the second pattern, dh = d− (i1,2-ic) × L / (Vs−Vo), and in the fourth pattern, (ic−i4,5) × L / Vo. There are various methods for obtaining the average value ic of the reactor current, which is a value that cannot be actually measured. The reactor current will be described later.FIG.It can obtain | require by the process illustrated to the flowchart of these.
[0045]
The pattern determination unit 51 stores in advance a pattern corresponding to the power supply voltage Vs, the output voltage Vo, the output current ic, and the carrier frequency ω as a table, so that the current pattern is the first pattern to the fifth pattern. It can be determined which one it belongs to.
[0046]
Control of the PWM inverter 1 is basically controlled by increasing / decreasing the ON time of the switching transistor. However, in the actual control, the value of the compensation value dh can be optimized. That is, the optimum compensation value dh can be obtained for each pattern in advance by simulation and stored in the dead time compensation time setting unit 52.
[0047]
  As described above, the reactor current ic is a value that cannot be measured. Therefore, in this embodiment,FIG.The estimated value <ic> of ic is obtained by executing the process shown in the flowchart of FIG.
  First, the current iL passing through the inductance L is represented by vL as the voltage applied to the inductance.
    diL = -vLdt / L
It is represented by
[0048]
Therefore, in this embodiment,
di_L: Δ <ic>
v_L: Vs × D− <ic> × R + Vo
dt: Sampling period (U × δt)
It is represented by
[0049]
Where <ic> is an estimated value of the average value ic of the reactor current, R is a resistance value of the inductance L, Vs is a voltage value of the DC power supply, D is a duty of PWM, Vo is an output voltage value (capacitor voltage value), δt is a PWM clock, and U is an integer representing one sampling period.
Therefore,
<Ic> = [Vs × D− <ic> × R + Vo] ∫dt
It is represented by
[0050]
When the above equation is expressed as discrete data,
<Ic>_k= Σ [Vs_k-1× D- <ic>_k-1× R + Vo] × (U × δt). Σ means accumulation from the start to the end (current) of the control unit. For example, if the control start is the nth sampling order and the current is the mth sampling order, Σ is represented by the accumulation of m sampling values from k = mn to k = n.
[0051]
  FIG.First, each parameter (Vs, Vo, etc.) is sampled (S100), and <ic> k is calculated (S101). Next, it is determined whether or not sampling has been performed m times from the start of the control unit (S102), and if it has not reached m times, the process returns to step S101.
[0052]
When the processing reaches m times in step S102, <ic>_kIs determined to belong to the first pattern (S103). Where <ic>_kWhether or not belongs to the first pattern
<Ic>_k≧ i_{1, 2}
However,
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Based on
[0053]
In step S103, <ic>_kIs determined to belong to the first pattern, dh is added to the PWM on-time, the parameter in the control unit is reset, and the execution of the control unit is newly started (S104).
The dh at this time is
dh = d
It is.
[0054]
In step S103, <ic>_kIs determined not to belong to the first pattern, it is determined whether it belongs to the second pattern (S105). Where <ic>_kWhether or not belongs to the second pattern
i_{2, 3}≦ <ic>_k<I_{1, 2}
However, i_{2, 3}= I_{1, 2}− (Vs−Vo) × d / L
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Based on
[0055]
In step S105, <ic>_kIs determined to belong to the second pattern, dh is added to the PWM on-time, the parameter in the control unit is reset, and the execution of the control unit is newly started (S106).
The dh at this time is
dh = d− (i_{1, 2}-Ic) * L / (Vs-Vo)
= D- (i_{1, 2}-<Ic>_k) × L / (Vs−Vo)
It is.
[0056]
In step S105, <ic>_kIs determined not to belong to the second pattern, it is determined whether it belongs to the third pattern (S107). Where <ic>_kWhether or not belongs to the third pattern
i_{3, 4}≦ <ic>_k<I_{2, 3}
However, i_{2, 3}= I_{1, 2}− (Vs−Vo) × d / L
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
i_{3, 4}=-(I_{1, 2}-Vo × d / L)
Based on
[0057]
In step S107, <ic>_kIs determined to belong to the third pattern, the PWM on-time is left as it is, the parameters in the control unit are reset, and the execution of the control unit is newly started (S108).
[0058]
In step S107, <ic>_kIs determined not to belong to the third pattern, it is determined whether it belongs to the fourth pattern (S109). Where <ic>_kWhether or not belongs to the fourth pattern
i_4,5= -I_{1, 2}≦ <ic>_k<I_{3, 4}
However,
i_{3, 4}=-(I_{1, 2}-Vo × d / L)
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Based on
[0059]
In step S109, <ic>_kIs determined to belong to the fourth pattern, dh is added to the PWM on-time, the parameter in the control unit is reset, and the execution of the control unit is newly started (S210).
The dh at this time is
dh = (ic−i_{3, 4}) X L / Vo
= (<Ic>_k-I_{3, 4}) X L / Vo
It is.
[0060]
In step S109, <ic>_kIs determined not to belong to the fourth pattern, it belongs to the fifth pattern. Where <ic>_kBelongs to the fifth pattern
<Ic>_k<I_4,5
However,
i_4,5= -I_{1, 2}≦ <ic>_k<I_{3, 4}
i_{3, 4}=-(I_{1, 2}-Vo × d / L)
i_{1, 2}= (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
It is to become.
[0061]
In this case, -dh is added to the PWM on-time, the parameter in the control unit is reset, and the execution of the control unit is newly started (S111).
[0062]
【The invention's effect】
The PWM inverter which compensated the state which the semiconductor switch based on dead time cannot operate | move by increasing ON time of the said semiconductor switch can be provided. Specifically, when the direction of the current flowing through the reactor during the dead time is the same as the direction of the current that should flow when the semiconductor switch is turned on, the ON time of the semiconductor switch is added for a predetermined time. Then, the effect of the dead time can be eliminated by shortening the semiconductor switch that is OFF for the predetermined time (the carrier frequency ω is not changed).
[0063]
As a result, control unevenness such as overshoot caused in a specific region due to discontinuity of output characteristics can be removed, and characteristics equivalent to those of other areas can be obtained without causing oscillation even in a region where rise characteristics are dull. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of a PWM inverter of the present invention.
FIG. 2 is a diagram showing five current patterns classified for control in the present embodiment.
FIG. 3 is a waveform diagram showing the correspondence between PWM signals and inverter control signals in a first pattern.
4A to 4E are time series diagrams showing changes in current in the first pattern. FIG.
FIG. 5 is a waveform diagram showing correspondence between PWM signals and inverter control signals in a second pattern.
6A to 6E are time series diagrams showing changes in current in a second pattern.
FIG. 7 is a waveform diagram showing correspondence between PWM signals and inverter control signals in a third pattern.
8A to 8E are time series diagrams showing changes in current in a third pattern.
FIG. 9 is a waveform diagram showing correspondence between PWM signals and inverter control signals in a fourth pattern.
FIGS. 10A to 10E are time-series diagrams showing changes in current in a fourth pattern. FIGS.
FIG. 11 is a waveform diagram showing correspondence between PWM signals and inverter control signals in a fifth pattern.
12A to 12E are time series diagrams showing changes in current in a fifth pattern.
FIG. 13 is a diagram showing a dead time compensation circuit mounted on the control circuit of the inverter according to the embodiment of the present invention.
FIG. 14 is a diagram showing processing in the control circuit according to the embodiment of the present invention.
FIG. 15 is a flowchart showing in detail processing in the embodiment of the present invention;
FIG. 16 is a circuit diagram showing a conventional PWM inverter.
17 is an operation explanatory diagram of the circuit of FIG. 16;
[Explanation of symbols]
1 PWM inverter
5 Dead time compensation circuit
6 PWM control waveform generator
11 DC power supply
12 Switching circuit
13 Control circuit
14 Reactor
15 capacitor
14a inductor
14b Line resistance
51 Pattern determination unit
52 Dead time compensation time setting section
Q1, Q2 switching transistor
D1, D2 commutation diode

Claims (5)

A DC power supply, a switching circuit composed of a first semiconductor switch and a second semiconductor switch, each of which has a commutation diode connected to the DC power supply terminal in a forward direction, and an ON / OFF control signal for each of the semiconductor switches. An inverter control circuit for outputting, a reactor having one terminal connected to a connection point of each semiconductor switch, and a smoothing circuit including a capacitor connected to the other terminal of the reactor and a ground terminal of the DC power source, ON / OFF of the first semiconductor switch and ON / OFF of the second semiconductor switch are alternately performed, and both semiconductors are between the ON period of the first semiconductor switch and the ON period of the second semiconductor switch. In a PWM inverter controlled by providing a period in which both switches are OFF,
A dead time compensation circuit including dead time compensation time setting means for estimating a reactor current from an output current value, an output voltage value, a power supply voltage value and a pulse width and setting an ON time of each semiconductor switch based on the estimation result A PWM inverter comprising:   In the dead time compensation time setting means, the operation of the semiconductor switch that should be in an ON state is limited by the dead time, and the direction of the current flowing through the reactor during the dead time is that the semiconductor switch is in the ON state. 2. The PWM inverter according to claim 1, wherein an ON time of each of the semiconductor switches is set when the direction of the current to flow is the same. From the ON time of the first semiconductor switch, the dead time for transition from the ON state of the first semiconductor switch, the ON time of the second semiconductor switch, and the ON state of the second semiconductor switch The PWM inverter according to claim 1 or 2, wherein a sum of transition dead time is constant.
The PWM inverter characterized in that the setting of the ON time of each semiconductor switch is a change in the ratio between the ON time of the first semiconductor switch and the ON time of the second semiconductor switch. In the dead time compensation circuit, the reactor current is
First pattern: When the maximum peak and the minimum peak are both positive Second pattern: When the maximum peak is positive and the minimum peak is near zero Third pattern: When the maximum peak is positive and the minimum peak is negative Fourth Pattern: When the maximum peak is near zero and the minimum peak is negative Fifth pattern: Pattern determining means for determining which of the cases where the maximum peak and the minimum peak are both negative,
The dead time compensation time setting means sets ON times of the semiconductor switches in accordance with the patterns determined by the pattern determination means. 4. PWM inverter. The pattern determining means includes
i _1,2 = (1/2) × Vo / Vs × [(Vs−Vo) / L] × ω
Vo: output voltage, Vs: power supply voltage, L: reactor inductance, ω: PWM carrier frequency,
First pattern: i _1,2 ≦ _ic
Second pattern: i _2,3 = i _1,2- (Vs-Vo) × d / L ≦ i _c <i _1,2
Third pattern: i _3,4 = − (i _1,2 −Vo × d / L) ≦ i _c <i _2,3
Fourth pattern: i _4,5 = −i _1,2 ≦ i _c <i _3,4
5th pattern: ic <i _4,5
The PWM inverter according to claim 1, wherein a pattern to which an average value ic of the reactor current belongs is determined.

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