JP2003250276A - PWM inverter - Google Patents

Abstract

[PROBLEMS] To provide a PWM inverter in which a state in which a semiconductor switch cannot operate based on a dead time is compensated for by increasing an ON time of the semiconductor switch. It comprises a pattern determination unit 51 and a dead time compensation time setting unit 52. The pattern determination unit 51 determines an estimated value of the current of the reactor 14 based on the output current value Io, the output voltage Vo, the power supply voltage Vs, and the carrier frequency ω of the PWM signal (H, L). And a dead time compensation time setting unit 5
According to 2, the ON time of the semiconductor switch is changed based on the estimation result by the reactor current estimation unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM inverter for controlling an output by alternately turning on and off two semiconductor switches, and in particular, a dead time mode for preventing a power source short circuit is set in a semiconductor switch on state. The present invention relates to a PWM inverter provided at the time of switching.

[0002]

2. Description of the Related Art FIG. 16 shows a typical PWM inverter 9
FIG. 3 is a diagram showing a DC power supply 91, a switching circuit 92 connected in series between both terminals a1 and a2 (a2 is a GND terminal) of the DC power supply 91, and these switching circuits 9
2, a control circuit 93 for sending an on / off control signal to the control terminal 2, a reactor 94 (composed of an inductance 94a and a resistance 94b) drawn from the switching circuit 92, and a capacitor 95 connected between the reactor 94 and the ground GND. It has and. From both terminals of the capacitor 95, the inverter output terminals b1 and b2
(B2 is a GND terminal) is pulled out.

In the example shown in FIG. 16, the switching circuit 9
2 is composed of two switching transistors Q1 and Q2, and a commutation diode D is provided between the drive terminals (emitter and collector) of each switching transistor Q1 and Q2.
1, D2 are connected. These diodes D1 and D2
Is for compensating the current path when the switching transistors Q1 and Q2 are off.

In the PWM inverter 9 of FIG. 16, it is assumed that a power source load is connected to the inverter output terminals b1 and b2 and an output current Io flows out from the output terminal. Then, in the circuit of FIG. 16, as shown in FIG.
Q1: ON, Q2: OFF, Q1: OFF, Q2:
OFF, Q1: OFF, Q2: ON, Q1: OF
F, Q2: 4 modes of OFF, →→→→
It is controlled to repeat in the order of →→→.

The modes of and of FIG. 17 are for compensating that the switching transistors Q1 and Q2 are not simultaneously turned on, and the period in this mode is referred to as dead time d. The voltage values of the switching transistors Q1 and Q2 during the dead time depend on the current flowing through the reactor via the commutation diode D1 or D2. The output characteristic of the PWM inverter 9 may be deteriorated due to the dead time d.

[0006]

By the way, when the dead time is provided, the output tends to decrease. If it is attempted to eliminate the output drop with high responsiveness while ensuring the dead time period, the current value must be increased. For example, according to the increase or decrease of the load current (output current Io), (Q
It is assumed that the positive feedback is adopted to increase / decrease (ON time of 1) / (ON time of Q2). That is, when the load current becomes large, the switching transistor Q
By changing the ON time ratio of 1 and Q2, the power supply from the power supply can be increased (the ON time of Q1 can be lengthened) and the increase in the load current can be met.

In the positive feedback control, the system is stable as long as the control is properly performed, but on the contrary, if the control is inappropriate, the system oscillates. That is, when the load current becomes large, if the power supply supplies enough current to match it,
Since the balance between the supply current and the load current is maintained, no oscillation occurs. However, if the supply current exceeds even a small amount when the load current increases, the output voltage increases (capacitor 95 is further charged), and the load current increases as the output voltage increases. If the load current increases, the power supply side further increases the current supplied to the load, resulting in a higher output voltage, resulting in oscillation. In particular, in the PWM inverter 9 of FIG. 16, the average value of the current is used as the control parameter, and the effect of dead time is not considered at all in the ON time ratio of the switching transistors Q1 and Q2, which is the control amount. Therefore, it is unavoidable to adopt the negative feedback control, which has a slow response speed.

An object of the present invention is to change the ON time of the semiconductor switch in a PWM inverter having a dead time mode in the control period in order to prevent a power supply short circuit according to the state in which switching based on the dead time cannot operate. The purpose is to provide a PWM inverter that is compensated by doing so.

[0009]

The present invention adopts the reactor current as the output current value of the control parameter, rather than the average value. However, since this reactor current cannot be measured, an estimated value is adopted.

Further, if the ON time of the switching transistors Q1 and Q2 is controlled in anticipation of an increase / decrease in the reactor current during the dead time, it is possible to perform accurate control in consideration of the influence of the commutation current during the dead time. The present invention has been accomplished by obtaining the knowledge of.

The PWM inverter of the present invention includes a first semiconductor switch and a second semiconductor switch, each of which has a direct current power source and a commutation diode forwardly connected to the direct current power source terminal.
A semiconductor switch, an inverter control circuit that outputs an ON / OFF control signal for each semiconductor switch, a reactor having one terminal connected to a connection point of each semiconductor switch, and the other terminal of the reactor. A smoothing circuit including a capacitor connected to the ground terminal of the DC power source, and turning on / off the first semiconductor switch and turning on / off the second semiconductor switch.
Alternately performing FF and O of the first semiconductor switch
It is premised that a period during which both semiconductor switches are turned off is provided between the N period and the ON period of the second semiconductor switch for control. Then, the reactor current is estimated from the output current value, the output voltage value, the power supply voltage value, and the pulse width, and the semiconductor switches are turned on based on the estimated value.
A dead time compensation circuit including a dead time compensation time setting means for setting time is provided.

In the PWM inverter of the present invention, the dead time compensation time setting means limits the operation of the semiconductor switch, which should be in the ON state, by the dead time.
When the direction of the current flowing through the reactor during the dead time is the same as the direction of the current that should flow when the semiconductor switch is in the ON state, the ON time of the semiconductor switch can be changed. .

In the PWM inverter of the present invention, the first
ON time of the semiconductor switch, dead time for transition of the first semiconductor switch from the ON state, ON time of the second semiconductor switch, and dead time for transition of the second semiconductor switch from the ON state When the sum of the time and the time is constant, changing the ON time of each of the semiconductor switches causes the first frequency to remain constant while keeping the PWM frequency constant.
The ON time of the semiconductor switch and the ON time of the second semiconductor switch can be changed.
In the present invention, the dead time compensating circuit has a reactor pattern in which the first pattern: when the maximum peak and the minimum peak are both positive, the second pattern: when the maximum peak is positive and the minimum peak is near zero, the third pattern: If the maximum peak is positive and the minimum peak is negative Fourth pattern: The maximum peak is near zero, and if the minimum peak is negative Fifth pattern: Which of the maximum peak and the minimum peak is negative? Including pattern determining means for determining,
The dead time compensation time setting means sets the O of each semiconductor switch according to the pattern determined by the pattern determining means.
N hours can be set.

Specifically, the pattern determining means is: i _1,2 = (1/2) × Vo / Vs × [(Vs-Vo)
/ L] × ω Vo: output voltage, Vs: power supply voltage, L: inductor inductance, ω: PWM carrier frequency, first pattern: i _1,2 ≦ ic second pattern: i _2,3 = i _{1 , 2−} (Vs−Vo) ×
d / L ≦ ic _{<i 1,2} third _{pattern: i 3,4 = - (i 1,2} -Vo × d /
L) ≦ ic <i _2,3 Fourth pattern: i _4,5 = −i _1,2 ≦ ic <i _3,4 Fifth pattern: ic <i _4,5 , and the average value of the reactor current (estimated value) ) The pattern to which ic belongs can be determined.

[0015]

1 is a circuit diagram showing an embodiment of a PWM inverter 1 of the present invention. In FIG. 1, a PWM inverter 1 includes a DC power supply 11, a switching circuit 12 connected in series between both terminals a1 and a2 (a2 is a GND terminal) of the DC power supply 11, and control of each semiconductor switch of the switching circuit 12. A control circuit 13 for sending an ON / OFF control signal to a terminal, and a switching circuit 12
It is composed of a reactor 14 drawn out from and a capacitor 15 connected between the reactor 14 and the ground GND. Further, inverter output terminals b1 and b2 (b2 is a GND terminal) are drawn out from both terminals of the capacitor 15.

In FIG. 1, the switching circuit 12 comprises two switching transistors (here, FETs) Q1,
Q2, each switching transistor Q1, Q2
The commutation diodes D1 and D2 are connected between the drive terminals of. The commutation diodes D1 and D2 compensate the current path when the switching transistors Q1 and Q2 are off. Reactor 14 is shown as a connection circuit between inductor 14a and line resistor 14b.

The control circuit 13 takes in the power supply voltage signal x of the DC power supply 11, the inverter output voltage y, and the inverter output current, and switches the switching transistors Q1 and Q2.
A control signal can be output to the control terminals (g1, g2) of. The control circuit 13 is provided with the dead time compensation circuit 5 and the PWM control waveform generation unit 6 as described in FIG.

The current flowing through the reactor 14 is classified into five patterns (indicated by currents i1 to i5) as shown in FIG. 2 according to the characteristics of the load and the control state. In the present embodiment, the H period or L period of PWM is adjusted depending on whether the reactor current belongs to the above pattern.
In FIG. 2, the PWM control signal is shown by a rectangular wave, and these signal states (states including dead time) are shown by pwm.

The reactor current is Q1: ON, Q2: O.
It rises in FF mode (area I), and Q1: OFF, Q
2: It descends in the ON mode (area III). The reactor current is Q1: ON, Q2: OF in the immediately preceding mode.
Q1: OFF, Q2: OFF which changed from F (area I)
Mode (area II: dead time), or the mode immediately preceding mode changed from Q1: OFF, Q2: ON (area III) to Q1: OFF, Q2: OFF mode (area I).
V), rising, falling, or having a peak, transitioning from rising to falling, or from falling to rising.

The first pattern is a case where the maximum peak Pmax and the minimum peak Pmin of the reactor current i are both positive. The second pattern is a case where the maximum peak Pmax of the reactor current i is positive and the minimum peak Pmin is zero. The third pattern is a case where the maximum peak Pmax of the reactor current i is positive and the minimum peak Pmin is negative. The fourth pattern is the maximum peak Pm of the reactor current i.
This is the case where ax is zero and the minimum peak Pmin is negative. The fifth pattern is a case where the maximum peak Pmax and the minimum peak Pmin of the reactor current i are both negative. In FIG. 2, α and β indicate the decay time and the increase time of the reactor current i.

First, the first pattern will be described with reference to FIGS. 3 and 4A to 4E. FIG. 3 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the first pattern.

In FIG. 3, the time indicated by d is the dead time. In the first pattern, the dead time d
Is included in the decay time α. As mentioned above, the first
In the pattern, the minimum peak Pmin ≧ 0.

If the cycle of PWM repetition, that is, the carrier frequency is ω, the average ic of the current values flowing in the reactor 14 is ic ≧ Pmax / 2 from the condition of Pmin ≧ 0. If the slope of the reactor current i at the decay time α is A and the slope of the reactor current i at the increase time β is B, then β = A / (A + B) × ω Pmax ≧ β × B. Therefore, ic ≧ (1/2) × A × B × ω / (A + B) is obtained.

The slope A at the decay time α and the slope B at the increase time β are detected from the voltages Vs and Vo applied to the reactor (inductance L) 14 as follows.
Here, Vs is a power supply voltage and Vo is an output voltage. A = | di / dt | = Vo / L B = | di / dt | = (Vs-Vo) / L Therefore, when the average current ic satisfies the following condition, it belongs to the first pattern, and accordingly, Control (corresponding to the first pattern) is performed.

Ic ≧ ((1/2) × Vo / Vs × [(V
s−Vo) / L] × ω Note that (1/2) × Vo / Vs × [(Vs−Vo) /
L] × ω is a current value representing the boundary between the first pattern and the second pattern. Hereinafter, this current value is represented by i _1,2 .
That is, the average current value ic is ic ≧ (i _{1, 2} = (1/2) × Vo / Vs × [(Vs
When −Vo) / L] × ω, the control according to the first pattern is performed.

FIGS. 4A to 4E are time series diagrams showing changes in current in the first pattern. Q in Figure 4 (A)
From the mode of 1: ON, Q2: OFF (area I),
(B) Q1: OFF, Q2: OFF mode (region I
I: When the dead time d) is reached, the influence of the dead time does not occur. That is, Q1: OFF, Q2:
In the OFF mode, the current flows in the positive direction through the commutation diode regardless of the ON / OFF operation of Q2, so there is no effect of dead time. Similarly, from the mode (area II: dead time) of Q1: OFF, Q2: OFF in FIG. 4B, Q1: OFF, Q2: O in FIG. 4C.
Even when the mode is changed to the N (region III) mode, there is no influence of the dead time.

On the other hand, Q1: OF in FIG.
From the F, Q2: ON (area III) mode,
(D) Q1: OFF, Q2: OFF mode (area I
V: When transitioning to the dead time d), it is necessary to consider the influence over the entire dead time d. That is, during the dead time d, the PWM signal is Lo
Since it is equivalent to w, this period (region I
The H period of PWM is increased by the time corresponding to dh = d in accordance with the dead time d of V).
Decrease the period by that amount of time.

In FIG. 4D, Q1: OFF, Q2: OFF
4 (E) from the mode (area IV: dead time)
When the mode changes to Q1: ON, Q2: OFF, the dead time d has no effect.

Secondly, referring to FIGS. 5 and 6A to 6E.
The pattern will be described. FIG. 5 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the second pattern. In FIG. 5, α and β indicate the decay time and the increase time of the reactor current i. In the second pattern, one dead time (region II) d is included in the decay time α, and the other dead time (region IV) d is included in the decay time α and the increase time β. In the second pattern, the minimum peak Pmin is almost 0.

In the second pattern, the current is adjusted at the dead time d in the area IV so that the increase in the current when the PWM signal is H and the decrease in the current when the PWM signal are L are balanced. The compensation value at the dead time d of the region IV is dh,
Since the average reactor current i is ic, this compensation value dh
Is given by the following equation as will be understood from FIG. 5 (details will be described later). dh = d− (i _{1, 2-} ic) × L / (Vs−Vo) The slope A at the decay time α and the slope B at the increase time β are
As described above, A = | di / dt | = Vo / L B = | di / dt | = (Vs-Vo) / L.

As described in the first pattern, in the area II, it is not necessary to compensate the dead time d. That is, in this case, there is no problem that "the switching transistor Q1 which should originally be turned on cannot be turned on and current flows to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side". Further, a current value representing the boundary between the third pattern and the second _pattern, when _{i 2,3, i 2,3 = i 1,2} - (Vs-Vo) × d / L

However, i _1,2 = (1/2) × Vo / V
s × [(Vs−Vo) / L] × ω. Therefore,
When the current ic flowing through the reactor 14 satisfies the following condition, i _2,3 ≦ ic <i _1,2 , since it belongs to the second pattern, the control according to the second pattern is performed.

FIGS. 6A to 6E are time series diagrams showing changes in current in the second pattern. The operation in the area II shown in FIG. 6B is not affected by the dead time d. Further, the dead time d is not affected even in the first half of the dead time d shown in FIG. However, in the latter half of the dead time d shown in FIG. 6 (D '), the switching transistor Q1 which should originally be turned on cannot be turned on, and the current is flowing to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side. Therefore, it is necessary to consider the influence of the dead time d. The period affected by the dead time d is the above-mentioned compensation value dh. Therefore, it is necessary to increase the H period of PWM by the time corresponding to the compensation value dh and simultaneously decrease the L period by the time.

The third pattern will be described with reference to FIGS. 7 and 8A to 8E. FIG. 7 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the third pattern. In the operation of the third pattern, Q1: OFF, Q2: O of FIG. 8B which has changed from the mode of Q1: ON, Q2: OFF of FIG. 8A (region I).
In the FF mode (area II: dead time d),
"The switching transistor Q2 that should be turned on is turned on."
It is not possible to do so, and the current flows to the reactor 14 via the commutation diode D1 on the side of the switching transistor Q1 ”. In addition, FIG.
(C ') shows how the direction of the current changes in the region III. In addition, Q1: OFF, Q in FIG.
Q1: O changed from 2: ON mode (area III)
Even in the FF, Q2: OFF mode (region IV: dead time d), “the switching transistor Q1 which should originally be turned on cannot be turned on, and the current flows to the reactor 14 via the commutation diode D2 on the switching transistor Q2 side. It does not happen. Therefore, dh = 0 and there is no need to compensate for the dead time d. The current value i _{3,4 that} is the boundary with the fourth pattern is expressed as follows.

I _3,4 = − (i _1,2- Vo × d / L) where i _1,2 = (1/2) × Vo / Vs × [(Vs
−Vo) / L] × ω Therefore, when the current i flowing through the reactor 14 satisfies the following condition, it belongs to the third pattern, and therefore the third pattern
Pattern control (control without dead time compensation)
I do.

I _3,4 ≦ ic <i _2,3 The fourth pattern will be described with reference to FIGS. 9 and 10A to _10E . FIG. 9 shows P in the fourth pattern.
FIG. 6 is a waveform diagram showing the correspondence between the WM signal and the output current i4 of the PWM inverter 1. In the operation of the fourth pattern, FIG.
(A) Q1: ON, Q2: OFF mode (area I)
Q1: OFF, Q2: O in FIG.
In the latter half mode of the FF (region II: dead time d), "the switching transistor Q2, which should originally be turned on, cannot be turned on, and a current flows to the reactor 14 via the commutation diode D1 on the switching transistor Q1 side". Things happen. Therefore, region II
It becomes necessary to compensate for the dead time d. Note that FIG.
0 (E) and (E ') show how the direction of the current changes in the region I.

The compensation value dh of the dead time d is shown in FIG.
As can be seen from the above, dh = (ic-i _3,4 ) × L / Vo.

The current values i ₄ , _{5 at} the boundary of the fourth pattern with the fifth pattern are expressed as follows. i _4,5 = −i _1,2 , where i _1,2 = (1/2) × Vo / Vs × [(Vs
−Vo) / L] × ω

Therefore, when the current ic flowing through the reactor 14 satisfies the following condition, it belongs to the fourth pattern, and therefore the control according to the fourth pattern is performed. i _4,5 ≦ ic <i _3,4 That is, the L period of PWM is increased by the time corresponding to the compensation value dh, and at the same time, the H period is decreased by the time.

The fifth pattern will be described with reference to FIGS. 11 and 12A to 12E. FIG. 11 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the PWM inverter 1 in the fifth pattern. In the operation of the fifth pattern,
The transition from the mode (area I) of Q1: ON, Q2: OFF in FIG. 12 (A), Q1: OFF, Q in FIG. 12 (B)
2: In the entire area of the OFF mode (area II: dead time d), “the switching transistor Q2 that should originally be turned on cannot be turned on,
The current flows to the reactor 1 via the commutation diode D1 on the first side.
The situation will occur. Therefore, it becomes necessary to compensate the dead time d in the region II.

Dead time compensation value dh at this time
Becomes dh = d. Therefore, the current ic flowing through the reactor 14
However, when the following condition, ic ≦ i _4,5, is satisfied, it belongs to the fifth pattern, and therefore the control according to the second pattern is performed. That is, the L period of PWM is increased by the time corresponding to dh = d, and at the same time, the H period is decreased by the time.

The following PWM control can be performed as described above. FIG. 13 shows the dead time compensation circuit 5 mounted in the control circuit 13. Further, FIG. 14 shows the processing in the control circuit 13. Dead time compensation circuit 5
Is composed of a pattern determining section 51 and a dead time compensation time setting section 52. The pattern determination unit 51 includes a reactor current value estimation unit. The pattern determination unit 51 determines which current pattern the current control state corresponds to by the output current value I.
It is determined based on o, the output voltage Vo, the power supply voltage Vs, and the carrier frequency ω (S01). Then, the dead time compensation time setting unit 52 determines the compensation value dh corresponding to the pattern determined by the pattern determination unit 51 and sends it to the PWM control waveform generation unit 6, and the PWM control waveform generation unit 6 causes the reactor current of the reactor current to flow. PW based on control signal according to pattern
M control is performed (S02).

When the compensation value dh is added to the ON time of the switching transistor Q1, for example, the ON time of the switching transistor Q2 is subtracted by dh.

In this case, as described in the above embodiment, the value of the compensation value dh differs depending on the pattern of the reactor current. That is, dh = d in the first pattern and the fifth pattern, and dh = 0 in the third pattern. In the second pattern _{dh = d- (i 1,2 -ic)} ×
L / (Vs-Vo), in the fourth pattern (ic-i _{4
, 5} ) × L / Vo. There are various methods for obtaining the average value ic of the reactor current, which is a value that cannot be measured. The reactor current can be obtained by the processing illustrated in the flowchart of FIG. 11 described later.

The pattern deciding section 51 is arranged in advance for the power supply voltage V.
By storing a pattern corresponding to s, output voltage Vo, output current ic, and carrier frequency ω as a table, it is possible to determine which of the first to fifth patterns the current pattern belongs to. .

The control of the control of the PWM inverter 1 is basically performed by increasing / decreasing the ON time of the switching transistor, but in the actual control, the value of the compensation value dh can be optimized. That is, the optimum compensation value dh is obtained in advance for each pattern by simulation, and this is calculated as the dead time compensation time setting unit 52.
Can be stored in.

As described above, the reactor current ic is
It is a value that cannot be measured. Therefore, in the present embodiment, the estimated value <ic> of ic is obtained by executing the process shown in the flowchart of FIG. First,
The current i _L passing through the inductance L is represented by di _L = −v _L dt / L, where v _L is the voltage applied to the inductance.

Therefore, in the present embodiment, it is represented by di _L : Δ <ic> v _L : Vs × D− <ic> × R + Vodt: sampling period (U × δt).

Where <ic> is the estimated value of the average value ic of the reactor current, R is the resistance value of the inductance L, and V is
s is the voltage value of the DC power supply, D is the duty of PWM, Vo
Is an output voltage value (capacitor voltage value), δt is a PWM clock, and U is an integer representing one sampling period. Therefore, it is represented by <ic> = [Vs × D− <ic> × R + Vo] ∫dt.

When the above equation is expressed as discrete data, <ic> _k = Σ [Vs _k-1 xD- <ic> _k-1 xR
+ Vo] × (U × δt). Σ means that the control units are accumulated from the start to the end (current). For example, the control start is n
If the th sampling order and the current sampling order are m, Σ is m from k = m−n to k = n.
It is expressed as the cumulative value of the sampling times.

In FIG. 11, first, each parameter (Vs,
Vo, etc.) is sampled (S100), <ic>
The calculation of _k is performed (S101). Then sampling
It is determined whether or not the control unit has been performed m times since the start (S1
02), if it has not reached m times, the process proceeds to step S.
Return to 101.

When the processing reaches m times in step S102, it is determined whether <ic> _k belongs to the first pattern (S103). Where <ic> _k is the first
Whether or not the pattern belongs is determined by <ic> _k ≧ i _1,2 , i _1,2 = (1/2) × Vo / Vs × [(Vs−Vo)
/ L] × ω.

When it is determined in step S103 that <ic> _k belongs to the first pattern, dh is added to the PWM on-time, the parameters in the control unit are reset, and the execution of the new control unit is started. (S10
4). At this time, dh is dh = d.

When it is determined in step S103 that <ic> _k does not belong to the first pattern, it is determined whether it belongs to the second pattern (S105). here,
Whether or not <ic> _k belongs to the second pattern is i _2,3 ≦ <ic> _k <i _1,2 , i _2,3 = i _1,2- (Vs-Vo) × d / L _i1,2 = (1/2) * Vo / Vs * [(Vs-Vo)
/ L] × ω.

When it is determined in step S105 that <ic> _k belongs to the second pattern, dh is added to the PWM on-time, the parameters in the control unit are reset, and the execution of the control unit is newly started. (S10
6). Dh of this _{time, dh = d- (i 1,2 -ic} ) × L / (Vs-Vo) = d- - is _{(i 1,2 <ic> k)} × L / (Vs-Vo) .

When it is determined in step S105 that <ic> _k does not belong to the second pattern, it is determined whether it belongs to the third pattern (S107). here,
Whether or not <ic> _k belongs to the third pattern is i _3,4 ≦ <ic> _k <i _2,3 where i _2,3 = i _1,2- (Vs-Vo) × d / L _i1,2 = (1/2) * Vo / Vs * [(Vs-Vo)
/ L] × ω i _3,4 = − (i _1,2- Vo × d / L).

If it is determined in step S107 that <ic> _k belongs to the third pattern, the PWM on-time is kept as it is, the parameters in the control unit are reset, and the execution of the new control unit is started. (S108).

When it is determined in step S107 that <ic> _k does not belong to the third pattern, it is determined whether it belongs to the fourth pattern (S109). here,
Whether or not <ic> _k belongs to the fourth pattern is i _4,5 = -i _1,2 ≤ <ic> _k <i _3,4 where i _3,4 =-(i _1,2- Vo × d / L) i _1,2 = (1/2) × Vo / Vs × [(Vs−Vo)
/ L] × ω.

When it is determined in step S109 that <ic> _k belongs to the fourth pattern, dh is added to the PWM on-time, the parameters in the control unit are reset, and the execution of the control unit is newly started. (S21
0). Dh at this time is _{dh = (ic-i 3,4)} × L / Vo = (<ic> k -i 3,4) × L / Vo.

When it is determined in step S109 that <ic> _k does not belong to the fourth pattern, it belongs to the fifth pattern. Here, that <ic> _k belongs to the fifth pattern means that <ic> _k <i _4,5 where i _4,5 = -i _1,2 ≤ <ic> _k <i _3,4 i _{3 , 4 = - (i 1,2 -Vo} × d / L) i 1,2 = (1/2) × Vo / Vs × [(Vs-Vo)
/ L] × ω.

In this case, -dh is added to the PWM on-time, the parameter in the control unit is reset, and the execution of the control unit is newly started (S111).

[0062]

As described above, it is possible to provide a PWM inverter that compensates for a state where a semiconductor switch cannot operate due to dead time by increasing the ON time of the semiconductor switch. Specifically, when the direction of the current flowing through the reactor during the dead time is the same as the direction of the current that should flow when the semiconductor switch is in the ON state, a predetermined ON time of the semiconductor switch is added. Then
The influence of dead time can be eliminated by shortening the predetermined time of the semiconductor switch that is OFF (the carrier frequency ω is not changed).

As a result, it is possible to eliminate control unevenness, such as overshoot, which occurs in a specific region due to the discontinuity of the output characteristic, and to oscillate even in the region where the rising characteristic is dull, and to make it equivalent to other regions. The characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a PWM inverter of the present invention.

FIG. 2 is a diagram showing five current patterns classified for control in the present embodiment.

FIG. 3 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the inverter in the first pattern.

FIGS. 4A to 4E are time series diagrams showing changes in current in the first pattern.

FIG. 5 is a waveform diagram showing correspondence between a PWM signal and an inverter control signal in the second pattern.

6A to 6E are time series diagrams showing changes in current in the second pattern.

FIG. 7 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the inverter in the third pattern.

8A to 8E are time series diagrams showing changes in current in a third pattern.

FIG. 9 is a waveform diagram showing the correspondence between the PWM signal and the control signal of the inverter in the fourth pattern.

10A to 10E are time series diagrams showing changes in current in a fourth pattern.

FIG. 11 is a waveform diagram showing the correspondence between the PWM signal and the inverter control signal in the fifth pattern.

12 (A) to (E) are time series diagrams showing changes in current in a fifth pattern.

FIG. 13 is a diagram showing a dead time compensating circuit mounted in the control circuit of the inverter according to the embodiment of the present invention.

FIG. 14 is a diagram showing processing in the control circuit according to the embodiment of the present invention.

FIG. 15 is a flowchart showing details of processing in the embodiment of the present invention.

FIG. 16 is a circuit diagram showing a conventional PWM inverter.

17 is an explanatory diagram of the operation of the circuit of FIG.

[Explanation of symbols]

1 PWM inverter 5 Dead time compensation circuit 6 PWM control waveform generator 11 DC power supply 12 Switching circuit 13 Control circuit 14 Reactor 15 capacitors 14a inductor 14b line resistance 51 pattern determination unit 52 Dead time compensation time setting section Q1, Q2 switching transistor D1, D2 Commutation diode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masato Nakatsuka             1 Toyota Town, Toyota City, Aichi Prefecture Toyota Auto             Car Co., Ltd. (72) Inventor Yasuyuki Nishimoto             1 Toyota Town, Toyota City, Aichi Prefecture Toyota Auto             Car Co., Ltd. F-term (reference) 5H007 AA07 BB11 CA01 CB17 CC09                       DA05 DB02 DB12 EA05 EA13                       FA06

Claims (5)

[Claims] 1. A DC power supply, a switching circuit comprising a first semiconductor switch and a second semiconductor switch, each of which has a commutation diode and which is connected in a forward direction to the DC power supply terminal, and each semiconductor switch is turned ON. / OF
A smoothing circuit including an inverter control circuit that outputs an F control signal, a reactor whose one terminal is connected to the connection point of each semiconductor switch, and a capacitor connected to the other terminal of the reactor and the ground terminal of the DC power supply. And ON / OFF of the first semiconductor switch and ON / OFF of the second semiconductor switch are alternately performed, and
In a PWM inverter that is controlled by providing a period during which both semiconductor switches are OFF between the ON period of the first semiconductor switch and the ON period of the second semiconductor switch, the reactor current is controlled by the output current value, the output voltage. A PWM inverter having a dead time compensation circuit including a dead time compensation time setting means for estimating the ON time of each semiconductor switch based on the estimation result based on the estimated value, the power supply voltage value and the pulse width. 2. The dead time compensation time setting means,
The operation of the semiconductor switch that should originally be in the ON state is limited by the dead time, and the direction of the current flowing through the reactor during the dead time is the direction of the current that should flow when the semiconductor switch is in the ON state. The PWM inverter according to claim 1, wherein when the same, the ON time of each semiconductor switch is set. 3. The ON time of the first semiconductor switch, the dead time when the first semiconductor switch transitions from the ON state, the ON time of the second semiconductor switch, and the second semiconductor switch. 3. The sum of the dead time of transition from the ON state of is constant is constant.
5. The PWM inverter according to claim 4, wherein the setting of the ON time of each of the semiconductor switches is a change of the ratio between the ON time of the first semiconductor switch and the ON time of the second semiconductor switch. Characteristic PWM inverter. 4. The dead time compensating circuit, when the reactor current has a first pattern: both maximum peak and minimum peak are positive, second pattern: maximum peak is positive and minimum peak is near zero, third Pattern: maximum peak is positive, minimum peak is negative Fourth pattern: maximum peak is near zero, minimum peak is negative Fifth pattern: both maximum peak and minimum peak are negative The dead time compensation time setting means sets the ON time of each of the semiconductor switches according to the pattern decided by the pattern deciding means. 4. The PWM inverter according to any one of 1 to 3. 5. The pattern determining means is i _1,2 = (1/2) × Vo / Vs × [(Vs−Vo)
/ L] × ω Vo: output voltage, Vs: power supply voltage, L: inductance of reactor, ω: carrier frequency of PWM, first pattern: i _1,2 ≦ i _c second pattern: i _2,3 = i _1,2- (Vs-Vo) ×
_{d / L ≦ i c <i} 1,2 third _{pattern: i 3,4 = - (i 1,2} -Vo × d /
L) ≦ i _c <i _2,3 Fourth pattern: i _4,5 = −i _1,2 ≦ i _c <i _3,4 Fifth pattern: ic <i _4,5 , and the average value ic of the reactor current ic The pattern according to claim 1, characterized in that the pattern to which it belongs is determined.
The PWM inverter according to the item.