JP4049126B2 - Motor drive circuit, electronic device, and motor drive method - Google Patents

Description

  The present invention relates to a so-called sensorless brushless motor drive circuit that does not have a position detection sensor for detecting the rotation angle of a rotor, an electronic device using the same, and a motor drive method.

As a sensorless motor driving circuit, for example, a circuit for driving a three-phase brushless motor is known.
The circuit that drives this three-phase brushless motor uses an induced voltage (also called back electromotive force or EMF (electromotive force)) generated in the drive coil without using a rotation detecting element such as a Hall element. The drive current (energization) energized to the coil is switched. This type of general sensorless motor drive circuit detects the induced voltage of the exciting coil, and switches the energization by giving a certain delay amount to the timing at which the polarity is inverted.

  Further, in a general sensorless motor drive circuit, spike voltage (flyback voltage) generated at energization switching is removed by a filter or the like. Furthermore, in a typical sensorless motor drive circuit, the motor rotor is already in a position to be stopped (also referred to as a reference position) and the motor rotor does not start immediately after the drive coil is energized. When the induced voltage in the drive coil cannot be detected within a certain period of time, a start pulse is generated to forcibly switch to the energization pattern.

Signal processing methods for giving a certain amount of delay at the timing of inversion of polarity, providing a filter for removing spike voltages, and generating a start pulse are largely divided into analog methods and digital methods. Can be separated.
The analog motor drive circuit uses the CR time constant to remove the phase delay amount, spike voltage, and start pulse. The digital motor drive circuit uses a microprocessor or the like to perform functional processing equivalent to the analog type. Therefore, a digital system can be used in a device with a large circuit scale. However, in an application where a circuit must be made small, a microprocessor or the like cannot be used in terms of cost and mounting area. There is no choice but to adopt an analog type.

  However, in the analog method, it is necessary to set optimum constants for each element of the CR time constant circuit, but it is difficult to set the optimum constant because there are constant values that interfere with each other's performance, and there are many resistors and capacitors. Since it is necessary, there is a disadvantage that the number of parts increases.

By the way, in recent years, in electronic devices typified by mobile phones, the size and thickness of vibration motors used as silence notification means for noise environment and barrier-free (for hearing impaired people) have been reduced.・ High reliability is required. Currently, coreless motors with brushes are commonly used, but they have a short diameter due to wear of the brushes and due to the structural fate of having to provide an air gap inside and outside the rotating coil. There is a problem that it is difficult to reduce the external dimensions in the direction.
Therefore, a brushless structure in which a coil of a vibration motor is fixed and a permanent magnet is used as a rotor has been studied. A brushless motor is highly reliable because it does not have a brush, and if the motor structure is a magnetic surface facing type, it is particularly advantageous for thinning. When the brushless motor is viewed from the side of designing the entire electronic device, there is a demand for incorporating the drive circuit in the motor module. However, of course, at this time, an operation function equivalent to that of the current brushless coreless motor is required.

  In order to incorporate a drive circuit in a small brushless motor, the drive circuit is integrated into an IC, the size of the IC is reduced, which leads to a reduction in the mounting area of the IC, the number of external electrical components other than the IC is small, and the external electrical The parts are required to have a sufficiently small outer shape.

A brushless motor drive circuit using a so-called PLL circuit is known (see, for example, Patent Document 1).
Patent Document 1 is to provide a motor driving circuit and a motor driving method for performing sensorless driving of a brushless DC motor with a simple circuit.
In order to achieve the object, in Patent Document 1, a phase loop is formed so that the frequency output phase of the VCO that determines the oscillation frequency matches the EMF phase, and this is a so-called PLL circuit. The goal of the PLL circuit unit is to match the rotational phase of the rotor and the drive circuit phase.
Japanese Patent Laid-Open No. 2001-061291

When a PLL circuit is used as in Patent Document 1, the problem is that the output signal of the phase comparator that compares the rotation phase of the rotor and the drive circuit phase inside the PLL circuit is received and smoothed. It is a loop filter (or LPF: low pass filter) for outputting as a frequency control signal to the VCO.
Generally, the rotational speed fluctuation of the rotor is gentler than the electric signal time constant because its operation depends on the mechanical time constant (several ms to several hundred ms). Therefore, it is necessary to set the cut-off frequency of the loop filter to a low value, and the capacitance value of the capacitor that is a constant tends to be a large value.

  In Patent Document 1, a so-called lag and lead type filter shown in FIG. 4 of Patent Document 1 is used, and the capacitance value of the capacitor is 1.291 μF to 11.621 μF (Patent Document 1: (Refer to the 18th line on the left side of page 7.)

  The current minimum “0603” JIS standard size chip-type multilayer ceramic capacitor has a maximum capacitance of 0.1 μF and a B characteristic of 6.3 V. Therefore, when trying to obtain the above capacitance value, a larger chip size It becomes an element.

  It is conceivable to reduce the operating current of the loop filter so that a smaller capacitance value can be used without changing the band of the loop filter, but reducing this includes the loop filter, and the operating impedance before and after the loop filter is reduced. There is a concern that the current accuracy of the circuit system will deteriorate and that it will be a problem in terms of resistance to external noise.

  In view of the above, development of a new driving method for stably driving the motor without smoothing the output signal of the phase comparator is required.

  The problem to be solved by the present invention is that it is suitable for IC as compared with the conventional circuit, the size of the IC circuit can be minimized, the number of external electric parts other than the IC is reduced, and the constant of the external electric parts Is a value obtained with the minimum chip size, and further provides a sensorless motor driving circuit for obtaining a stable motor rotation operation.

A motor drive circuit according to the present invention is a motor drive circuit for driving a sensorless brushless DC motor including a rotor and a plurality of coils opposed to the rotor, according to a control voltage applied to a control terminal. incorporating a voltage controlled oscillator for generating an oscillating clock signal at a frequency based on the clock signal from the voltage controlled oscillator, a phase difference is sequentially different has a period defined by the frequency of the clock signal a drive signal generator for generating a plurality of drive signals, when rotating the rotor by supplying said plurality of drive signals to said plurality of coils, to monitor the voltage induced in the plurality of coils, A first detection signal is generated when a rotor phase obtained from the induced voltage is delayed with respect to an electrical phase obtained from the drive signal, and a first detection signal is generated before the electrical phase. A phase shift detection unit for generating a second detection signal when the rotor phase leads, and enter the first detection signal and the second detection signal, for the duration of the active state of the inputted first detection signal A charge / discharge circuit that charges the control terminal and discharges the control terminal for a duration of an active state of the input second detection signal; and is connected to the control terminal, and a current change at the time of charging or discharging, A conversion element that converts the change in the control voltage to have opposite directions, and a maximum control time when the charge / discharge circuit and the conversion element control the control voltage to increase the oscillation frequency of the voltage-controlled oscillation circuit. , For each of the first detection signal and the second detection signal so as to be shorter than a maximum control time when the control voltage is controlled to lower the oscillation frequency. And a control regulating portion for regulating an upper limit of the duration of state.

  In the present invention, the drive signal generation unit preferably includes a start control circuit having a lower limit frequency as a start frequency at which the rotor is reliably started from a stop.

An electronic apparatus according to the present invention includes a sensor and a brushless DC motor having a plurality of coils facing the rotor, and a motor drive circuit that drives the brushless DC motor in a modular manner. an electronic apparatus are, the motor drive circuit incorporates a voltage controlled oscillator for generating an oscillating clock signal at a frequency corresponding to the control voltage applied to the control terminal, the clock from the voltage controlled oscillator on the basis of the signal, and the clock signal driving signal generating unit having a phase difference to generate a sequential plurality of different drive signals has a period that is defined at a frequency of, by supplying the plurality of drive signals to said plurality of coils when rotating the rotor, the plurality of voltage induced on the coil monitor, drive the rotor phase obtained from the induced voltage A phase shift detection unit for generating a first detection signal to generate a second detection signal when with respect to the electrical phase is progressing the rotor phase when delayed relative electrical phase obtained from the signal, the second One detection signal and the second detection signal are input, the control terminal is charged for the duration of the active state of the input first detection signal, and the control is performed for the duration of the active state of the input second detection signal. A charge / discharge circuit that discharges a terminal; a conversion element that is connected to the control terminal and converts a change in current during the charge or discharge into a change in the control voltage having opposite directions; and the charge / discharge circuit; Maximum control time when the conversion element controls the control voltage to increase the oscillation frequency of the voltage controlled oscillation circuit, maximum control when the conversion element controls the control voltage and decreases the oscillation frequency To be shorter than during, for each of said first detection signal and the second detection signal, and a control regulating portion for regulating an upper limit of duration of the active state.

A motor driving method according to the present invention is a motor driving method for driving a sensorless brushless DC motor including a rotor and a plurality of coils opposed to the rotor, and has a frequency corresponding to a held control voltage. generating a clock signal, a plurality of drive signals having a phase difference sequentially different has a period defined by the frequency of the clock signal, and generating, based on said clock signal, said plurality of drive signals when rotating the rotor by supplying said plurality of coils, the induced voltage induced in the coils to monitor the electrical phase of the rotor phase obtained from the induced voltage is obtained from the driving signal to A step of generating a first detection signal when delayed and generating a second detection signal when the rotor phase is advanced with respect to the electrical phase. And charging the control voltage holding node for the duration of the active state of the first detection signal, thereby changing the control voltage in the step of generating the clock signal, and maintaining the active state of the second detection signal. Changing the control voltage in the generation step of the clock signal in a direction opposite to that during the charging by discharging the holding node of the control voltage for a time, and the control voltage is reduced by the charging and discharging. In the step of changing, the maximum control time when the frequency of the clock signal increases when the control voltage changes, and the maximum control time when the frequency of the clock signal decreases when the control voltage changes in the opposite direction For each of the first detection signal and the second detection signal, the activation To restrict the upper limit of the duration of the state.

  In the present invention, preferably, at the time of generating the clock signal, the lower limit frequency is controlled with the lower limit being the starting frequency at which the rotor is reliably started from when stopped.

  According to the present invention, it is suitable for IC compared with the conventional circuit, the circuit scale can be minimized, the number of external electric parts other than the IC is reduced, and the constant of the external electric parts is also the minimum chip size. Thus, a more stable motor rotation operation can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a sensorless three-phase brushless DC motor and its motor drive circuit according to an embodiment of the present invention.

  The motor drive circuit 1 illustrated in FIG. 1 is driven by a sensorless three-phase brushless DC motor (hereinafter simply referred to as “motor”) 100. The motor 100 includes a rotor 101 having magnets and a stator having, for example, three-phase (U-phase, V-phase, W-phase) motor drive coils (hereinafter simply referred to as “coils”) 102.

  For example, an 8-pole magnet is magnetized around the rotation axis of the rotor 101.

The coil 102 is composed of three coils that are disposed to face the rotor 101 with a phase difference of 120 ° electrically, that is, a U-phase coil 102U, a V-phase coil 102V, and a W-phase coil 102W.
The three coils are star-connected, and the midpoint of connection is connected to the terminal T_COM for the midpoint potential COM of the motor drive circuit 1. Further, the opposite ends of the three coils, that is, the U-phase coil 102U, the V-phase coil 102V, and the W-phase coil 102W are connected to the drive signal supply terminals TU, TV, and TW of the motor drive circuit 1, respectively. Connected.

  Hereinafter, on the premise that the motor 100 shown in FIG. 1 is to be driven, the configuration and operation of the motor drive circuit 1 corresponding thereto will be described.

The motor drive circuit 1 shown in FIG. 1 integrates most functions in a motor drive IC 2 having, for example, a bi-CMOS configuration, and reduces the number of external electrical components as much as possible.
As external electric components, there are a charge pump current setting resistor R_Iref, a charge pump capacitor C_cp, a charge pump resistor R_cp, and a decoupling capacitor C_DC. These four external electric components, the motor driving IC 2 and the motor 100 are mounted on a single printed circuit board to be modularized.

  A decoupling capacitor C_DC is connected between the supply terminal T_vcc of the power supply voltage Vcc of the motor drive circuit 1 and the supply terminal T_GND of the ground voltage GND. The decoupling capacitor C_DC can stabilize the impedance between the supply line of the power supply voltage Vcc and the supply line of the ground voltage GND.

The power supply voltage Vcc supplied from the terminal T_vcc and the ground voltage GND supplied from the terminal T_GND are supplied to the motor drive IC 2, and the motor drive IC 2 and the motor 100 are operated with the electric power generated thereby.
A charge pump capacitor C_cp and a charge pump resistor R_cp are connected in series between the internal supply line of the power supply voltage Vcc and the control terminal T_cp of the motor drive IC 2. Further, a charge pump current setting resistor R_Iref is connected between the supply terminal T_Iref of the reference current I_ref of the motor driving IC 2 and the internal supply line of the ground voltage GND. The role of these capacitors and resistors will be described later.

  In the configuration example shown in FIG. 1, the charge pump current setting resistor R_Iref and the charge pump resistor R_cp are installed outside the motor drive IC 2. However, the magnetic characteristics and mechanical properties of the brushless motor 100 to be driven are described. By limiting the target time constant, these two resistors R_Iref and R_cp can be built in the motor drive IC 2. In that case, the number of external parts can be further reduced.

  The motor drive IC 2 drives the motor 100, detects the phase (U phase, V phase, or W phase) of the rotor 101 at that time, and drives the rotor with the phase (hereinafter referred to as the rotor phase or EMF phase). And the phase of the drive signal is adjusted in accordance with the comparison result, and the adjusted drive signal is supplied to the coil 102 so that the rotational speed of the rotor 101 is set to a desired value. It is for controlling to a value.

In order to achieve the object, as shown in FIG. 1, the motor drive IC 2 includes a rotor phase detection unit 3, a logic unit 4, a charge pump circuit 5, a charge pump current setting device 6, a voltage controlled oscillator (VCO) 7, a preamplifier. 8 and an output unit 9.
The logic unit 4 further includes a drive pulse generation unit 41, a regulation signal generation unit 43 that regulates the pulse width of the control signal based on the maximum control times T_late and T_early, and a selector 44.

These parts constituting the motor drive IC 2 are roughly divided into a drive system circuit for generating three-phase drive signals U, V, and W for driving the coil 102 based on the clock signal CLK_vco from the VCO 7, and a drive signal. It can be classified into a control system circuit that controls the motor rotation speed by changing the frequencies of U, V, and W.
In FIG. 1, the VCO 7, the drive pulse generator 41, the preamplifier 8 and the output unit 9 constitute a drive system circuit and constitute one embodiment of the “drive signal generator” of the present invention. The other components constitute a control system circuit, details of which will be described later.

  First, the configuration and operation of each part of the drive system circuit will be described. Hereinafter, in the description of the operation, the signal waveforms in FIGS. 2 and 3 and the timing chart showing the timing thereof will be referred to as appropriate.

The VCO 7 is a voltage control type oscillation circuit, and oscillates at a frequency corresponding to the potential of the control input, and generates a clock signal CLK_vco having a constant period corresponding to the oscillation frequency. The control input of the VCO 7 is connected to the control terminal T_cp of the motor drive IC 2. The clock output of the VCO 7 is connected to the input of the drive pulse generator 41 connected to the next stage.
The VCO of this example operates with the frequency of the clock signal CLK_vco to be output increased as the potential of the control terminal T_cp falls below the power supply voltage Vcc, with the power supply voltage Vcc as a reference.

  The feature of the VCO 7 of this example is that the VCO 7 does not stop oscillating and continues to oscillate at a low frequency even when the potential of the control terminal T_cp is the reference power supply voltage Vcc. This lower limit frequency is an oscillation frequency that is a rotational speed at which the motor is reliably started from the time of stoppage, and is defined by a start control circuit in the VCO 7 not shown.

  More specifically, the activation control circuit has a time constant for reliably oscillating operation at a low frequency, the activation period t0 being the inherent vibration period T0 of the drive system, the number of magnet poles P, the number of coils or slots, and the magnet poles. It is defined by the following equation (1) using the least common multiple g of the number.

  In order to set the time constant defined in this way to the VCO 7, an oscillation starting capacitor 71 is connected to the VCO 7.

  The drive pulse generator 41 belongs to the circuit block of the logic unit 4 and is a logic circuit for generating a drive pulse group (Up, Vp, Wp, Un, Vn, Wn) for driving the output unit 9. The output unit 9 driven by the drive pulse group (Up, Vp, Wp, Un, Vn, Wn) outputs three-phase drive signals U, V, W, which are supplied to the three-phase coil 102. Is done.

A specific circuit of the drive pulse generator 41 is not shown. The circuit of the output unit 9 is shown in FIG.
The output unit 9 includes six bipolar transistors 91H, 91L, 92H, 92L, 93H, and 93L for outputting the three-phase drive signals U, V, and W. The breakdown includes three PNP transistors 91H, 92H, and 93H as high-side switches and three NPN transistors 91L, 92L, and 93L as low-side switches. A transistor 91H to which the drive pulse Up is applied to the base and a transistor 91L to which the drive pulse Un is applied to the base are connected in series between the power supply voltage Vcc and the ground voltage GND, and a U-phase drive signal U is connected from the connection middle point. Is output. Similarly, a transistor 92H to which the drive pulse Vp is applied and a transistor 91L to which the drive pulse Vn is applied are connected in series, and a V-phase drive signal V is output from the midpoint of connection, and the drive pulse Wp is applied. The transistor 93H and 93L to which the drive pulse Wn is applied are connected in series, and a W-phase drive signal W is output from the midpoint of connection.

  The preamplifier 8 receives an output from the drive pulse generation unit 41 and supplies a base current necessary to turn on or off the six transistors 91H, 91L, 92H, 92L, 93H, and 93L of the output unit 9.

FIG. 2H shows three-phase drive signals U, V, and W that are finally generated. In FIG. 2H, the drive electrical angle with respect to the drive signal U is shown. The drive electrical angle is defined such that an intermediate point of the rising period of the drive signal U is 0 ° and one cycle is 360 °.
The three-phase drive signals U, V, and W for driving the DC motor 100 are basically binary pulse waveforms having a high level and a low level. In this example, the weight is ± 30 ° when the level changes. There is a period. The three-phase drive signals U, V, and W have a phase difference of about 120 °. Therefore, the three-phase coil is always in a high level application, low level application, and wait state at an arbitrary time.

The waveform of the drive pulse group (Up, Vp, Wp, Un, Vn, Wn) for generating such three-phase drive signals U, V, W is shown in FIG.
Each of the drive pulses Up, Vp, Wp, Un, Vn, Wn has a waveform with a pulse width of 120 ° in electrical angle, a cycle of 360 °, and a duty ratio of 1/3.
Among these, the three drive pulses Up, Vp, Wp for driving the high side of the output unit 9 have a phase difference of 120 °. Further, the drive pulse pairs of each phase, that is, Up and Un, Vp and Vn, and Wp and Wn have a phase difference of 60 °.

  Such a drive pulse width, period, and phase difference are determined by the specifications of the motor 100, that is, the number of drive phases and the number of rotor magnetizations, and the configuration of the output unit 9. In this example, since the rotor 101 having the number of magnetizations 8 is three-phase driven by the output unit 9 having the configuration shown in FIG. 1, the drive signals U, V, W from the output unit 9 have a phase difference of about 120 °. The drive pulses Up, Vp, Wp, Un, Vn, and Wn necessary for the generation thereof are generated by the drive pulse generator 41 so as to have the waveform shown in FIG.

  Although a specific circuit configuration of the drive pulse generation unit 41 is omitted, in this example, FIGS. 2A to 2E show waveforms generated during the generation of the drive pulse, and are used instead. As is apparent from these waveforms, the drive pulse generator 41 can be configured by a logic circuit based on a general frequency divider.

First, the drive pulse generation unit 41 receives the clock signal CLK_vco (FIG. 2A) having the oscillation frequency F_vco from the VCO 7 and divides it four times.
A signal generated in this frequency division process is shown in FIG. In the figure, signal QA is a signal after the first frequency division, signal QB is a signal after the second frequency division, signal QC is a signal after the third frequency division, and signal QD is a signal after the fourth frequency division. The fourth frequency-divided signal QD is a clock signal having a period 16 times that of the clock signal CLK_vco.

  The drive pulse generation unit 41 includes, for example, six counters, and the six counters start counting the number of pulses of the clock signal CLK_vco sequentially at the rising edge of the pulse of the fourth divided signal QD. The counter of each stage sets the output (for example, carry-up) to the high level during the counting operation, and transitions the output to the low level when the counting operation ends. Further, the counter of each stage is incremented by 16 pulses of the input clock signal CLK_vco and stops the counting operation.

Therefore, the six-stage counter has a pulse width of 16 cycles of the clock signal CLK_vco and a cycle of 96 cycles of the clock signal CLK_vco, as shown in FIGS. 2C and 2E. Pulse signals y0, y1, y2, y3, y4, and y5 are output. The generation of six pulse signals y0 to y5 having a period 96 times that of the reference pulse (the pulse of the clock signal CLK_vco) by the frequency dividing circuit and the counter is referred to as “1/96 count operation” for convenience.
Thereafter, the drive pulse generator 41 decodes the pulse signals y0 to y5 to generate drive pulses Up to Wn shown in FIG.

  The drive pulse generation unit 41 generates the drive pulses Up to Wn. As another role, the drive pulse generation unit 41 gives drive electrical angle information (EMF selector control signal: FIG. 3B) to the restriction signal generation unit 43, and further outputs it. There is a role of giving phase output drive information (FIG. 2F) to the preamplifier 8 that controls the unit 9.

First, phase output drive information will be described.
The phase output drive information takes one of the values “y0”, “y1”, “y2”, “y3”, “y4”, or “y5” as shown in FIG. This phase output drive information is a signal for controlling the drive output phase and selecting the phase and polarity of the EMF. That is, six types of input signals Up, Vp, Wp, Un, Vn, and Wn of the preamplifier 8 are determined in accordance with the phase output drive information (FIG. 2F). As a result, a U-phase drive signal U, a V-phase drive signal V, and a W-phase drive signal W are generated at the output unit 9.

Regarding the selection of the phase and polarity of the EMF, the selector 7 performs selection according to the phase output drive information (FIG. 2F) of the phase difference signal from the phase comparison unit 42. The phase to be selected is shown in FIG. 3B as an EMF selector control signal.
Here, “U +” represents selecting the EMF comparator output on the U-phase rising side (+ side). “V−” indicates that the V-phase falling side (−side) EMF comparator output is selected.

Here, FIG. 3C illustrates EMF signals of U, V, and W phases as EMF_U, EMF_V, and EMF_W as EMF waveforms when the motor 100 is in steady operation. In FIG. 3C, the horizontal broken line is the midpoint potential COM potential.
Thereby, the output signal (U_det signal) of the comparator 3U takes a high level when the U-phase EMF signal EMF_U is higher than the midpoint voltage COM of the drive coil, and takes a low level when it is low. The same is true for the other two phases.
The EMF selector control signal (FIG. 3B) is information indicating whether a rising edge or a falling edge is detected for each phase.

Next, the configuration and operation of the control system circuit will be described.
The control system circuit is an external circuit connected to the circuits in the logic unit 4 excluding the drive pulse generation unit 41, the rotor phase detection unit 3, the charge pump circuit 5, the charge pump current setting device 6, and the terminals T_cp and T_Iref. Consists of parts.
Among these, the charge pump circuit 5, the charge pump current setting device 6, and the external components connected to the terminals T_cp and T_Iref constitute an embodiment of the “oscillation control unit” of the present invention.

The circuit in the logic unit 4 constituting the control system circuit is expressed as “T_late / T_early” in FIG. 1, and by defining the maximum pulse width of the signal output to the transmission control unit, A regulation signal generation unit 43 that generates regulation signals M_late and M_early for regulating the maximum control time, a selector 44, and a phase comparison unit 42 are provided. The selector 44, the phase comparison unit 42, and the rotor phase detection unit 3 constitute an example of the “phase shift detection unit” of the present invention.
In particular, the restriction signal generation unit 43, the selector 44, and the phase comparison unit 42 are not necessarily configured separately as physical circuit blocks, and may be provided as functions of the logic unit 4.

In the present embodiment, the control system circuit that controls the oscillation of the VCO roughly has the following three functions.
The first function is to detect the polarity change point of each rotor phase by the rotor phase detector 3, and compare the polarity change point of each rotor phase with the polarity change point of the drive phase obtained from the drive pulse generator 41. And a function of detecting a phase shift of the rotor phase with respect to the drive phase.

  The second function generates an up signal f_up for increasing the oscillation frequency F_vco of the VCO 7 and a down signal f_down for decreasing the oscillation frequency F_vco based on the detection result of the phase shift, and outputs either of them. It is a function.

  The third function is a function of the regulation signal generation unit 43 that regulates the operation of the oscillation control unit. In this example, the pulse width indicating the active period of the up signal f_up is changed from a predetermined advance electrical angle to an electrical angle of zero. Phase range (active state maximum pulse duration T_early) and pulse width indicating the active state of the down signal f_down from the electrical angle zero to a predetermined delayed electrical angle (active state) This is a function of limiting the pulse width to the maximum duration T_late). This embodiment is characterized in that, in the third function, the maximum duration T_late for the down signal f_down is longer than the maximum duration T_early for the up signal f_up, that is, (T_late> T_early). One.

  The configuration and operation of each unit for realizing these functions will be described below.

The rotor phase detection unit 3 includes three comparators (CMP) 3U, 3V, and 3W. Each comparator detects, for example, that the polarity of the phase (rotor phase) of the induced voltage (EMF) induced in the coil 102 is reversed when the rotor 101 rotates in the motor 100.
In order to provide a reference for the polarity of the rotor phase, one input of each of the comparators 3U, 3V, 3W is connected to a terminal T_COM for inputting the midpoint potential COM of the star-connected coil 102.
In order to monitor the time-varying EMF, the other input of the comparator 3U is connected to a terminal TU that supplies an EMF signal (hereinafter referred to as “EMF_U”) of the U-phase coil 102U. Similarly, the other input of the comparator 3V is connected to a terminal TV that supplies an EMF signal (hereinafter referred to as “EMF_V”) of the V-phase coil 102V, and the other input of the comparator 3W is connected to the EMF of the W-phase coil 102W. It is connected to a terminal TW that supplies a signal (hereinafter referred to as “EMF_W”).
The comparators 3U to 3W output comparator output signals U_det, V_det, and W_det that take a high level when the polarity of the EMF is “+” and take a low level when the polarity is “−”.

In short, the phase comparison unit 42 compares the drive phase and the rotor phase (EMF phase). As a specific comparison method, since it depends on the drive phase information obtained from the drive pulse generation unit 41, it cannot be generally stated, but for example, the following method can be adopted.
Here, regarding the U phase, the phase comparison unit 42 regards the time center of the period in which the U phase drive signal U rises as the point where the polarity of the U phase changes from negative to positive, and changes the polarity of the drive (electrical) phase. The function of “U + comparison” that compares the phase with the polarity change point of the rotor phase from negative to positive indicated by the output signal U_det of the comparator 3U and the time center of the period during which the U-phase drive signal U falls is the U-phase polarity The phase change of the polarity change point of the driving (electrical) phase is compared with the polarity change point of the rotor phase indicated by the output signal U_det of the comparator 3U from the polarity change from positive to negative. And a “comparison” function.
The phase comparison unit 42 has the functions of “V + comparison” and “V− comparison” and “W + comparison” and “W− comparison” in the same manner for the V phase and the W phase. These functions are shown in the phase comparison unit 42 shown in FIG.

  The selector 44 receives, for example, phase output drive information (FIG. 2 (F)) given by six pulse signals y0 to y5 from the drive pulse generator 41, and outputs the drive signals U, V, An appropriate phase and polarity comparison result is selected and output from the comparison result of the rotor phase and the drive phase for each rising side (“+” side) and falling side (“−” side) of each phase of W. This output is output to the charge pump circuit 5 as an up signal f_up and a down signal f_down.

  The restriction signal generator 43 only needs to be able to restrict the pulse width of the up state of the up signal f_up and the down signal f_down as a result. If the object can be achieved, the target directly controlled by the restriction signal generator 43 is arbitrary. That is, the signal selection time by the selector 44 may be restricted, the signal input to the preceding phase comparison unit 42 may be restricted, or the output signals (f_up signal and f_down signal) of the selector 44 may be used. Direct regulation may be used.

The “regulation control unit” of the present invention is configured by the regulation signal generation unit 43 and the circuit portion that is regulated by the regulation signal from the regulation signal generation unit 43.
For example, the restriction signal generator 43 generates a restriction signal M_late having a width of T_late and a restriction signal M_early having a width of T_early, and ANDing these restriction signals with the restriction target signal. Take (logical AND). At this time, if an AND gate incorporated in the phase comparison unit 42 or the like is used, it is preferable from the viewpoint of suppressing the circuit scale because there is no need to provide an AND gate.

FIG. 4 shows a circuit example of the restriction control unit 43 that generates the restriction signal M_late having the width T_late and the restriction signal M_late having the width T_early.
In FIG. 4, the restriction control unit 43 includes two 2-input AND gates 43A and 43B, an inverter 43C, and a 3-input NAND gate 43D.
In order to make the maximum pulse width T_early on the phase advance side equivalent to an electrical angle of 30 °, the AND gate 43A is used to perform a logical product of the third divided signal QC and the fourth divided signal QD shown in FIG. The signals QC and QD are given to the input, and the restriction signal M_early is output from the output. The period of the restriction signal M_early is equivalent to an electrical angle of 60 °.
The fourth divided signal QD is inverted by the inverter 43C and applied to one input of the 2-input AND gate 43B, and the third divided signal QC is applied to the first input of the NAND gate 43D. At this time, the second divided signal QB is applied to the second input of the NAND gate 43D, the first divided signal QA is applied to the third input, and the output of the NAND gate 43D is applied to the other input of the AND gate 43B. The AND gate 43B outputs a restriction signal M_Late having a cycle equivalent to an electrical angle of 60 ° and a pulse width equivalent to about 7.5 ° which is the same as the first divided signal QA.
This circuit configuration is merely an example, and can be arbitrarily changed according to the maximum regulation time to be obtained (pulse width of the regulation signal).

5A and 5B show a circuit block and a specific circuit of this desirable mode.
In the circuit shown in FIG. 5B, as shown in FIG. 5A, the selector 44 and the phase comparison unit 42 are configured as one circuit block.
This circuit has six AND gate pairs 45 each composed of three input AND gates 45u and 45d, three inverters 46u, 46v and 46w, and two 6-input NOR gates 47u and 47d.

Six pulse signals y0 to y5 from the drive pulse generation unit 41 are input one by one to the first inputs of six AND gates 45u in total.
One of the comparator output signals U_det, V_det, and W_det is input to the second input of the AND gate 45u. More specifically, an AND gate in which the comparator output signal U_det is input to the second input of the AND gate 45u to which the signal y2 or y5 is input to the first input, and similarly, the signal y1 or y4 is input to the first input. The comparator output signal V_det is input to the second input of 45u, the signal y0 or y3 is input to the first input, and the comparator output signal W_det is input to the second input of the AND gate 45u.
The restriction signal M_early generated by the restriction signal generator 43 is input to the third input of the AND gate 45u.

On the other hand, the same pulse signal (any of y0 to y5) as that of the adjacent AND gate 45u in the same pair is input to the first inputs of the remaining six AND gates 45d.
Any one of the inverted signals of the comparator output signals U_det, V_det, W_det by the inverters 46u to 46w is input to the second input of the AND gate 45u. More specifically, an inverted signal of the comparator output signal U_det is input to the second input of the AND gate 45d where the signal y2 or y5 is input to the first input, and similarly, the signal y1 or y4 is input to the first input. An inverted signal of the comparator output signal V_det is input to the second input of the AND gate 45d, and an inverted signal of the comparator output signal W_det is input to the second input of the AND gate 45d where the signal y0 or y3 is input to the first input. The
The restriction signal M_late generated by the restriction signal generator 43 is input to the third input of the AND gate 45d.

  The pulse signals y0 to y5 shown in FIG. 2C are sequentially turned on (become a high level state), and this is repeated. Accordingly, one of the pulse signals y0 to y5 is turned on at an arbitrary time. In FIG. 4B, only the AND gate pair 45 to which the ON pulse signal y0, y1, y2, y3, y4 or y5 is input can output a high level.

In the AND gate pair capable of outputting the high level in FIG. 5B, the AND gate 45u can output a high level only when the EMF polarity is “+”, and the AND gate 45d has an EMF polarity of “−”. High level can be output only when At this time, each of the AND gates 45u and 45d is further subjected to pulse width restriction by the restriction signal M_early or M_late.
Therefore, from the NOR gate 47u, when the EMF polarity is “+”, an inverted signal (low active signal) of a signal subjected to pulse width restriction as necessary is output as the up signal f_up. Further, from the NOR gate 47d, when the EMF polarity is “−”, an inverted signal (low active signal) of a signal subjected to pulse width restriction as necessary is output as the down signal f_down.

The charge pump current setting resistor R_Iref as an external component generates a current corresponding to the charge pump current setting resistor R_Iref. This current is supplied to the charge pump current setter 6.
The charge pump current setting unit 6 generates reference currents I_ref1 and I_ref2 for the charge pump circuit 5 based on the input current.

FIG. 6 shows a specific circuit example of the charge pump circuit 5.
The charge pump circuit 5 outputs the charge pump currents I_ref1 and I_ref2 generated by the charge pump current setting device 6 according to the charge pump current setting resistor R_Iref from the NOR gate 47u (FIG. 5B). Alternatively, it is controlled by the down signal f_down output from the NOR gate 47d (FIG. 5B).
Here, the up signal f_up and the down signal f_down normally have an “H” level, and transition to an “L” level when activated.

Two current sources I_ref1 and I_ref2 shown in FIG. 6 are set by a charge pump current setting device 6 using a charge pump current setting resistor R_Iref.
The charge pump circuit 5 shown in FIG. 6 includes so-called digital transistors DP1, DQ1, and DQ2 with resistors, normal transistors P1, P2, Q1, and Q2, and resistors R1, R2, R3, and R4. Transistors DP1, P1, and P2 are formed of PNP bipolar transistors, and transistors DQ1, DQ2, Q1, and Q2 are formed of NPN bipolar transistors.

When the up signal f_up and the down signal f_down are at the H level, so-called digital transistors DQ1, DQ2, and DP1 with resistors are all turned on, so that no current flows through the transistors P1, P2, Q1, and Q2. If the input impedance of the VCO 7 is set to a sufficiently high value, the potential of the control terminal T_cp at this time maintains a constant value.
When the up signal f_up changes to the L level and is activated, the digital transistor DQ2 is turned off and the transistors Q1 and Q2 are turned on.
At this time, a current equivalent to that of the current source I_ref1 flows from the charge pump resistor R_cp to the ground voltage GND through the control terminal T_cp and the transistor Q2.
When the down signal f_down transitions to the L level and is activated, the digital transistors DQ1 and DP1 are turned off and the transistors P1 and P2 are turned on. At this time, a current equivalent to that of the current source I_ref2 flows from the control terminal T_cp to the charge pump resistor R_cp.

  Thus, when the input up signal f_up is activated, the charge pump circuit 5 causes the motor drive IC 2 from the charge pump capacitor C_cp and the charge pump resistor R_cp connected to the control terminal T_cp of the motor drive IC 2. The charge pump current flows in the direction of. Since the potential of the control terminal T_cp decreases in this current direction, the VCO 7 operates in the direction of increasing the oscillation frequency.

  On the other hand, when the input down signal f_down is activated, the charge pump circuit 5 moves from the motor drive IC 2 in the direction of the charge pump capacitor C_cp and the charge pump resistor R_cp connected to the control terminal T_cp. Apply charge pump current. In this current direction, since the potential of the control terminal T_cp increases, the VCO 7 operates in a direction to decrease the oscillation frequency.

  One control time for increasing the oscillation frequency of the VCO 7 or one control time for decreasing the oscillation frequency of the VCO 7 is a time until the direction of the charge pump current is switched to the opposite direction. The period during which the f_up or the down signal f_down is activated is defined by the L-level pulse width. As the width increases, the oscillation frequency of the VCO 7 increases or decreases and the control amount increases. Therefore, the potential of the control terminal T_cp fluctuates with time and dynamically changes in a short period, but the average potential seen in a relatively long period increases and decreases relatively when the frequency is increased. Is relatively low.

Conventionally, since this VCO control potential is set to DC by a smoothing filter, a very large capacity and resistance are required. Also, the response was slow.
On the other hand, in the present embodiment to which the present invention is applied, the VCO control voltage is directly raised and lowered without going through a smoothing filter. More specifically, when the up signal f_up or the down signal f_down is activated, the direction of the current of the charge pump circuit 5 is instantaneously switched, and the VCO control voltage instantaneously increases or decreases correspondingly. Is very early.
Here, the charge pump capacitor C_cp in this example is a constant of the charge pump operation and becomes an integral element. Further, the charge pump resistor R_cp becomes an instantaneous element by a constant of the charge pump operation, that is, plays a role of a conversion element that changes a current into a voltage value. These values can be as small as the value of the charge pump capacitor C_cp of 0.22 μF, for example, and the value of the charge pump resistor R_cp of 68 kΩ, for example.

FIG. 7 shows four examples of voltage changes at the VCO control terminal (T_cp terminal) corresponding to the pulse widths of the up signal f_up and the down signal f_down. In this example, the relationship waveform between the EMF polarity inversion phase of each phase detected by the rotor phase detector 3 and the voltage of the control terminal T_cp is shown. FIG. 7 shows the response waveforms of the respective parts according to the EMF polarity inversion phase position in four examples.
Example 1 is shown in FIGS. 7B1 to 7B5, Example 2 is shown in FIGS. 7C1 to 7C5, and Example 3 is shown in FIGS. 7C1 to 7C5. Example 4 is shown in FIGS. 7D1 to 7D5.

Here, the restriction signals M_early and M_late used in this example are shown in FIG. 7 (A3) and FIG. 7 (A4). For comparison, the oscillation clock signal CLK_vco, the fourth divided signal QD, the electrical angle scale, and the phase output drive information (pulse signal y5) are shown in FIGS. 7A1, 7A2, and 7A5, respectively. Shown in
In this example, the pulse width T_early of the restriction signal M_early is set to -15 [deg] to 0 [deg] corresponding to the drive electrical angle. Further, the pulse width T_late of the restriction signal M_late is also changed from 0 [deg] to 26.25 [deg]. Again, setting the T_late side pulse width wider than the T_early side pulse width is one of the major features of this embodiment.
For the sake of explanation, the phase output drive information (FIG. 2 (F)) is fixed at the position “y5”, but the same operation is performed in “y0” to “y5” which are all phase output drive states. Accordingly, the target phase range is −30 [deg] to +30 [deg] in terms of drive electrical angle as shown in FIG. 7 (A2).

Example 1 shows a case where the EMF polarity reversal position by the rotor phase, that is, the rising phase of the U_det signal is much earlier than the zero degree phase of the drive electrical angle (FIG. 7 (B1)).
At this time, the up signal f_up (FIG. 7 (B2)) is subjected to phase restriction by the pulse width T_early of the restriction signal M_early signal, and the L level active time is restricted. Further, the down signal f_down at this time holds the H level (FIG. 7 (B3)). Further, the charge pump current (FIG. 7B4) flows from the charge pump resistor R_cp toward the control terminal T_cp by the pulse width T_early of the regulation signal M_early. The L level shown in the voltage of the control terminal T_cp (FIG. 7 (B5)) is a potential drop corresponding to the instantaneous correction of δVCP during the period in which the charge pump current (FIG. 7 (B4)) flows. This value is the product of the charge pump current (FIG. 7 (B4)) and the charge pump resistor R_cp. After the charge pump current (FIG. 7 (B4)) has finished flowing, the voltage at the control terminal T_cp drops to a potential corresponding to δVCP integral correction. This δVCP integral correction value is the product of the charge pump current value (FIG. 7 (B4)) and the active time of the up signal f_up (the charge fluctuation amount of the charge pump capacitor C_cp) as the capacitance value of the charge pump capacitor C_cp. The divided value.
As a result, the output frequency of the VCO 7 increases due to the change in the voltage of the control terminal T_cp.

Example 2 shows a case where the EMF polarity reversal position by the rotor phase, that is, the rising phase of the U_det signal is delayed by about 20 ° in driving electric angle from the rising phase of the U_det signal in Example 1 (FIG. 7 (A2 )). At this time, since the restriction by the mask signal M_early is not received, the up signal f_up is activated at the rising edge of the U_det signal.
In Example 2, the period during which the charge pump current flows is shorter than that in Example 1 (FIG. 7 (C4)). Therefore, the potential drop for the δVCP integral correction of the voltage at the control terminal T_cp is smaller than in Example 1. (FIG. 7 (C5)).

In Example 3, the EMF polarity inversion position by the rotor phase, that is, the rising phase of the U_det signal coincides with the zero phase position of the drive electrical angle.
At this time, neither the up signal f_up nor the down signal f_down signal is activated (FIG. 7 (D2) and FIG. 7 (D3)), so that the voltage of the control terminal T_cp maintains a constant value (FIG. 7 (D5)).

Example 4 shows a case where the EMF polarity inversion position by the rotor phase, that is, the rising phase of the U_det signal is about 30 ° later than the zero degree phase of the drive electrical angle.
At this time, the down signal f_down (FIG. 7 (E3)) is subjected to phase restriction by the pulse width T_late of the restriction signal M_late signal, and the L level active time is restricted. Further, the up signal f_up at this time holds the H level (FIG. 7 (E2)). The direction in which the charge pump current is output is the direction from the control terminal T_cp toward the charge pump resistor R_cp, contrary to the first and second examples. In this example, since the voltage of the control terminal T_cp increases (FIG. 7 (E5)), the frequency output by the VCO 7 decreases.
However, when the VCO 7 is operating at a low frequency such as at the time of start-up due to the configuration of the VCO 7 described above, the lower limit frequency is provided in the VCO 7, so that the frequency is not lower than this.

FIG. 8 shows an example of input / output characteristics of the VCO 7.
If the number P of rotor poles of the motor is 8 in the frequency division ratio of the drive pulse generator 41, the relationship between the motor rotation speed N and the output frequency F_vco of the VCO 7 is as follows.
[Equation 2]
N [rpm] = F_vco [Hz] /6.4 (2)

A large white circle shown in FIG. 8 indicates the motor rotation speed N, and a small square circle indicates the oscillation frequency F_vco of the VCO 7. Further, the horizontal axis of FIG. 8 defines the potential difference in which the voltage at the control terminal T_cp has decreased from the Vcc voltage as δVcp [V].
It can be seen that even when δVcp is 0 [V], that is, when the voltage at the control terminal T_cp is at the same level as the Vcc voltage, the VCO 7 does not stop oscillating and continues to oscillate at about 2.56 [kHz]. This lower limit oscillation frequency is about 400 rpm when converted by the motor rotation speed N.

The motor was driven using the motor drive circuit 1 of the present embodiment.
The motor 100 used at this time is a three-phase brushless motor having a rotor pole number P of 8 poles, a rated voltage of 3 V, a starting current of 0.1 A, a rotor inertia of 3 × 10 ⁻⁸ [kg · m ² ], and a torque constant of 2 ×. 10 ⁻³ [N · m / A].
The charge pump current is 1.5 μA, the charge pump capacitor C_cp is 0.022 μF, and the charge pump resistor R_cp is 68 kΩ. The voltage generated when the charge pump current flows through the charge pump resistor R_cp is 102 mV. This voltage is converted to a rotational speed displacement of about 3984 rpm by the VCO 7.
The motor starting frequency is 420 rpm, and the VCO gain is about 250 kHz / V (about 39062.5 rpm / V in terms of rotational speed gain). The maximum oscillation frequency of the VCO is approximately 22,500 rpm in terms of rotation speed.
Since the rated rotational speed of the motor at the rated voltage of 3V is about 12000 rpm, the performance of the VCO is sufficient.

9 to 13 show actual operation waveforms.
FIG. 9 shows operation waveforms in a steady state.
From the top, the waveforms are the U-phase drive signal U (U-phase terminal voltage), the V-phase drive signal V (V-phase terminal voltage), and the W-phase drive signal W (W-phase terminal voltage). The scale of the vertical axis and the horizontal axis is shown in the name of each waveform. For example, the U-phase terminal voltage has a vertical scale of 2V and a horizontal scale of 2ms, which is expressed as (2V / 2ms). This notation is the same for the other waveforms in FIG. 9 and FIGS. The energization rule is a 120 ° energization type and a full wave drive type. This is the same as the contents of the operation explanation so far.
The EMF waveform can be seen when the U, V, and W phase voltages are in the non-energization period where neither the H level output nor the L level output is present. It can be seen that the motor is operating in each phase with the EMF phase, that is, the rotor phase equal to the drive phase.

FIG. 10 also shows an operation waveform in a steady state. From the top, the waveforms are the U-phase terminal voltage, the up signal f_up voltage (f_up voltage), the down signal f_down voltage (f_down voltage), and the control terminal T_cp voltage (CP). Terminal voltage).
Since it is in a steady state, the rotor phase and the drive circuit phase coincide with each other, there is little period in which both the up signal f_up voltage and the down signal f_down voltage are in the active state, and only a small AC signal component is seen in the voltage at the control terminal T_cp. I can't.

FIG. 11 shows operation waveforms from the start-up due to power-on to the acceleration state.
From the top, the waveforms are the U-phase terminal voltage, f_up voltage, f_down voltage, and CP terminal voltage.
FIG. 12 and FIG. 13 are time-expanded operation waveforms at startup and acceleration from this figure.

FIG. 12 is a time-enlarged view of the operation waveform immediately after startup by turning on the power among the operation waveforms shown in FIG. From the top, the waveforms are the U-phase terminal voltage, f_up voltage, f_down voltage, and CP terminal voltage.
Immediately after startup, the voltage at the control terminal T_cp (CP terminal voltage) is equal to the Vcc voltage, so the VCO 7 outputs the oscillation frequency set as the lower limit, and the motor starts to start at this starting rotational speed. When the motor starts to start, EMF is generated by the rotational movement of the rotor. An EMF waveform is visible when the U phase is not energized. The charge pump current is changed by the up signal f_up and the down signal f_down obtained by detecting the rotor phase from the EMF phase and comparing the drive circuit phases, thereby changing the voltage of the control terminal T_cp.
In the phase determination immediately after startup, even if the rotor phase is behind the drive circuit phase and the down signal f_down is activated to L level, the VCO 7 does not output a frequency lower than the startup rotational speed. For this reason, the motor does not stop during startup.

In this example, the rotor phase at startup is indefinite.
In the waveform example of FIG. 12, the rotor rotates at the starting rotational speed with almost no acceleration until the rotor phase is suitable for acceleration for a period of about 40 ms immediately after starting. The motor starts to accelerate from a period after about 40 ms from immediately after starting.
When the up signal f_up is activated when the motor starting rotational speed is about 420 rpm, the charge pump current flows through the charge pump resistor R_cp described above, resulting in a rotational speed displacement of about 3984 rpm. However, since the rotational motion of the rotor is limited by the motor driving torque and the acceleration capability by the rotor inertia, the rotational tracking of the driving circuit is not synchronously followed.

  The displacement dN of the motor rotational speed is expressed by the following equation (3).

[Equation 3]
dN = 60 · τ / (J · 2π) · dt (3)

Here, “τ” is a motor driving torque, “J” is a rotor inertia, and “dt” is a displacement period.
If the number of rotor poles is 8 at the starting rotational speed of about 420 rpm, the electrical angle equivalent to 360 ° is about 35.7 ms. Since the period during which the up signal f_up is activated corresponds to an electrical angle of 15 ° at the maximum, this period is about 1.5 ms.

From the starting current 0.1 A, rotor inertia 3 × 10 ⁻⁸ [kg · m ² ] and torque constant 2 × 10 ⁻³ [N · m / A], the motor drive torque τ is 2 × 10 ⁻⁴ [N · m. The motor rotation speed displacement dN is 95.5 [rpm]. This is only about 1/42 of about 3984 rpm which is the rotational speed displacement value of the circuit.
In other words, when the motor is rotating in a low rotational speed range such as the starting rotational speed, the activation of the up signal f_up can increase the drive circuit frequency instantaneously rather than contributing to the acceleration motion of the rotor. The operation phase of the phase output drive is quickly shifted to advance to an appropriate drive phase for acceleration.

FIG. 13 is an operation waveform during motor acceleration among the operation waveforms shown in FIG. From the top, the waveforms are the U-phase terminal voltage, f_up voltage, f_down voltage, and CP terminal voltage.
FIG. 13 shows that the EMF phase and the drive circuit phase are accelerating while matching.

In the present embodiment, the maximum oscillation frequency of the VCO 7 needs to be a value obtained by converting the maximum oscillation frequency of the VCO 7 to exceed the maximum rotation number of the motor. This is because, in the control of the present embodiment, the entire system forms one closed loop by combining three open loops, and the operating point is determined by the voltage of the control terminal T_cp, thereby the VCO oscillation frequency, that is, the rotor. The rotation speed is specified.
In order to stabilize the operating point, a loop gain must exist near the operating point. In other words, the VCO gain must not be zero even in a frequency range that exceeds the rated rotational speed of the motor that is the operating point.

Hereinafter, three open loop components will be described.
The first is the motor 100. The rotor 101 rotates by driving the U, V, and W phase coils 102U, 102V, and 102W, and generates EMF when each phase is not energized.
The second is a control system circuit that determines a phase difference from the rotor phase detector 3 to the charge pump circuit 5 in the motor drive circuit 1 and generates an up signal f_up and a down signal f_down. This control system circuit obtains circuit phase information from the drive pulse generator 41 in order to determine the drive circuit phase, but no feedback loop is formed by these signals in the control system circuit.
The third is a drive system circuit from the VCO 7 to the output unit 9 in the motor drive circuit 1.

In the present embodiment, these independent three open loop components are combined like a cocoon to form one closed loop.
The advantage of having each component open is great. That is, it is one of the advantages that there is no risk of abnormal oscillation and that circuit design and circuit inspection are easy. In addition, there is an advantage that operation parameters such as T_early phase width and charge pump current can be optimally set only for the purpose of operation because there is no circuit stabilization tradeoff.

The motor and its drive circuit according to the present embodiment have the following effects.
First, it is possible to provide a sensorless motor drive circuit that can be reliably started and can obtain a stable motor rotation operation. At this time, since the voltage of the control terminal T_cp of the VCO 7 is directly and instantaneously driven according to the information on the phase lag and phase advance at that time, the response is fast.
Second, since it is a simple circuit suitable for IC implementation, the IC circuit scale can be minimized.
Third, since there is no feedback loop in the drive circuit, the circuit is stable. As a result, circuit design and circuit inspection are easy.

Fourth, the number of external electrical components other than the driving IC is small.
In the example of FIG. 1, in addition to the motor drive IC 2, the power supply decoupling capacitor C_DC is included and the number of external electrical components is four, but two of these resistances can be taken into the motor drive IC 2. As a result, the number of external electrical components can be reduced to two.
The constants of the external electrical components are independent values that do not depend on the operation of the drive circuit. Since it is only necessary to correspond to the magnetic characteristics and mechanical time constant of the motor, the optimization of the constant is easy, and there is a relatively wide tolerance for the constant.

Fifth, since the constants of these external electric components are small and are values obtained with a so-called “0603: JIS standard” chip size, there is an advantage that the whole can be reduced in this point as well.
Necessary operations when using motor 100 with power supply voltage V_cc = 3 V, starting current 0.1 A, inertia 3 × 10 ⁻⁸ [kg · m ² ], torque constant 2 × 10 ⁻³ [N · m / A] As constants for obtaining the waveform, for example, the resistance value of the charge pump resistor R_cp may be as small as 68 kΩ and the capacitance value of the charge pump capacitor C_cp as small as 0.022 μF. Therefore, there is an advantage that the mounting area occupied by these external parts is extremely small.

The motor drive circuit of the present invention is not limited to a three-phase brushless motor, and can be applied to a multiphase or single-phase brushless motor other than three-phase. Further, the number of magnetizations of the rotor is not limited to 8 poles.
However, when the drive target is changed, it is necessary to change the configuration and operation of the motor drive circuit 1 in conformity with the change. That is, the configuration for changing the number of comparators, the number of phase comparisons, and the configuration of the output circuit according to the number of drive phases, and generating a signal for driving the output unit according to the number of drive phases and the number of magnetizations, for example, a clock It is necessary to change the count number and the phase difference of the output decode signal. However, even if the number of drive phases and the number of magnetizations are different, the above description can be applied by analogy with respect to the basic configuration and operation regardless of them.

Note that the electronic apparatus according to the present embodiment includes the motor drive circuit 1 and the motor 100.
Although not particularly illustrated, an eccentric member is attached to the rotor rotation shaft of the motor 100, and the motor 100, the eccentric member, and the motor drive circuit 1 are mounted as a vibration motor module on the same module substrate. The vibration motor module is built in an electronic device such as a mobile phone terminal, for example, and used as a notification means at the time of incoming call. Note that the electronic device of the present invention is not limited to a mobile phone terminal, but the present invention is suitable for a portable electronic device because it is small, has good controllability, and can reduce power consumption. Applicable to.

1 is a configuration diagram illustrating a sensorless three-phase brushless DC motor and a motor drive circuit thereof according to an embodiment of the present invention. 4 is a timing chart showing signal waveforms and timings in a drive system circuit mainly of a motor drive circuit. 5 is a timing chart showing signal waveforms and timings in a motor system mainly in a control system circuit. It is a circuit diagram which shows the structural example of the restriction | limiting control part which produces | generates a restriction | limiting signal. It is the block diagram and circuit diagram which show the structural example which has the function of a selector and a phase comparison part. It is a circuit diagram which shows the structural example of a charge pump circuit. 6 is a timing chart showing four examples of voltage changes at the VCO control terminal (CP terminal) according to the pulse widths of the up signal and the down signal. It is a graph which shows the input-output characteristic example of VCO. It is a figure which shows the 1st example of an actual operation | movement waveform. It is a figure which shows the 2nd example of an actual operation | movement waveform. It is a figure which shows the 3rd example of an actual operation | movement waveform. It is a figure which shows the 4th example of an actual operation | movement waveform. It is a figure which shows the 5th example of an actual operation | movement waveform.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Motor drive circuit, 2 ... Motor drive IC, 3 ... Rotor phase detection part, 4 ... Logic part, 41 ... Drive pulse generation part, 42 ... Pulse width phase comparison part, 43 ... Control signal generation part, 44 ... Selector, DESCRIPTION OF SYMBOLS 5 ... Charge pump circuit, 6 ... Charge pump electric current setting device, 7 ... Voltage control oscillator (VCO), 71 ... Capacitor for VCO, 8 ... Preamplifier, 9 ... Output part, 100 ... Motor, 101 ... Rotor, 102 ... Coil, 102U ... U phase coil, 102V ... V phase coil, 102W ... W phase coil, C_cp ... charge pump capacitor, C_DC ... decoupling capacitor, CLK_vco ... clock signal, R_Iref ... charge pump current setting resistor, R_cp ... charge pump Resistors, U, V, W ... drive signals

Claims (5)

A motor drive circuit for driving a sensorless brushless DC motor comprising a rotor and a plurality of coils facing the rotor,
A built-in voltage controlled oscillator for generating an oscillating clock signal at a frequency according to the applied control voltage to the control terminal, based on the clock signal from the voltage controlled oscillator circuit is defined by the frequency of the clock signal A drive signal generating unit that generates a plurality of drive signals having sequentially different phase differences,
When rotating the rotor by supplying said plurality of drive signals to said plurality of coils, to monitor the voltage induced in the plurality of coils, the rotor phase is the driving signal obtained from the induced voltage A phase shift detector that generates a first detection signal when the electrical phase is delayed with respect to the obtained electrical phase, and generates a second detection signal when the rotor phase is advanced with respect to the electrical phase ;
The first detection signal and the second detection signal are input, the control terminal is charged only for the duration of the active state of the input first detection signal, and only the duration of the active state of the input second detection signal A charge / discharge circuit for discharging the control terminal ;
A conversion element connected to the control terminal for converting a change in current during the charging or discharging into a change in the control voltage having opposite directions;
The maximum control time when the charge / discharge circuit and the conversion element control the control voltage to increase the oscillation frequency of the voltage controlled oscillation circuit, and the maximum control time when the control voltage is controlled to decrease the oscillation frequency A control restricting part for restricting an upper limit of the duration of the active state for each of the first detection signal and the second detection signal so as to be shorter;
A motor drive circuit. The motor drive circuit according to claim 1, wherein the drive signal generation unit includes a start control circuit having a start frequency that reliably starts the rotor from when stopped as a lower limit frequency . A sensorless brushless DC motor including a rotor and a plurality of coils facing the rotor;
A motor drive circuit for driving the brushless DC motor;
Is an electronic device that is built into a module,
The motor drive circuit is
A voltage-controlled oscillation circuit that oscillates at a frequency according to the control voltage applied to the control terminal and generates a clock signal is built in, and is defined by the frequency of the clock signal based on the clock signal from the voltage-controlled oscillation circuit. A drive signal generating unit that generates a plurality of drive signals having sequentially different phase differences,
When the plurality of drive signals are supplied to the plurality of coils and the rotor is rotated, the induced voltage induced in the plurality of coils is monitored, and the rotor phase obtained from the induced voltage is determined from the drive signal. A phase shift detector that generates a first detection signal when the electrical phase is delayed with respect to the obtained electrical phase, and generates a second detection signal when the rotor phase is advanced with respect to the electrical phase;
The first detection signal and the second detection signal are input, the control terminal is charged only for the duration of the active state of the input first detection signal, and only the duration of the active state of the input second detection signal A charge / discharge circuit for discharging the control terminal ;
A conversion element connected to the control terminal for converting a change in current during the charging or discharging into a change in the control voltage having opposite directions;
The maximum control time when the charge / discharge circuit and the conversion element control the control voltage to increase the oscillation frequency of the voltage controlled oscillation circuit, and the maximum control time when the control voltage is controlled to decrease the oscillation frequency A control restricting part for restricting an upper limit of the duration of the active state for each of the first detection signal and the second detection signal so as to be shorter;
Electronic equipment having A motor driving method for driving a sensorless brushless DC motor comprising a rotor and a plurality of coils facing the rotor,
Generating a clock signal having a frequency according to the held control voltage;
Generating a plurality of drive signals having a cycle defined by the frequency of the clock signal and having sequentially different phase differences based on the clock signal;
When the plurality of drive signals are supplied to the plurality of coils and the rotor is rotated, the induced voltage induced in the plurality of coils is monitored, and the rotor phase obtained from the induced voltage is determined from the drive signal. Generating a first detection signal when delayed with respect to the resulting electrical phase, and generating a second detection signal when the rotor phase is advanced relative to the electrical phase;
By charging the holding node of the control voltage for the duration of the active state of the first detection signal, the control voltage in the generation step of the clock signal is changed, and only for the duration of the active state of the second detection signal. Changing the control voltage in the generation step of the clock signal in a direction opposite to that during the charging by discharging the holding node of the control voltage; and
Including
In the step of changing the control voltage by the charging and discharging, the maximum control time when the frequency of the clock signal is increased by changing the control voltage, the control voltage is changed in the opposite direction, and the clock signal The upper limit of the duration of the active state is regulated for each of the first detection signal and the second detection signal so as to be shorter than the maximum control time when the frequency decreases.
Motor drive method . When the clock signal is generated, the lower limit frequency is controlled so that the lower limit is the starting frequency at which the rotor is reliably started from when stopped.
The motor driving method according to claim 4 .

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