JP5325607B2 - Frequency-locked loop circuit, speed discriminator circuit, motor drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an FLL (Frequency Locked Loop) circuit eliminating the need for the multiplication of an REFCLK. <P>SOLUTION: The FLL circuit 12 has a counter circuit X10 starting the counting of an ICLK when an FG edge arrives and completing the counting when a count value C1 reaches a STOP 1, a counter circuit X20 starting the counting of the ICLK when the counter circuit X10 completes the counting and completing the counting thereof when the count value C2 reaches a STOP 2. The FLL circuit 12 further has a reference counter Y1 counting the number of pulses of the ICLK contained in one period of the REFCLK, a reference register Y2 storing the count value C0 of the reference counter Y1 every one period of the REFCLK and a completing count-value setting section Y0 distributing the register data REG0 of the reference register Y2 and setting the STOP 1 and the STOP 2. The FLL circuit 12 further has a logic gate section X30 generating frequency-error signals (U1 and D1) in response to the operating states of the counter circuits X10 and X20. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a frequency-locked loop circuit that generates a frequency error signal by comparing the frequencies of two input signals, and a speed discriminator circuit and a motor driving device using the same.

  FIG. 19 is a block diagram showing a conventional example of a speed discriminator circuit used for motor rotation speed control. As shown in FIG. 19, a conventional speed discriminator circuit generally includes a phase locked loop circuit 100 (hereinafter referred to as a PLL [Phase Locked Loop] circuit 100), a filter circuit 110, and a voltage controlled oscillator 120 (hereinafter referred to as a PLL). , VCO [Voltage Controlled Oscilator] 120), frequency divider 130, and frequency locked loop circuit 140 (hereinafter referred to as FLL [Frequency Locked Loop] circuit 140).

  The PLL circuit 100 compares the phase between the speed control signal Sa (= reference clock signal REFCLK) input from the outside of the circuit and the frequency-divided signal Sb in order to set the target rotational speed of the motor, whereby the phase error signal Sc Is a means for generating As shown in FIG. 20, the phase error signal Sc is a digital signal that is at a high level from the rising edge of the speed control signal Sa to the rising edge of the divided signal Sb.

  The filter circuit 110 is means for generating a DC control voltage signal Sd by performing D / A [Digital / Analog] conversion of the phase error signal Sc, and includes an external resistor and a capacitor (see FIG. 21). ).

  The VCO 120 has the input / output characteristics shown in FIG. 22, and is a means for generating the oscillation signal Se (= multiplied clock signal VCOCLK) at an output frequency corresponding to the control voltage signal Sd (input voltage).

The frequency divider 130 divides the output frequency of the oscillation signal Se by N (where N = 10), for example, by inputting the oscillation signal Se to a counter formed by n flip-flops DFF1 to DFFn. = ²ⁿ , for example, means for generating a frequency-divided signal Sb divided by N = 1024 (see FIGS. 23 and 24).

  By forming a feedback loop including the PLL circuit 100, the filter circuit 110, the VCO 130, and the frequency divider 140, the output frequency of the speed control signal Sa (= reference clock signal REFCLK) is multiplied by N (for example, N = 1024). The oscillation signal Se (= multiplication clock signal VCOCLK) can be obtained.

  The FLL circuit 140 is means for generating a frequency error signal Sg (acceleration signal U and deceleration signal D) by comparing the frequency of the oscillation signal Se and the FG [Frequency Generator] pulse signal Sf, as shown in FIG. As described above, the first counter Z1a, the second counter Z1b, the first comparison unit Z2a, the second comparison unit Z2b, and the control unit Z3 are included.

  FIG. 26 is a timing chart showing an operation example of the FLL circuit 140. In the upper part of FIG. 26, a reference clock signal REFCLK and a multiplied clock signal VCOCLK (an oscillation signal obtained by multiplying the reference clock signal REFCLK by 1024) are shown. 26, the count value C1 of the first counter Z1a when the frequency of the FG pulse signal Sf is lower than the frequency of the reference clock signal REFCLK (that is, when the rotational speed of the motor is slower than the target rotational speed). The count value C2 of the second counter Z1b, the acceleration signal U, and the deceleration signal D are shown. In the lower part of FIG. 26, the count value C1 of the first counter Z1a when the frequency of the FG pulse signal Sf is higher than the frequency of the reference clock signal REFCLK (that is, when the rotational speed of the motor is faster than the target rotational speed). The count value C2 of the second counter Z1b, the acceleration signal U, and the deceleration signal D are shown.

  First, an operation when the frequency of the FG pulse signal Sf is lower than the frequency of the reference clock signal REFCLK will be described with reference to the middle part of FIG. When one rising edge arrives in the FG pulse signal Sf, the count operation of the multiplied clock signal VCOCLK by the first counter Z1a is started using this as a trigger. When the count value C1 of the first counter Z1a reaches a predetermined first end count value STOP1 (for example, 256 counts), the count operation of the first counter Z1a is terminated, the count value C1 is reset, and the second counter The counting operation of the multiplied clock signal VCOCLK by Z1b is started. When the count value C2 of the second counter Z1b reaches a predetermined second end count value STOP2 (for example, 768 counts), the count operation of the second counter Z1b is ended and the count value C2 is reset. At this time, if the next rising edge has not arrived in the FG pulse signal Sf, neither the first counter Z1a nor the second counter Z1b is in a state of performing the counting operation. If such a state occurs, the motor rotation speed is slower than the target rotation speed, so the next rising edge arrives in the FG pulse signal Sf, and the count operation of the first counter Z1a starts. Until this is done, the acceleration signal U is kept at a high level.

  Next, an operation when the frequency of the FG pulse signal Sf is higher than the frequency of the reference clock signal REFCLK will be described with reference to the lower part of FIG. The operation from the arrival of one rising edge to the FG pulse signal Sf to the start of the counting operation of the multiplied clock signal VCOCLK by the second counter Z1b is the same as described above, but the count value C2 of the second counter Z1b is When the next rising edge of the FG pulse signal Sf arrives before reaching the second end count value STOP2, the count operation of the first counter Z1a starts without waiting for the count end of the second counter Z1b. Thus, the first counter Z1a and the second counter Z1b are in a state where they are simultaneously counting. If such a state occurs, the motor rotation speed is faster than the target rotation speed, so the count value C2 of the second counter Z1b reaches the second end count value STOP2 and the second counter Z1b Until the counting operation is completed, the deceleration signal D is kept at the high level.

  Thus, if the cycle of the FG pulse signal Sf is longer than the cycle of the reference clock signal REFCLK (1024 counts of the multiplied clock signal VCOCLK), the FLL circuit 140 determines that the rotational speed of the motor is slower than the target rotational speed. The acceleration signal U is output, and if the cycle of the FG pulse signal Sf is shorter than the cycle of the reference clock signal REFCLK, it is determined that the rotation speed of the motor is faster than the target rotation speed, and the deceleration signal D is output. It was.

  In addition, the motor drive device using the speed discriminator circuit having the above configuration uses the charge pump circuit or the integration circuit to generate the frequency error signal Sg (the acceleration signal U and the deceleration signal D) generated by the FLL circuit 140. A corresponding speed command signal is generated, and the rotational speed control of the motor is performed based on the generated speed command signal.

  In addition, patent documents 1-3 can be mentioned as an example of the prior art relevant to the above.

JP 2007-288896 A JP 2007-336653 A JP-A-6-189575

  Certainly, if the rotational speed of the motor is controlled using the conventional speed discriminator circuit, the rotational speed of the motor can be controlled by arbitrarily controlling the frequency of the speed control signal Sa (= reference clock signal REFCLK). Can be adjusted to a desired target rotational speed.

  However, in the conventional speed discriminator circuit, the FLL circuit 140 is configured to set the first end count value STOP1 of the first counter Z1a and the second end count value STOP2 of the second counter Z1b as fixed values. It was. For this reason, the FLL circuit 140 always uses a constant clock signal VCOCLK (a constant clock signal REFCLK in one cycle) as a signal to be counted by the first counter Z1a and the second counter Z1b by multiplying the reference clock signal REFCLK by N. A number N (= clock signal having STOP1 + STOP2) must be input, and a feedback circuit comprising a PLL circuit 100, a filter circuit 110, a VCO 120, and a frequency divider 130 as means for generating a multiplied clock signal VCOCLK. It was necessary to form a loop. Such a conventional configuration solves problems such as an increase in circuit scale and an increase in the number of external elements, a filter constant adjustment, and a delay in response to changes in the frequency of the reference clock signal REFCLK. It included various issues to be solved.

  The speed control device described in the conventional document 3 is similar to the present invention in that it includes counter value switching means for switching the count value (number of bits) of the counter according to the target speed to be controlled. However, the speed control device of the conventional document 3 only sets the count value (number of bits) of the counter to either 10 bits or 11 bits depending on whether the target speed is faster or slower than the predetermined speed. The present invention differs from the present invention in which the end count value of the counter is variably controlled by digital signal processing.

  In view of the above problems, the present invention has an object to provide a frequency locked loop circuit that does not require a means for multiplying a reference clock signal, a speed discriminator circuit using the same, and a motor drive device. To do.

  In order to achieve the above object, a frequency-locked loop circuit according to the present invention is a frequency-locked loop circuit that generates a frequency error signal by comparing the frequency of a pulse signal to be controlled with the frequency of a reference clock signal. When the pulse edge of the pulse signal arrives, the count operation of the internal clock signal is started and the first count start flag is set, and when the count value reaches the first end count value, the first count ends A first counter circuit for setting a flag; when the first count end flag is set, the count operation of the internal clock signal is started and a second count start flag is set, and the count value becomes the second end count value; A second counter circuit that sets a second count end flag when the internal clock signal is reached; and the internal circuit included in one cycle of the reference clock signal A reference counter for counting the number of pulses of the lock signal; a reference register for storing a count value of the reference counter for each period of the reference clock signal; and a first end based on register data stored in the reference register An end count value setting unit for setting the count value and the second end count value; and a logic gate unit for generating the frequency error signal in accordance with the operating states of the first counter circuit and the second counter circuit. The configuration is the first configuration.

  In the frequency-locked loop circuit having the first configuration, the end count value setting unit sets the register data stored in the reference register at a ratio of s: 1-s (where 0 <s <1). It is preferable to adopt a configuration (second configuration) in which the first end count value and the second end count value are set by distributing.

  Further, in the frequency locked loop circuit having the second configuration, the end count value setting unit sets a surplus of the register data generated when the first end count value is set as a standby count value. The first counter circuit waits for the start of the count operation from the arrival of the pulse edge of the pulse signal until the number of pulses of the internal clock signal reaches the standby count value. The circuit may have a configuration (third configuration) in which the start of the count operation is waited until the first count end flag is set.

  In the frequency locked loop circuit having the second configuration, the end count value setting unit corresponds to the upper (i−1) bits of i-bit register data stored in the reference register. It has an adder that adds register data and register data corresponding to upper (i-2) bits to generate addition data, and corresponds to upper (i-2) bits as the first end count value The register data to be set is set, and the addition data is set as the second end count value (fourth configuration).

  The frequency locked loop circuit having the fourth configuration starts counting the internal clock signal when the pulse edge of the pulse signal arrives, and the count value reaches the standby count value. And a third counter circuit for setting a third count end flag, wherein the end count value setting unit uses the lower 2 of the i-bit register data stored in the reference register as the standby count value. The first counter circuit waits for the start of the count operation until the third count end flag is set after the pulse edge of the pulse signal arrives. The second counter circuit waits for the count operation to start until the first count end flag is set. Configuration is shall better to (fifth configuration).

  In the frequency locked loop circuit having the first configuration, the end count value setting unit sets 1 / x (where x> 1) of the register data stored in the reference register as a first end count value. 1 / y (y ≧ x) is set as the second end count value, and the first counter circuit starts counting the internal clock signal when the pulse edge of the pulse signal arrives. The first count start flag is set, and when the count value reaches the first end count value, the first count end flag is set. When the first count end flag is set, the second counter circuit The count operation of the internal clock signal is started, the second count start flag is set, and the count value is reset every time the count value reaches the second end count value. Then, the count value arrival count is incremented by one, and when the count value arrival count reaches α times (where α = {(x−1) × y / x}), the second count end flag is set. A configuration (sixth configuration) is preferable.

  Further, in the frequency locked loop circuit having the sixth configuration, the end count value setting unit sets a surplus of the register data generated when the first end count value is set as a standby count value. The second counter circuit is configured to wait for the start of the count operation until the number of pulses of the internal clock signal reaches the standby count value after the first count end flag is set (seventh Configuration).

  In the frequency locked loop circuit having the sixth configuration described above, the end count value setting unit corresponds to upper (i-2) bits of i-bit register data stored in the reference register. A configuration (eighth configuration) may be employed in which the register data is set as the first end count value and the second end count value.

  In the frequency locked loop circuit having the sixth configuration described above, the end count value setting unit corresponds to upper (i-2) bits of i-bit register data stored in the reference register. The register data may be set as the first end count value, and the register data corresponding to the (i-4) bits may be set as the second end count value (ninth configuration).

  Further, the frequency locked loop circuit having the ninth configuration detects whether the count value arrival count of the second counter circuit is within a predetermined range when the pulse edge of the pulse signal arrives, A configuration (tenth configuration) including a ready signal generation unit that generates a ready signal of a logic level corresponding to the detection result may be used.

  The frequency locked loop circuit having any one of the eighth to tenth configurations starts counting the internal clock signal when the first count end flag is set, and the count value is the standby count. A third counter circuit that sets a third count end flag when the value reaches a value, and the end count value setting unit stores i-bit register data stored in the reference register as the standby count value Register data corresponding to the lower 2 bits is set, and the second counter circuit counts from the time when the first count end flag is set until the time when the third count end flag is set. It is good to set it as the structure (11th structure) by which a start is waited.

  The frequency locked loop circuit having any one of the first to eleventh configurations reads out the register data stored in the reference register at a timing different from the data update timing of the reference register, The end count value setting unit sets a first end count value and a second end count value based on the register data stored in the second reference register. It is preferable to adopt a configuration (a twelfth configuration).

  In the frequency locked loop circuit having the twelfth configuration described above, the reference register updates data when a pulse edge of the reference clock signal arrives, and the second reference register inverts the reference clock signal. A configuration (a thirteenth configuration) may be employed in which data is updated when a pulse edge arrives.

  In the frequency locked loop circuit having the twelfth configuration described above, the reference register updates data when a pulse edge of the reference clock signal arrives, and the second reference register has a first count end flag. A configuration (14th configuration) in which data is updated immediately after being set up may be used.

  A speed discriminator circuit according to the present invention includes a frequency locked loop circuit having any one of the first to fourteenth configurations, and generates a speed command signal corresponding to the frequency error signal ( 14th configuration).

  The speed discriminator circuit having the fourteenth configuration includes a phase-locked loop circuit that generates a phase error signal by comparing phases of the pulse signal and the reference clock signal, and the frequency error signal And a configuration for generating a speed command signal corresponding to both the phase error signal (sixteenth configuration).

  A motor driving apparatus according to the present invention includes a speed discriminator circuit having the fifteenth or sixteenth configuration described above, and performs a rotational speed control of the motor based on the speed command signal (a seventeenth configuration). It is said that.

  According to the present invention, it is possible to provide a frequency locked loop circuit that does not require a means for multiplying a reference clock signal, a speed discriminator circuit using the frequency locked loop circuit, and a motor driving device.

The block diagram which shows 1st Embodiment of the motor drive device which concerns on this invention. Block diagram showing a first configuration example of the FLL circuit 12 Timing chart showing an operation example of the FLL circuit 12 of the first configuration example Block diagram showing a second configuration example of the FLL circuit 12 Block diagram showing a third configuration example of the FLL circuit 12 Timing chart showing how problems occur when updating registers Timing chart showing how the problem at the time of register update is resolved in the FLL circuit 12 of the third configuration example Block diagram showing a fourth configuration example of the FLL circuit 12 Timing chart showing an operation example of the FLL circuit 12 of the fourth configuration example (when the rotation speed of the motor M matches the target rotation speed). Timing chart showing an operation example of the FLL circuit 12 of the fourth configuration example (when the rotational speed of the motor M is faster than the target rotational speed). Timing chart showing an operation example of the FLL circuit 12 of the fourth configuration example (when the rotational speed of the motor M is slower than the target rotational speed). Timing chart showing how the problem at the time of register update is solved in the FLL circuit 12 of the fourth configuration example Block diagram showing a fifth configuration example of the FLL circuit 12 The block diagram which shows one structural example of the ready signal production | generation part X50. Timing chart showing an operation example of the FLL circuit 12 of the fifth configuration example (when the rotation speed of the motor M matches the target rotation speed). Timing chart showing an operation example of the FLL circuit 12 of the fifth configuration example (when the rotational speed of the motor M is faster than the target rotational speed). Timing chart showing an operation example of the FLL circuit 12 of the fifth configuration example (when the rotational speed of the motor M is slower than the target rotational speed). The block diagram which shows 2nd Embodiment of the motor drive device which concerns on this invention. Block diagram showing a conventional example of a speed discriminator circuit Timing chart showing an operation example of the PLL circuit 100 Circuit diagram showing one configuration example of the filter circuit 110 Input / output characteristics of VCO120 Block diagram showing one configuration example of the frequency divider 130 Timing chart showing one operation example of frequency divider 130 The block diagram which shows the example of 1 structure of the FLL circuit 140 Timing chart showing an operation example of the FLL circuit 140

  In the following, a detailed description will be given by taking as an example a configuration using a frequency-locked loop circuit according to the present invention as an element of a speed discriminator circuit mounted in a motor drive device.

  FIG. 1 is a block diagram showing a first embodiment of a motor drive device according to the present invention. As shown in FIG. 1, the motor driving device of the present embodiment is means for controlling the driving of the motor M, and includes a speed discriminator circuit 10, an integrating circuit 20, a logic circuit 30, a pre-driver 40, And a driver 50.

  The speed discriminator circuit 10 determines whether the rotational speed of the motor M is faster or slower than the desired target rotational speed, and sends the speed command signal VC so that the rotational speed of the motor M matches the target rotational speed. It is a means for generating, and comprises an FG pulse signal generation unit 11, a frequency locked loop circuit 12 (hereinafter referred to as an FLL circuit 12), and a charge pump circuit 13.

  The FG pulse signal generation unit 11 includes a differential amplifier and a comparator (both not shown), and generates a rectangular waveform FG pulse signal from a differential pattern signal (FGP, FGN) corresponding to the rotational speed of the motor M. Is a means for generating

  The FLL circuit 12 performs a frequency comparison between the reference clock signal REFCLK input from the outside of the circuit and the FG pulse signal input from the FG pulse signal generation unit 11 in order to set the target rotation speed of the motor M, This is means for generating frequency error signals (acceleration signal U1 and deceleration signal D1). The circuit configuration and operation of the FLL circuit 12 will be described in detail later.

  The charge pump circuit 13 is a means for generating an output voltage corresponding to the frequency error signal (acceleration signal U1 and deceleration signal D1) input from the FLL circuit 12, and increases the output voltage when the acceleration signal U1 is input. On the contrary, the generation control of the output voltage is performed so that the output voltage is lowered when the deceleration signal D1 is input.

  The integration circuit 20 is means for generating the speed command signal VC by integrating the output voltage generated by the charge pump circuit 13.

  The logic circuit 30 includes a speed command signal VC input from the integrating circuit 20 and hall sensors HU, HV, and HW added to coils of each phase (U phase, V phase, and W phase) constituting the motor M. Based on the input hall signal of each phase (more precisely, a hall comparator signal obtained by converting a sinusoidal hall signal into a rectangular wave shape), the rotational speed control and excitation phase switching control of the motor M are performed. It is means for generating a pre-drive signal for each phase of the motor as it does.

  The pre-driver 40 is means for performing level shift and waveform shaping of the pre-drive signal input from the logic circuit 30 and generating a drive signal for each phase of the motor.

  The driver 50 performs switching control of a power transistor (not shown) connected in an H-bridge based on a driving signal of each phase of the motor input from the pre-driver 40 and drives a driving current to each phase coil constituting the motor M. It is a means to supply.

  Next, the circuit configuration of the FLL circuit 12 will be described in detail with reference to FIG.

  FIG. 2 is a block diagram showing a first configuration example of the FLL circuit 12. As shown in FIG. 2, the FLL circuit 12 of this configuration example includes a first counter X11, a second counter X21, a first comparison unit X12, a second comparison unit X22, a first SR latch X13, and a second SR. In addition to the latch X23, the negative AND operator X24, the AND operator X25, the negative OR operator X31, and the AND operator X32, the first end count value STOP1 of the first counter X11 As means for variably controlling the second end count value STOP2 of the second counter X21, a reference counter Y1, a reference register Y2, and an adder Y3 are provided.

  The clock end of the first counter X11 is connected to the input end of the internal clock signal ICLK. The set end (S) of the first counter X11 is connected to the output end (Q) of the first SR latch X13. The reset terminal (R) of the first counter X11 is connected to the output terminal of the first comparison unit X12. The first input terminal of the first comparison unit X12 is connected to the output terminal of the first counter X11. The second input terminal of the first comparison unit X12 is connected to the input terminal of the first end count value STOP1. The set end (S) of the first SR latch X13 is connected to the input end of the FG pulse signal. The reset terminal (R) of the first SR latch X13 is connected to the output terminal of the first comparison unit X12.

  The first counter X11, the first comparison unit X12, and the first SR latch X13 start the count operation of the internal clock signal ICLK when the rising edge of the FG pulse signal arrives, and serve as the first count start flag. The first latch signal Q1 rises from the low level to the high level, and when the count value C1 of the first counter X11 reaches the first end count value STOP1, the first latch signal Q1 is used as a first count end flag. Is formed from the high level to the low level.

  The clock end of the second counter X21 is connected to the input end of the internal clock signal ICLK. The set end (S) of the second counter X21 is connected to the output end of the AND operator X25. The reset terminal (R) of the second counter X21 is connected to the output terminal of the second comparison unit X22. The first input terminal of the second comparison unit X22 is connected to the output terminal of the second counter X21. The second input end of the second comparison unit X22 is connected to the input end of the second end count value STOP2. The set end (S) of the second SR latch X23 is connected to the output end of the first comparison unit X12. The reset terminal (R) of the second SR latch X23 is connected to the output terminal of the NAND operator X24.

  The first input terminal (non-inverting input terminal) of the NAND operator X24 is connected to the output terminal of the first comparison unit X12. The second input terminal (inverted input terminal) of the NAND operator X24 is connected to the output terminal of the second comparison unit X22. The first input terminal of the AND operator X25 is connected to the output terminal of the first comparison unit X12. The second input terminal of the AND operator X25 is connected to the output terminal (Q) of the second SR latch X23.

  Note that the second counter X21, the second comparison unit X22, the second SR latch X23, the negative AND operator X24, and the AND operator X25 are set when the first count end flag of the first counter circuit X10 is set. In addition, the count operation of the internal clock signal ICLK is started, and the second latch signal Q2 is raised from the low level to the high level as the second count start flag, while the count value C2 of the second counter X21 is the second end count value. A second counter circuit X20 is formed that lowers the second latch signal Q2 from the high level to the low level as the second count end flag when STOP2 is reached.

  The first input terminal of the NOR circuit X31 is connected to the output terminal (Q) of the first SR latch X13. Further, the second input terminal of the NOR circuit X31 is connected to the output terminal (Q) of the second SR latch X23. The output terminal of the negative OR calculator X31 is connected to the output terminal of the acceleration signal U1. The first input terminal of the AND operator X32 is connected to the output terminal (Q) of the first SR latch X13. The second input terminal of the AND operator X32 is connected to the output terminal (Q) of the second SR latch X23. The output terminal of the AND operator X32 is connected to the output terminal of the deceleration signal D1.

  Note that the NOR operator X31 and the AND operator X32 generate frequency error signals (acceleration signal U1 and deceleration signal D1) according to the operating states of the first counter circuit X10 and the second counter circuit X20. A logic gate portion X30 is formed.

  The clock end of the reference counter Y1 is connected to the input end of the internal clock signal ICLK. The reset terminal (R) of the reference counter Y1 is connected to the input terminal of the reference clock signal REFCLK. The clock end of the reference register Y2 is connected to the input end of the internal clock signal ICLK. The set end of the reference register Y2 is connected to the input end of the reference clock signal REFCLK. The data input terminal of the reference register Y2 is connected to the output terminal of the reference counter Y1.

  The reference register Y2 outputs i-bit (for example, i = 18 bits) register data REG0. Of the i-bit register data REG0, the register data REG2 corresponding to the upper (i-2) bits is sent to the second input terminal of the first comparison unit X12 as the first end count value STOP1. Of the i-bit register data REG0, register data REG1 corresponding to the upper (i-1) bits and register data REG2 corresponding to the upper (i-2) bits are sent to the adder Y3. . The adder Y3 adds the register data REG1 and the register data REG2, and outputs addition data ADD1. The addition data ADD1 is sent to the second input terminal of the second comparison unit X22 as the second end count value STOP2.

  That is, in the FLL circuit 12 of this configuration example, the end count value setting unit Y0 sets the first end count value STOP1 and the second end count value STOP2 based on the register data REG0 stored in the reference register Y2. It is said that. More specifically, the end count value setting unit Y0 converts the register data REG0 stored in the reference register Y2 to s: 1-s (where 0 <s <1, and s = 1/4 in FIG. 3). The first end count value STOP1 and the second end count value STOP2 are set by distributing at the ratio.

  The operation of the FLL circuit 12 having the above configuration will be described in detail with reference to FIG.

  FIG. 3 is a timing chart showing an operation example of the FLL circuit 12. In the upper part of FIG. 3, a reference clock signal REFCLK, a count value C0 of the reference counter Y1, register data REG1, register data REG2, and addition data ADD1 are shown. 3, the count value C1 of the first counter X11 when the frequency of the FG pulse signal is lower than the frequency of the reference clock signal REFCLK (that is, when the rotation speed of the motor M is slower than the target rotation speed). The comparison signal CS1 of the first comparison unit X12, the count value C2 of the second counter X21, the comparison signal CS2 of the second comparison unit X22, the acceleration signal U1, and the deceleration signal D1 are shown. In the lower part of FIG. 3, the count value C1 of the first counter X11 when the frequency of the FG pulse signal is higher than the frequency of the reference clock signal REFCLK (that is, when the rotation speed of the motor M is faster than the target rotation speed). The comparison signal CS1 of the first comparison unit X12, the count value C2 of the second counter X21, the comparison signal CS2 of the second comparison unit X22, the acceleration signal U1, and the deceleration signal D1 are shown.

  First, the variable control operation of the first end count value STOP1 and the second end count value STOP2 will be described in detail with reference to the upper part of FIG.

  The reference counter Y1 is a means for counting the internal clock signal ICLK (a clock signal having a sufficiently higher frequency than the reference clock signal REFCLK), and its count value is reset by using the rising edge of the reference clock signal REFCLK as a trigger. Is. That is, in the reference counter Y1, the internal clock signal ICLK included in one cycle of the reference clock signal REFCLK (during the period from the arrival of one rising edge of the reference clock signal REFCLK until the arrival of the next rising edge). The number of pulses is counted. In the example of FIG. 3, the internal clock signal ICLK of 1600 pulses is counted during one cycle of the reference clock signal REFCLK.

  The reference register Y2 is i-bit (for example, i = 18 bits) data holding means for storing the count value C0 (count value immediately before being reset) of the reference counter Y1 triggered by the rising edge of the reference clock signal REFCLK. That is, in the example of FIG. 3, the count value “1600” is stored as the register data REG0 of the reference register Y2 for each rising edge of the reference clock signal REFCLK.

  When the first end count value STOP1 and the second end count value STOP2 are set based on the register data REG0, the total value of the first end count value STOP1 and the second end count value STOP is the register data REG0. Must match. For this purpose, the register data REG0 is distributed at a ratio of s: 1-s (where 0 <s <1 and s = 1/4 in FIG. 3), whereby the first end count value STOP1 (= s × REG0) and the second end count value STOP2 (= (1-s) × REG0) may be set.

  As described above, as the first end count value STOP1, the register data REG2 corresponding to the upper (i-2) bits of the i-bit register data REG0 is set. That is, as the first end count value STOP1, a count value (= (1/4) × REG0) obtained by shifting the register data REG0 by 2 bits is set. More specifically, referring to the example of FIG. 3, the count value “400” is set as the first end count value STOP1.

  As the second end count value STOP2, among the i-bit register data REG0, register data REG1 corresponding to upper (i-1) bits and register data REG2 corresponding to upper (i-2) bits. Is added to add data ADD1. That is, as the second end count value STOP2, the count value obtained by shifting the register data REG0 by 1 bit (= (1/2) × REG0) and the count value obtained by shifting the register data REG0 by 2 bits (= (1 / 4) × REG0) plus the count value (= (3/4) × REG0) is set. More specifically, the count value “1200” is set as the second end count value STOP2.

  With such a configuration, the register data REG0 is distributed at a ratio of s: 1-s by extremely simple digital signal processing, and the first end count value STOP1 and the second end count value STOP2 are appropriately variably controlled. It becomes possible.

  In the example of FIG. 3, the configuration in which s = 1/4 is set as the distribution ratio of the register data REG0 has been described as an example. However, the configuration of the present invention is not limited to this, and the addition is performed. An arbitrary distribution ratio can be set by changing the configuration of the device Y3.

  Next, an operation when the frequency of the FG pulse signal is lower than the frequency of the reference clock signal REFCLK will be described with reference to the middle part of FIG. When one rising edge arrives in the FG pulse signal, the count operation of the internal clock signal ICLK by the first counter X11 is started using this as a trigger. When the count value C1 of the first counter X11 reaches the first end count value STOP1 (400 counts in the example of FIG. 3), the count operation of the first counter X11 is ended, and the count value C1 is reset, The count operation of the internal clock signal ICLK by the second counter X21 is started. When the count value C2 of the second counter X21 reaches the second end count value STOP2 (1200 counts in the example of FIG. 3), the count operation of the second counter X21 is ended and the count value C2 is reset. At this time, if the next rising edge has not arrived in the FG pulse signal, neither the first counter X11 nor the second counter X21 is in the state of performing the counting operation. If such a state occurs, the rotational speed of the motor M is slower than the target rotational speed, so the next rising edge arrives in the FG pulse signal and the count operation of the first counter X11 starts. Until this is done, the acceleration signal U is kept at a high level.

  Next, an operation when the frequency of the FG pulse signal is higher than the frequency of the reference clock signal REFCLK will be described with reference to the lower part of FIG. The operation from the arrival of one rising edge to the FG pulse signal to the start of the counting operation of the internal clock signal ICLK by the second counter X21 is the same as described above, but the count value C2 of the second counter X21 is 2 When the next rising edge of the FG pulse signal arrives before reaching the end count value STOP2, the count operation of the first counter X11 is started without waiting for the count end of the second counter X21, The first counter X11 and the second counter X21 are in a state where they are simultaneously counting. If such a state occurs, the rotational speed of the motor M is faster than the target rotational speed, so the count value C2 of the second counter X21 reaches the second end count value STOP2, and the second counter The deceleration signal D is kept at a high level until the X21 counting operation is completed.

  That is, if the cycle of the FG pulse signal is longer than the cycle of the reference clock signal REFCLK, the FLL circuit 12 determines that the rotation speed of the motor M is slower than the target rotation speed, and outputs the acceleration signal U1. Is shorter than the cycle of the reference clock signal REFCLK, it is determined that the rotational speed of the motor M is faster than the target rotational speed, and the deceleration signal D1 is output.

  In particular, the FLL circuit 12 of this configuration example generates a frequency error signal (acceleration signal U1, deceleration signal D1) by comparing the frequency of the FG pulse signal to be controlled with the frequency of the reference clock signal REFCLK. When the rising edge of the FG pulse signal arrives, the count operation of the internal clock signal ICLK is started to set the first count start flag, and when the count value C1 reaches the first end count value STOP1, A first counter circuit X10 for setting a 1 count end flag; when the first count end flag is set, a count operation of the internal clock signal ICLK is started to set a second count start flag, and the count value C2 is When the second end count value STOP2 is reached, the second counter circuit X2 sets a second count end flag. A reference counter Y1 that counts the number of pulses of the internal clock signal ICLK included in one cycle of the reference clock signal REFCLK; and a reference register Y2 that stores the count value C0 of the reference counter Y1 for each cycle of the reference clock signal REFCLK Based on the register data REG0 stored in the reference register Y2 (more specifically, by distributing the register data REG0 at a ratio of s: 1-s (where 0 <s <1)), the first An end count value setting unit Y0 for setting the end count value STOP1 and the second end count value STOP; frequency error signals (acceleration signal U1, deceleration signal D1) according to the operating states of the first counter circuit X10 and the second counter circuit X20. And a logic gate section X30 for generating

  With such a configuration, the FLL circuit 12 that does not require the multiplication means of the reference clock signal REFCLK can be realized. Therefore, when the speed discriminator circuit 10 is configured, a feedback loop including a filter circuit is provided. There is no need to provide it. Therefore, it is possible to reduce the circuit scale of the speed discriminator circuit 10 and the motor driving device including the speed discriminator circuit 10 and to reduce the number of external elements. Further, by adopting this configuration, it is not necessary to adjust the filter constants, and it is possible to respond more rapidly to changes in the frequency of the reference clock signal REFCLK.

  Next, a second configuration example of the FLL circuit 12 will be described. In the FLL circuit 12 of the first configuration example described above, since digital signal processing is performed to divide the register data REG0 stored in the reference register Y2 by 1/2 to 1/4, it is stored as register data REG0. Depending on the number of pulses of the internal clock signal ICLK, a remainder may be generated when the first end count value STOP1 is set.

  Therefore, as shown in FIG. 4, the FLL circuit 12 of the second configuration example starts counting the internal clock signal ICLK when the pulse edge of the FG pulse signal arrives in addition to the previous components. A third counter X41 whose counting operation is terminated when the count value C3 reaches the standby count value WAIT; depending on whether or not the counter value C3 of the third counter X41 has reached the standby count value WAIT And a third comparison unit X42 that generates the comparison signal CS3.

  Note that the third counter X41 and the third comparison unit X42 start the count operation of the internal clock signal ICK when the rising edge of the FG pulse signal arrives, and the count value C3 of the third counter X41 is the standby count. When the value WAIT is reached, a third counter circuit X30 is formed that sets a pulse on the comparison signal CS3 as a third count end flag.

  Further, in the FLL circuit 12 of the second configuration example, the end count value setting unit sets the register data corresponding to the lower 2 bits of the i-bit register data REG0 stored in the reference register Y2 as the standby count value WAIT. The REM 2 is set.

  In the FLL circuit 12 of the second configuration example, the first counter circuit X10 starts its counting operation until the counting operation of the third counter circuit X40 is completed after the rising edge of the FG pulse signal has arrived. Is configured to wait. The second counter circuit X20 is configured to wait for the start of the counting operation until the counting operation of the first counter circuit X10 is completed.

  In other words, in a more general concept, in the FLL circuit 12 of the second configuration example, the end count value setting unit uses the surplus of the register data REG0 generated when the first end count value STOP1 is set as the standby count value WAIT. The first counter circuit X10 waits for the count operation to start until the number of pulses of the internal clock signal ICLK reaches the standby count value WAIT after the pulse edge of the FG pulse signal arrives. The second counter circuit X20 is configured to wait for the start of the counting operation until the counting operation of the first counter circuit X10 is completed.

  By adopting such a configuration, even when a remainder occurs during the division processing of the register data REG0, it is possible to avoid an error caused by this, and to control the rotation speed of the motor M with higher accuracy. Can be done.

  Next, a third configuration example of the FLL circuit 12 will be described with reference to FIG. FIG. 5 is a block diagram showing a third configuration example of the FLL circuit 12. As shown in FIG. 5, the FLL circuit 12 of this configuration example has substantially the same configuration as the second configuration example described above. Therefore, the same components as those in the second configuration example are denoted by the same reference numerals as those in FIG. 4, and redundant description is omitted. Hereinafter, the characteristic portions of the third configuration example will be mainly described.

  The FLL circuit 12 of the third configuration example includes a second reference register Y4 and an inverter Y5 in addition to the components shown in FIG. The clock end of the second reference register Y4 is connected to the input end of the internal clock signal ICLK. The set end of the second reference register Y4 is connected to the output end of the inverter Y5. The input end of the inverter Y5 is connected to the input end of the reference clock signal REFCLK. The data input terminal of the second reference register Y4 is connected to the output terminal of the reference register Y2.

  The second reference register Y4 outputs i-bit (for example, i = 18 bits) register data REG0 '. Of the i-bit register data REG0 ', the register data REG2 corresponding to the upper (i-2) bits is sent to the second input terminal of the first comparison unit X12 as the first end count value STOP1. Of the i-bit register data REG0 ', register data REG1 corresponding to the upper (i-1) bits and register data REG2 corresponding to the upper (i-2) bits are sent to the adder Y3. The The adder Y3 adds the register data REG1 and the register data REG2, and outputs addition data ADD1. The addition data ADD1 is sent to the second input terminal of the second comparison unit X22 as the second end count value STOP2.

  In the FLL circuit 12 having the above configuration, the reference register Y2 updates the register data REG0 when the rising edge of the reference clock signal REFCLK arrives, and the second reference register Y4 has the falling edge of the reference clock signal REFCLK. When it arrives, the register data REG0 ′ is updated.

  That is, the FLL circuit 12 of the third configuration example is stored in the reference register Y2 at a timing (falling edge of the reference clock signal REFCLK) different from the data update timing (rising edge of the reference clock signal REFCLK) of the reference register Y2. The end count value setting unit Y0 stores the register data REG0 ′ (stored in the second reference register Y4). As a result, the first end count value STOP1 and the second end count value STOP2 are set based on the register data REG0) stored in the reference register Y2.

  The significance of adopting the third configuration example will be described in detail with reference to FIG. 6 and FIG. FIG. 6 is a timing chart showing how a problem occurs during register update, and FIG. 7 is a timing chart showing how the problem during register update is eliminated in the FLL circuit 12 of the third configuration example.

  When the frequency error signal (acceleration signal U1, deceleration signal D1) generated by the FLL circuit 12 is used and the rotational speed of the motor M is feedback-controlled so that the frequencies of the FG pulse signal and the reference clock signal REFCLK coincide with each other, The timing at which the count value C2 of the 2 counter X21 reaches the second end count value STOP2 is necessarily near the rising edge of the reference clock signal REFCLK. On the other hand, in the first configuration example and the second configuration example, as described above, the register data REG0 of the reference register Y2 is updated at the rising edge of the reference clock signal REFCLK. The 1 end count value STOP1 and the second end count value STOP2 are updated.

  Here, when the count value C2 of the second counter X21 reaches the second end count value STOP2 before the data update timing, or at the data update timing, the count value C2 of the second counter X21 is Although the second end count value STOP2 has not been reached, the second end count value STOP2 is updated to a value larger than the current value, or at the above data update timing, the count value C2 of the second counter X21 Has not yet reached the second end count value STOP2, and the second end count value STOP2 has been updated to a value smaller than the current value, but the second end count value STOP2 after the update is stored in the second counter X21. If it is larger than the count value C2, a special problem occurs in the comparison operation of the second comparison unit X22. , The counter value C2 of the second counter X21 is normally reset when it reaches the second terminal count value STOP2.

  However, at the data update timing, the count value C2 of the second counter X21 has not reached the second end count value STOP2, and the second end count value STOP2 has been updated to a value smaller than the current value. At this time, if the updated second end count value STOP2 is smaller than the count value C2 of the second counter X21, the count value C2 of the second counter X21 and the second end count value STOP2 do not coincide thereafter. Therefore, the second counter circuit X20 cannot lower the second latch signal Q2 from the high level to the low level as the second count end flag, and the FLL circuit 12 performs the counting operation of the first counter circuit X10. During this time, the deceleration signal D1 is always set to a high level (full deceleration state).

  On the other hand, in the FLL circuit 12 of the third configuration example, after the register data REG0 of the reference register Y2 is updated at the rising edge of the reference clock signal REFCLK, the register of the second register Y2 is updated at the falling edge of the reference clock signal REFCLK. The data REG0 ′ is updated, and the first end count value STOP1 and the second end count value STOP2 are updated based on the value.

  Therefore, in the case of the FLL circuit 12 of the third configuration example, the second end count value STOP2 is updated at a timing when the count value C2 of the second counter X21 is sufficiently small, so that the count value C2 of the second counter X21 The second end count value STOP2 can be surely matched, and the above-described problem can be avoided in advance.

  Next, a fourth configuration example of the FLL circuit 12 will be described with reference to FIG. FIG. 8 is a block diagram showing a fourth configuration example of the FLL circuit 12. As shown in FIG. 8, the FLL circuit 12 of this configuration example has a configuration approximate to the third configuration example described above. Therefore, the same components as those in the third configuration example are denoted by the same reference numerals as those in FIG. 5, and redundant description is omitted. Hereinafter, the characteristic portions of the fourth configuration example will be mainly described.

  The first characteristic part in the FLL circuit 12 of this configuration example is that the adder Y3 is removed from the end count value setting unit Y0. In the FLL circuit 12 of this configuration example, among the i-bit register data REG0 ′ output from the second reference register Y4, the register data REG2 corresponding to the upper (i−2) bits is the first end count. The value STOP1 and the second end count value STOP2 are sent to the second input terminal of the first comparison unit X12 and the second input terminal of the second comparison unit X22, respectively.

  That is, in the FLL circuit 12 of this configuration example, the end count value setting unit Y0 is 1 of the register data REG0 ′ stored in the second reference register Y4 (and hence the register data REG0 stored in the reference register Y2). / X (where x> 1 and x = 4 in FIG. 8) is set as the first end count value STOP1, and 1 / y (where y ≧ x and y = 4 in FIG. 8) is the second end. The count value STOP2 is set.

  The second characteristic part of the FLL circuit 12 of this configuration example is that the third counter circuit X40 is used to wait for the count operation of the second counter circuit X20, not to wait for the count operation of the first counter circuit X10. It is a point. More specifically, the third counter circuit X40 starts the count operation of the internal clock signal ICLK when the first count end flag is set, and the count value C3 of the third counter X41 becomes the standby count value WAIT. When the signal reaches the reference signal CS3, the comparison signal CS3 is pulsed as the third count end flag. By adopting such a configuration, as in the second configuration example and the third configuration example described above, even when a remainder occurs during the division processing of the register data REG0, an error due to this is avoided. Therefore, the rotational speed control of the motor M can be performed with higher accuracy.

  That is, in order to solve the problem of the remainder caused by the division process of the register data REG0, the third counter circuit X40 is used to wait for the count operation of the first counter circuit X10, or the second counter circuit X20 is caused to perform the count operation. It can be said that whether to wait is arbitrary.

  The third characteristic part of the FLL circuit 12 of this configuration example is that the logical product calculator X25 is removed as a component of the second counter circuit X20, while a fourth counter X26 and a fourth comparison unit X27 are added. Is a point. The clock end of the fourth counter X26 is connected to the output end of the second comparison unit X22. The set end (S) of the fourth counter X26 is connected to the output end of the first comparison unit X12. The reset terminal (R) of the fourth counter X26 is connected to the output terminal of the fourth comparison unit X27. The first input terminal of the fourth comparison unit X27 is connected to the output terminal of the fourth counter X26. A reference value REF4 for setting the number of loops α (where α = {(x−1) × y / x}, α = 3 in FIG. 8) at the second input terminal of the fourth comparison unit X27. Is entered. The output terminal of the fourth comparison unit X27 is connected to the reset terminal (R) of the second counter X21.

  In FIG. 8, for the sake of convenience of explanation, an example is described in which the count value C4 of the fourth counter X26 and the predetermined reference value REF4 are input to the fourth comparison unit X27, and both are compared to generate the comparison signal CS4. Although described, the configuration of the present invention is not limited to this, and a configuration may be adopted in which predetermined logical operation processing is performed on the count value C4 of the fourth counter X26 and the operation result is output as the comparison signal CS4. . For example, when the loop count α is 3 (“11b” in 2-bit notation), the logical product operation of the first bit and the second bit from the lower order of the count value C4 is performed, and the operation result is compared. What is necessary is just to output as signal CS4. At this time, the comparison signal CS4 becomes low level until the count value C4 reaches the loop count α, and becomes high level when the count value C4 reaches the loop count α.

  As described above, in the FLL circuit 12 of this configuration example, when the first count end flag is set (when the third count end flag is set in FIG. 8), the second counter circuit X20 When the count operation of ICLK is started and the second latch signal Q2 rises from the low level to the high level as the second count start flag, every time the count value C2 of the second counter X21 reaches the second end count value STOP2 When the count value C2 is reset, the count value C4 (count value arrival count) of the fourth counter X26 is incremented by one, and when the count value C4 reaches the loop count α (= 3), the second count end flag As a result, the second latch signal Q2 falls from the high level to the low level.

  9 to 11 are timing charts showing an operation example of the FLL circuit 12 of the fourth configuration example. When the rotation speed of the motor M matches the target rotation speed, the rotation speed of the motor M is as follows. It shows a case where the rotational speed is higher than the target rotational speed and a case where the rotational speed of the motor M is slower than the target rotational speed. 9 to 11, reference clock signal REFCLK, FG pulse signal, reference counter Y1 count value C0, register data REG0, register data REG0 ′, first counter X11 count value C1, and second counter, respectively. A count value C2 of X21, a first latch signal Q1, a second latch signal Q2, an acceleration signal U1, and a deceleration signal D1 are shown.

  As can be seen from FIGS. 9 to 11, the first counter circuit X10 counts the number of pulses of the internal clock signal ICLK by the first end count value STOP1 (= (1/4) × REG0 ′), and the second counter The circuit X20 repeatedly counts the number of pulses of the internal clock signal ICLK by the second end count value STOP2 × the number of loops α (= {(1/4) × REG0 ′} × 3 = (3/4) × REG0 ′). To do.

  By adopting such a configuration, the same configuration as the first to third configuration examples described above can be obtained by simply adding the fourth counter X26 and the fourth comparison unit X27 without using the adder Y4 having a large circuit scale. An effect can be produced. In addition, since the number of bits of the second counter X21 can be reduced with the FLL circuit 12 of this configuration example, the circuit scale of the second counter circuit X20 can also be reduced.

  Returning to FIG. 8, the detailed description of the characteristic part of the FLL circuit 12 of this configuration example will be continued. The fourth characteristic part of the FLL circuit 12 of this configuration example is that a fifth counter Y6 and a fifth comparison unit Y7 are provided instead of the inverter Y5 added in the third configuration example. The clock end of the fifth counter Y6 is connected to the input end of the internal clock signal ICLK. The set end (S) of the fifth counter Y6 is connected to the output end of the first comparison unit X12. The reset terminal (R) of the fifth counter XY6 is connected to the output terminal of the fifth comparison unit Y7. The first input terminal of the fifth comparison unit Y7 is connected to the output terminal of the fifth counter Y6. The second input terminal of the fifth comparison unit Y7 is connected to the input terminal of the reference value REF5 for setting the delay time Td (see FIG. 12 described later). The output terminal of the fifth comparison unit Y7 is connected to the set terminal (S) of the second reference register Y4.

  The significance of adopting the above technical features will be described in detail with reference to FIGS. 9 to 11 and FIG. FIG. 12 is a timing chart showing how the problem at the time of register update is resolved in the FLL circuit 12 of the fourth configuration example. As shown in these drawings, in the FLL circuit 12 of this configuration example, the reference register Y2 performs data update when the rising edge of the reference clock signal REFCLK arrives, and the second reference register Y4 has the first count. The data is updated immediately after the end flag is set. In the example of FIG. 12, when the count operation of the first counter circuit X10 is completed and the count operation of the third counter circuit X40 is completed, the data update of the second reference register Y4 is performed promptly. In addition, a waiting time Td (that is, a reference value REF5) is set.

  With such a configuration, since the second end count value STOP2 is updated at a timing when the count value C2 of the second counter X21 is sufficiently small, the count value C2 of the second counter X21 and the second end count value It is possible to reliably match STOP2, and it is possible to avoid problems such as inability to reset. In particular, in the fourth configuration example in which the reset opportunity of the second counter X21 increases, it is desirable to use the fifth counter Y6 and the fifth comparison unit Y7 instead of the inverter Y5 in the third configuration example.

  In FIG. 8, for the sake of convenience of explanation, a configuration in which the count value C5 of the fifth counter Y6 and the predetermined reference value REF5 are input to the fifth comparison unit Y7 and compared to generate the comparison signal CS5 is taken as an example. Although described, the configuration of the present invention is not limited to this, and the comparison signal CS5 may be directly generated from the count value C5 of the fifth counter Y6.

  For example, in the FLL circuit 12 of the fourth configuration example, the third counter X41 is input with the register data REM2 corresponding to the lower 2 bits of the register data REG0 ′ as the standby count value WAIT. The count value C3 of X41 is 3 at the maximum ("11b" in binary notation). Therefore, in order to update the data in the second reference register Y4 without delay when the counting operation of the third counter circuit X40 is completed, a 3-bit counter is used as the fifth counter Y6, and the count of the fifth counter Y6 is performed. The most significant bit of the value C5 may be output as the comparison signal CS5. At this time, the comparison signal CS5 becomes low level until the count value C5 exceeds 3 (= 011b), and becomes high level when the count value C5 reaches 4 (= 100b).

  Next, a fifth configuration example of the FLL circuit 12 will be described with reference to FIG. FIG. 13 is a block diagram illustrating a fifth configuration example of the FLL circuit 12. As shown in FIG. 13, the FLL circuit 12 of this configuration example has a configuration substantially similar to that of the fourth configuration example described above. Therefore, the same components as those in the fourth configuration example are denoted by the same reference numerals as those in FIG. 8, and redundant description is omitted. Hereinafter, the characteristic portions of the fifth configuration example will be mainly described.

  The first characteristic part of the FLL circuit 12 of this configuration example is that the register data REG2 corresponding to the upper (i-2) bits out of the i-bit register data REG0 ′ output from the second reference register Y4 is the first. The first end count value STOP1 is sent to the second input terminal of the first comparison unit X12, and the register data REG4 corresponding to the upper (i-4) bits is used as the second end count value STOP2 in the second comparison unit X22. This is the point sent to the input end.

  In other words, in the FLL circuit 12 of this configuration example, the end count value setting unit Y0 is 1 / of the register data REG0 ′ (and hence the register data REG0 stored in the reference register Y2) stored in the second reference register Y4. x (where x> 1 and x = 4 in FIG. 13) is set as the first end count value STOP1, and 1 / y (where y ≧ x and y = 16 in FIG. 13) is set as the second end count. The value is set as STOP2.

  The second characteristic part of the FLL circuit 12 of this configuration example is that a logical sum calculator X28 is added as a component of the second counter circuit X20, and the second counter X21 is ready for generating the ready signal READY. It is also used as a counter. The first input terminal of the logical sum calculator X28 is connected to the output terminal of the second comparison unit X22. The second input terminal of the logical sum calculator X28 is connected to the mask signal output terminal of the ready signal generator X50. The output terminal of the logical sum calculator X28 is connected to the set terminal (S) of the fourth counter X26.

  Note that a 4-bit counter is used as the fourth counter X26, and the second input terminal of the fourth comparison unit X27 has a loop count α (where α = {(x−1) × y / x}). In FIG. 13, a reference value REF4 for setting α = 12) is input. Further, the signal path connecting the output terminal of the fourth comparison unit X27 and the reset terminal (R) of the second counter X21 is deleted.

  When the count value C4 of the fourth counter X26 reaches its maximum value 15, the mask signal (comparison signal CS8) input from the ready signal generation unit X50 to the logical sum calculator X28 is set to the high level. The input logic to the counter X26 is fixed at a high level.

  As described above, in the FLL circuit 12 of this configuration example, when the first count end flag is set (in FIG. 13, when the third count end flag is set), the second counter circuit X20 When the count operation of ICLK is started and the second latch signal Q2 rises from the low level to the high level as the second count start flag, every time the count value C2 of the second counter X21 reaches the second end count value STOP2 The count value C2 is reset, and the count value C4 (count value arrival count) of the fourth counter X26 is incremented by 1. When the count value C4 reaches the loop count α (= 12), the second count end flag As a result, the second latch signal Q2 falls from the high level to the low level. However, as described above, in the FLL circuit 12 of this configuration example, since the second counter X21 is also used as a ready counter for generating the ready signal READY, the count value C4 of the fourth counter X26 is used. After reaching the predetermined number of loops α, the counting operation of the second counter circuit X20 is not ended, and the counting operation similar to the above is continued.

  FIG. 14 is a block diagram illustrating a configuration example of the ready signal generation unit X50. As shown in FIG. 14, the ready signal generation unit X50 of this configuration example includes a sixth comparison unit X51, a seventh comparison unit X52, an eighth comparison unit X53, a third SR latch X54, a D latch X55, It has.

  The first input terminal of the sixth comparison unit X51 is connected to the output terminal of the fourth counter X26. A reference value REF6 (= 11) for setting the gate period start timing is input to the second input terminal of the sixth comparison unit X51. The first input terminal of the seventh comparison unit X52 is connected to the output terminal of the fourth counter X26. A reference value REF7 (= 13) for setting the gate period end timing is input to the second input terminal of the seventh comparison unit X52. The first input terminal of the eighth comparison unit X53 is connected to the output terminal of the fourth counter X26. A reference value REF8 (= 15) for setting the mask period start timing is input to the second input terminal of the eighth comparison unit X53. The output terminal of the eighth comparison unit X53 is connected to the second input terminal of the logical sum calculator X28 as the output terminal of the mask signal (comparison signal CS8). The set input terminal (S) of the third SR latch X54 is connected to the output terminal of the sixth comparison unit X51 and receives the comparison signal CS6. The reset input terminal (R) of the third SR latch X54 is connected to the output terminal of the seventh comparison unit X52, and receives the comparison signal CS7. The data input terminal (D) of the D latch X55 is connected to the output terminal (Q) of the third SR latch X54, and the gate signal G1 is input thereto. The clock input terminal of the D latch X55 is connected to the input terminal of the FG pulse signal. The output terminal (Q) of the D latch X55 is connected to the output terminal of the ready signal READY.

  In FIG. 14, for convenience of explanation, the count value C4 of the fourth counter X26 and predetermined reference values REF6 to REF8 are respectively input to the sixth comparison unit X51 to the eighth comparison unit X53, and the two are compared and compared. The configuration for generating the signals CS6 to CS8 has been described as an example, but the configuration of the present invention is not limited to this, and a predetermined logical operation process is performed on the count value C4 of the fourth counter X26, and the operation result is obtained. A configuration may be adopted in which comparison signals CS6 to CS8 are output.

  FIGS. 15 to 17 are timing charts showing an operation example of the FLL circuit 12 of the fifth configuration example. When the rotational speed of the motor M matches the target rotational speed, the rotational speed of the motor M is as follows. It shows a case where the rotational speed is higher than the target rotational speed and a case where the rotational speed of the motor M is slower than the target rotational speed. 15 to 17, reference clock signal REFCLK, FG pulse signal, reference counter Y1 count value C0, register data REG0, register data REG0 ′, first counter X11 count value C1, and second counter, respectively. A count value C2 of X21, a first latch signal Q1, a second latch signal Q2, an acceleration signal U1, a deceleration signal D1, a gate signal G1, and a ready signal READY are shown.

  As can be seen from FIGS. 15 to 17, the first counter circuit X10 counts the number of pulses of the internal clock signal ICLK by the first end count value STOP1 (= (1/4) × REG0 ′), and the second counter The circuit X20 repeatedly counts the number of pulses of the internal clock signal ICLK by the second end count value STOP2 × the number of loops α (= {(1/16) × REG0 ′} × 12 = (3/4) × REG0 ′). To do. Further, the second counter circuit X20 continues the above counting operation in order to generate the ready signal READY.

  By adopting such a configuration, the same effects as those of the first to third configuration examples can be obtained without using the adder Y4 having a large circuit scale as in the fourth configuration example. Further, with the FLL circuit 12 of this configuration example, the number of bits of the second counter X21 can be further reduced as compared with the fourth configuration example, so that the circuit scale of the second counter circuit X20 can be further reduced. It becomes.

  Further, in the FLL circuit 12 of this configuration example, the ready signal generation unit X50, when the rising edge of the FG pulse signal arrives, the count value C4 of the fourth counter X26 (that is, the count value arrival count of the second counter circuit X20) ) Is within a predetermined range, and a ready signal READY having a logic level corresponding to the detection result is generated.

  Specifically, referring to FIGS. 15 to 17, the ready signal generation unit X50 sets the gate signal G1 to the high level when the count value C4 of the fourth counter X26 becomes the reference value REF6 (= 11). When the count value C4 of the fourth counter X26 becomes the reference value REF7 (= 13), the gate signal G1 is set to the low level. When the rising edge of the FG pulse signal arrives during the high level period (gate period) of the gate signal G1 set in this way, the cycle of the FG pulse signal is ± 6. 5 with respect to the cycle of the reference clock signal REFCLK. Since it is within 25% and it can be determined that the rotation of the motor M is stable, the ready signal READY goes high in order to notify this state. On the other hand, when the rising edge of the FG pulse signal arrives during the low level period (non-gate period) of the gate signal G1, the cycle of the FG pulse signal is not within ± 6.25% with respect to the cycle of the reference clock signal REFCLK. Since it can be determined that the rotation of the motor M is unstable, the ready signal READY is at a low level in order to notify this state.

  As described above, in the FLL circuit 12 of this configuration example, the second counter X21 can be shared as a ready counter for generating the ready signal READY, which can contribute to a reduction in circuit scale. Become. Further, in the case of the FLL circuit 12 of this configuration example, the second end count is reached at a timing when the count value C2 of the second counter X21 is sufficiently small by the functions of the fifth counter Y6 and the seventh comparison unit Y7 described above. Since the value STOP2 is updated, the count value C2 of the second counter X21 and the second end count value STOP2 can be surely matched, and there is a problem such as inability to reset (in this configuration example, in addition to the aforementioned full deceleration state) In other words, it is possible to avoid a stationary ready state).

  In the above embodiment, the configuration using the frequency locked loop circuit according to the present invention has been described as an example of the speed discriminator circuit mounted on the motor drive device. The application target of is not limited to this, and can be widely applied to frequency-locked loop circuits used for other purposes.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  For example, in the above embodiment, in order to focus on the circuit configuration and operation of the FLL circuit 12, the speed discriminator circuit 10 uses only the frequency error signals (acceleration signal U 1 and deceleration signal D 1) of the FLL circuit 12. Accordingly, the configuration for generating the speed command signal VC has been described as an example. However, the configuration of the present invention is not limited to this, and as shown in FIG. The phase-locked loop circuit 14 that compares the phases of the FG pulse signal and the reference clock signal REFCLK to generate a phase error signal (acceleration signal U2 and deceleration signal D2) includes both a frequency error signal and a phase error signal. A configuration may be adopted in which a corresponding speed command signal VC is generated. If such a configuration is adopted, the rotational speed of the motor M can be controlled with higher accuracy.

  The present invention is a technique useful for realizing, for example, reducing the circuit scale of a speed discriminator circuit mounted on a motor drive device and reducing the number of external elements.

10 Speed Discriminator Circuit 11 FG Pulse Signal Generation Circuit 12 Frequency Locked Loop Circuit (FLL Circuit)
13 Charge pump circuit 14 Phase-locked loop circuit (PLL circuit)
15 charge pump circuit 20 integrating circuit 30 logic circuit 40 pre-driver 50 driver M motor X10 first counter circuit X11 first counter X12 first comparison unit X13 first SR latch X20 second counter circuit X21 second counter X22 second comparison unit X23 2nd SR latch X24 NAND operator X25 AND operator X26 4th counter X27 4th comparison unit X28 OR operator X30 logic gate X31 NOT OR operator X32 AND operator X40 3rd counter circuit X41 1st 3 counter X42 3rd comparison part X50 ready signal generation part X51 6th comparison part X52 7th comparison part X53 8th comparison part X54 3SR latch X55 D latch Y1 reference counter Y2 reference register Y3 adder Y4 2nd reference register Y5 in Over data Y6 fifth counter Y7 fifth comparison unit Y0 terminal count value setting unit

Claims (17)

A frequency locked loop circuit that generates a frequency error signal by comparing the frequency of a pulse signal to be controlled with the frequency of a reference clock signal,
When the pulse edge of the pulse signal arrives, the count operation of the internal clock signal is started to set a first count start flag, and when the count value reaches the first end count value, the first count end flag A first counter circuit that stands up;
When the first count end flag is set, the counting operation of the internal clock signal is started and the second count start flag is set. When the count value reaches the second end count value, the second count ends. A second counter circuit for setting a flag;
A reference counter for counting the number of pulses of the internal clock signal included in one cycle of the reference clock signal;
A reference register for storing a count value of the reference counter for each cycle of the reference clock signal;
An end count value setting unit that sets a first end count value and a second end count value based on register data stored in the reference register;
A logic gate unit that generates the frequency error signal in accordance with operating states of the first counter circuit and the second counter circuit;
A frequency-locked loop circuit comprising:   The end count value setting unit distributes the register data stored in the reference register at a ratio of s: 1-s (where 0 <s <1), whereby the first end count value and the second end count value are set. The frequency-locked loop circuit according to claim 1, wherein: The end count value setting unit sets a surplus of the register data generated when setting the first end count value as a standby count value,
The first counter circuit waits for the start of the count operation from the arrival of the pulse edge of the pulse signal until the number of pulses of the internal clock signal reaches the standby count value,
3. The frequency locked loop circuit according to claim 2, wherein the second counter circuit waits for the start of the count operation until the first count end flag is set.   The end count value setting unit includes register data corresponding to upper (i-1) bits and register corresponding to upper (i-2) bits among i-bit register data stored in the reference register. It has an adder that adds data to generate addition data, sets register data corresponding to the upper (i-2) bits as the first end count value, and sets the second end count value as The frequency-locked loop circuit according to claim 2, wherein the addition data is set. A third counter circuit that starts counting the internal clock signal when the pulse edge of the pulse signal arrives and sets a third count end flag when the count value reaches the standby count value; And
The end count value setting unit sets register data corresponding to lower 2 bits of i-bit register data stored in the reference register as the standby count value.
The first counter circuit waits for the start of the count operation from the arrival of the pulse edge of the pulse signal until the third count end flag is set,
5. The frequency locked loop circuit according to claim 4, wherein the second counter circuit waits for the start of the count operation until the first count end flag is set. The end count value setting unit sets 1 / x (where x> 1) of the register data stored in the reference register as the first end count value, and sets 1 / y (where y ≧ x) as the second end. Set as count value,
The first counter circuit starts counting the internal clock signal when the pulse edge of the pulse signal arrives, sets a first count start flag, and when the count value reaches the first end count value To set the first count end flag,
The second counter circuit starts the count operation of the internal clock signal when the first count end flag is set, sets a second count start flag, and every time the count value reaches the second end count value When the count value is reset, the count value arrival count is incremented by one, and the count value arrival count reaches α times (where α = {(x−1) × y / x}) 2. The frequency locked loop circuit according to claim 1, wherein a count end flag is set. The end count value setting unit sets a surplus of the register data generated when setting the first end count value as a standby count value,
The second counter circuit waits for the start of the count operation until the number of pulses of the internal clock signal reaches the standby count value after the first count end flag is set. The frequency-locked loop circuit according to claim 6.   The end count value setting unit sets register data corresponding to upper (i-2) bits among i-bit register data stored in the reference register as a first end count value and a second end count value. The frequency-locked loop circuit according to claim 6.   The end count value setting unit sets, as a first end count value, register data corresponding to upper (i-2) bits among i-bit register data stored in the reference register, 4) The frequency-locked loop circuit according to claim 6, wherein register data corresponding to bits is set as a second end count value.   When the pulse edge of the pulse signal arrives, it detects whether or not the count value arrival count of the second counter circuit is within a predetermined range, and generates a ready signal having a logic level according to the detection result. The frequency locked loop circuit according to claim 9, further comprising a signal generation unit. A third counter circuit that starts counting the internal clock signal when the first count end flag is set and sets a third count end flag when the count value reaches the standby count value; And
The end count value setting unit sets register data corresponding to lower 2 bits of i-bit register data stored in the reference register as the standby count value.
The second counter circuit waits for the start of the counting operation from when the first count end flag is set until the third count end flag is set. The frequency locked loop circuit according to any one of 10. It has a second reference register that reads out the register data stored in the reference register at a timing different from the data update timing of the reference register and stores it as its own register data.
12. The end count value setting unit sets a first end count value and a second end count value based on register data stored in a second reference register. A frequency-locked loop circuit according to claim 1.   The reference register updates data when a pulse edge of the reference clock signal arrives, and the second reference register updates data when an inverted pulse edge of the reference clock signal arrives The frequency-locked loop circuit according to claim 12.   The reference register updates data when a pulse edge of the reference clock signal arrives, and the second reference register updates data immediately after a first count end flag is set. 12. The frequency locked loop circuit according to 12.   15. A speed discriminator circuit comprising the frequency locked loop circuit according to claim 1 and generating a speed command signal corresponding to the frequency error signal.   Comprising a phase-locked loop circuit that generates a phase error signal by comparing the phase of the pulse signal and the phase of the reference clock signal, and a speed command signal corresponding to both the frequency error signal and the phase error signal The speed discriminator circuit according to claim 15, wherein:   17. A motor drive device comprising the speed discriminator circuit according to claim 15 or 16, wherein the motor rotational speed is controlled based on the speed command signal.

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