CN116345961B

CN116345961B - Motor control system, motor control method, electronic equipment and readable storage medium

Info

Publication number: CN116345961B
Application number: CN202310266460.8A
Authority: CN
Inventors: 贤飞; 李勇; 雷响; 申沛东; 夏俊雄
Original assignee: Longxin Zhongke Jinhua Technology Co ltd
Current assignee: Longxin Zhongke Jinhua Technology Co ltd
Priority date: 2023-03-13
Filing date: 2023-03-13
Publication date: 2024-04-19
Anticipated expiration: 2043-03-13
Also published as: CN116345961A

Abstract

The application provides a control system of a motor, comprising: the device comprises a decoder, a first AND gate circuit, a second AND gate circuit, a singlechip and a motor; the decoder is used for converting the three-bit position coding signals acquired from the motor into multi-bit coding signals; the first AND gate circuit is used for converting the six-bit coded signal extracted from the multi-bit coded signal into a six-bit phase-change signal; the singlechip is used for responding to the pulse generation instruction to generate six paths of pulse signals; the second AND gate circuit is used for fusing the six-way pulse signals and the six-bit phase conversion signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase conversion and driving, so that the DC brushless motor is subjected to phase conversion through the decoder chip and the AND gate circuit, the delay time of the decoder chip and the AND gate circuit is in nanosecond level, and compared with microsecond level delay time in the prior art, the operation efficiency of the DC brushless motor is improved.

Description

Motor control system, motor control method, electronic equipment and readable storage medium

Technical Field

The application relates to a control system and method of a motor, electronic equipment and a readable storage medium.

Background

In order to commutate a brushless dc motor, a control system for the motor is required.

In the prior art, a direct current brushless motor is subjected to phase change through a built-in program of a singlechip.

It should be noted that, the built-in program of the single chip microcomputer includes a plurality of subroutines, each subroutine includes a plurality of instructions, and the time of one instruction period is about 1us, so the execution time of the built-in program of the single chip microcomputer is about 100 us.

In carrying out the present application, the inventors have found that at least the following problems exist in the prior art: because the execution time of the built-in program of the singlechip is about 100us, the delay time for commutation of the direct-current brushless motor is too long, so that the commutation time of the direct-current brushless motor is inaccurate, and the running efficiency is low.

Disclosure of Invention

The application aims to provide a control system and method of a motor, electronic equipment and a readable storage medium, and at least solves the problems of inaccurate commutation time and low operation efficiency of a direct-current brushless motor caused by overlong delay time for commutation of the direct-current brushless motor due to the fact that the execution time of a built-in program of a singlechip is about 100us in the prior art.

In order to solve the technical problems, the application is realized as follows:

in a first aspect, an embodiment of the present application provides a control system for an electric motor, the system including:

the decoder, the first AND gate circuit, the second AND gate circuit and the singlechip;

the decoder is used for converting the three-bit position coding signals acquired from the motor into multi-bit coding signals and outputting the multi-bit coding signals to the first AND gate circuit; the three-position encoded signal is used to characterize the position of the rotor of the motor;

The first AND gate circuit is used for extracting a six-bit coded signal from the multi-bit coded signal, converting the six-bit coded signal into a six-bit phase-change signal and outputting the six-bit phase-change signal to the second AND gate circuit; the singlechip is used for responding to an externally input pulse generation instruction, generating six paths of pulse signals and outputting the six paths of pulse signals to the second AND gate circuit; the six paths of pulse signals are used for controlling the rotating speed of the rotor;

And the second AND gate circuit is used for fusing the six paths of pulse signals and the six-bit phase-change signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase-change and driving.

In a second aspect, an embodiment of the present application further provides a method for controlling a motor, where the method includes:

Converting the three-bit coded signal acquired from the motor into a multi-bit coded signal; the three-bit coded signal is used for characterizing the position of a rotor of the motor;

Converting the six-bit coded signal extracted from the multi-bit coded signal into a six-bit phase-change signal through AND gate logic;

Generating six paths of pulse signals in response to the pulse generation instruction; the six paths of pulse signals are used for controlling the rotating speed of the rotor;

Fusing the six paths of pulse signals and the six-bit phase-change signals through AND gate logic to generate six-bit driving signals;

and according to the six-bit driving signal, controlling the motor to perform phase change and driving the rotor.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor, a memory, and a program or instruction stored on the memory and executable on the processor, the program or instruction implementing the steps of the method according to the second aspect when executed by the processor.

In a fourth aspect, embodiments of the present application also provide a readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the method according to the second aspect.

Aiming at the prior art, the application has the following advantages:

The control system of the motor of the embodiment of the application comprises: the decoder, the first AND gate circuit, the second AND gate circuit and the singlechip; the decoder is used for converting the three-bit position coding signals acquired from the motor into multi-bit coding signals and outputting the multi-bit coding signals to the first AND gate circuit; the three-position coded signal is used for representing the position of a rotor of the motor; the first AND gate circuit is used for extracting a six-bit coded signal from the multi-bit coded signal, converting the six-bit coded signal into a six-bit phase-change signal and outputting the six-bit phase-change signal to the second AND gate circuit; the singlechip is used for responding to an externally input pulse generation instruction, generating six paths of pulse signals and outputting the six paths of pulse signals to the second AND gate circuit; the six paths of pulse signals are used for controlling the rotating speed of the rotor; the second AND gate circuit is used for fusing six pulse signals and six-bit phase conversion signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase conversion and driving, so that the direct-current brushless motor is subjected to phase conversion through the decoder chip and the AND gate circuit, and the delay time of the decoder chip and the AND gate circuit is in nanosecond level, therefore, the delay time of the direct-current brushless motor is in nanosecond level, compared with the microsecond delay time of the direct-current brushless motor subjected to phase conversion through the built-in program of the singlechip in the prior art, the operation efficiency of the direct-current brushless motor is improved, and the problems that the delay time of the direct-current brushless motor subjected to phase conversion is overlong, the direct-current brushless motor is inaccurate in phase conversion time and the operation efficiency is low in the prior art due to the fact that the execution time of the built-in program of the singlechip is about 100us are solved.

Drawings

In the drawings:

fig. 1 is a schematic diagram of a control system of a motor according to an embodiment of the present application;

Fig. 2 is a schematic diagram of a main circuit of a motor control system according to an embodiment of the present application when the motor is subjected to forward commutation and a rotor is driven to rotate in a forward direction;

fig. 3 is a schematic diagram of a main circuit of a motor control system according to an embodiment of the present application when the motor is reversely commutated and the rotor is driven to reversely rotate;

Fig. 4 is a schematic signal waveform timing diagram corresponding to a control system of a motor according to an embodiment of the present application when the motor is forward commutated and the rotor is driven to rotate forward;

Fig. 5 is a specific schematic diagram of a control system of a motor according to an embodiment of the present application;

fig. 6 is a flowchart of steps of a method for controlling a motor according to an embodiment of the present application;

Fig. 7 is a schematic hardware structure of an electronic device according to an embodiment of the present application;

fig. 8 is a schematic diagram of a control system of a related art motor.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that, the motor in the embodiment of the present application refers to a dc brushless motor; the decoder is a chip, such as a chip model 74HC 138; the second and gate circuit is composed of a plurality of parallel chips, for example, as shown in fig. 2 or 3, and the second and gate circuit is composed of two parallel chips of model 74HC08, the chip 1 of model 74HC08 includes a synthesizing sub-circuit U2A, a synthesizing sub-circuit U2B, a synthesizing sub-circuit U2C, a synthesizing sub-circuit U2D, and the chip 2 of model 74HC08 includes a synthesizing sub-circuit U3A, a synthesizing sub-circuit U3B.

Referring to fig. 1, an embodiment of the present application provides a control system of an electric motor, the system including: the decoder, the first AND gate circuit, the second AND gate circuit and the singlechip; the decoder is used for converting the three-bit position coding signals acquired from the motor into multi-bit coding signals and outputting the multi-bit coding signals to the first AND gate circuit; the three-position encoded signal is used to characterize the position of the rotor of the motor; the first AND gate circuit is used for extracting a six-bit coded signal from the multi-bit coded signal, converting the six-bit coded signal into a six-bit phase-change signal and outputting the six-bit phase-change signal to the second AND gate circuit; the singlechip is used for responding to an externally input pulse generation instruction, generating six paths of pulse signals and outputting the six paths of pulse signals to the second AND gate circuit; the six paths of pulse signals are used for controlling the rotating speed of the rotor; and the second AND gate circuit is used for fusing the six paths of pulse signals and the six-bit phase-change signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase-change and driving.

Fig. 8 is a schematic diagram of a control system of a related art motor, which includes a single chip microcomputer, a motor, a power driving unit and a rotor signal collecting unit, wherein the single chip microcomputer includes a pulse generating unit, and includes an interrupt step, an operation step and a built-in program of an execution step, and the pulse generating unit mainly functions to generate a driving pulse signal of a dc brushless motor; the interrupt step, the operation step and the execution step mainly function to perform phase change processing, the rotor signal acquisition unit acquires a rotor position signal and sends the rotor position signal to the singlechip, and the singlechip starts to execute a built-in program, and the method comprises the following steps: the interruption step is responsible for receiving and analyzing the position signal of the rotor, then entering the operation step for logic operation, then entering the execution step, combining the operation result and the driving pulse signal to obtain a mixed driving signal, inputting the mixed driving signal to the power driving unit, driving the DC brushless motor for phase change and driving the rotor to rotate. The process of processing the commutation signal by the singlechip needs to carry out program operation of three steps of interruption, operation and execution, each operation step can bring time delay, each program instruction occupies microsecond time delay because the main frequency of the singlechip at the low end is low, the total time delay usually reaches more than 100 microseconds from the time of outputting the position signal of the rotor by the rotor position acquisition unit to the time of finishing processing by the singlechip and outputting the mixed driving signal, and the time delay needs to be delayed by more than 100 microseconds. The problem brought by the delay of the commutation time is inaccurate commutation time, which results in low operation efficiency of the brushless DC motor.

The control system of the motor provided by the embodiment of the application can realize that the DC brushless motor is commutated through the decoder chip and the AND gate circuit, and the delay time of the decoder chip and the AND gate circuit is in nanosecond level, so that the delay time of the decoder chip and the AND gate circuit for commutating the DC brushless motor is in nanosecond level, and compared with the microsecond delay time of the prior art for commutating the DC brushless motor through the built-in program of the singlechip, the control system of the motor improves the operation efficiency of the DC brushless motor, and solves the problems of inaccurate commutation time and low operation efficiency of the DC brushless motor caused by overlong delay time for commutating the DC brushless motor due to about 100us of the execution time of the built-in program of the singlechip in the prior art.

Specifically, in some embodiments, a plurality of diodes connected in parallel and a plurality of pull-up resistors are used to form a first and gate, a chip with the model number of 74HC138 is used as a decoder, and two chips with the model number of 74HC08 connected in parallel are used as a second and gate. For example, a chip with a product model SN74HC138D is used as a decoder, two parallel chips with a product model SN74HC08D are used as a second and gate, according to a corresponding chip product manual, it can be known that the maximum delay time of the chip with the product model SN74HC138D is 225 ns, the maximum delay time of the chip with the product model SN74HC08D is 125 ns, the total delay time is 350 ns, and the first and gate is composed of a plurality of diodes and a plurality of pull-up resistors which are connected in parallel, and the delay time is also in nanosecond level.

Fig. 2 is a schematic circuit diagram of the motor control system when the motor is forward commutated and the rotor is driven to rotate forward, and when a chip with the model of 74HC138 is used as the decoder U1, the three-position-coding signals include a position-coding signal I1, a position-coding signal I2, and a position-coding signal I3.

The position coding signal I1 is input to an input end A of the decoder U1, the position coding signal I2 is input to an input end B of the decoder U1, and the position coding signal I3 is input to an input end C of the decoder U1; the power supply end VDD is connected to a port G1 of the decoder U1, and a port G2A and a port G2B of the decoder U1 are Grounded (GND); the output end of the decoder U1 comprises an output end Y0, an output end Y1, an output end Y2, an output end Y3, an output end Y4, an output end Y5, an output end Y6 and an output end Y7, and the output end of the decoder U1 outputs a multi-bit coding signal (eight-bit coding signal);

The first and gate circuit includes six input ends, namely an input end J1, an input end J2, an input end J3, an input end J4, an input end J5 and an input end J6, and the six-bit coded signal is extracted from the coded signal by connecting the output end Y1 of the decoder U1 to the input end J1 of the first and gate circuit, connecting the output end Y1 of the decoder U1 to the input end J2 of the first and gate circuit, connecting the output end Y3 of the decoder U1 to the input end J3 of the first and gate circuit, connecting the output end Y4 of the decoder U1 to the input end J4 of the first and gate circuit, connecting the output end Y5 of the decoder U1 to the input end J5 of the first and gate circuit, and connecting the output end Y6 of the decoder U1 to the input end J6 of the first and gate circuit.

The correspondence of the codes of the three-bit position encoded signal, the codes of the multi-bit encoded signal (i.e., the eight-bit encoded signal) and the codes of the six-bit encoded signal is shown in the following table (table 1):

TABLE 1

It should be noted that, the three-bit position-coded signals listed in the above table (table 1) are encoded in the corresponding order of the input terminal a, the input terminal B, and the input terminal C of the decoder U1, for example, the encoding 1"001" of the three-bit position-coded signal indicates that the position-coded signal I1 encoded with 0 is input to the input terminal a of the decoder U1, the position-coded signal I2 encoded with 0 is input to the input terminal B of the decoder U1, and the position-coded signal I3 encoded with 1 is input to the input terminal C of the decoder U1;

The codes of the multi-bit encoded signals listed in the above table (table 1) are listed in the corresponding order of the output terminal Y0, the output terminal Y1, the output terminal Y2, the output terminal Y3, the output terminal Y4, the output terminal Y5, the output terminal Y6, and the output terminal Y7 of the decoder U1, for example, the code 1"10111111" of the multi-bit encoded signal indicates that the output terminal Y0 of the decoder U1 outputs the code signal of 1, the output terminal Y1 of the decoder U1 outputs the code signal of 0, the output terminal Y2 of the decoder U1 outputs the code signal of 1, the output terminal Y3 of the decoder U1 outputs the code signal of 1, the output terminal Y4 of the decoder U1 outputs the code signal of 1, the output terminal Y6 of the decoder U1 outputs the code signal of 1, and the output terminal Y7 of the decoder U1 outputs the code signal of 1;

The six-bit encoded signal input to the first gate listed in the above table (table 1) is encoded in the order of input terminal J1, input terminal J2, input terminal J3, input terminal J4, input terminal J5, input terminal J6 of the first and gate, for example, encoding 1 "01111" of the six-bit encoded signal indicates that encoding signal input to input terminal J1 of the first and gate is 0, encoding signal input to input terminal J2 of the first and gate is 1, encoding signal input to input terminal J3 of the first and gate is 1, encoding signal input to input terminal J4 of the first and gate is 1, encoding signal input to input terminal J5 of the first and gate is 1, and encoding signal input to input terminal J6 of the first and gate is 1.

In the above table (table 1), the code "1" indicates a high level, and the code "0" indicates a low level.

Fig. 3 is a schematic circuit diagram of the motor control system when the motor is reversely commutated and the rotor is reversely driven, and when a chip with the model of 74HC138 is used as the decoder U1, the input end, the output end and the corresponding relationship of the decoder U1 are similar to those described above, and are not repeated here.

Optionally, in some embodiments, the first and circuit includes six conversion sub-circuits connected in parallel with each other; the six-bit phase conversion signals are formed by combining one-bit phase conversion signals output by each of the six conversion sub-circuits; each path of the conversion sub-circuit is used for: and selecting a corresponding four-bit coded signal from the extracted six-bit coded signals, processing the four-bit coded signal through AND gate logic, and respectively outputting a one-bit phase-change signal corresponding to the conversion sub-circuit, so that the first AND gate circuit outputs the six-bit phase-change signal.

Because the extracted six-bit coded signal cannot be directly used as a phase-change signal and needs to be converted into a six-bit phase-change signal suitable for phase change, the embodiment of the application can realize that each path of conversion sub-circuit processes the four-bit coded signal according to the four-bit coded signal selected from the six-bit coded signal through AND gate logic, outputs a one-bit phase-change signal corresponding to the conversion sub-circuit, and further combines the one-bit phase-change signals respectively output by the six paths of conversion sub-circuits into the six-bit phase-change signal to be input into the second AND gate circuit.

Specifically, referring to fig. 2, in some embodiments, in the first and circuit, the inputs of the conversion sub-circuit outputting the one-bit commutation signal H1 are the one-bit encoded signal J2, the one-bit encoded signal J4, the one-bit encoded signal J5, the one-bit encoded signal J6. The input of the conversion sub-circuit outputting a one-bit phase-change signal H2 is a one-bit coding signal J1, a one-bit coding signal J2, a one-bit coding signal J3 and a one-bit coding signal J5; the input of the conversion sub-circuit outputting a one-bit phase-change signal H3 is a one-bit coding signal J1, a one-bit coding signal J3, a one-bit coding signal J4 and a one-bit coding signal J5; the input of the conversion sub-circuit outputting a one-bit phase-change signal H4 is a one-bit coded signal J2, a one-bit coded signal J3, a one-bit coded signal J4 and a one-bit coded signal J6; the input of the conversion sub-circuit outputting a one-bit phase-change signal H5 is a one-bit coded signal J1, a one-bit coded signal J2, a one-bit coded signal J3 and a one-bit coded signal J6; the inputs of the conversion sub-circuit outputting a bit-inversion signal H6 are a bit-encoded signal J1, a bit-encoded signal J4, a bit-encoded signal J5, and a bit-encoded signal J6.

Optionally, in some embodiments, each of the diodes is configured to determine a corresponding one-bit encoded signal, and each of the conversion sub-circuits includes four diodes connected in parallel and a pull-up resistor; each diode is used for respectively determining a corresponding one-bit coded signal; each path of the conversion sub-circuit is specifically configured to output a low-level one-bit phase-change signal when a low level exists in the corresponding four-bit coded signal; and outputting a high-level one-bit phase-change signal when the corresponding four-bit coded signals are all high-level.

The embodiment of the application specifically realizes that the conversion sub-circuit of each path outputs a one-bit phase-change signal corresponding to the conversion sub-circuit according to four-bit coded signals selected from six-bit coded signals, namely, the corresponding one-bit coded signal is determined through a diode, and then the low-level one-bit phase-change signal is output through AND gate logic under the condition that the one-bit coded signal in the corresponding four-bit coded signal is low level; under the condition that the corresponding four-bit coding signals are all high level, outputting a high-level one-bit phase-change signal through the corresponding pull-up resistor, and further combining the one-bit phase-change signals respectively output by the six-way conversion sub-circuit into a six-bit phase-change signal to be input into the second AND gate circuit.

Specifically, referring to fig. 2, in some embodiments, pull-up resistor R1, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, pull-up resistor R5, pull-up resistor R6 are all connected to VDD power; the pull-up resistor R1, the pull-up resistor R2, the pull-up resistor R3, the pull-up resistor R4, the pull-up resistor R5 and the pull-up resistor R6 are connected in parallel;

In the conversion sub-circuit outputting a one-bit phase-change signal H1, the corresponding pull-up resistor is a pull-up resistor R1, the corresponding four parallel diodes are a Schottky diode D1, a Schottky diode D2, a Schottky diode D3 and a Schottky diode D4, the pull-up resistor R1 is connected with the four Schottky diodes in parallel, the Schottky diode D1 determines a one-bit coding signal J6, the Schottky diode D2 determines a one-bit coding signal J4, the Schottky diode D3 determines a one-bit coding signal J5, and the Schottky diode D4 determines a one-bit coding signal J2;

In the conversion sub-circuit outputting the one-bit phase-change signal H2, the corresponding pull-up resistor is a pull-up resistor R2, the corresponding four parallel diodes are a Schottky diode D6, a Schottky diode D9, a Schottky diode D10 and a Schottky diode D16, the pull-up resistor R2 is connected with the four Schottky diodes in parallel, the Schottky diode D6 determines a one-bit coding signal J5, the Schottky diode D9 determines a one-bit coding signal J3, the Schottky diode D10 determines a one-bit coding signal J1, and the Schottky diode D16 determines a one-bit coding signal J2;

In the converting sub-circuit outputting the one-bit phase-change signal H3, the corresponding pull-up resistor is a pull-up resistor R3, the corresponding four parallel diodes are a Schottky diode D5, a Schottky diode D12, a Schottky diode D14 and a Schottky diode D17, the pull-up resistor R3 is connected with the four Schottky diodes in parallel, the Schottky diode D5 determines a one-bit coded signal J4, the Schottky diode D12 determines a one-bit coded signal J1, the Schottky diode D14 determines a one-bit coded signal J3, and the Schottky diode D17 determines a one-bit coded signal J5.

In the conversion sub-circuit outputting a one-bit phase-change signal H4, the corresponding pull-up resistor is a pull-up resistor R4, the corresponding four parallel diodes are a Schottky diode D7, a Schottky diode D8, a Schottky diode D15 and a Schottky diode D18, the pull-up resistor R4 is connected with the four Schottky diodes in parallel, the Schottky diode D7 determines a one-bit coding signal J6, the Schottky diode D8 determines a one-bit coding signal J4, the Schottky diode D15 determines a one-bit coding signal J3 and the Schottky diode D18 determines a one-bit coding signal J2;

In the conversion sub-circuit outputting a one-bit phase-change signal H5, the corresponding pull-up resistor is a pull-up resistor R5, the corresponding four parallel diodes are a Schottky diode D11, a Schottky diode D13, a Schottky diode D20 and a Schottky diode D21, the pull-up resistor R5 is connected with the four Schottky diodes in parallel, the Schottky diode D11 determines a one-bit coding signal J6, the Schottky diode D13 determines a one-bit coding signal J1, the Schottky diode D20 determines a one-bit coding signal J2 and the Schottky diode D21 determines a one-bit coding signal J3;

in the converting sub-circuit outputting the one-bit phase-change signal H6, the corresponding pull-up resistor is a pull-up resistor R6, the corresponding four parallel diodes are a Schottky diode D19, a Schottky diode D22, a Schottky diode D23 and a Schottky diode D24, the pull-up resistor R6 is connected with the four Schottky diodes in parallel, the Schottky diode D19 determines a one-bit coded signal J1, the Schottky diode D22 determines a one-bit coded signal J4, the Schottky diode D23 determines a one-bit coded signal J5 and the Schottky diode D24 determines a one-bit coded signal J6.

For example, when the one-bit encoded signal J2 is at a low level, the one-bit encoded signal J4 is at a high level, the one-bit encoded signal J5 is at a high level, and the one-bit phase-change signal H1 output by the corresponding sub-circuit is at a low level; when the one-bit encoded signal J2 is at a high level, the one-bit encoded signal J4 is at a high level, the one-bit encoded signal J5 is at a high level, and the one-bit phase-change signal H1 output from the corresponding sub-circuit is at a high level.

The correspondence of the six-bit encoded signal and the six-bit phase change signal is shown in the following table (table 2):

TABLE 2

It should be noted that, through the correspondence of the above table (table 2), the motor can be commutated forward and the rotor can be driven to rotate forward, and the six-bit code signals listed in the above table (table 2) are listed according to the order of the input end J1, the input end J2, the input end J3, the input end J4, the input end J5, and the input end J6 of the first and circuit.

For example, the code 1 "01111" of the six-bit code signal inputted by the encoder indicates that the code of the code signal inputted to the input terminal J1 of the first and gate circuit is 0, the code of the code signal inputted to the input terminal J2 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J3 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J4 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J5 of the first and gate circuit is 1.

The six-bit commutation signal codes listed in the above table (table 2) are listed in the order of one-bit commutation signal H1, one-bit commutation signal H2, one-bit commutation signal H3, one-bit commutation signal H4, one-bit commutation signal H5, one-bit commutation signal H6. For example, the code 1"100100" of the six-bit commutation signal outputted by the first and gate indicates that the code of the one-bit commutation signal H1 is 1, the code of the one-bit commutation signal H2 is 0, the code of the one-bit commutation signal H3 is 0, the code of the one-bit commutation signal H4 is 1, the code of the one-bit commutation signal H5 is 0, and the code of the one-bit commutation signal H6 is 0.

In the above table (table 2), the code "1" indicates a high level, and the code "0" indicates a low level.

Alternatively, referring to fig. 4, in some embodiments, when the motor rotates in the forward direction, the motor performs a commutation every 60 degrees of forward rotation of the rotor of the motor, and the commutation sequence sequentially commutates according to the sequence of codes 1,2, 3, 4, 5, and 6 in table 2; and (3) completing a phase conversion period after the rotor of the motor rotates 360 degrees in the forward direction.

Optionally, in some embodiments, the second and circuit includes six synthesis subcircuits connected in parallel with each other; the six-bit driving signals are formed by combining one-bit driving signals output by six paths of synthesis subcircuits respectively; each path of the synthesis subcircuit is used for: and respectively outputting the corresponding one-bit driving signals through AND gate logic according to the corresponding one-bit phase-change signals in the six-bit phase-change signals and the corresponding one-path pulse signals in the six-path pulse signals, so that the second AND gate circuit outputs the six-bit driving signals.

In practical application, when the motor commutation is controlled, the motor driving needs to be controlled, and thus the driving control signal, namely the six-bit pulse signal, is needed.

Specifically, referring to fig. 2 or 3, in some embodiments, in the second and circuit, the input of the synthesizing sub-circuit U2A outputting the one-bit driving signal Q1 is the one-bit phase-change signal H1 and one-way pulse signal M1;

the input of the synthesis subcircuit U2B which outputs a one-bit driving signal Q2 is a one-bit phase-change signal H2 and a pulse signal M2;

the input of the synthesis subcircuit U2C which outputs a one-bit driving signal Q3 is a one-bit phase-change signal H3 and a pulse signal M3;

the input of the synthesis subcircuit U2D which outputs a one-bit driving signal Q4 is a one-bit phase-change signal H4 and a pulse signal M4;

The input of the synthesis subcircuit U3A which outputs a one-bit driving signal Q5 is a one-bit phase-change signal H5 and a pulse signal M5;

The input of the synthesis subcircuit U3B, which outputs a one-bit drive signal Q6, is a one-bit phase-change signal H6 and a one-way pulse signal M6.

Optionally, in some embodiments, each of the synthesis subcircuits is an and gate logic circuit; each path of synthesis subcircuit is specifically configured to output, as the one-bit driving signal, the corresponding one path of pulse signal when the corresponding one-bit phase-change signal is at a high level; and outputting the one-bit driving signal of a low level when the corresponding one-bit phase-change signal is of a low level.

The embodiment of the application particularly realizes that the corresponding one-way pulse signal is output as one-bit driving signal by the synthesis sub-circuit of each way under the condition that the corresponding one-bit phase-change signal is high level; under the condition that the corresponding one-bit phase-change signal is low level, outputting the low-level one-bit driving signal, and further combining the one-bit driving signals respectively output by the six paths of synthesis sub-circuits to form a six-bit driving signal so as to control the motor to perform phase change and drive the motor.

Specifically, referring to fig. 4, in some embodiments, in a case where a one-bit phase-change signal input to the synthesizing sub-circuit is at a high level, a one-way pulse signal input to the synthesizing sub-circuit is used as a one-bit driving signal output by the synthesizing sub-circuit; in the case where the one-bit phase-change signal input to the synthesizing sub-circuit is low level, the synthesizing sub-circuit outputs a one-bit driving signal of low level.

For example, the code 1 of the six-bit commutation signal is "100100", that is, the code of the one-bit commutation signal H1 is 1, the code of the one-bit commutation signal H2 is 0, the code of the one-bit commutation signal H3 is 0, the code of the one-bit commutation signal H4 is 1, the code of the one-bit commutation signal H5 is 0, and the code of the one-bit commutation signal H6 is 0, then one pulse signal M1 is output as one-bit driving signal Q1, one-bit driving signal Q2 of low level is output, one-bit driving signal Q3 of low level is output, one pulse signal M4 is output as one-bit driving signal Q4, one-bit driving signal Q5 of low level is output, and one-bit driving signal Q6 of low level is output.

Optionally, in some embodiments, the first and gate circuit includes two first sub-circuits, two second sub-circuits, and two third sub-circuits connected in parallel with each other; the six-bit phase-change signal is formed by corresponding combination of one-bit phase-change signals output by the two paths of first sub-circuits, the two paths of second sub-circuits and the two paths of third sub-circuits respectively;

Each first sub-circuit is used for selecting a corresponding three-bit coded signal from the six-bit coded signals, respectively processing the three-bit coded signals through AND gate logic, and respectively outputting one-bit phase-change signals corresponding to the first sub-circuits;

each second sub-circuit is used for selecting a corresponding four-bit coded signal from the six-bit coded signals, respectively processing the four-bit coded signals through AND gate logic, and respectively outputting one-bit phase-change signals corresponding to the second sub-circuits;

Each path of third sub-circuit is used for selecting a corresponding five-bit coded signal from the six-bit coded signals, processing the five-bit coded signals through AND gate logic respectively, and outputting one-bit phase-change signals corresponding to the third sub-circuit respectively.

Because the extracted six-bit coded signal cannot be directly used as a commutation signal and needs to be converted into a six-bit commutation signal suitable for commutation, the embodiment of the application can realize that each path of first sub-circuit processes the three-bit coded signal through AND gate logic according to the three-bit coded signal selected from the six-bit coded signal and outputs a one-bit commutation signal corresponding to the first sub-circuit; each second sub-circuit processes the four-bit coded signals through AND gate logic according to the four-bit coded signals selected from the six-bit coded signals, and outputs a one-bit phase-change signal corresponding to the second sub-circuit; and each third sub-circuit processes the five-bit coded signals through AND gate logic according to the five-bit coded signals selected from the six-bit coded signals, and outputs one-bit phase-change signals corresponding to the third sub-circuits, so that the two first sub-circuits, the two second sub-circuits and the two third sub-circuits respectively output one-bit phase-change signals to be combined into six-bit phase-change signals, and the six-bit phase-change signals are input to the second AND gate circuit.

Specifically, referring to fig. 3, in some embodiments, in the first and circuit, the inputs of the second sub-circuit outputting the one-bit commutation signal H1 are the one-bit encoded signal J1, the one-bit encoded signal J2, the one-bit encoded signal J3, the one-bit encoded signal J5;

The input of the third sub-circuit outputting the one-bit phase-change signal H2 is a one-bit coded signal J2, a one-bit coded signal J3, a one-bit coded signal J4, a one-bit coded signal J5 and a one-bit coded signal J6;

The input of the first sub-circuit outputting a one-bit phase-change signal H3 is a one-bit coded signal J2, a one-bit coded signal J4 and a one-bit coded signal J6;

The input of the second sub-circuit outputting a one-bit phase-change signal H4 is a one-bit coded signal J1, a one-bit coded signal J3, a one-bit coded signal J4 and a one-bit coded signal J5;

The input of the third sub-circuit outputting the one-bit phase-change signal H5 is one-bit coded signal J1, one-bit coded signal J3, one-bit coded signal J4, one-bit coded signal J5 and one-bit coded signal J6;

the inputs of the first sub-circuit outputting a one-bit phase-change signal H6 are a one-bit encoded signal J1, a one-bit encoded signal J2, and a one-bit encoded signal J6.

Optionally, in some embodiments, each of the first sub-circuits includes three diodes connected in parallel and a pull-up resistor; each path of the second sub-circuit comprises four diodes connected in parallel and a pull-up resistor; each path of the third sub-circuit comprises five diodes connected in parallel and a pull-up resistor; each diode is used for respectively determining a corresponding one-bit coded signal; each first sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the first sub-circuit when a low level exists in the corresponding three-bit coded signal; outputting a high-level one-bit phase-change signal corresponding to the first sub-circuit through the corresponding pull-up resistor under the condition that the corresponding three-bit coded signals are all high-level; each second sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the second sub-circuit when a low level exists in the corresponding four-bit coded signal; outputting a high-level one-bit phase-change signal corresponding to the second sub-circuit through the corresponding pull-up resistor under the condition that the corresponding four-bit coded signals are all high-level; each third sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the third sub-circuit when a low level exists in the corresponding five-bit coded signal; and outputting a high-level one-bit phase-change signal corresponding to the third sub-circuit through the corresponding pull-up resistor under the condition that the corresponding five-bit coded signals are all high-level.

The embodiment of the application specifically realizes:

each first sub-circuit processes the three-bit coded signals through AND gate logic according to the three-bit coded signals selected from the six-bit coded signals, and outputs a one-bit phase-change signal corresponding to the first sub-circuit;

each second sub-circuit processes the four-bit coded signals through AND gate logic according to the four-bit coded signals selected from the six-bit coded signals, and outputs a one-bit phase-change signal corresponding to the second sub-circuit;

Each third sub-circuit processes the five-bit coded signals according to the five-bit coded signals selected from the six-bit coded signals through AND gate logic, outputs a one-bit phase-change signal corresponding to the third sub-circuit, namely, determines the corresponding one-bit coded signal through a diode, and outputs a low-level one-bit phase-change signal corresponding to the first sub-circuit through AND gate logic, for example, when one-bit coded signal in the corresponding three-bit coded signals is low-level;

Under the condition that the corresponding three-bit coding signals are all high levels, outputting a high-level one-bit phase-change signal corresponding to the first sub-circuit through the corresponding pull-up resistor, and further combining the two paths of first sub-circuits, the two paths of second sub-circuits and the two paths of third sub-circuits into a six-bit phase-change signal so as to be input into the second AND gate circuit.

Specifically, referring to fig. 3, in some embodiments, pull-up resistor R1, pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, pull-up resistor R5, pull-up resistor R6 are all connected to VDD power; the pull-up resistor R1, the pull-up resistor R2, the pull-up resistor R3, the pull-up resistor R4, the pull-up resistor R5 and the pull-up resistor R6 are connected in parallel.

In the second sub-circuit outputting the one-bit phase-change signal H1, the corresponding pull-up resistor is a pull-up resistor R1, the corresponding four parallel diodes are a Schottky diode D3, a Schottky diode D4, a Schottky diode D9 and a Schottky diode D10, the pull-up resistor R1 is connected with the four Schottky diodes in parallel, the Schottky diode D3 determines a one-bit coding signal J5, the Schottky diode D4 determines a one-bit coding signal J2, the Schottky diode D9 determines a one-bit coding signal J3, and the Schottky diode D10 determines a one-bit coding signal J1;

In the third sub-circuit outputting the one-bit phase-change signal H2, the corresponding pull-up resistor is a pull-up resistor R2, the corresponding five parallel diodes are a Schottky diode D1, a Schottky diode D2, a Schottky diode D6, a Schottky diode D14 and a Schottky diode D16, the pull-up resistor R2 is connected with the five Schottky diodes in parallel, the Schottky diode D1 determines a one-bit coding signal J6, the Schottky diode D2 determines a one-bit coding signal J4, the Schottky diode D6 determines a one-bit coding signal J5, the Schottky diode D14 determines a one-bit coding signal J3 and the Schottky diode D16 determines a one-bit coding signal J2;

In the first sub-circuit outputting the one-bit phase-change signal H3, the corresponding pull-up resistor is a pull-up resistor R3, the corresponding three parallel diodes are a Schottky diode D5, a Schottky diode D7 and a Schottky diode D18, the pull-up resistor R3 is connected with the three Schottky diodes in parallel, the Schottky diode D5 determines a one-bit code signal J4, the Schottky diode D7 determines a one-bit code signal J6, and the Schottky diode D18 determines a one-bit code signal J2.

In the second sub-circuit outputting the one-bit phase-change signal H4, the corresponding pull-up resistor is a pull-up resistor R4, the corresponding four parallel diodes are a Schottky diode D8, a Schottky diode D12, a Schottky diode D15 and a Schottky diode D17, the pull-up resistor R4 is connected with the four Schottky diodes in parallel, the Schottky diode D8 determines a one-bit coding signal J4, the Schottky diode D12 determines a one-bit coding signal J1, the Schottky diode D15 determines a one-bit coding signal J3 and the Schottky diode D17 determines a one-bit coding signal J5;

in the third sub-circuit outputting the one-bit phase-change signal H5, the corresponding pull-up resistor is a pull-up resistor R5, the corresponding five parallel diodes are a Schottky diode D11, a Schottky diode D13 and a Schottky diode D21, the Schottky diode D22 and the Schottky diode D23 are all connected in parallel, the pull-up resistor R5 is connected with the five Schottky diodes in parallel, the Schottky diode D11 determines a one-bit coding signal J6, the Schottky diode D13 determines a one-bit coding signal J1, the Schottky diode D21 determines a one-bit coding signal J3, the Schottky diode D22 determines a one-bit coding signal J4 and the Schottky diode D23 determines a one-bit coding signal J5;

In the first sub-circuit outputting the one-bit phase-change signal H6, the corresponding pull-up resistor is a pull-up resistor R6, the corresponding three parallel diodes are a Schottky diode D19, a Schottky diode D20 and a Schottky diode D24, the pull-up resistor R6 and the three Schottky diodes are all connected in parallel, the Schottky diode D19 determines the one-bit code signal J1, the Schottky diode D20 determines the one-bit code signal J2 and the Schottky diode D24 determines the one-bit code signal J6.

For example, in the case where the one-bit encoded signal J1 is high, the one-bit encoded signal J2 is low, the one-bit encoded signal J3 is high, and the one-bit encoded signal J5 is high, the one-bit phase shift signal H1 is low; when the one-bit encoded signal J1 is high, the one-bit encoded signal J2 is high, the one-bit encoded signal J3 is high, and the one-bit encoded signal J5 is high, the one-bit phase shift signal H1 is low.

The correspondence of the six-bit encoded signal and the six-bit phase change signal is shown in the following table (table 3):

TABLE 3 Table 3

It should be noted that, the reverse commutation of the motor and the reverse rotation of the rotor can be implemented by the correspondence relationship of the above table (table 3), and the six-bit code signals listed in the above table (table 3) are listed in the order of the input terminal J1, the input terminal J2, the input terminal J3, the input terminal J4, the input terminal J5, and the input terminal J6 of the first and circuit.

For example, the code 1 "01111" of the six-bit code signal outputted by the decoder indicates that the code of the code signal inputted to the input terminal J1 of the first and gate circuit is 0, the code of the code signal inputted to the input terminal J2 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J3 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J4 of the first and gate circuit is 1, the code of the code signal inputted to the input terminal J5 of the first and gate circuit is 1;

The six-bit commutation signal codes listed in the above table (table 3) are listed in the order of one-bit commutation signal H1, one-bit commutation signal H2, one-bit commutation signal H3, one-bit commutation signal H4, one-bit commutation signal H5, one-bit commutation signal H6. For example, code 1"100100" of the six-bit commutation signal indicates that code 1 of the one-bit commutation signal H1, code 0 of the one-bit commutation signal H2, code 0 of the one-bit commutation signal H3, code 1 of the one-bit commutation signal H4, code 0 of the one-bit commutation signal H5, code 0 of the one-bit commutation signal H6.

In the above table (table 3), the code "1" indicates a high level, and the code "0" indicates a low level.

Alternatively, in some embodiments, when the motor rotates in reverse, the motor performs a commutation every time the rotor of the motor rotates in reverse by 60 degrees, the sequence of the commutation is sequentially commutated according to the sequence of codes 1, 2,3, 4, 5, 6 in table 3 above; every time the rotor of the motor reversely rotates for 360 degrees, one phase conversion period is completed.

Optionally, referring to fig. 5, in some embodiments, the system further comprises a signal acquisition circuit connected to the motor; the signal acquisition circuit is connected with the decoder; the signal acquisition circuit is used for acquiring a position signal of a rotor of the motor; and generating the three-bit position coding signal according to the position signal of the rotor and outputting the three-bit position coding signal to the decoder.

The embodiment of the application can be used for collecting the position signal of the rotor of the motor from the motor and generating the three-position coding signal representing the position of the rotor to be input into the first AND gate circuit.

Specifically, in some embodiments, the signal acquisition circuit acquires a position signal of a rotor of the motor through a hall element or a comparator, and then generates a three-position-coded signal of the rotor according to the position signal of the rotor.

Referring to fig. 4, the correspondence relationship between the position of the rotor and the encoding of the three-bit position encoded signal of the rotor is as follows (table 4):

TABLE 4 Table 4

It should be noted that, the three-bit position-coded signals listed in the above table (table 4) are encoded in the order corresponding to the input terminal a, the input terminal B, and the input terminal C of the decoder U1, for example, the encoding 1"001" of the three-bit position-coded signal indicates that the position-coded signal I1 encoded with 0 is input to the input terminal a of the decoder U1, the position-coded signal I2 encoded with 0 is input to the input terminal B of the decoder U1, and the position-coded signal I3 encoded with 1 is input to the input terminal C of the decoder U1; in the above table (table 4), the code "1" indicates a high level, and the code "0" indicates a low level.

As shown in fig. 4, when the position of the rotor of the motor is at the position indicated by the code 1"001" of the three-bit position code signal, I1 is low, I2 is low, I3 is high, the code of the six-bit phase-change signal is "100100", i.e., the signal of H1 is high, the signal of H2 is low, the signal of H3 is low, the signal of H4 is high, the signal of H5 is low, the signal of H6 is low, at this time, one pulse signal M1 is output as one-bit drive signal Q1, one-bit drive signal Q2 of low is output, one-bit drive signal Q3 of low is output, one pulse signal M4 is output as one-bit drive signal Q4, one-bit drive signal Q5 of low is output, one-bit drive signal Q6 of low is output, the rotor of the motor is rotated from 0 degrees to 60 degrees, and the position of the rotor of the motor is rotated from the position indicated by the code 1"001" of the three-bit position indicated by the code 1 "011" of the three-bit position code signal is output;

When the position of the rotor of the motor is at the position indicated by the code 2 '011' of the three-bit position code signal, i.e. I1 is low level, I2 is high level, I3 is high level, at this time, the code of the six-bit phase-change signal is '100001', i.e. the signal of H1 is high level, the signal of H2 is low level, the signal of H3 is low level, the signal of H4 is low level, the signal of H5 is low level, at this time, one-way pulse signal M1 is output as one-bit drive signal Q1, one-bit drive signal Q2 of low level is output, one-bit drive signal Q4 of low level is output, one-way pulse signal M6 is output as one-bit drive signal Q6, the rotor of the motor is rotated from 60 degrees to 120 degrees, and the position indicated by the code 2 '011' of the three-bit position code signal is rotated to the position indicated by the code 3 '010' of the three-bit position code signal;

When the position of the rotor of the motor is at the position indicated by the code 3 '010' of the three-position code signal, i.e. I1 is low level, I2 is high level, I3 is low level, at this time, the code of the six-position phase-change signal is '001001', i.e. the signal of H1 is low level, the signal of H2 is low level, the signal of H3 is high level, the signal of H4 is low level, the signal of H5 is low level, the signal of H6 is high level, at this time, the one-position drive signal Q1 of low level is output, the one-position drive signal Q2 of low level is output, one-position drive signal Q3 of one pulse signal is output, the one-position drive signal Q4 of low level is output, the one-position drive signal Q5 of one-position drive signal is output, the one-position drive signal M6 is output as the one-position drive signal Q6, the rotor of the motor is rotated from 120 degrees to 180 degrees, and the position indicated by the code 3 '010' of the three-position drive signal is rotated to the position indicated by the code 4 '110' of the three-position code signal;

when the position of the rotor of the motor is at the position indicated by the code 4 '110' of the three-position code signal, i.e. I1 is high level, I2 is high level, I3 is low level, at this time, the code of the six-position phase-change signal is '011000', i.e. the signal of H1 is low level, the signal of H2 is high level, the signal of H3 is high level, the signal of H4 is low level, the signal of H5 is low level, the signal of H6 is low level, at this time, the one-position drive signal Q1 of low level is output, one-path pulse signal M2 is output as one-position drive signal Q2, one-path pulse signal M3 is output as one-position drive signal Q3, the one-position drive signal Q4 of low level is output, the one-position drive signal Q5 of low level is output, the one-position drive signal Q6 of low level is output, the rotor of the motor is rotated from 180 degrees to 240 degrees, and the position indicated by the code 4 '110' of the three-position drive signal is rotated to the position indicated by the code 5 '100' of the three-position code signal;

when the position of the rotor of the motor is at the position indicated by the code 5 '100' of the three-position code signal, i.e. I1 is at a high level, I2 is at a low level, I3 is at a low level, at this time, the code of the six-position phase-change signal is '010010', i.e. the signal of H1 is at a low level, the signal of H2 is at a high level, the signal of H3 is at a low level, the signal of H4 is at a low level, the signal of H5 is at a high level, at this time, the one-position drive signal Q1 of the low level is output, one-way pulse signal M2 is output as the one-position drive signal Q2, the one-position drive signal Q3 of the low level is output, one-way pulse signal M5 is output as the one-position drive signal Q5, the one-position drive signal Q6 of the low level is output, the rotor of the motor is rotated from 240 degrees to 300 degrees, and the position indicated by the code 5 '100' of the three-position drive signal is rotated to the position indicated by the code 6 '101' of the three-position code signal;

When the position of the rotor of the motor is at the position indicated by the code 6"101" of the three-position code signal, i.e., I1 is at a high level, I2 is at a low level, I3 is at a high level, at this time, the code of the six-position phase-change signal is "000110", i.e., the signal of H1 is at a low level, the signal of H2 is at a low level, the signal of H3 is at a low level, the signal of H4 is at a high level, the signal of H5 is at a high level, at this time, the signal of H6 is at a low level, at this time, the one-position drive signal Q1 of the low level is output, the one-position drive signal Q2 of the low level is output, the one-position drive signal Q3 of the low level is output, one-position drive signal M4 is output as one-position drive signal Q4, one-position drive signal M5 is output as one-position drive signal Q5, the one-position drive signal Q6 of the low level is output, the rotor of the motor is rotated from 300 degrees to 360 degrees (overlapping with 0 degrees), the position indicated by the code 6"101" of the three-position code signal of the rotor of the motor is at the high level, the position indicated by the code 1"001" of the three-position code signal of the motor is at this time, one-position drive signal is at the low level, one positive cycle of the rotation of the rotor is completed, one forward rotation cycle of the rotor is completed.

Under the condition that the motor is continuously commutated according to the forward commutation period, the rotor of the motor is continuously rotated along the forward direction.

Optionally, referring to fig. 5, in some embodiments, the system further comprises a power drive circuit connected to the motor; the power driving circuit is connected with the second AND gate circuit; the power driving circuit is used for generating a driving amplification signal according to the six-bit driving signal and outputting the driving amplification signal to the motor; the motor is specifically used for carrying out phase change and driving the rotor according to the driving amplification signal.

It should be noted that the power driving circuit in the embodiment is a conventional power driving circuit without pre-driving.

The six-bit driving signal needs to be amplified to drive the motor, and the method can be realized by generating a driving amplified signal according to the six-bit driving signal, and then inputting the driving amplified signal into the motor so as to perform phase change and drive the rotor by the power supply.

Alternatively, in some embodiments, for power driving circuits with pre-driving, it may be necessary to add an even bit inverter to convert the six bit driving signal to a six bit inverted driving signal, i.e., to invert the encoded even bits of the six bit driving signal, with the odd bits unchanged.

For example, a six-bit drive signal encoded as "100100" is converted to be encoded as "110001" by an even-bit inverter; and inputting the six-bit reverse phase driving signal into the pre-driving circuit, driving the power driving circuit by the pre-driving circuit according to the six-bit reverse phase driving signal, and driving the motor to change phase and drive the rotor by the power driving circuit.

Specifically, in some embodiments, the power driving circuit is formed by six MOS (metal-oxide-Semiconductor Field-Effect Transistor, MOSFET, metal-oxide semiconductor field effect transistor) power transistors, and each one of the six driving signals is input to a corresponding MOS power transistor to drive the motor to change phase and drive the rotor.

Optionally, in some embodiments, the three-bit position-coded signal comprises at least one high-level position-coded signal and at least one low-level position-coded signal; the six-bit coded signal comprises a low-level coded signal and five high-level coded signals; the six-bit phase-change signal comprises two high-level phase-change signals and four low-level phase-change signals.

Through the embodiment of the application, the corresponding relation among the three-bit position coding signal, the six-bit coding signal and the six-bit phase-change signal is realized through the decoder chip and the circuit, so that the aim of phase-change according to the position information of the rotor of the motor is fulfilled.

Specifically, in some embodiments, the correspondence between the three-bit position encoded signal, the six-bit encoded signal and the six-bit phase-change signal refers to the encoding listed in the foregoing table 1, and will not be repeated here.

Optionally, in some embodiments, the multi-bit encoded signal is an eight-bit encoded signal or a sixteen-bit encoded signal.

The control system of the motor in the embodiment of the application is applicable to different decoder chips.

Specifically, in some embodiments, when a chip with a model number of 74HC138 is used as the decoder, the multi-bit encoded signal is an eight-bit encoded signal, and the implementation manner is as described above, which is not repeated herein; when the chip of 74HC154 is used as the decoder, the three-bit position coding signal is connected to three of the four input ends of the chip, the other input end is fixed at high potential or low potential, the outputted multi-bit coding signal is sixteen-bit coding signal, and six-bit coding signal is selected from sixteen-bit coding signal to be used as the input signal of the first AND gate circuit, and the implementation manner is similar to the above, and the description is omitted here.

For example, when the three-bit position-encoded signal is connected to three of four input terminals of the decoder chip of model 74HC154 and the other input terminal is fixed at a high potential, the correspondence relationship of the three-bit position-encoded signal, the multi-bit encoded signal, and the six-bit encoded signal is as follows (table 5):

TABLE 5

The code descriptions in the above table (table 5) are similar to those described above and will not be repeated here.

In summary, a control system for a motor according to an embodiment of the present application includes: the decoder, the first AND gate circuit, the second AND gate circuit and the singlechip; the decoder is used for converting the three-bit position coding signals acquired from the motor into multi-bit coding signals and outputting the multi-bit coding signals to the first AND gate circuit; the three-position coded signal is used for representing the position of a rotor of the motor; the first AND gate circuit is used for extracting a six-bit coded signal from the multi-bit coded signal, converting the six-bit coded signal into a six-bit phase-change signal and outputting the six-bit phase-change signal to the second AND gate circuit; the singlechip is used for responding to an externally input pulse generation instruction, generating six paths of pulse signals and outputting the six paths of pulse signals to the second AND gate circuit; the six paths of pulse signals are used for controlling the rotating speed of the rotor; the second AND gate circuit is used for fusing six pulse signals and six-bit phase conversion signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase conversion and driving, so that the direct-current brushless motor is subjected to phase conversion through the decoder chip and the AND gate circuit, and the delay time of the decoder chip and the AND gate circuit is in nanosecond level, therefore, the delay time of the direct-current brushless motor is in nanosecond level, compared with the microsecond delay time of the direct-current brushless motor subjected to phase conversion through the built-in program of the singlechip in the prior art, the operation efficiency of the direct-current brushless motor is improved, and the problems that the delay time of the direct-current brushless motor subjected to phase conversion is overlong, the direct-current brushless motor is inaccurate in phase conversion time and the operation efficiency is low in the prior art due to the fact that the execution time of the built-in program of the singlechip is about 100us are solved.

Fig. 6 is a flowchart of steps of a method for controlling a motor according to an embodiment of the present application, as shown in fig. 6, the method may include:

And step 101, converting the three-bit coded signals acquired from the motor into multi-bit coded signals.

Wherein the three-bit encoded signal is used to characterize the position of a rotor of the motor.

The implementation of this step is similar to the implementation of the control system of the motor described above, and will not be repeated here.

Step 102, converting the six-bit coded signal extracted from the multi-bit coded signal into a six-bit phase-change signal through AND gate logic.

Step 103, generating six paths of pulse signals in response to an externally input pulse generation command.

The six paths of pulse signals are used for controlling the rotating speed of the rotor.

And 104, fusing the six paths of pulse signals and the six-bit phase-change signals through AND gate logic to generate six-bit driving signals.

And 105, controlling the motor to perform phase change and driving the rotor according to the six-bit driving signal.

In summary, the embodiment of the application can realize that the direct-current brushless motor is commutated through the decoder chip and the AND gate circuit, and the delay time of the decoder chip and the AND gate circuit is in nanosecond level, so that the delay time of the decoder chip and the AND gate circuit for commutating the direct-current brushless motor is in nanosecond level, and compared with the microsecond delay time of the prior art for commutating the direct-current brushless motor through the built-in program of the singlechip, the application improves the operation efficiency of the direct-current brushless motor, and solves the problems of inaccurate commutation time and low operation efficiency of the direct-current brushless motor caused by overlong commutation delay time of the direct-current brushless motor due to about 100us of the execution time of the built-in program of the singlechip in the prior art.

Optionally, the embodiment of the present application further provides an electronic device, including a processor, a memory, and a program or an instruction stored in the memory and capable of running on the processor, where the program or the instruction when executed by the processor implements each process of the foregoing embodiment of the method for controlling a motor, and the process can achieve the same technical effect, so that repetition is avoided, and details are not repeated here.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Fig. 7 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 200 includes, but is not limited to: radio frequency unit 201, network module 202, audio output unit 203, input unit 204, sensor 205, display unit 206, user input unit 207, interface unit 208, memory 209, and processor 210.

Those skilled in the art will appreciate that the electronic device 200 may further include a power source (e.g., a battery) for providing direct current to the various components, and the power source may be logically connected to the processor 210 through a power management system, so as to perform functions of managing charging, discharging, and managing power consumption through the power management system. The electronic device structure shown in fig. 5 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.

Wherein, the processor 210 is configured to convert the three-bit coded signal collected from the motor into a multi-bit coded signal; the three-bit coded signal is used for characterizing the position of a rotor of the motor;

The embodiment of the application also provides a readable storage medium, wherein the readable storage medium stores a program or an instruction, and the program or the instruction realizes each process of the motor control method embodiment when being executed by a processor, and can achieve the same technical effect, so that repetition is avoided and redundant description is omitted.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A control system for an electric machine, the system comprising: the decoder, the first AND gate circuit, the second AND gate circuit and the singlechip;

The first AND gate circuit is used for extracting a six-bit coded signal from the multi-bit coded signal, converting the six-bit coded signal into a six-bit phase-change signal and outputting the six-bit phase-change signal to the second AND gate circuit;

the singlechip is used for responding to an externally input pulse generation instruction, generating six paths of pulse signals and outputting the six paths of pulse signals to the second AND gate circuit; the six paths of pulse signals are used for controlling the rotating speed of the rotor;

the second AND gate circuit is used for fusing the six paths of pulse signals and the six-bit phase-change signals through AND gate logic, generating six-bit driving signals and outputting the six-bit driving signals to the motor for phase-change and driving;

When the motor is subjected to forward phase conversion and the rotor is driven to rotate forward, the first AND gate circuit comprises six conversion sub-circuits which are mutually connected in parallel; the six-bit phase conversion signals are formed by combining one-bit phase conversion signals output by each of the six conversion sub-circuits; each path of the conversion sub-circuit is used for: and selecting a corresponding four-bit coded signal from the extracted six-bit coded signals, processing the four-bit coded signal through AND gate logic, and respectively outputting a one-bit phase-change signal corresponding to the conversion sub-circuit, so that the first AND gate circuit outputs the six-bit phase-change signal.

2. The system of claim 1, wherein each of said conversion subcircuits includes four diodes in parallel and a pull-up resistor, respectively; each diode is used for respectively determining a corresponding one-bit coded signal;

each path of the conversion sub-circuit is specifically configured to output a low-level one-bit phase-change signal when a low level exists in the corresponding four-bit coded signal; and outputting a high-level one-bit phase-change signal when the corresponding four-bit coded signals are all high-level.

3. The system of claim 1, wherein the second and circuit comprises six synthesis subcircuits connected in parallel with each other; the six-bit driving signals are formed by combining one-bit driving signals output by six paths of synthesis subcircuits respectively;

Each path of the synthesis subcircuit is used for: and respectively outputting the corresponding one-bit driving signals through AND gate logic according to the corresponding one-bit phase-change signals in the six-bit phase-change signals and the corresponding one-path pulse signals in the six-path pulse signals, so that the second AND gate circuit outputs the six-bit driving signals.

4. A system according to claim 3, wherein each of said synthesis subcircuits is an and logic circuit;

Each path of synthesis subcircuit is specifically configured to output, as the one-bit driving signal, the corresponding one path of pulse signal when the corresponding one-bit phase-change signal is at a high level; and outputting the one-bit driving signal of a low level when the corresponding one-bit phase-change signal is of a low level.

5. The system of claim 1, wherein the first and gate circuit comprises two first sub-circuits, two second sub-circuits and two third sub-circuits connected in parallel with each other when the motor is reversely commutated and the rotor is reversely driven;

The six-bit phase-change signal is formed by corresponding combination of one-bit phase-change signals output by the two paths of first sub-circuits, the two paths of second sub-circuits and the two paths of third sub-circuits respectively;

6. The system of claim 5, wherein each of said first sub-circuits comprises three diodes connected in parallel and a pull-up resistor; each path of the second sub-circuit comprises four diodes connected in parallel and a pull-up resistor; each path of the third sub-circuit comprises five diodes connected in parallel and a pull-up resistor; each diode is used for respectively determining a corresponding one-bit coded signal;

Each first sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the first sub-circuit when a low level exists in the corresponding three-bit coded signal; outputting a high-level one-bit phase-change signal corresponding to the first sub-circuit through the corresponding pull-up resistor under the condition that the corresponding three-bit coded signals are all high-level;

Each second sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the second sub-circuit when a low level exists in the corresponding four-bit coded signal; outputting a high-level one-bit phase-change signal corresponding to the second sub-circuit through the corresponding pull-up resistor under the condition that the corresponding four-bit coded signals are all high-level;

each third sub-circuit is specifically configured to output a low-level one-bit phase-change signal corresponding to the third sub-circuit when a low level exists in the corresponding five-bit coded signal; and outputting a high-level one-bit phase-change signal corresponding to the third sub-circuit through the corresponding pull-up resistor under the condition that the corresponding five-bit coded signals are all high-level.

7. The system of claim 1, further comprising a signal acquisition circuit coupled to the motor; the signal acquisition circuit is connected with the decoder;

the signal acquisition circuit is used for acquiring a position signal of a rotor of the motor; and generating the three-bit position coding signal according to the position signal of the rotor and outputting the three-bit position coding signal to the decoder.

8. The system of claim 1, further comprising a power drive circuit coupled to the motor; the power driving circuit is connected with the second AND gate circuit;

the power driving circuit is used for generating a driving amplification signal according to the six-bit driving signal and outputting the driving amplification signal to the motor;

The motor is specifically used for carrying out phase change and driving the rotor according to the driving amplification signal.

9. The system according to any one of claims 1 to 8, wherein the three-bit position-coded signal comprises at least one high-level position-coded signal and at least one low-level position-coded signal;

The six-bit coded signal comprises a low-level coded signal and five high-level coded signals;

the six-bit phase-change signal comprises two high-level phase-change signals and four low-level phase-change signals.

10. A method of controlling an electric machine, the method comprising:

Generating six paths of pulse signals in response to an externally input pulse generation instruction; the six paths of pulse signals are used for controlling the rotating speed of the rotor;

According to the six-bit driving signal, the motor is controlled to perform phase change and the rotor is driven;

When the motor is subjected to forward phase conversion and the rotor is driven to rotate forward, the six-bit coded signal extracted from the multi-bit coded signal is converted into a six-bit phase conversion signal through AND gate logic, and the method comprises the following steps: for each bit of transposition signal, selecting a corresponding four-bit coding signal from the extracted six-bit coding signals, processing the four-bit coding signal through AND gate logic, and outputting a one-bit transposition signal; and combining the phase-change signals to form the six-bit phase-change signal.

11. An electronic device comprising a processor, a memory and a program or instruction stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the method of controlling a motor as claimed in claim 10.

12. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, realize the steps of the method of controlling an electric machine according to claim 10.